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tools: Mass fixing of empty prototypes (for -Wstrict-prototypes)

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This commit is contained in:
Anton Maklakov
2019-07-16 16:33:30 +07:00
parent 50629eec27
commit afbaf74007
507 changed files with 1295 additions and 1295 deletions
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8
components/soc/esp32/include/soc/cpu.h
View File

@@ -30,7 +30,7 @@
/** @brief Read current stack pointer address
*
*/
static inline void *get_sp()
static inline void *get_sp(void)
{
void *sp;
asm volatile ("mov %0, sp;" : "=r" (sp));
@@ -52,7 +52,7 @@ static inline void cpu_write_itlb(unsigned vpn, unsigned attr)
asm volatile ("witlb %1, %0; isync\n" :: "r" (vpn), "r" (attr));
}
static inline void cpu_init_memctl()
static inline void cpu_init_memctl(void)
{
#if XCHAL_ERRATUM_572
uint32_t memctl = XCHAL_CACHE_MEMCTL_DEFAULT;
@@ -71,7 +71,7 @@ static inline void cpu_init_memctl()
* 15 — no access, raise exception
*/
static inline void cpu_configure_region_protection()
static inline void cpu_configure_region_protection(void)
{
const uint32_t pages_to_protect[] = {0x00000000, 0x80000000, 0xa0000000, 0xc0000000, 0xe0000000};
for (int i = 0; i < sizeof(pages_to_protect)/sizeof(pages_to_protect[0]); ++i) {
@@ -108,7 +108,7 @@ void esp_cpu_reset(int cpu_id);
* @note If "Make exception and panic handlers JTAG/OCD aware"
* is disabled, this function always returns false.
*/
bool esp_cpu_in_ocd_debug_mode();
bool esp_cpu_in_ocd_debug_mode(void);
/**
* @brief Convert the PC register value to its true address

28
components/soc/esp32/include/soc/rtc.h
View File

@@ -176,7 +176,7 @@ void rtc_clk_init(rtc_clk_config_t cfg);
*
* @return XTAL frequency, one of rtc_xtal_freq_t
*/
rtc_xtal_freq_t rtc_clk_xtal_freq_get();
rtc_xtal_freq_t rtc_clk_xtal_freq_get(void);
/**
* @brief Update XTAL frequency
@@ -197,13 +197,13 @@ void rtc_clk_32k_enable(bool en);
/**
* @brief Configure 32 kHz XTAL oscillator to accept external clock signal
*/
void rtc_clk_32k_enable_external();
void rtc_clk_32k_enable_external(void);
/**
* @brief Get the state of 32k XTAL oscillator
* @return true if 32k XTAL oscillator has been enabled
*/
bool rtc_clk_32k_enabled();
bool rtc_clk_32k_enabled(void);
/**
* @brief Enable 32k oscillator, configuring it for fast startup time.
@@ -239,13 +239,13 @@ void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en);
* @brief Get the state of 8 MHz internal oscillator
* @return true if the oscillator is enabled
*/
bool rtc_clk_8m_enabled();
bool rtc_clk_8m_enabled(void);
/**
* @brief Get the state of /256 divider which is applied to 8MHz clock
* @return true if the divided output is enabled
*/
bool rtc_clk_8md256_enabled();
bool rtc_clk_8md256_enabled(void);
/**
* @brief Enable or disable APLL
@@ -276,7 +276,7 @@ void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq);
* @brief Get the RTC_SLOW_CLK source
* @return currently selected clock source (one of rtc_slow_freq_t values)
*/
rtc_slow_freq_t rtc_clk_slow_freq_get();
rtc_slow_freq_t rtc_clk_slow_freq_get(void);
/**
* @brief Get the approximate frequency of RTC_SLOW_CLK, in Hz
@@ -290,7 +290,7 @@ rtc_slow_freq_t rtc_clk_slow_freq_get();
*
* @return RTC_SLOW_CLK frequency, in Hz
*/
uint32_t rtc_clk_slow_freq_get_hz();
uint32_t rtc_clk_slow_freq_get_hz(void);
/**
* @brief Select source for RTC_FAST_CLK
@@ -302,7 +302,7 @@ void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq);
* @brief Get the RTC_FAST_CLK source
* @return currently selected clock source (one of rtc_fast_freq_t values)
*/
rtc_fast_freq_t rtc_clk_fast_freq_get();
rtc_fast_freq_t rtc_clk_fast_freq_get(void);
/**
* @brief Switch CPU frequency
@@ -355,7 +355,7 @@ void rtc_clk_cpu_freq_set_fast(rtc_cpu_freq_t cpu_freq) __attribute__((deprecate
*
* @return CPU frequency (one of rtc_cpu_freq_t values)
*/
rtc_cpu_freq_t rtc_clk_cpu_freq_get() __attribute__((deprecated));
rtc_cpu_freq_t rtc_clk_cpu_freq_get(void) __attribute__((deprecated));
/**
* @brief Get corresponding frequency value for rtc_cpu_freq_t enum value
@@ -444,7 +444,7 @@ uint32_t rtc_clk_cpu_freq_value(rtc_cpu_freq_t cpu_freq) __attribute__((depreca
* rtc_clk_cpu_freq_set_config when a switch to XTAL is needed.
* Assumes that XTAL frequency has been determined — don't call in startup code.
*/
void rtc_clk_cpu_freq_set_xtal();
void rtc_clk_cpu_freq_set_xtal(void);
/**
@@ -465,7 +465,7 @@ void rtc_clk_apb_freq_update(uint32_t apb_freq);
* @brief Get the current stored APB frequency.
* @return The APB frequency value as last set via rtc_clk_apb_freq_update(), in Hz.
*/
uint32_t rtc_clk_apb_freq_get();
uint32_t rtc_clk_apb_freq_get(void);
#define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal
@@ -522,7 +522,7 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period);
*
* @return current value of RTC counter
*/
uint64_t rtc_time_get();
uint64_t rtc_time_get(void);
/**
* @brief Busy loop until next RTC_SLOW_CLK cycle
@@ -531,7 +531,7 @@ uint64_t rtc_time_get();
* In some cases (e.g. when RTC_SLOW_CLK cycle is very close), it may return
* one RTC_SLOW_CLK cycle later.
*/
void rtc_clk_wait_for_slow_cycle();
void rtc_clk_wait_for_slow_cycle(void);
/**
* @brief sleep configuration for rtc_sleep_init function
@@ -710,7 +710,7 @@ typedef struct rtc_vddsdio_config_s {
* Otherwise, use default values and the level of MTDI bootstrapping pin.
* @return currently used VDDSDIO configuration
*/
rtc_vddsdio_config_t rtc_vddsdio_get_config();
rtc_vddsdio_config_t rtc_vddsdio_get_config(void);
/**
* Set new VDDSDIO configuration using RTC registers.