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tools: Mass fixing of empty prototypes (for -Wstrict-prototypes)

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This commit is contained in:
Anton Maklakov
2019-07-16 16:33:30 +07:00
parent 50629eec27
commit afbaf74007
507 changed files with 1295 additions and 1295 deletions
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36
components/soc/esp32/rtc_clk.c
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@@ -100,9 +100,9 @@
#define RTC_PLL_FREQ_320M 320
#define RTC_PLL_FREQ_480M 480
static void rtc_clk_cpu_freq_to_8m();
static void rtc_clk_bbpll_disable();
static void rtc_clk_bbpll_enable();
static void rtc_clk_cpu_freq_to_8m(void);
static void rtc_clk_bbpll_disable(void);
static void rtc_clk_bbpll_enable(void);
static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz);
static bool rtc_clk_cpu_freq_from_mhz_internal(int mhz, rtc_cpu_freq_t* out_val);
@@ -161,7 +161,7 @@ void rtc_clk_32k_enable(bool enable)
}
}
void rtc_clk_32k_enable_external()
void rtc_clk_32k_enable_external(void)
{
rtc_clk_32k_enable_common(XTAL_32K_EXT_DAC_VAL, XTAL_32K_EXT_DRES_VAL, XTAL_32K_EXT_DBIAS_VAL);
}
@@ -201,7 +201,7 @@ void rtc_clk_32k_bootstrap(uint32_t cycle)
XTAL_32K_BOOTSTRAP_DRES_VAL, XTAL_32K_BOOTSTRAP_DBIAS_VAL);
}
bool rtc_clk_32k_enabled()
bool rtc_clk_32k_enabled(void)
{
return GET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_XPD_XTAL_32K) != 0;
}
@@ -224,12 +224,12 @@ void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en)
}
}
bool rtc_clk_8m_enabled()
bool rtc_clk_8m_enabled(void)
{
return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0;
}
bool rtc_clk_8md256_enabled()
bool rtc_clk_8md256_enabled(void)
{
return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0;
}
@@ -284,12 +284,12 @@ void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq)
ets_delay_us(DELAY_SLOW_CLK_SWITCH);
}
rtc_slow_freq_t rtc_clk_slow_freq_get()
rtc_slow_freq_t rtc_clk_slow_freq_get(void)
{
return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL);
}
uint32_t rtc_clk_slow_freq_get_hz()
uint32_t rtc_clk_slow_freq_get_hz(void)
{
switch(rtc_clk_slow_freq_get()) {
case RTC_SLOW_FREQ_RTC: return RTC_SLOW_CLK_FREQ_150K;
@@ -305,7 +305,7 @@ void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq)
ets_delay_us(DELAY_FAST_CLK_SWITCH);
}
rtc_fast_freq_t rtc_clk_fast_freq_get()
rtc_fast_freq_t rtc_clk_fast_freq_get(void)
{
return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL);
}
@@ -435,7 +435,7 @@ void rtc_clk_cpu_freq_to_xtal(int freq, int div)
}
}
static void rtc_clk_cpu_freq_to_8m()
static void rtc_clk_cpu_freq_to_8m(void)
{
ets_update_cpu_frequency(8);
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL);
@@ -444,7 +444,7 @@ static void rtc_clk_cpu_freq_to_8m()
rtc_clk_apb_freq_update(RTC_FAST_CLK_FREQ_8M);
}
static void rtc_clk_bbpll_disable()
static void rtc_clk_bbpll_disable(void)
{
SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG,
RTC_CNTL_BB_I2C_FORCE_PD | RTC_CNTL_BBPLL_FORCE_PD |
@@ -459,7 +459,7 @@ static void rtc_clk_bbpll_disable()
}
}
static void rtc_clk_bbpll_enable()
static void rtc_clk_bbpll_enable(void)
{
CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG,
RTC_CNTL_BIAS_I2C_FORCE_PD | RTC_CNTL_BB_I2C_FORCE_PD |
@@ -516,7 +516,7 @@ void rtc_clk_cpu_freq_set_fast(rtc_cpu_freq_t cpu_freq)
rtc_clk_cpu_freq_set_config_fast(&config);
}
void rtc_clk_cpu_freq_set_xtal()
void rtc_clk_cpu_freq_set_xtal(void)
{
int freq_mhz = (int) rtc_clk_xtal_freq_get();
@@ -525,7 +525,7 @@ void rtc_clk_cpu_freq_set_xtal()
rtc_clk_bbpll_disable();
}
rtc_cpu_freq_t rtc_clk_cpu_freq_get()
rtc_cpu_freq_t rtc_clk_cpu_freq_get(void)
{
rtc_cpu_freq_config_t config;
rtc_clk_cpu_freq_get_config(&config);
@@ -766,7 +766,7 @@ void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t* config)
}
}
rtc_xtal_freq_t rtc_clk_xtal_freq_get()
rtc_xtal_freq_t rtc_clk_xtal_freq_get(void)
{
/* We may have already written XTAL value into RTC_XTAL_FREQ_REG */
uint32_t xtal_freq_reg = READ_PERI_REG(RTC_XTAL_FREQ_REG);
@@ -790,7 +790,7 @@ void rtc_clk_apb_freq_update(uint32_t apb_freq)
WRITE_PERI_REG(RTC_APB_FREQ_REG, clk_val_to_reg_val(apb_freq >> 12));
}
uint32_t rtc_clk_apb_freq_get()
uint32_t rtc_clk_apb_freq_get(void)
{
uint32_t freq_hz = reg_val_to_clk_val(READ_PERI_REG(RTC_APB_FREQ_REG)) << 12;
// round to the nearest MHz
@@ -802,4 +802,4 @@ uint32_t rtc_clk_apb_freq_get()
/* Name used in libphy.a:phy_chip_v7.o
* TODO: update the library to use rtc_clk_xtal_freq_get
*/
rtc_xtal_freq_t rtc_get_xtal() __attribute__((alias("rtc_clk_xtal_freq_get")));
rtc_xtal_freq_t rtc_get_xtal(void) __attribute__((alias("rtc_clk_xtal_freq_get")));