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Merge branch 'feat/esp32c5_sdm_support' into 'master'

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feat(sdm): add support for esp32c5

Closes IDF-8687

See merge request espressif/esp-idf!32010
This commit is contained in:
morris
2024-07-12 10:51:07 +08:00
parent 5d609daa6a a717fecf94
commit b06b483dfc
20 changed files with 148 additions and 38 deletions
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20
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
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@@ -75,6 +75,10 @@ config SOC_RMT_SUPPORTED
bool
default y
config SOC_SDM_SUPPORTED
bool
default y
config SOC_GPSPI_SUPPORTED
bool
default y
@@ -723,6 +727,22 @@ config SOC_ECDSA_SUPPORT_EXPORT_PUBKEY
bool
default y
config SOC_SDM_GROUPS
int
default 1
config SOC_SDM_CHANNELS_PER_GROUP
int
default 4
config SOC_SDM_CLK_SUPPORT_PLL_F80M
bool
default y
config SOC_SDM_CLK_SUPPORT_XTAL
bool
default y
config SOC_SPI_PERIPH_NUM
int
default 2

2
components/soc/esp32c5/include/soc/clk_tree_defs.h
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@@ -385,7 +385,7 @@ typedef enum {
/**
* @brief Sigma Delta Modulator clock source
*/
typedef enum { // TODO: [ESP32C5] IDF-8687 (inherit from C6)
typedef enum {
SDM_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL clock as the source clock */
SDM_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */
SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the default clock choice */

6
components/soc/esp32c5/include/soc/gpio_ext_reg.h
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@@ -57,7 +57,7 @@ extern "C" {
#define GPIO_EXT_SD0_PRESCALE_S 8
/** GPIO_EXT_SIGMADELTA1_REG register
* Duty cycle configuration register for SDM channel 0
* Duty cycle configuration register for SDM channel 1
*/
#define GPIO_EXT_SIGMADELTA1_REG (DR_REG_GPIO_EXT_BASE + 0xc)
/** GPIO_EXT_SD1_IN : R/W; bitpos: [7:0]; default: 0;
@@ -76,7 +76,7 @@ extern "C" {
#define GPIO_EXT_SD1_PRESCALE_S 8
/** GPIO_EXT_SIGMADELTA2_REG register
* Duty cycle configuration register for SDM channel 0
* Duty cycle configuration register for SDM channel 2
*/
#define GPIO_EXT_SIGMADELTA2_REG (DR_REG_GPIO_EXT_BASE + 0x10)
/** GPIO_EXT_SD2_IN : R/W; bitpos: [7:0]; default: 0;
@@ -95,7 +95,7 @@ extern "C" {
#define GPIO_EXT_SD2_PRESCALE_S 8
/** GPIO_EXT_SIGMADELTA3_REG register
* Duty cycle configuration register for SDM channel 0
* Duty cycle configuration register for SDM channel 3
*/
#define GPIO_EXT_SIGMADELTA3_REG (DR_REG_GPIO_EXT_BASE + 0x14)
/** GPIO_EXT_SD3_IN : R/W; bitpos: [7:0]; default: 0;

10
components/soc/esp32c5/include/soc/gpio_ext_struct.h
View File

@@ -1067,11 +1067,14 @@ typedef union {
uint32_t val;
} gpio_ext_version_reg_t;
typedef struct gpio_sd_dev_t {
volatile gpio_ext_clock_gate_reg_t clock_gate;
volatile gpio_ext_sigmadelta_misc_reg_t misc;
volatile gpio_ext_sigmadeltan_reg_t channel[4];
} gpio_sd_dev_t;
typedef struct {
volatile gpio_ext_clock_gate_reg_t clock_gate;
volatile gpio_ext_sigmadelta_misc_reg_t sigmadelta_misc;
volatile gpio_ext_sigmadeltan_reg_t sigmadeltan[4];
volatile gpio_sd_dev_t sigma_delta;
uint32_t reserved_018[16];
volatile gpio_ext_pad_comp_config_0_reg_t pad_comp_config_0;
volatile gpio_ext_pad_comp_filter_0_reg_t pad_comp_filter_0;
@@ -1096,6 +1099,7 @@ typedef struct {
volatile gpio_ext_version_reg_t version;
} gpio_ext_dev_t;
extern gpio_sd_dev_t SDM;
extern gpio_ext_dev_t GPIO_EXT;
#ifndef __cplusplus

1
components/soc/esp32c5/include/soc/reg_base.h
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@@ -57,6 +57,7 @@
*/
#define DR_REG_IO_MUX_BASE 0x60090000
#define DR_REG_GPIO_BASE 0x60091000
#define DR_REG_GPIO_EXT_BASE 0x60091e00
#define DR_REG_MEM_MONITOR_BASE 0x60092000
#define DR_REG_PAU_BASE 0x60093000
#define DR_REG_HP_SYSTEM_BASE 0x60095000

10
components/soc/esp32c5/include/soc/soc_caps.h
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@@ -41,7 +41,7 @@
#define SOC_RTC_MEM_SUPPORTED 1
#define SOC_I2S_SUPPORTED 1
#define SOC_RMT_SUPPORTED 1
// #define SOC_SDM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8687
#define SOC_SDM_SUPPORTED 1
#define SOC_GPSPI_SUPPORTED 1
#define SOC_LEDC_SUPPORTED 1
#define SOC_I2C_SUPPORTED 1
@@ -388,10 +388,10 @@
#define SOC_ECDSA_SUPPORT_EXPORT_PUBKEY (1)
/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
// #define SOC_SDM_GROUPS 1U
// #define SOC_SDM_CHANNELS_PER_GROUP 4
// #define SOC_SDM_CLK_SUPPORT_PLL_F80M 1
// #define SOC_SDM_CLK_SUPPORT_XTAL 1
#define SOC_SDM_GROUPS 1U
#define SOC_SDM_CHANNELS_PER_GROUP 4
#define SOC_SDM_CLK_SUPPORT_PLL_F80M 1
#define SOC_SDM_CLK_SUPPORT_XTAL 1
/*-------------------------- SPI CAPS ----------------------------------------*/
#define SOC_SPI_PERIPH_NUM 2