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feat(i2c): Add i2c support on esp32c5 mp

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C.S.M
2024-06-17 17:13:16 +08:00
parent 0479494e7a
commit b0f2205f70
19 changed files with 161 additions and 225 deletions
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26
components/soc/esp32c5/include/soc/soc_caps.h
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@@ -43,7 +43,7 @@
// #define SOC_SDM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8687
#define SOC_GPSPI_SUPPORTED 1
#define SOC_LEDC_SUPPORTED 1
// #define SOC_I2C_SUPPORTED 1 // TODO: [ESP32C5] IDF-8694, IDF-8696
#define SOC_I2C_SUPPORTED 1
#define SOC_SYSTIMER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8707
#define SOC_AES_SUPPORTED 1
#define SOC_MPI_SUPPORTED 1
@@ -235,20 +235,18 @@
#define SOC_I2C_NUM (1U)
#define SOC_HP_I2C_NUM (1U)
// #define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */
// #define SOC_I2C_CMD_REG_NUM (8) /*!< Number of I2C command registers */
// #define SOC_I2C_SUPPORT_SLAVE (1)
#define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */
#define SOC_I2C_CMD_REG_NUM (8) /*!< Number of I2C command registers */
#define SOC_I2C_SUPPORT_SLAVE (1)
// FSM_RST only resets the FSM, not using it. So SOC_I2C_SUPPORT_HW_FSM_RST not defined.
// #define SOC_I2C_SUPPORT_HW_CLR_BUS (1)
// #define SOC_I2C_SUPPORT_XTAL (1)
// #define SOC_I2C_SUPPORT_RTC (1)
// #define SOC_I2C_SUPPORT_10BIT_ADDR (1)
// #define SOC_I2C_SLAVE_SUPPORT_BROADCAST (1)
// #define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE (1)
// #define SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS (1)
// #define SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH (1)
#define SOC_I2C_SUPPORT_HW_FSM_RST (1)
#define SOC_I2C_SUPPORT_XTAL (1)
#define SOC_I2C_SUPPORT_RTC (1)
#define SOC_I2C_SUPPORT_10BIT_ADDR (1)
#define SOC_I2C_SLAVE_SUPPORT_BROADCAST (1)
#define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE (1)
#define SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS (1)
#define SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH (1)
// #define SOC_I2C_SUPPORT_SLEEP_RETENTION (1) // TODO: IDF-9693