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feat(system): add option to allow user disable USJ module to save power
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -29,6 +29,19 @@ static inline void usb_fsls_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
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hw->conf0.usb_pad_enable = 1;
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}
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/**
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* @brief Disable the internal PHY for USB_Serial_JTAG
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*
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* @param hw Start address of the USB Serial_JTAG registers
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*/
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static inline void usb_fsls_phy_ll_int_jtag_disable(usb_serial_jtag_dev_t *hw)
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{
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// Disable USB D+ pullup
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hw->conf0.dp_pullup = 0;
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// Disable USB pad function
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hw->conf0.usb_pad_enable = 0;
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}
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#ifdef __cplusplus
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}
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#endif
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@@ -206,13 +206,13 @@ FORCE_INLINE_ATTR void usb_serial_jtag_ll_enable_pad(bool enable_pad)
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* @brief Enable the bus clock for USB Serial_JTAG module
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* @param clk_en True if enable the clock of USB Serial_JTAG module
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*/
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FORCE_INLINE_ATTR void usb_serial_jtag_ll_enable_bus_clock(bool clk_en)
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FORCE_INLINE_ATTR void _usb_serial_jtag_ll_enable_bus_clock(bool clk_en)
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{
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SYSTEM.perip_clk_en0.reg_usb_device_clk_en = clk_en;
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}
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// SYSTEM.perip_clk_enx are shared registers, so this function must be used in an atomic way
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#define usb_serial_jtag_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; usb_serial_jtag_ll_enable_bus_clock(__VA_ARGS__)
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#define usb_serial_jtag_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _usb_serial_jtag_ll_enable_bus_clock(__VA_ARGS__)
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/**
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* @brief Reset the usb serial jtag module
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