mirror of
https://github.com/espressif/esp-idf.git
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feat(volt): chip auto adjust volt for esp32c6 & esp32h2
This commit is contained in:
@@ -179,6 +179,10 @@ config SOC_PMU_SUPPORTED
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bool
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default y
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config SOC_PMU_PVT_SUPPORTED
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bool
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default y
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config SOC_PAU_SUPPORTED
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bool
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default y
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876
components/soc/esp32c6/include/soc/pvt_reg.h
Normal file
876
components/soc/esp32c6/include/soc/pvt_reg.h
Normal file
@@ -0,0 +1,876 @@
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/**
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define PVT_PMUP_BITMAP_HIGH0_REG (DR_REG_PVT_MONITOR_BASE + 0x0000)
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#define PVT_PUMP_BITMAP_HIGH0 0xFFFFFFFF
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#define PVT_PUMP_BITMAP_HIGH0_S 0
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#define PVT_PMUP_BITMAP_HIGH1_REG (DR_REG_PVT_MONITOR_BASE + 0x0004)
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#define PVT_PUMP_BITMAP_HIGH1 0xFFFFFFFF
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#define PVT_PUMP_BITMAP_HIGH1_S 0
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#define PVT_PMUP_BITMAP_HIGH2_REG (DR_REG_PVT_MONITOR_BASE + 0x0008)
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#define PVT_PUMP_BITMAP_HIGH2 0xFFFFFFFF
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#define PVT_PUMP_BITMAP_HIGH2_S 0
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#define PVT_PMUP_BITMAP_HIGH3_REG (DR_REG_PVT_MONITOR_BASE + 0x000C)
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#define PVT_PUMP_BITMAP_HIGH3 0xFFFFFFFF
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#define PVT_PUMP_BITMAP_HIGH3_S 0
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#define PVT_PMUP_BITMAP_HIGH4_REG (DR_REG_PVT_MONITOR_BASE + 0x0010)
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#define PVT_PUMP_BITMAP_HIGH4 0xFFFFFFFF
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#define PVT_PUMP_BITMAP_HIGH4_S 0
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#define PVT_PMUP_BITMAP_LOW0_REG (DR_REG_PVT_MONITOR_BASE + 0x0014)
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#define PVT_PUMP_BITMAP_LOW0 0xFFFFFFFF
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#define PVT_PUMP_BITMAP_LOW0_S 0
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#define PVT_PMUP_BITMAP_LOW1_REG (DR_REG_PVT_MONITOR_BASE + 0x0018)
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#define PVT_PUMP_BITMAP_LOW1 0xFFFFFFFF
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#define PVT_PUMP_BITMAP_LOW1_S 0
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#define PVT_PMUP_BITMAP_LOW2_REG (DR_REG_PVT_MONITOR_BASE + 0x001C)
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#define PVT_PUMP_BITMAP_LOW2 0xFFFFFFFF
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#define PVT_PUMP_BITMAP_LOW2_S 0
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#define PVT_PMUP_BITMAP_LOW3_REG (DR_REG_PVT_MONITOR_BASE + 0x0020)
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#define PVT_PUMP_BITMAP_LOW3 0xFFFFFFFF
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#define PVT_PUMP_BITMAP_LOW3_S 0
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#define PVT_PMUP_BITMAP_LOW4_REG (DR_REG_PVT_MONITOR_BASE + 0x0024)
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#define PVT_PUMP_BITMAP_LOW4 0xFFFFFFFF
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#define PVT_PUMP_BITMAP_LOW4_S 0
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#define PVT_PMUP_DRV_CFG_REG (DR_REG_PVT_MONITOR_BASE + 0x0028)
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#define PVT_PUMP_DRV0 0x0000000F
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#define PVT_PUMP_DRV0_S 27
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#define PVT_PUMP_DRV1 0x0000000F
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#define PVT_PUMP_DRV1_S 23
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#define PVT_PUMP_DRV2 0x0000000F
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#define PVT_PUMP_DRV2_S 19
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#define PVT_PUMP_DRV3 0x0000000F
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#define PVT_PUMP_DRV3_S 15
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#define PVT_PUMP_DRV4 0x0000000F
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#define PVT_PUMP_DRV4_S 11
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#define PVT_CLK_EN (BIT(10))
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#define PVT_CLK_EN_S 10
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#define PVT_PUMP_EN (BIT(9))
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#define PVT_PUMP_EN_S 9
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#define PVT_PMUP_CHANNEL_CFG_REG (DR_REG_PVT_MONITOR_BASE + 0x002C)
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#define PVT_PUMP_CHANNEL_CODE0 0x0000001F
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#define PVT_PUMP_CHANNEL_CODE0_S 27
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#define PVT_PUMP_CHANNEL_CODE1 0x0000001F
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#define PVT_PUMP_CHANNEL_CODE1_S 22
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#define PVT_PUMP_CHANNEL_CODE2 0x0000001F
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#define PVT_PUMP_CHANNEL_CODE2_S 17
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#define PVT_PUMP_CHANNEL_CODE3 0x0000001F
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#define PVT_PUMP_CHANNEL_CODE3_S 12
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#define PVT_PUMP_CHANNEL_CODE4 0x0000001F
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#define PVT_PUMP_CHANNEL_CODE4_S 7
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#define PVT_CLK_CFG_REG (DR_REG_PVT_MONITOR_BASE + 0x0030)
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#define PVT_CLK_SEL (BIT(31))
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#define PVT_CLK_SEL_S 31
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#define PVT_MONITOR_CLK_PVT_EN (BIT(8))
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#define PVT_MONITOR_CLK_PVT_EN_S 8
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#define PVT_PUMP_CLK_DIV_NUM 0x000000FF
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#define PVT_PUMP_CLK_DIV_NUM_S 0
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#define PVT_DBIAS_CHANNEL_SEL0_REG (DR_REG_PVT_MONITOR_BASE + 0x0034)
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#define PVT_DBIAS_CHANNEL0_SEL 0x0000007F
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#define PVT_DBIAS_CHANNEL0_SEL_S 25
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#define PVT_DBIAS_CHANNEL1_SEL 0x0000007F
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#define PVT_DBIAS_CHANNEL1_SEL_S 18
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#define PVT_DBIAS_CHANNEL2_SEL 0x0000007F
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#define PVT_DBIAS_CHANNEL2_SEL_S 11
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#define PVT_DBIAS_CHANNEL3_SEL 0x0000007F
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#define PVT_DBIAS_CHANNEL3_SEL_S 4
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#define PVT_DBIAS_CHANNEL_SEL1_REG (DR_REG_PVT_MONITOR_BASE + 0x0038)
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#define PVT_DBIAS_CHANNEL4_SEL 0x0000007F
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#define PVT_DBIAS_CHANNEL4_SEL_S 25
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#define PVT_DBIAS_CHANNEL0_SEL_REG (DR_REG_PVT_MONITOR_BASE + 0x003C)
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#define PVT_DBIAS_CHANNEL0_CFG 0x0001FFFF
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#define PVT_DBIAS_CHANNEL0_CFG_S 0
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#define PVT_DBIAS_CHANNEL1_SEL_REG (DR_REG_PVT_MONITOR_BASE + 0x0040)
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#define PVT_DBIAS_CHANNEL1_CFG 0x0001FFFF
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#define PVT_DBIAS_CHANNEL1_CFG_S 0
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#define PVT_DBIAS_CHANNEL2_SEL_REG (DR_REG_PVT_MONITOR_BASE + 0x0044)
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#define PVT_DBIAS_CHANNEL2_CFG 0x0001FFFF
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#define PVT_DBIAS_CHANNEL2_CFG_S 0
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#define PVT_DBIAS_CHANNEL3_SEL_REG (DR_REG_PVT_MONITOR_BASE + 0x0048)
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#define PVT_DBIAS_CHANNEL3_CFG 0x0001FFFF
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#define PVT_DBIAS_CHANNEL3_CFG_S 0
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#define PVT_DBIAS_CHANNEL4_SEL_REG (DR_REG_PVT_MONITOR_BASE + 0x004C)
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#define PVT_DBIAS_CHANNEL4_CFG 0x0001FFFF
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#define PVT_DBIAS_CHANNEL4_CFG_S 0
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#define PVT_DBIAS_CMD0_REG (DR_REG_PVT_MONITOR_BASE + 0x0050)
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#define PVT_DBIAS_CMD0 0x0001FFFF
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#define PVT_DBIAS_CMD0_S 0
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#define PVT_DBIAS_CMD1_REG (DR_REG_PVT_MONITOR_BASE + 0x0054)
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#define PVT_DBIAS_CMD1 0x0001FFFF
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#define PVT_DBIAS_CMD1_S 0
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#define PVT_DBIAS_CMD2_REG (DR_REG_PVT_MONITOR_BASE + 0x0058)
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#define PVT_DBIAS_CMD2 0x0001FFFF
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#define PVT_DBIAS_CMD2_S 0
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#define PVT_DBIAS_CMD3_REG (DR_REG_PVT_MONITOR_BASE + 0x005C)
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#define PVT_DBIAS_CMD3 0x0001FFFF
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#define PVT_DBIAS_CMD3_S 0
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#define PVT_DBIAS_CMD4_REG (DR_REG_PVT_MONITOR_BASE + 0x0060)
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#define PVT_DBIAS_CMD4 0x0001FFFF
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#define PVT_DBIAS_CMD4_S 0
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#define PVT_DBIAS_TIMER_REG (DR_REG_PVT_MONITOR_BASE + 0x0064)
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#define PVT_TIMER_EN (BIT(31))
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#define PVT_TIMER_EN_S 31
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#define PVT_TIMER_TARGET 0x0000FFFF
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#define PVT_TIMER_TARGET_S 15
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#define PVT_COMB_PD_SITE0_UNIT0_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x0068)
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#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT0 (BIT(31))
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#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT0_S 31
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#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT0 0x000000FF
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#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT0_S 23
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#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT0 0x000000FF
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#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT0_S 2
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#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0 (BIT(1))
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#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT0_S 1
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#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT0 (BIT(0))
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#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT0_S 0
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#define PVT_COMB_PD_SITE0_UNIT1_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x006C)
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#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT1 (BIT(31))
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#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT1_S 31
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#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT1 0x000000FF
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#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT1_S 23
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#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT1 0x000000FF
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#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT1_S 2
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#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1 (BIT(1))
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#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT1_S 1
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#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT1 (BIT(0))
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#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT1_S 0
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#define PVT_COMB_PD_SITE0_UNIT2_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x0070)
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#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT2 (BIT(31))
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#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT2_S 31
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#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT2 0x000000FF
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#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT2_S 23
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#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT2 0x000000FF
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#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT2_S 2
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#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2 (BIT(1))
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#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT2_S 1
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#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT2 (BIT(0))
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#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT2_S 0
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#define PVT_COMB_PD_SITE0_UNIT3_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x0074)
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#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT3 (BIT(31))
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#define PVT_TIMING_ERR_VT0_PD_SITE0_UNIT3_S 31
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#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT3 0x000000FF
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#define PVT_DELAY_NUM_O_VT0_PD_SITE0_UNIT3_S 23
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#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT3 0x000000FF
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#define PVT_DELAY_LIMIT_VT0_PD_SITE0_UNIT3_S 2
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#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3 (BIT(1))
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#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE0_UNIT3_S 1
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#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT3 (BIT(0))
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#define PVT_MONITOR_EN_VT0_PD_SITE0_UNIT3_S 0
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#define PVT_COMB_PD_SITE0_UNIT0_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x0078)
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#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT0 (BIT(31))
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#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT0_S 31
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#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT0 0x000000FF
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#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT0_S 23
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#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT0 0x000000FF
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#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT0_S 2
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#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0 (BIT(1))
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#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT0_S 1
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#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT0 (BIT(0))
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#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT0_S 0
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#define PVT_COMB_PD_SITE0_UNIT1_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x007C)
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#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT1 (BIT(31))
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#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT1_S 31
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#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT1 0x000000FF
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#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT1_S 23
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#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT1 0x000000FF
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#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT1_S 2
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#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1 (BIT(1))
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#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT1_S 1
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#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT1 (BIT(0))
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#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT1_S 0
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#define PVT_COMB_PD_SITE0_UNIT2_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x0080)
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#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT2 (BIT(31))
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#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT2_S 31
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#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT2 0x000000FF
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#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT2_S 23
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#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT2 0x000000FF
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#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT2_S 2
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#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2 (BIT(1))
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#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT2_S 1
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#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT2 (BIT(0))
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#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT2_S 0
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#define PVT_COMB_PD_SITE0_UNIT3_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x0084)
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#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT3 (BIT(31))
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#define PVT_TIMING_ERR_VT1_PD_SITE0_UNIT3_S 31
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#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT3 0x000000FF
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#define PVT_DELAY_NUM_O_VT1_PD_SITE0_UNIT3_S 23
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#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT3 0x000000FF
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#define PVT_DELAY_LIMIT_VT1_PD_SITE0_UNIT3_S 2
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#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3 (BIT(1))
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#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE0_UNIT3_S 1
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#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT3 (BIT(0))
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#define PVT_MONITOR_EN_VT1_PD_SITE0_UNIT3_S 0
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#define PVT_COMB_PD_SITE0_UNIT0_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x0088)
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#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT0 (BIT(31))
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#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT0_S 31
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#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT0 0x000000FF
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#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT0_S 23
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#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT0 0x000000FF
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#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT0_S 2
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#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0 (BIT(1))
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#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT0_S 1
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#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT0 (BIT(0))
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#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT0_S 0
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#define PVT_COMB_PD_SITE0_UNIT1_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x008C)
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#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT1 (BIT(31))
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#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT1_S 31
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#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT1 0x000000FF
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#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT1_S 23
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#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT1 0x000000FF
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#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT1_S 2
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#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1 (BIT(1))
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#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT1_S 1
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#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT1 (BIT(0))
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#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT1_S 0
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#define PVT_COMB_PD_SITE0_UNIT2_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x0090)
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#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT2 (BIT(31))
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#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT2_S 31
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#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT2 0x000000FF
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#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT2_S 23
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#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT2 0x000000FF
|
||||
#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT2_S 2
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2 (BIT(1))
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT2_S 1
|
||||
#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT2 (BIT(0))
|
||||
#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT2_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE0_UNIT3_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x0094)
|
||||
#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT3 (BIT(31))
|
||||
#define PVT_TIMING_ERR_VT2_PD_SITE0_UNIT3_S 31
|
||||
#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT3 0x000000FF
|
||||
#define PVT_DELAY_NUM_O_VT2_PD_SITE0_UNIT3_S 23
|
||||
#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT3 0x000000FF
|
||||
#define PVT_DELAY_LIMIT_VT2_PD_SITE0_UNIT3_S 2
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3 (BIT(1))
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE0_UNIT3_S 1
|
||||
#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT3 (BIT(0))
|
||||
#define PVT_MONITOR_EN_VT2_PD_SITE0_UNIT3_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE1_UNIT0_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x0098)
|
||||
#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT0 (BIT(31))
|
||||
#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT0_S 31
|
||||
#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT0 0x000000FF
|
||||
#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT0_S 23
|
||||
#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT0 0x000000FF
|
||||
#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT0_S 2
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0 (BIT(1))
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT0_S 1
|
||||
#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT0 (BIT(0))
|
||||
#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT0_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE1_UNIT1_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x009C)
|
||||
#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT1 (BIT(31))
|
||||
#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT1_S 31
|
||||
#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT1 0x000000FF
|
||||
#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT1_S 23
|
||||
#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT1 0x000000FF
|
||||
#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT1_S 2
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1 (BIT(1))
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT1_S 1
|
||||
#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT1 (BIT(0))
|
||||
#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT1_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE1_UNIT2_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00A0)
|
||||
#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT2 (BIT(31))
|
||||
#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT2_S 31
|
||||
#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT2 0x000000FF
|
||||
#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT2_S 23
|
||||
#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT2 0x000000FF
|
||||
#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT2_S 2
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2 (BIT(1))
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT2_S 1
|
||||
#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT2 (BIT(0))
|
||||
#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT2_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE1_UNIT3_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00A4)
|
||||
#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT3 (BIT(31))
|
||||
#define PVT_TIMING_ERR_VT0_PD_SITE1_UNIT3_S 31
|
||||
#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT3 0x000000FF
|
||||
#define PVT_DELAY_NUM_O_VT0_PD_SITE1_UNIT3_S 23
|
||||
#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT3 0x000000FF
|
||||
#define PVT_DELAY_LIMIT_VT0_PD_SITE1_UNIT3_S 2
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3 (BIT(1))
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE1_UNIT3_S 1
|
||||
#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT3 (BIT(0))
|
||||
#define PVT_MONITOR_EN_VT0_PD_SITE1_UNIT3_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE1_UNIT0_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00A8)
|
||||
#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT0 (BIT(31))
|
||||
#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT0_S 31
|
||||
#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT0 0x000000FF
|
||||
#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT0_S 23
|
||||
#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT0 0x000000FF
|
||||
#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT0_S 2
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0 (BIT(1))
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT0_S 1
|
||||
#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT0 (BIT(0))
|
||||
#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT0_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE1_UNIT1_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00AC)
|
||||
#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT1 (BIT(31))
|
||||
#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT1_S 31
|
||||
#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT1 0x000000FF
|
||||
#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT1_S 23
|
||||
#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT1 0x000000FF
|
||||
#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT1_S 2
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1 (BIT(1))
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT1_S 1
|
||||
#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT1 (BIT(0))
|
||||
#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT1_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE1_UNIT2_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00B0)
|
||||
#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT2 (BIT(31))
|
||||
#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT2_S 31
|
||||
#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT2 0x000000FF
|
||||
#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT2_S 23
|
||||
#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT2 0x000000FF
|
||||
#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT2_S 2
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2 (BIT(1))
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT2_S 1
|
||||
#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT2 (BIT(0))
|
||||
#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT2_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE1_UNIT3_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00B4)
|
||||
#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT3 (BIT(31))
|
||||
#define PVT_TIMING_ERR_VT1_PD_SITE1_UNIT3_S 31
|
||||
#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT3 0x000000FF
|
||||
#define PVT_DELAY_NUM_O_VT1_PD_SITE1_UNIT3_S 23
|
||||
#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT3 0x000000FF
|
||||
#define PVT_DELAY_LIMIT_VT1_PD_SITE1_UNIT3_S 2
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3 (BIT(1))
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE1_UNIT3_S 1
|
||||
#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT3 (BIT(0))
|
||||
#define PVT_MONITOR_EN_VT1_PD_SITE1_UNIT3_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE1_UNIT0_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00B8)
|
||||
#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT0 (BIT(31))
|
||||
#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT0_S 31
|
||||
#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT0 0x000000FF
|
||||
#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT0_S 23
|
||||
#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT0 0x000000FF
|
||||
#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT0_S 2
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0 (BIT(1))
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT0_S 1
|
||||
#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT0 (BIT(0))
|
||||
#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT0_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE1_UNIT1_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00BC)
|
||||
#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT1 (BIT(31))
|
||||
#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT1_S 31
|
||||
#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT1 0x000000FF
|
||||
#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT1_S 23
|
||||
#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT1 0x000000FF
|
||||
#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT1_S 2
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1 (BIT(1))
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT1_S 1
|
||||
#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT1 (BIT(0))
|
||||
#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT1_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE1_UNIT2_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00C0)
|
||||
#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT2 (BIT(31))
|
||||
#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT2_S 31
|
||||
#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT2 0x000000FF
|
||||
#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT2_S 23
|
||||
#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT2 0x000000FF
|
||||
#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT2_S 2
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2 (BIT(1))
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT2_S 1
|
||||
#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT2 (BIT(0))
|
||||
#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT2_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE1_UNIT3_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00C4)
|
||||
#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT3 (BIT(31))
|
||||
#define PVT_TIMING_ERR_VT2_PD_SITE1_UNIT3_S 31
|
||||
#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT3 0x000000FF
|
||||
#define PVT_DELAY_NUM_O_VT2_PD_SITE1_UNIT3_S 23
|
||||
#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT3 0x000000FF
|
||||
#define PVT_DELAY_LIMIT_VT2_PD_SITE1_UNIT3_S 2
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3 (BIT(1))
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE1_UNIT3_S 1
|
||||
#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT3 (BIT(0))
|
||||
#define PVT_MONITOR_EN_VT2_PD_SITE1_UNIT3_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE2_UNIT0_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00C8)
|
||||
#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT0 (BIT(31))
|
||||
#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT0_S 31
|
||||
#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT0 0x000000FF
|
||||
#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT0_S 23
|
||||
#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT0 0x000000FF
|
||||
#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT0_S 2
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0 (BIT(1))
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT0_S 1
|
||||
#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT0 (BIT(0))
|
||||
#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT0_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE2_UNIT1_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00CC)
|
||||
#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT1 (BIT(31))
|
||||
#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT1_S 31
|
||||
#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT1 0x000000FF
|
||||
#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT1_S 23
|
||||
#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT1 0x000000FF
|
||||
#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT1_S 2
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1 (BIT(1))
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT1_S 1
|
||||
#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT1 (BIT(0))
|
||||
#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT1_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE2_UNIT2_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00D0)
|
||||
#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT2 (BIT(31))
|
||||
#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT2_S 31
|
||||
#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT2 0x000000FF
|
||||
#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT2_S 23
|
||||
#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT2 0x000000FF
|
||||
#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT2_S 2
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2 (BIT(1))
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT2_S 1
|
||||
#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT2 (BIT(0))
|
||||
#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT2_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE2_UNIT3_VT0_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00D4)
|
||||
#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT3 (BIT(31))
|
||||
#define PVT_TIMING_ERR_VT0_PD_SITE2_UNIT3_S 31
|
||||
#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT3 0x000000FF
|
||||
#define PVT_DELAY_NUM_O_VT0_PD_SITE2_UNIT3_S 23
|
||||
#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT3 0x000000FF
|
||||
#define PVT_DELAY_LIMIT_VT0_PD_SITE2_UNIT3_S 2
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3 (BIT(1))
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT0_PD_SITE2_UNIT3_S 1
|
||||
#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT3 (BIT(0))
|
||||
#define PVT_MONITOR_EN_VT0_PD_SITE2_UNIT3_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE2_UNIT0_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00D8)
|
||||
#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT0 (BIT(31))
|
||||
#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT0_S 31
|
||||
#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT0 0x000000FF
|
||||
#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT0_S 23
|
||||
#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT0 0x000000FF
|
||||
#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT0_S 2
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0 (BIT(1))
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT0_S 1
|
||||
#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT0 (BIT(0))
|
||||
#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT0_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE2_UNIT1_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00DC)
|
||||
#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT1 (BIT(31))
|
||||
#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT1_S 31
|
||||
#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT1 0x000000FF
|
||||
#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT1_S 23
|
||||
#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT1 0x000000FF
|
||||
#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT1_S 2
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1 (BIT(1))
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT1_S 1
|
||||
#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT1 (BIT(0))
|
||||
#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT1_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE2_UNIT2_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00E0)
|
||||
#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT2 (BIT(31))
|
||||
#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT2_S 31
|
||||
#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT2 0x000000FF
|
||||
#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT2_S 23
|
||||
#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT2 0x000000FF
|
||||
#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT2_S 2
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2 (BIT(1))
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT2_S 1
|
||||
#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT2 (BIT(0))
|
||||
#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT2_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE2_UNIT3_VT1_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00E4)
|
||||
#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT3 (BIT(31))
|
||||
#define PVT_TIMING_ERR_VT1_PD_SITE2_UNIT3_S 31
|
||||
#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT3 0x000000FF
|
||||
#define PVT_DELAY_NUM_O_VT1_PD_SITE2_UNIT3_S 23
|
||||
#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT3 0x000000FF
|
||||
#define PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT3_S 2
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3 (BIT(1))
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT1_PD_SITE2_UNIT3_S 1
|
||||
#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT3 (BIT(0))
|
||||
#define PVT_MONITOR_EN_VT1_PD_SITE2_UNIT3_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE2_UNIT0_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00E8)
|
||||
#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT0 (BIT(31))
|
||||
#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT0_S 31
|
||||
#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT0 0x000000FF
|
||||
#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT0_S 23
|
||||
#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0 0x000000FF
|
||||
#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT0_S 2
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0 (BIT(1))
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT0_S 1
|
||||
#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT0 (BIT(0))
|
||||
#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT0_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE2_UNIT1_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00EC)
|
||||
#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT1 (BIT(31))
|
||||
#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT1_S 31
|
||||
#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT1 0x000000FF
|
||||
#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT1_S 23
|
||||
#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1 0x000000FF
|
||||
#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT1_S 2
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1 (BIT(1))
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT1_S 1
|
||||
#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT1 (BIT(0))
|
||||
#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT1_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE2_UNIT2_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00F0)
|
||||
#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT2 (BIT(31))
|
||||
#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT2_S 31
|
||||
#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT2 0x000000FF
|
||||
#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT2_S 23
|
||||
#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2 0x000000FF
|
||||
#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT2_S 2
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2 (BIT(1))
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT2_S 1
|
||||
#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT2 (BIT(0))
|
||||
#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT2_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE2_UNIT3_VT2_CONF1_REG (DR_REG_PVT_MONITOR_BASE + 0x00F4)
|
||||
#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT3 (BIT(31))
|
||||
#define PVT_TIMING_ERR_VT2_PD_SITE2_UNIT3_S 31
|
||||
#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT3 0x000000FF
|
||||
#define PVT_DELAY_NUM_O_VT2_PD_SITE2_UNIT3_S 23
|
||||
#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT3 0x000000FF
|
||||
#define PVT_DELAY_LIMIT_VT2_PD_SITE2_UNIT3_S 2
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3 (BIT(1))
|
||||
#define PVT_TIMING_ERR_CNT_CLR_VT2_PD_SITE2_UNIT3_S 1
|
||||
#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT3 (BIT(0))
|
||||
#define PVT_MONITOR_EN_VT2_PD_SITE2_UNIT3_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE0_UNIT0_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x00F8)
|
||||
#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0 0x0000FFFF
|
||||
#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT0_S 16
|
||||
#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT0 (BIT(15))
|
||||
#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT0_S 15
|
||||
#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0 0x00000003
|
||||
#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT0_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE0_UNIT1_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x00FC)
|
||||
#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1 0x0000FFFF
|
||||
#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT1_S 16
|
||||
#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT1 (BIT(15))
|
||||
#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT1_S 15
|
||||
#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1 0x00000003
|
||||
#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT1_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE0_UNIT2_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0100)
|
||||
#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2 0x0000FFFF
|
||||
#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT2_S 16
|
||||
#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT2 (BIT(15))
|
||||
#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT2_S 15
|
||||
#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2 0x00000003
|
||||
#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT2_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE0_UNIT3_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0104)
|
||||
#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3 0x0000FFFF
|
||||
#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE0_UNIT3_S 16
|
||||
#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT3 (BIT(15))
|
||||
#define PVT_DELAY_OVF_VT0_PD_SITE0_UNIT3_S 15
|
||||
#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3 0x00000003
|
||||
#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE0_UNIT3_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE0_UNIT0_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0108)
|
||||
#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0 0x0000FFFF
|
||||
#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT0_S 16
|
||||
#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT0 (BIT(15))
|
||||
#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT0_S 15
|
||||
#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0 0x00000003
|
||||
#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT0_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE0_UNIT1_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x010C)
|
||||
#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1 0x0000FFFF
|
||||
#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT1_S 16
|
||||
#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT1 (BIT(15))
|
||||
#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT1_S 15
|
||||
#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1 0x00000003
|
||||
#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT1_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE0_UNIT2_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0110)
|
||||
#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2 0x0000FFFF
|
||||
#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT2_S 16
|
||||
#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT2 (BIT(15))
|
||||
#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT2_S 15
|
||||
#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2 0x00000003
|
||||
#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT2_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE0_UNIT3_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0114)
|
||||
#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3 0x0000FFFF
|
||||
#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE0_UNIT3_S 16
|
||||
#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT3 (BIT(15))
|
||||
#define PVT_DELAY_OVF_VT1_PD_SITE0_UNIT3_S 15
|
||||
#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3 0x00000003
|
||||
#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE0_UNIT3_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE0_UNIT0_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0118)
|
||||
#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0 0x0000FFFF
|
||||
#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT0_S 16
|
||||
#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT0 (BIT(15))
|
||||
#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT0_S 15
|
||||
#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0 0x00000003
|
||||
#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT0_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE0_UNIT1_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x011C)
|
||||
#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1 0x0000FFFF
|
||||
#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT1_S 16
|
||||
#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT1 (BIT(15))
|
||||
#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT1_S 15
|
||||
#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1 0x00000003
|
||||
#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT1_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE0_UNIT2_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0120)
|
||||
#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2 0x0000FFFF
|
||||
#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT2_S 16
|
||||
#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT2 (BIT(15))
|
||||
#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT2_S 15
|
||||
#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2 0x00000003
|
||||
#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT2_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE0_UNIT3_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0124)
|
||||
#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3 0x0000FFFF
|
||||
#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE0_UNIT3_S 16
|
||||
#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT3 (BIT(15))
|
||||
#define PVT_DELAY_OVF_VT2_PD_SITE0_UNIT3_S 15
|
||||
#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3 0x00000003
|
||||
#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE0_UNIT3_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE1_UNIT0_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0128)
|
||||
#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0 0x0000FFFF
|
||||
#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT0_S 16
|
||||
#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT0 (BIT(15))
|
||||
#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT0_S 15
|
||||
#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0 0x00000003
|
||||
#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT0_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE1_UNIT1_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x012C)
|
||||
#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1 0x0000FFFF
|
||||
#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT1_S 16
|
||||
#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT1 (BIT(15))
|
||||
#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT1_S 15
|
||||
#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1 0x00000003
|
||||
#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT1_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE1_UNIT2_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0130)
|
||||
#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2 0x0000FFFF
|
||||
#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT2_S 16
|
||||
#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT2 (BIT(15))
|
||||
#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT2_S 15
|
||||
#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2 0x00000003
|
||||
#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT2_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE1_UNIT3_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0134)
|
||||
#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3 0x0000FFFF
|
||||
#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE1_UNIT3_S 16
|
||||
#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT3 (BIT(15))
|
||||
#define PVT_DELAY_OVF_VT0_PD_SITE1_UNIT3_S 15
|
||||
#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3 0x00000003
|
||||
#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE1_UNIT3_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE1_UNIT0_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0138)
|
||||
#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0 0x0000FFFF
|
||||
#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT0_S 16
|
||||
#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT0 (BIT(15))
|
||||
#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT0_S 15
|
||||
#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0 0x00000003
|
||||
#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT0_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE1_UNIT1_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x013C)
|
||||
#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1 0x0000FFFF
|
||||
#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT1_S 16
|
||||
#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT1 (BIT(15))
|
||||
#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT1_S 15
|
||||
#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1 0x00000003
|
||||
#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT1_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE1_UNIT2_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0140)
|
||||
#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2 0x0000FFFF
|
||||
#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT2_S 16
|
||||
#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT2 (BIT(15))
|
||||
#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT2_S 15
|
||||
#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2 0x00000003
|
||||
#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT2_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE1_UNIT3_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0144)
|
||||
#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3 0x0000FFFF
|
||||
#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE1_UNIT3_S 16
|
||||
#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT3 (BIT(15))
|
||||
#define PVT_DELAY_OVF_VT1_PD_SITE1_UNIT3_S 15
|
||||
#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3 0x00000003
|
||||
#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE1_UNIT3_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE1_UNIT0_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0148)
|
||||
#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0 0x0000FFFF
|
||||
#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT0_S 16
|
||||
#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT0 (BIT(15))
|
||||
#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT0_S 15
|
||||
#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0 0x00000003
|
||||
#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT0_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE1_UNIT1_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x014C)
|
||||
#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1 0x0000FFFF
|
||||
#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT1_S 16
|
||||
#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT1 (BIT(15))
|
||||
#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT1_S 15
|
||||
#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1 0x00000003
|
||||
#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT1_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE1_UNIT2_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0150)
|
||||
#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2 0x0000FFFF
|
||||
#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT2_S 16
|
||||
#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT2 (BIT(15))
|
||||
#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT2_S 15
|
||||
#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2 0x00000003
|
||||
#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT2_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE1_UNIT3_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0154)
|
||||
#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3 0x0000FFFF
|
||||
#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE1_UNIT3_S 16
|
||||
#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT3 (BIT(15))
|
||||
#define PVT_DELAY_OVF_VT2_PD_SITE1_UNIT3_S 15
|
||||
#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3 0x00000003
|
||||
#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE1_UNIT3_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE2_UNIT0_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0158)
|
||||
#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0 0x0000FFFF
|
||||
#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT0_S 16
|
||||
#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT0 (BIT(15))
|
||||
#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT0_S 15
|
||||
#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0 0x00000003
|
||||
#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT0_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE2_UNIT1_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x015C)
|
||||
#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1 0x0000FFFF
|
||||
#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT1_S 16
|
||||
#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT1 (BIT(15))
|
||||
#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT1_S 15
|
||||
#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1 0x00000003
|
||||
#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT1_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE2_UNIT2_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0160)
|
||||
#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2 0x0000FFFF
|
||||
#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT2_S 16
|
||||
#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT2 (BIT(15))
|
||||
#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT2_S 15
|
||||
#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2 0x00000003
|
||||
#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT2_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE2_UNIT3_VT0_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0164)
|
||||
#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3 0x0000FFFF
|
||||
#define PVT_TIMING_ERR_CNT_O_VT0_PD_SITE2_UNIT3_S 16
|
||||
#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT3 (BIT(15))
|
||||
#define PVT_DELAY_OVF_VT0_PD_SITE2_UNIT3_S 15
|
||||
#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3 0x00000003
|
||||
#define PVT_MONITOR_EDG_MOD_VT0_PD_SITE2_UNIT3_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE2_UNIT0_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0168)
|
||||
#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0 0x0000FFFF
|
||||
#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT0_S 16
|
||||
#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT0 (BIT(15))
|
||||
#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT0_S 15
|
||||
#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0 0x00000003
|
||||
#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT0_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE2_UNIT1_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x016C)
|
||||
#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1 0x0000FFFF
|
||||
#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT1_S 16
|
||||
#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT1 (BIT(15))
|
||||
#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT1_S 15
|
||||
#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1 0x00000003
|
||||
#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT1_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE2_UNIT2_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0170)
|
||||
#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2 0x0000FFFF
|
||||
#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT2_S 16
|
||||
#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT2 (BIT(15))
|
||||
#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT2_S 15
|
||||
#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2 0x00000003
|
||||
#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT2_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE2_UNIT3_VT1_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0174)
|
||||
#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3 0x0000FFFF
|
||||
#define PVT_TIMING_ERR_CNT_O_VT1_PD_SITE2_UNIT3_S 16
|
||||
#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT3 (BIT(15))
|
||||
#define PVT_DELAY_OVF_VT1_PD_SITE2_UNIT3_S 15
|
||||
#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3 0x00000003
|
||||
#define PVT_MONITOR_EDG_MOD_VT1_PD_SITE2_UNIT3_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE2_UNIT0_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0178)
|
||||
#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0 0x0000FFFF
|
||||
#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT0_S 16
|
||||
#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT0 (BIT(15))
|
||||
#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT0_S 15
|
||||
#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0 0x00000003
|
||||
#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT0_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE2_UNIT1_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x017C)
|
||||
#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1 0x0000FFFF
|
||||
#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT1_S 16
|
||||
#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT1 (BIT(15))
|
||||
#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT1_S 15
|
||||
#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1 0x00000003
|
||||
#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT1_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE2_UNIT2_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0180)
|
||||
#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2 0x0000FFFF
|
||||
#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT2_S 16
|
||||
#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT2 (BIT(15))
|
||||
#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT2_S 15
|
||||
#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2 0x00000003
|
||||
#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT2_S 0
|
||||
|
||||
#define PVT_COMB_PD_SITE2_UNIT3_VT2_CONF2_REG (DR_REG_PVT_MONITOR_BASE + 0x0184)
|
||||
#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3 0x0000FFFF
|
||||
#define PVT_TIMING_ERR_CNT_O_VT2_PD_SITE2_UNIT3_S 16
|
||||
#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT3 (BIT(15))
|
||||
#define PVT_DELAY_OVF_VT2_PD_SITE2_UNIT3_S 15
|
||||
#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3 0x00000003
|
||||
#define PVT_MONITOR_EDG_MOD_VT2_PD_SITE2_UNIT3_S 0
|
||||
|
||||
#define PVT_DATE_REG (DR_REG_PVT_MONITOR_BASE + 0xFFC)
|
||||
#define PVT_DATE 0xFFFFFFFF
|
||||
#define PVT_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
@@ -117,6 +117,26 @@ set sleep_init default param
|
||||
#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1
|
||||
#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254
|
||||
|
||||
/*
|
||||
set pvt default param
|
||||
*/
|
||||
#define PVT_CHANNEL0_SEL 34
|
||||
#define PVT_CHANNEL1_SEL 38
|
||||
#define PVT_CHANNEL0_CFG 0x1033e
|
||||
#define PVT_CHANNEL1_CFG 0x1033e
|
||||
#define PVT_CHANNEL2_CFG 0x10000
|
||||
#define PVT_CMD0 0x24
|
||||
#define PVT_CMD1 0x5
|
||||
#define PVT_CMD2 0x427
|
||||
#define PVT_TARGET 0x1f40
|
||||
#define PVT_CLK_DIV 1
|
||||
#define PVT_EDG_MODE 1
|
||||
#define PVT_DELAY_NUM_HIGH 108
|
||||
#define PVT_DELAY_NUM_LOW 98
|
||||
#define PVT_PUMP_CHANNEL_CODE 1
|
||||
#define PVT_PUMP_BITMAP 512
|
||||
#define PVT_PUMP_DRV 0
|
||||
|
||||
/*
|
||||
The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value
|
||||
storing in efuse (based on ATE 5k ECO3 chips)
|
||||
|
@@ -69,6 +69,7 @@
|
||||
#define SOC_BOD_SUPPORTED 1
|
||||
#define SOC_APM_SUPPORTED 1
|
||||
#define SOC_PMU_SUPPORTED 1
|
||||
#define SOC_PMU_PVT_SUPPORTED 1
|
||||
#define SOC_PAU_SUPPORTED 1
|
||||
#define SOC_LP_TIMER_SUPPORTED 1
|
||||
#define SOC_LP_AON_SUPPORTED 1
|
||||
|
Reference in New Issue
Block a user