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[hal]: cleaned up interrupt mask functions

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* Functions for setting and clearing interrupts
  as well as function to read interrupt mask
  should be clearer now.
* Using hal layer interrupt set and clear
  functions in esp_wifi component
This commit is contained in:
Jakob Hasse
2021-02-24 12:07:11 +08:00
parent f13b10a17b
commit b23c9142d5
11 changed files with 96 additions and 177 deletions
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40
components/hal/esp32c3/include/hal/interrupt_controller_ll.h
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@@ -49,6 +49,16 @@ static inline void intr_cntrl_ll_disable_interrupts(uint32_t mask)
RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE);
}
/**
* @brief Read the current interrupt mask of the CPU running this code.
*
* @return The current interrupt bitmask.
*/
static inline uint32_t intr_cntrl_ll_read_interrupt_mask(void)
{
return REG_READ(INTERRUPT_CORE0_CPU_INT_ENABLE_REG);
}
/**
* @brief checks if given interrupt number has a valid handler
*
@@ -85,36 +95,6 @@ static inline void *intr_cntrl_ll_get_int_handler_arg(uint8_t intr)
return intr_handler_get_arg(intr);
}
/**
* @brief Disables interrupts that are not located in iram
*
* @param newmask mask of interrupts TO KEEP ENABLED (note: this is probably a bug, see IDF-2308)
* @return oldmask previous interrupt mask value
*/
static inline uint32_t intr_cntrl_ll_disable_int_mask(uint32_t newmask)
{
// Disable interrupts in order to atomically update the interrupt enable register
unsigned old_mstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE);
uint32_t old_int_enable = REG_READ(INTERRUPT_CORE0_CPU_INT_ENABLE_REG);
REG_WRITE(INTERRUPT_CORE0_CPU_INT_ENABLE_REG, old_int_enable & newmask);
RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE);
return old_int_enable;
}
/**
* @brief Enables interrupts that are not located in iram
*
* @param newmask mask of interrupts needs to be enabled
*/
static inline void intr_cntrl_ll_enable_int_mask(uint32_t newmask)
{
unsigned old_mstatus = RV_CLEAR_CSR(mstatus, MSTATUS_MIE);
esprv_intc_int_enable(newmask);
RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE);
}
/**
* @brief Acknowledge an edge-trigger interrupt by clearing its pending flag
*