mirror of
https://github.com/espressif/esp-idf.git
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change(cache): use bus id to get cache vaddr bus
This commit is contained in:

committed by
Armando (Dou Yiwen)

parent
84ae601fef
commit
b25bde3378
@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -100,7 +100,6 @@ __attribute__((always_inline))
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#endif
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static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
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{
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HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
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cache_bus_mask_t mask = (cache_bus_mask_t)0;
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uint32_t vaddr_end = vaddr_start + len - 1;
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@@ -131,20 +130,18 @@ static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t v
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/**
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* Enable the Cache Buses
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*
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* @param cache_id cache ID (when l1 cache is per core)
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* @param bus_id bus ID
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* @param mask To know which buses should be enabled
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* @param enable 1: enable; 0: disable
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*/
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#if !BOOTLOADER_BUILD
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__attribute__((always_inline))
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#endif
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static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask)
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static inline void cache_ll_l1_enable_bus(uint32_t bus_id, cache_bus_mask_t mask)
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{
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(void) mask;
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HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
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uint32_t bus_mask = 0;
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if (cache_id == 0) {
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if (bus_id == 0) {
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bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS0) ? DPORT_PRO_CACHE_MASK_IRAM0 : 0);
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bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS1) ? DPORT_PRO_CACHE_MASK_IRAM1 : 0);
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bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS2) ? DPORT_PRO_CACHE_MASK_IROM0 : 0);
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@@ -200,18 +197,16 @@ static inline cache_bus_mask_t cache_ll_l1_get_enabled_bus(uint32_t cache_id)
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/**
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* Disable the Cache Buses
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*
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* @param cache_id cache ID (when l1 cache is per core)
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* @param bus_id bus ID
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* @param mask To know which buses should be enabled
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* @param enable 1: enable; 0: disable
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*/
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__attribute__((always_inline))
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static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask)
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static inline void cache_ll_l1_disable_bus(uint32_t bus_id, cache_bus_mask_t mask)
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{
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(void) mask;
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HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
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uint32_t bus_mask = 0;
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if (cache_id == 0) {
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if (bus_id == 0) {
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bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS0) ? DPORT_PRO_CACHE_MASK_IRAM0 : 0);
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bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS1) ? DPORT_PRO_CACHE_MASK_IRAM1 : 0);
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bus_mask = bus_mask | ((mask & CACHE_BUS_IBUS2) ? DPORT_PRO_CACHE_MASK_IROM0 : 0);
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