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fix(clk): XTAL_X2 clock is not usable on H21 MPW and H4 BETA5

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This commit is contained in:
Song Ruo Jing
2025-07-09 22:11:02 +08:00
parent caa382047b
commit b3fd9b6afa
15 changed files with 256 additions and 253 deletions
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4
components/hal/esp32h21/clk_tree_hal.c
View File

@@ -17,8 +17,8 @@ uint32_t clk_hal_soc_root_get_freq_mhz(soc_cpu_clk_src_t cpu_clk_src)
return clk_ll_bbpll_get_freq_mhz();
case SOC_CPU_CLK_SRC_RC_FAST:
return SOC_CLK_RC_FAST_FREQ_APPROX / MHZ;
case SOC_CPU_CLK_SRC_XTAL_X2:
return clk_ll_xtal_x2_get_freq_mhz();
// case SOC_CPU_CLK_SRC_XTAL_X2:
// return clk_ll_xtal_x2_get_freq_mhz();
default:
// Unknown CPU_CLK mux input
HAL_ASSERT(false);

68
components/hal/esp32h21/include/hal/clk_tree_ll.h
View File

@@ -27,7 +27,7 @@ extern "C" {
#define MHZ (1000000)
#define CLK_LL_PLL_48M_FREQ_MHZ (48)
#define CLK_LL_PLL_64M_FREQ_MHZ (64)
// #define CLK_LL_PLL_64M_FREQ_MHZ (64)
#define CLK_LL_PLL_96M_FREQ_MHZ (96)
#define CLK_LL_XTAL32K_CONFIG_DEFAULT() { \
@@ -79,26 +79,26 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_disable(void)
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_GLOBAL_BBPLL_ICG);
}
/**
* @brief Power up XTAL_X2 circuit
*/
static inline __attribute__((always_inline)) void clk_ll_xtal_x2_enable(void)
{
CLEAR_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_XPD_XTALX2);
CLEAR_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_GLOBAL_XTALX2_ICG);
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_XTALX2);
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_GLOBAL_XTALX2_ICG);
}
// /**
// * @brief Power up XTAL_X2 circuit
// */
// static inline __attribute__((always_inline)) void clk_ll_xtal_x2_enable(void)
// {
// CLEAR_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_XPD_XTALX2);
// CLEAR_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_GLOBAL_XTALX2_ICG);
// SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_XTALX2);
// SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_GLOBAL_XTALX2_ICG);
// }
/**
* @brief Power down XTAL_X2 circuit
*/
static inline __attribute__((always_inline)) void clk_ll_xtal_x2_disable(void)
{
CLEAR_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_XTALX2 | PMU_TIE_HIGH_GLOBAL_XTALX2_ICG);
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_XPD_XTALX2);
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_GLOBAL_XTALX2_ICG);
}
// /**
// * @brief Power down XTAL_X2 circuit
// */
// static inline __attribute__((always_inline)) void clk_ll_xtal_x2_disable(void)
// {
// CLEAR_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_XTALX2 | PMU_TIE_HIGH_GLOBAL_XTALX2_ICG);
// SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_XPD_XTALX2);
// SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_GLOBAL_XTALX2_ICG);
// }
/**
* @brief Enable the 32kHz crystal oscillator
@@ -277,15 +277,15 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DLREF_SEL, oc_dlref_sel);
}
/**
* @brief Get XTAL_X2_CLK frequency
*
* @return XTAL_X2 clock frequency, in MHz
*/
static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_x2_get_freq_mhz(void)
{
return SOC_XTAL_FREQ_32M * 2;
}
// /**
// * @brief Get XTAL_X2_CLK frequency
// *
// * @return XTAL_X2 clock frequency, in MHz
// */
// static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_x2_get_freq_mhz(void)
// {
// return SOC_XTAL_FREQ_32M * 2;
// }
/**
* @brief To enable the change of soc_clk_sel, cpu_div_num, and ahb_div_num
@@ -313,9 +313,9 @@ static inline __attribute__((always_inline)) void clk_ll_cpu_set_src(soc_cpu_clk
case SOC_CPU_CLK_SRC_RC_FAST:
PCR.sysclk_conf.soc_clk_sel = 2;
break;
case SOC_CPU_CLK_SRC_XTAL_X2:
PCR.sysclk_conf.soc_clk_sel = 3;
break;
// case SOC_CPU_CLK_SRC_XTAL_X2:
// PCR.sysclk_conf.soc_clk_sel = 3;
// break;
default:
// Unsupported CPU_CLK mux input sel
abort();
@@ -337,8 +337,8 @@ static inline __attribute__((always_inline)) soc_cpu_clk_src_t clk_ll_cpu_get_sr
return SOC_CPU_CLK_SRC_PLL;
case 2:
return SOC_CPU_CLK_SRC_RC_FAST;
case 3:
return SOC_CPU_CLK_SRC_XTAL_X2;
// case 3:
// return SOC_CPU_CLK_SRC_XTAL_X2;
default:
// Invalid SOC_CLK_SEL value
return SOC_CPU_CLK_SRC_INVALID;

6
components/hal/esp32h21/include/hal/mspi_ll.h
View File

@@ -51,9 +51,9 @@ static inline void _mspi_timing_ll_set_flash_clk_src(uint32_t mspi_id, soc_perip
case FLASH_CLK_SRC_RC_FAST:
PCR.mspi_conf.mspi_clk_sel = 1;
break;
case FLASH_CLK_SRC_PLL_F64M:
PCR.mspi_conf.mspi_clk_sel = 2;
break;
// case FLASH_CLK_SRC_PLL_F64M:
// PCR.mspi_conf.mspi_clk_sel = 2;
// break;
case FLASH_CLK_SRC_PLL_F48M:
PCR.mspi_conf.mspi_clk_sel = 3;
break;