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fix(clk): XTAL_X2 clock is not usable on H21 MPW and H4 BETA5

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This commit is contained in:
Song Ruo Jing
2025-07-09 22:11:02 +08:00
parent caa382047b
commit b3fd9b6afa
15 changed files with 256 additions and 253 deletions
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3
components/bootloader/Kconfig.projbuild
View File

@@ -41,7 +41,8 @@ menu "Bootloader config"
config BOOTLOADER_CPU_CLK_FREQ_MHZ
int
default 64 if IDF_TARGET_ESP32H2 || IDF_TARGET_ESP32H21 || IDF_TARGET_ESP32H4
default 64 if IDF_TARGET_ESP32H2
default 48 if IDF_TARGET_ESP32H21 || IDF_TARGET_ESP32H4
default 90 if IDF_TARGET_ESP32P4
default 80
help

9
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h21.c
View File

@@ -81,10 +81,11 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
static void IRAM_ATTR bootloader_flash_clock_init(void)
{
// To raise the MSPI clock to 64MHz, needs to enable the 64MHz clock source, which is XTAL_X2_CLK
// (FPGA image fixed MSPI0/1 clock to 64MHz)
clk_ll_xtal_x2_enable();
_mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_PLL_F64M);
// // To raise the MSPI clock to 64MHz, needs to enable the 64MHz clock source, which is XTAL_X2_CLK
// // (FPGA image fixed MSPI0/1 clock to 64MHz)
// clk_ll_xtal_x2_enable();
// _mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_PLL_F64M);
_mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_PLL_F48M);
}
static void update_flash_config(const esp_image_header_t *bootloader_hdr)

56
components/esp_hw_support/port/esp32h21/esp_clk_tree.c
View File

@@ -33,9 +33,9 @@ uint32_t *freq_value)
case SOC_MOD_CLK_PLL_F48M:
clk_src_freq = CLK_LL_PLL_48M_FREQ_MHZ * MHZ;
break;
case SOC_MOD_CLK_XTAL_X2_F64M:
clk_src_freq = CLK_LL_PLL_64M_FREQ_MHZ * MHZ;
break;
// case SOC_MOD_CLK_XTAL_X2_F64M:
// clk_src_freq = CLK_LL_PLL_64M_FREQ_MHZ * MHZ;
// break;
case SOC_MOD_CLK_PLL_F96M:
clk_src_freq = CLK_LL_PLL_96M_FREQ_MHZ * MHZ;
break;
@@ -60,22 +60,22 @@ uint32_t *freq_value)
return ESP_OK;
}
static int16_t s_xtal_x2_ref_cnt = 0;
// static int16_t s_xtal_x2_ref_cnt = 0;
void esp_clk_tree_initialize(void)
{
// In bootloader, flash clock source will always be switched to use XTAL_X2 clock
s_xtal_x2_ref_cnt++;
if (clk_ll_cpu_get_src() == SOC_CPU_CLK_SRC_XTAL_X2) {
s_xtal_x2_ref_cnt++;
}
// // In bootloader, flash clock source will always be switched to use XTAL_X2 clock
// s_xtal_x2_ref_cnt++;
// if (clk_ll_cpu_get_src() == SOC_CPU_CLK_SRC_XTAL_X2) {
// s_xtal_x2_ref_cnt++;
// }
}
bool esp_clk_tree_is_power_on(soc_root_clk_circuit_t clk_circuit)
{
switch (clk_circuit) {
case SOC_ROOT_CIRCUIT_CLK_XTAL_X2:
return s_xtal_x2_ref_cnt > 0;
// case SOC_ROOT_CIRCUIT_CLK_XTAL_X2:
// return s_xtal_x2_ref_cnt > 0;
default:
break;
}
@@ -85,21 +85,21 @@ bool esp_clk_tree_is_power_on(soc_root_clk_circuit_t clk_circuit)
esp_err_t esp_clk_tree_enable_power(soc_root_clk_circuit_t clk_circuit, bool enable)
{
switch (clk_circuit) {
case SOC_ROOT_CIRCUIT_CLK_XTAL_X2:
if (enable) {
s_xtal_x2_ref_cnt++;
} else {
s_xtal_x2_ref_cnt--;
}
// case SOC_ROOT_CIRCUIT_CLK_XTAL_X2:
// if (enable) {
// s_xtal_x2_ref_cnt++;
// } else {
// s_xtal_x2_ref_cnt--;
// }
if (s_xtal_x2_ref_cnt == 1) {
clk_ll_xtal_x2_enable();
} else if (s_xtal_x2_ref_cnt == 0) {
clk_ll_xtal_x2_disable();
}
// if (s_xtal_x2_ref_cnt == 1) {
// clk_ll_xtal_x2_enable();
// } else if (s_xtal_x2_ref_cnt == 0) {
// clk_ll_xtal_x2_disable();
// }
assert(s_xtal_x2_ref_cnt >= 0);
break;
// assert(s_xtal_x2_ref_cnt >= 0);
// break;
default:
break;
}
@@ -109,10 +109,10 @@ esp_err_t esp_clk_tree_enable_power(soc_root_clk_circuit_t clk_circuit, bool ena
esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable)
{
switch (clk_src) {
case SOC_MOD_CLK_XTAL_X2_F64M:
// later, here should handle ref count for XTAL_X2_F64M clock gating, then also handle XTAL_X2 circuit enable/disable
esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_XTAL_X2, enable);
break;
// case SOC_MOD_CLK_XTAL_X2_F64M:
// // later, here should handle ref count for XTAL_X2_F64M clock gating, then also handle XTAL_X2 circuit enable/disable
// esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_XTAL_X2, enable);
// break;
default:
break;
}

88
components/esp_hw_support/port/esp32h21/rtc_clk.c
View File

@@ -199,22 +199,22 @@ static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz);
}
/**
* Switch to XTAL_X2 as cpu clock source.
* On ESP32H21, XTAL_X2 frequency is 64MHz.
* XTAL_X2 circuit must already been enabled.
*/
static void rtc_clk_cpu_freq_to_xtal_x2(uint32_t cpu_freq_mhz, uint32_t cpu_divider)
{
// f_hp_root = 64MHz
clk_ll_cpu_set_divider(cpu_divider);
// Constraint: f_ahb <= 32MHz; f_cpu = N * f_ahb (N = 1, 2, 3...)
uint32_t ahb_divider = (cpu_divider == 1) ? 2 : cpu_divider;
clk_ll_ahb_set_divider(ahb_divider);
clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_XTAL_X2);
clk_ll_bus_update();
esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz);
}
// /**
// * Switch to XTAL_X2 as cpu clock source.
// * On ESP32H21, XTAL_X2 frequency is 64MHz.
// * XTAL_X2 circuit must already been enabled.
// */
// static void rtc_clk_cpu_freq_to_xtal_x2(uint32_t cpu_freq_mhz, uint32_t cpu_divider)
// {
// // f_hp_root = 64MHz
// clk_ll_cpu_set_divider(cpu_divider);
// // Constraint: f_ahb <= 32MHz; f_cpu = N * f_ahb (N = 1, 2, 3...)
// uint32_t ahb_divider = (cpu_divider == 1) ? 2 : cpu_divider;
// clk_ll_ahb_set_divider(ahb_divider);
// clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_XTAL_X2);
// clk_ll_bus_update();
// esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz);
// }
bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config)
{
@@ -239,11 +239,11 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou
source = SOC_CPU_CLK_SRC_PLL;
source_freq_mhz = CLK_LL_PLL_96M_FREQ_MHZ;
divider = 1;
} else if (freq_mhz == 64) {
real_freq_mhz = freq_mhz;
source = SOC_CPU_CLK_SRC_XTAL_X2;
source_freq_mhz = CLK_LL_PLL_64M_FREQ_MHZ;
divider = 1;
// } else if (freq_mhz == 64) {
// real_freq_mhz = freq_mhz;
// source = SOC_CPU_CLK_SRC_XTAL_X2;
// source_freq_mhz = CLK_LL_PLL_64M_FREQ_MHZ;
// divider = 1;
} else if (freq_mhz == 48) {
real_freq_mhz = freq_mhz;
source = SOC_CPU_CLK_SRC_PLL;
@@ -271,12 +271,12 @@ static void rtc_clk_cpu_src_clk_enable(soc_cpu_clk_src_t new_src, uint32_t new_s
if (new_src == SOC_CPU_CLK_SRC_PLL) {
rtc_clk_bbpll_enable();
rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), new_src_freq_mhz);
} else if (new_src == SOC_CPU_CLK_SRC_XTAL_X2) {
#if BOOTLOADER_BUILD
clk_ll_xtal_x2_enable();
#else
esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_XTAL_X2, true);
#endif
// } else if (new_src == SOC_CPU_CLK_SRC_XTAL_X2) {
// #if BOOTLOADER_BUILD
// clk_ll_xtal_x2_enable();
// #else
// esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_XTAL_X2, true);
// #endif
}
}
@@ -284,12 +284,12 @@ static void rtc_clk_cpu_src_clk_disable(soc_cpu_clk_src_t old_src)
{
if ((old_src == SOC_CPU_CLK_SRC_PLL) && !s_bbpll_digi_consumers_ref_count) {
rtc_clk_bbpll_disable();
} else if (old_src == SOC_CPU_CLK_SRC_XTAL_X2) {
#if BOOTLOADER_BUILD
clk_ll_xtal_x2_disable();
#else
esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_XTAL_X2, false);
#endif
// } else if (old_src == SOC_CPU_CLK_SRC_XTAL_X2) {
// #if BOOTLOADER_BUILD
// clk_ll_xtal_x2_disable();
// #else
// esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_XTAL_X2, false);
// #endif
}
}
@@ -309,8 +309,8 @@ void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config)
rtc_clk_set_cpu_switch_to_pll(SLEEP_EVENT_HW_PLL_EN_STOP);
} else if (config->source == SOC_CPU_CLK_SRC_RC_FAST) {
rtc_clk_cpu_freq_to_rc_fast();
} else if (config->source == SOC_CPU_CLK_SRC_XTAL_X2) {
rtc_clk_cpu_freq_to_xtal_x2(config->freq_mhz, config->div);
// } else if (config->source == SOC_CPU_CLK_SRC_XTAL_X2) {
// rtc_clk_cpu_freq_to_xtal_x2(config->freq_mhz, config->div);
}
if (old_cpu_clk_src != config->source) {
@@ -334,9 +334,9 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config)
case SOC_CPU_CLK_SRC_RC_FAST:
source_freq_mhz = 20;
break;
case SOC_CPU_CLK_SRC_XTAL_X2:
source_freq_mhz = clk_ll_xtal_x2_get_freq_mhz();
break;
// case SOC_CPU_CLK_SRC_XTAL_X2:
// source_freq_mhz = clk_ll_xtal_x2_get_freq_mhz();
// break;
default:
ESP_HW_LOGE(TAG, "unsupported frequency configuration");
abort();
@@ -360,9 +360,9 @@ void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config)
rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz);
} else if (config->source == SOC_CPU_CLK_SRC_RC_FAST) {
rtc_clk_cpu_freq_to_rc_fast();
} else if (config->source == SOC_CPU_CLK_SRC_XTAL_X2
&& esp_clk_tree_is_power_on(SOC_ROOT_CIRCUIT_CLK_XTAL_X2)) {
rtc_clk_cpu_freq_to_xtal_x2(config->freq_mhz, config->div);
// } else if (config->source == SOC_CPU_CLK_SRC_XTAL_X2
// && esp_clk_tree_is_power_on(SOC_ROOT_CIRCUIT_CLK_XTAL_X2)) {
// rtc_clk_cpu_freq_to_xtal_x2(config->freq_mhz, config->div);
} else {
/* fallback */
rtc_clk_cpu_freq_set_config(config);
@@ -410,9 +410,9 @@ static uint32_t rtc_clk_ahb_freq_get(void)
case SOC_CPU_CLK_SRC_RC_FAST:
soc_root_freq_mhz = 20;
break;
case SOC_CPU_CLK_SRC_XTAL_X2:
soc_root_freq_mhz = clk_ll_xtal_x2_get_freq_mhz();
break;
// case SOC_CPU_CLK_SRC_XTAL_X2:
// soc_root_freq_mhz = clk_ll_xtal_x2_get_freq_mhz();
// break;
default:
// Unknown SOC_ROOT clock source
soc_root_freq_mhz = 0;

70
components/esp_hw_support/port/esp32h4/esp_clk_tree.c
View File

@@ -30,15 +30,15 @@ uint32_t *freq_value)
case SOC_MOD_CLK_XTAL:
clk_src_freq = clk_hal_xtal_get_freq_mhz() * MHZ;
break;
case SOC_MOD_CLK_XTAL_X2_F32M:
clk_src_freq = CLK_LL_PLL_32M_FREQ_MHZ * MHZ;
break;
// case SOC_MOD_CLK_XTAL_X2_F32M:
// clk_src_freq = CLK_LL_PLL_32M_FREQ_MHZ * MHZ;
// break;
case SOC_MOD_CLK_PLL_F48M:
clk_src_freq = CLK_LL_PLL_48M_FREQ_MHZ * MHZ;
break;
case SOC_MOD_CLK_XTAL_X2_F64M:
clk_src_freq = CLK_LL_PLL_64M_FREQ_MHZ * MHZ;
break;
// case SOC_MOD_CLK_XTAL_X2_F64M:
// clk_src_freq = CLK_LL_PLL_64M_FREQ_MHZ * MHZ;
// break;
case SOC_MOD_CLK_PLL_F96M:
clk_src_freq = CLK_LL_PLL_96M_FREQ_MHZ * MHZ;
break;
@@ -63,23 +63,23 @@ uint32_t *freq_value)
return ESP_OK;
}
static int16_t s_xtal_x2_ref_cnt = 0;
// static int16_t s_xtal_x2_ref_cnt = 0;
void esp_clk_tree_initialize(void)
{
// TODO: IDF-12388
// // In bootloader, flash clock source will always be switched to use XTAL_X2 clock
// // TODO: IDF-12388
// // // In bootloader, flash clock source will always be switched to use XTAL_X2 clock
// // s_xtal_x2_ref_cnt++;
// if (clk_ll_cpu_get_src() == SOC_CPU_CLK_SRC_XTAL_X2) {
// s_xtal_x2_ref_cnt++;
if (clk_ll_cpu_get_src() == SOC_CPU_CLK_SRC_XTAL_X2) {
s_xtal_x2_ref_cnt++;
}
// }
}
bool esp_clk_tree_is_power_on(soc_root_clk_circuit_t clk_circuit)
{
switch (clk_circuit) {
case SOC_ROOT_CIRCUIT_CLK_XTAL_X2:
return s_xtal_x2_ref_cnt > 0;
// case SOC_ROOT_CIRCUIT_CLK_XTAL_X2:
// return s_xtal_x2_ref_cnt > 0;
default:
break;
}
@@ -89,21 +89,21 @@ bool esp_clk_tree_is_power_on(soc_root_clk_circuit_t clk_circuit)
esp_err_t esp_clk_tree_enable_power(soc_root_clk_circuit_t clk_circuit, bool enable)
{
switch (clk_circuit) {
case SOC_ROOT_CIRCUIT_CLK_XTAL_X2:
if (enable) {
s_xtal_x2_ref_cnt++;
} else {
s_xtal_x2_ref_cnt--;
}
// case SOC_ROOT_CIRCUIT_CLK_XTAL_X2:
// if (enable) {
// s_xtal_x2_ref_cnt++;
// } else {
// s_xtal_x2_ref_cnt--;
// }
if (s_xtal_x2_ref_cnt == 1) {
clk_ll_xtal_x2_enable();
} else if (s_xtal_x2_ref_cnt == 0) {
clk_ll_xtal_x2_disable();
}
// if (s_xtal_x2_ref_cnt == 1) {
// clk_ll_xtal_x2_enable();
// } else if (s_xtal_x2_ref_cnt == 0) {
// clk_ll_xtal_x2_disable();
// }
assert(s_xtal_x2_ref_cnt >= 0);
break;
// assert(s_xtal_x2_ref_cnt >= 0);
// break;
default:
break;
}
@@ -113,14 +113,14 @@ esp_err_t esp_clk_tree_enable_power(soc_root_clk_circuit_t clk_circuit, bool ena
esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable)
{
switch (clk_src) {
case SOC_MOD_CLK_XTAL_X2_F32M:
// later, here should handle ref count for XTAL_X2_F32M clock gating, then also handle XTAL_X2 circuit enable/disable
esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_XTAL_X2, enable);
break;
case SOC_MOD_CLK_XTAL_X2_F64M:
// later, here should handle ref count for XTAL_X2_F64M clock gating, then also handle XTAL_X2 circuit enable/disable
esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_XTAL_X2, enable);
break;
// case SOC_MOD_CLK_XTAL_X2_F32M:
// // later, here should handle ref count for XTAL_X2_F32M clock gating, then also handle XTAL_X2 circuit enable/disable
// esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_XTAL_X2, enable);
// break;
// case SOC_MOD_CLK_XTAL_X2_F64M:
// // later, here should handle ref count for XTAL_X2_F64M clock gating, then also handle XTAL_X2 circuit enable/disable
// esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_XTAL_X2, enable);
// break;
default:
break;
}

92
components/esp_hw_support/port/esp32h4/rtc_clk.c
View File

@@ -198,22 +198,22 @@ static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz);
}
/**
* Switch to XTAL_X2 as cpu clock source.
* On ESP32H4, XTAL_X2 frequency is 64MHz.
* XTAL_X2 circuit must already been enabled.
*/
static void rtc_clk_cpu_freq_to_xtal_x2(uint32_t cpu_freq_mhz, uint32_t cpu_divider)
{
// f_hp_root = 64MHz
clk_ll_cpu_set_divider(cpu_divider);
// Constraint: f_ahb <= 32MHz
uint32_t ahb_divider = (cpu_divider == 1) ? 2 : 1;
clk_ll_ahb_set_divider(ahb_divider);
clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_XTAL_X2);
clk_ll_bus_update();
esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz);
}
// /**
// * Switch to XTAL_X2 as cpu clock source.
// * On ESP32H4, XTAL_X2 frequency is 64MHz.
// * XTAL_X2 circuit must already been enabled.
// */
// static void rtc_clk_cpu_freq_to_xtal_x2(uint32_t cpu_freq_mhz, uint32_t cpu_divider)
// {
// // f_hp_root = 64MHz
// clk_ll_cpu_set_divider(cpu_divider);
// // Constraint: f_ahb <= 32MHz
// uint32_t ahb_divider = (cpu_divider == 1) ? 2 : 1;
// clk_ll_ahb_set_divider(ahb_divider);
// clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_XTAL_X2);
// clk_ll_bus_update();
// esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz);
// }
bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config)
{
@@ -238,11 +238,11 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou
source = SOC_CPU_CLK_SRC_PLL;
source_freq_mhz = CLK_LL_PLL_96M_FREQ_MHZ;
divider = 1;
} else if (freq_mhz == 64) {
real_freq_mhz = freq_mhz;
source = SOC_CPU_CLK_SRC_XTAL_X2;
source_freq_mhz = CLK_LL_PLL_64M_FREQ_MHZ;
divider = 1;
// } else if (freq_mhz == 64) {
// real_freq_mhz = freq_mhz;
// source = SOC_CPU_CLK_SRC_XTAL_X2;
// source_freq_mhz = CLK_LL_PLL_64M_FREQ_MHZ;
// divider = 1;
} else if (freq_mhz == 48) {
real_freq_mhz = freq_mhz;
source = SOC_CPU_CLK_SRC_PLL;
@@ -270,12 +270,12 @@ static void rtc_clk_cpu_src_clk_enable(soc_cpu_clk_src_t new_src, uint32_t new_s
if (new_src == SOC_CPU_CLK_SRC_PLL) {
rtc_clk_bbpll_enable();
rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), new_src_freq_mhz);
} else if (new_src == SOC_CPU_CLK_SRC_XTAL_X2) {
#if BOOTLOADER_BUILD
clk_ll_xtal_x2_enable();
#else
esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_XTAL_X2, true);
#endif
// } else if (new_src == SOC_CPU_CLK_SRC_XTAL_X2) {
// #if BOOTLOADER_BUILD
// clk_ll_xtal_x2_enable();
// #else
// esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_XTAL_X2, true);
// #endif
}
}
@@ -283,12 +283,12 @@ static void rtc_clk_cpu_src_clk_disable(soc_cpu_clk_src_t old_src)
{
if ((old_src == SOC_CPU_CLK_SRC_PLL) && !s_bbpll_digi_consumers_ref_count) {
rtc_clk_bbpll_disable();
} else if (old_src == SOC_CPU_CLK_SRC_XTAL_X2) {
#if BOOTLOADER_BUILD
clk_ll_xtal_x2_disable();
#else
esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_XTAL_X2, false);
#endif
// } else if (old_src == SOC_CPU_CLK_SRC_XTAL_X2) {
// #if BOOTLOADER_BUILD
// clk_ll_xtal_x2_disable();
// #else
// esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_XTAL_X2, false);
// #endif
}
}
@@ -308,8 +308,8 @@ void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config)
rtc_clk_set_cpu_switch_to_bbpll(SLEEP_EVENT_HW_PLL_EN_STOP);
} else if (config->source == SOC_CPU_CLK_SRC_RC_FAST) {
rtc_clk_cpu_freq_to_rc_fast();
} else if (config->source == SOC_CPU_CLK_SRC_XTAL_X2) {
rtc_clk_cpu_freq_to_xtal_x2(config->freq_mhz, config->div);
// } else if (config->source == SOC_CPU_CLK_SRC_XTAL_X2) {
// rtc_clk_cpu_freq_to_xtal_x2(config->freq_mhz, config->div);
}
if (old_cpu_clk_src != config->source) {
@@ -333,9 +333,9 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config)
case SOC_CPU_CLK_SRC_RC_FAST:
source_freq_mhz = 8;
break;
case SOC_CPU_CLK_SRC_XTAL_X2:
source_freq_mhz = clk_ll_xtal_x2_get_freq_mhz();
break;
// case SOC_CPU_CLK_SRC_XTAL_X2:
// source_freq_mhz = clk_ll_xtal_x2_get_freq_mhz();
// break;
default:
ESP_HW_LOGE(TAG, "unsupported frequency configuration");
abort();
@@ -359,9 +359,9 @@ void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config)
rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz);
} else if (config->source == SOC_CPU_CLK_SRC_RC_FAST) {
rtc_clk_cpu_freq_to_rc_fast();
} else if (config->source == SOC_CPU_CLK_SRC_XTAL_X2
&& esp_clk_tree_is_power_on(SOC_ROOT_CIRCUIT_CLK_XTAL_X2)) {
rtc_clk_cpu_freq_to_xtal_x2(config->freq_mhz, config->div);
// } else if (config->source == SOC_CPU_CLK_SRC_XTAL_X2
// && esp_clk_tree_is_power_on(SOC_ROOT_CIRCUIT_CLK_XTAL_X2)) {
// rtc_clk_cpu_freq_to_xtal_x2(config->freq_mhz, config->div);
} else {
/* fallback */
rtc_clk_cpu_freq_set_config(config);
@@ -391,8 +391,8 @@ void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz)
{
if (cpu_freq_mhz == 96 || cpu_freq_mhz == 48) {
rtc_clk_cpu_freq_to_pll_mhz(cpu_freq_mhz);
} else { // cpu_freq_mhz == 64
rtc_clk_cpu_freq_to_xtal_x2(cpu_freq_mhz, 1);
// } else { // cpu_freq_mhz == 64
// rtc_clk_cpu_freq_to_xtal_x2(cpu_freq_mhz, 1);
}
clk_ll_cpu_clk_src_lock_release();
}
@@ -420,9 +420,9 @@ static uint32_t rtc_clk_ahb_freq_get(void)
case SOC_CPU_CLK_SRC_RC_FAST:
soc_root_freq_mhz = 8;
break;
case SOC_CPU_CLK_SRC_XTAL_X2:
soc_root_freq_mhz = clk_ll_xtal_x2_get_freq_mhz();
break;
// case SOC_CPU_CLK_SRC_XTAL_X2:
// soc_root_freq_mhz = clk_ll_xtal_x2_get_freq_mhz();
// break;
default:
// Unknown SOC_ROOT clock source
soc_root_freq_mhz = 0;

7
components/esp_system/port/soc/esp32h21/Kconfig.cpu
View File

@@ -11,8 +11,9 @@ choice ESP_DEFAULT_CPU_FREQ_MHZ
config ESP_DEFAULT_CPU_FREQ_MHZ_48
bool "48 MHz"
depends on !IDF_ENV_FPGA
config ESP_DEFAULT_CPU_FREQ_MHZ_64
bool "64 MHz"
#config ESP_DEFAULT_CPU_FREQ_MHZ_64
# bool "64 MHz"
# depends on !IDF_ENV_FPGA
config ESP_DEFAULT_CPU_FREQ_MHZ_96
bool "96 MHz"
depends on !IDF_ENV_FPGA
@@ -22,5 +23,5 @@ config ESP_DEFAULT_CPU_FREQ_MHZ
int
default 32 if ESP_DEFAULT_CPU_FREQ_MHZ_32
default 48 if ESP_DEFAULT_CPU_FREQ_MHZ_48
default 64 if ESP_DEFAULT_CPU_FREQ_MHZ_64
#default 64 if ESP_DEFAULT_CPU_FREQ_MHZ_64
default 96 if ESP_DEFAULT_CPU_FREQ_MHZ_96

8
components/esp_system/port/soc/esp32h4/Kconfig.cpu
View File

@@ -11,9 +11,9 @@ choice ESP_DEFAULT_CPU_FREQ_MHZ
config ESP_DEFAULT_CPU_FREQ_MHZ_48
bool "48 MHz"
depends on !IDF_ENV_FPGA
config ESP_DEFAULT_CPU_FREQ_MHZ_64
bool "64 MHz"
depends on !IDF_ENV_FPGA
#config ESP_DEFAULT_CPU_FREQ_MHZ_64
# bool "64 MHz"
# depends on !IDF_ENV_FPGA
config ESP_DEFAULT_CPU_FREQ_MHZ_96
bool "96 MHz"
depends on !IDF_ENV_FPGA
@@ -23,5 +23,5 @@ config ESP_DEFAULT_CPU_FREQ_MHZ
int
default 32 if ESP_DEFAULT_CPU_FREQ_MHZ_32
default 48 if ESP_DEFAULT_CPU_FREQ_MHZ_48
default 64 if ESP_DEFAULT_CPU_FREQ_MHZ_64
#default 64 if ESP_DEFAULT_CPU_FREQ_MHZ_64
default 96 if ESP_DEFAULT_CPU_FREQ_MHZ_96

4
components/hal/esp32h21/clk_tree_hal.c
View File

@@ -17,8 +17,8 @@ uint32_t clk_hal_soc_root_get_freq_mhz(soc_cpu_clk_src_t cpu_clk_src)
return clk_ll_bbpll_get_freq_mhz();
case SOC_CPU_CLK_SRC_RC_FAST:
return SOC_CLK_RC_FAST_FREQ_APPROX / MHZ;
case SOC_CPU_CLK_SRC_XTAL_X2:
return clk_ll_xtal_x2_get_freq_mhz();
// case SOC_CPU_CLK_SRC_XTAL_X2:
// return clk_ll_xtal_x2_get_freq_mhz();
default:
// Unknown CPU_CLK mux input
HAL_ASSERT(false);

68
components/hal/esp32h21/include/hal/clk_tree_ll.h
View File

@@ -27,7 +27,7 @@ extern "C" {
#define MHZ (1000000)
#define CLK_LL_PLL_48M_FREQ_MHZ (48)
#define CLK_LL_PLL_64M_FREQ_MHZ (64)
// #define CLK_LL_PLL_64M_FREQ_MHZ (64)
#define CLK_LL_PLL_96M_FREQ_MHZ (96)
#define CLK_LL_XTAL32K_CONFIG_DEFAULT() { \
@@ -79,26 +79,26 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_disable(void)
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_GLOBAL_BBPLL_ICG);
}
/**
* @brief Power up XTAL_X2 circuit
*/
static inline __attribute__((always_inline)) void clk_ll_xtal_x2_enable(void)
{
CLEAR_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_XPD_XTALX2);
CLEAR_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_GLOBAL_XTALX2_ICG);
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_XTALX2);
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_GLOBAL_XTALX2_ICG);
}
// /**
// * @brief Power up XTAL_X2 circuit
// */
// static inline __attribute__((always_inline)) void clk_ll_xtal_x2_enable(void)
// {
// CLEAR_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_XPD_XTALX2);
// CLEAR_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_GLOBAL_XTALX2_ICG);
// SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_XTALX2);
// SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_GLOBAL_XTALX2_ICG);
// }
/**
* @brief Power down XTAL_X2 circuit
*/
static inline __attribute__((always_inline)) void clk_ll_xtal_x2_disable(void)
{
CLEAR_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_XTALX2 | PMU_TIE_HIGH_GLOBAL_XTALX2_ICG);
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_XPD_XTALX2);
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_GLOBAL_XTALX2_ICG);
}
// /**
// * @brief Power down XTAL_X2 circuit
// */
// static inline __attribute__((always_inline)) void clk_ll_xtal_x2_disable(void)
// {
// CLEAR_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_XTALX2 | PMU_TIE_HIGH_GLOBAL_XTALX2_ICG);
// SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_XPD_XTALX2);
// SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_GLOBAL_XTALX2_ICG);
// }
/**
* @brief Enable the 32kHz crystal oscillator
@@ -277,15 +277,15 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DLREF_SEL, oc_dlref_sel);
}
/**
* @brief Get XTAL_X2_CLK frequency
*
* @return XTAL_X2 clock frequency, in MHz
*/
static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_x2_get_freq_mhz(void)
{
return SOC_XTAL_FREQ_32M * 2;
}
// /**
// * @brief Get XTAL_X2_CLK frequency
// *
// * @return XTAL_X2 clock frequency, in MHz
// */
// static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_x2_get_freq_mhz(void)
// {
// return SOC_XTAL_FREQ_32M * 2;
// }
/**
* @brief To enable the change of soc_clk_sel, cpu_div_num, and ahb_div_num
@@ -313,9 +313,9 @@ static inline __attribute__((always_inline)) void clk_ll_cpu_set_src(soc_cpu_clk
case SOC_CPU_CLK_SRC_RC_FAST:
PCR.sysclk_conf.soc_clk_sel = 2;
break;
case SOC_CPU_CLK_SRC_XTAL_X2:
PCR.sysclk_conf.soc_clk_sel = 3;
break;
// case SOC_CPU_CLK_SRC_XTAL_X2:
// PCR.sysclk_conf.soc_clk_sel = 3;
// break;
default:
// Unsupported CPU_CLK mux input sel
abort();
@@ -337,8 +337,8 @@ static inline __attribute__((always_inline)) soc_cpu_clk_src_t clk_ll_cpu_get_sr
return SOC_CPU_CLK_SRC_PLL;
case 2:
return SOC_CPU_CLK_SRC_RC_FAST;
case 3:
return SOC_CPU_CLK_SRC_XTAL_X2;
// case 3:
// return SOC_CPU_CLK_SRC_XTAL_X2;
default:
// Invalid SOC_CLK_SEL value
return SOC_CPU_CLK_SRC_INVALID;

6
components/hal/esp32h21/include/hal/mspi_ll.h
View File

@@ -51,9 +51,9 @@ static inline void _mspi_timing_ll_set_flash_clk_src(uint32_t mspi_id, soc_perip
case FLASH_CLK_SRC_RC_FAST:
PCR.mspi_conf.mspi_clk_sel = 1;
break;
case FLASH_CLK_SRC_PLL_F64M:
PCR.mspi_conf.mspi_clk_sel = 2;
break;
// case FLASH_CLK_SRC_PLL_F64M:
// PCR.mspi_conf.mspi_clk_sel = 2;
// break;
case FLASH_CLK_SRC_PLL_F48M:
PCR.mspi_conf.mspi_clk_sel = 3;
break;

4
components/hal/esp32h4/clk_tree_hal.c
View File

@@ -17,8 +17,8 @@ uint32_t clk_hal_soc_root_get_freq_mhz(soc_cpu_clk_src_t cpu_clk_src)
return clk_ll_bbpll_get_freq_mhz();
case SOC_CPU_CLK_SRC_RC_FAST:
return SOC_CLK_RC_FAST_FREQ_APPROX / MHZ;
case SOC_CPU_CLK_SRC_XTAL_X2:
return clk_ll_xtal_x2_get_freq_mhz();
// case SOC_CPU_CLK_SRC_XTAL_X2:
// return clk_ll_xtal_x2_get_freq_mhz();
default:
// Unknown CPU_CLK mux input
HAL_ASSERT(false);

70
components/hal/esp32h4/include/hal/clk_tree_ll.h
View File

@@ -26,9 +26,9 @@ extern "C" {
#define MHZ (1000000)
#define CLK_LL_PLL_8M_FREQ_MHZ (8)
#define CLK_LL_PLL_32M_FREQ_MHZ (32)
// #define CLK_LL_PLL_32M_FREQ_MHZ (32)
#define CLK_LL_PLL_48M_FREQ_MHZ (48)
#define CLK_LL_PLL_64M_FREQ_MHZ (64)
// #define CLK_LL_PLL_64M_FREQ_MHZ (64)
#define CLK_LL_PLL_96M_FREQ_MHZ (96)
#define CLK_LL_XTAL32K_CONFIG_DEFAULT() { \
@@ -83,26 +83,26 @@ static inline __attribute__((always_inline)) void clk_ll_cpu_clk_src_lock_releas
SET_PERI_REG_MASK(PMU_IMM_SLEEP_SYSCLK_REG, PMU_UPDATE_DIG_SYS_CLK_SEL);
}
/**
* @brief Power up XTAL_X2 circuit
*/
static inline __attribute__((always_inline)) void clk_ll_xtal_x2_enable(void)
{
CLEAR_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_XPD_XTALX2);
CLEAR_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_GLOBAL_XTALX2_ICG);
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_XTALX2);
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_GLOBAL_XTALX2_ICG);
}
// /**
// * @brief Power up XTAL_X2 circuit
// */
// static inline __attribute__((always_inline)) void clk_ll_xtal_x2_enable(void)
// {
// CLEAR_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_XPD_XTALX2);
// CLEAR_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_GLOBAL_XTALX2_ICG);
// SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_XTALX2);
// SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_GLOBAL_XTALX2_ICG);
// }
/**
* @brief Power down XTAL_X2 circuit
*/
static inline __attribute__((always_inline)) void clk_ll_xtal_x2_disable(void)
{
CLEAR_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_XTALX2 | PMU_TIE_HIGH_GLOBAL_XTALX2_ICG);
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_XPD_XTALX2);
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_GLOBAL_XTALX2_ICG);
}
// /**
// * @brief Power down XTAL_X2 circuit
// */
// static inline __attribute__((always_inline)) void clk_ll_xtal_x2_disable(void)
// {
// CLEAR_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_XTALX2 | PMU_TIE_HIGH_GLOBAL_XTALX2_ICG);
// SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_XPD_XTALX2);
// SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_GLOBAL_XTALX2_ICG);
// }
/**
* @brief Enable the 32kHz crystal oscillator
@@ -281,15 +281,15 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DLREF_SEL, oc_dlref_sel);
}
/**
* @brief Get XTAL_X2_CLK frequency
*
* @return XTAL_X2 clock frequency, in MHz
*/
static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_x2_get_freq_mhz(void)
{
return SOC_XTAL_FREQ_32M * 2;
}
// /**
// * @brief Get XTAL_X2_CLK frequency
// *
// * @return XTAL_X2 clock frequency, in MHz
// */
// static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_x2_get_freq_mhz(void)
// {
// return SOC_XTAL_FREQ_32M * 2;
// }
/**
* @brief To enable the change of soc_clk_sel, cpu_div_num, ahb_div_num, apb_div_num
@@ -316,9 +316,9 @@ static inline __attribute__((always_inline)) void clk_ll_cpu_set_src(soc_cpu_clk
case SOC_CPU_CLK_SRC_RC_FAST:
PCR.sysclk_conf.soc_clk_sel = 1;
break;
case SOC_CPU_CLK_SRC_XTAL_X2:
PCR.sysclk_conf.soc_clk_sel = 2;
break;
// case SOC_CPU_CLK_SRC_XTAL_X2:
// PCR.sysclk_conf.soc_clk_sel = 2;
// break;
case SOC_CPU_CLK_SRC_PLL:
PCR.sysclk_conf.soc_clk_sel = 3;
break;
@@ -341,8 +341,8 @@ static inline __attribute__((always_inline)) soc_cpu_clk_src_t clk_ll_cpu_get_sr
return SOC_CPU_CLK_SRC_XTAL;
case 1:
return SOC_CPU_CLK_SRC_RC_FAST;
case 2:
return SOC_CPU_CLK_SRC_XTAL_X2;
// case 2:
// return SOC_CPU_CLK_SRC_XTAL_X2;
case 3:
return SOC_CPU_CLK_SRC_PLL;
default:

12
components/soc/esp32h21/include/soc/clk_tree_defs.h
View File

@@ -68,7 +68,7 @@ typedef enum {
*/
typedef enum {
SOC_ROOT_CIRCUIT_CLK_BBPLL, /*!< BBPLL_CLK is the output of the PLL generator circuit */
SOC_ROOT_CIRCUIT_CLK_XTAL_X2, /*!< XTAL_X2_CLK is the output of the XTAL_X2 generator circuit */
// SOC_ROOT_CIRCUIT_CLK_XTAL_X2, /*!< XTAL_X2_CLK is the output of the XTAL_X2 generator circuit */
} soc_root_clk_circuit_t;
/**
@@ -79,7 +79,7 @@ typedef enum {
SOC_CPU_CLK_SRC_XTAL = 0, /*!< Select XTAL_CLK as CPU_CLK source */
SOC_CPU_CLK_SRC_PLL = 1, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is one of the outputs of 32MHz crystal oscillator frequency multiplier, 96MHz) */
SOC_CPU_CLK_SRC_RC_FAST = 2, /*!< Select RC_FAST_CLK as CPU_CLK source */
SOC_CPU_CLK_SRC_XTAL_X2 = 3, /*!< Select XTAL_X2_CLK as CPU_CLK source (XTAL_X2_CLK is the other output of 32MHz crystal oscillator frequency multiplier, 64MHz) */
// SOC_CPU_CLK_SRC_XTAL_X2 = 3, /*!< Select XTAL_X2_CLK as CPU_CLK source (XTAL_X2_CLK is the other output of 32MHz crystal oscillator frequency multiplier, 64MHz) */
SOC_CPU_CLK_SRC_INVALID, /*!< Invalid CPU_CLK source */
} soc_cpu_clk_src_t;
@@ -134,7 +134,7 @@ typedef enum {
SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, OSC_SLOW, or RC32K by configuring soc_rtc_slow_clk_src_t */
// For digital domain: peripherals, BLE
SOC_MOD_CLK_PLL_F48M, /*!< PLL_F48M_CLK is derived from PLL (clock gating + fixed divider of 2), it has a fixed frequency of 48MHz */
SOC_MOD_CLK_XTAL_X2_F64M, /*!< XTAL_X2_F64M_CLK is derived from XTAL_X2 (clock gating), it has a fixed frequency of 64MHz */
// SOC_MOD_CLK_XTAL_X2_F64M, /*!< XTAL_X2_F64M_CLK is derived from XTAL_X2 (clock gating), it has a fixed frequency of 64MHz */
SOC_MOD_CLK_PLL_F96M, /*!< PLL_F96M_CLK is derived from PLL (clock gating), it has a fixed frequency of 96MHz */
SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */
SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */
@@ -301,16 +301,16 @@ typedef enum {
/**
* @brief Array initializer for all supported clock sources of FLASH MSPI controller
*/
#define SOC_FLASH_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL_X2_F64M, SOC_MOD_CLK_PLL_F48M}
#define SOC_FLASH_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_PLL_F48M}
/**
* @brief FLASH MSPI controller clock source
*/
typedef enum {
FLASH_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
FLASH_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
FLASH_CLK_SRC_PLL_F64M = SOC_MOD_CLK_XTAL_X2_F64M, /*!< Select PLL_F64M as the source clock */
// FLASH_CLK_SRC_PLL_F64M = SOC_MOD_CLK_XTAL_X2_F64M, /*!< Select PLL_F64M as the source clock */
FLASH_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M as the source clock */
FLASH_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL_X2_F64M, /*!< Select PLL_F64M as the default clock choice */
FLASH_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M as the default clock choice */
FLASH_CLK_SRC_ROM_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as ROM default clock source */
} soc_periph_flash_clk_src_t;

10
components/soc/esp32h4/include/soc/clk_tree_defs.h
View File

@@ -68,7 +68,7 @@ typedef enum {
*/
typedef enum {
SOC_ROOT_CIRCUIT_CLK_BBPLL, /*!< BBPLL_CLK is the output of the PLL generator circuit */
SOC_ROOT_CIRCUIT_CLK_XTAL_X2, /*!< XTAL_X2_CLK is the output of the XTAL_X2 generator circuit */
// SOC_ROOT_CIRCUIT_CLK_XTAL_X2, /*!< XTAL_X2_CLK is the output of the XTAL_X2 generator circuit */
} soc_root_clk_circuit_t;
/**
@@ -78,7 +78,7 @@ typedef enum {
typedef enum {
SOC_CPU_CLK_SRC_XTAL = 0, /*!< Select XTAL_CLK as CPU_CLK source */
SOC_CPU_CLK_SRC_RC_FAST = 1, /*!< Select RC_FAST_CLK as CPU_CLK source */
SOC_CPU_CLK_SRC_XTAL_X2 = 2, /*!< Select XTAL_X2_CLK as CPU_CLK source (XTAL_X2_CLK is the other output of 32MHz crystal oscillator frequency multiplier, 64MHz) */
// SOC_CPU_CLK_SRC_XTAL_X2 = 2, /*!< Select XTAL_X2_CLK as CPU_CLK source (XTAL_X2_CLK is the other output of 32MHz crystal oscillator frequency multiplier, 64MHz) */
SOC_CPU_CLK_SRC_PLL = 3, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 32MHz crystal oscillator frequency multiplier, 96MHz) */
SOC_CPU_CLK_SRC_INVALID, /*!< Invalid CPU_CLK source */
} soc_cpu_clk_src_t;
@@ -134,9 +134,9 @@ typedef enum {
SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t */
SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW_D4, XTAL32K, or OSC_SLOW by configuring soc_rtc_slow_clk_src_t */
// For digital domain: peripherals, BLE
SOC_MOD_CLK_XTAL_X2_F32M, /*!< XTAL_X2_F32M_CLK is derived from XTAL_X2 (clock gating + fixed divider of 2), it has a fixed frequency of 32MHz */
// SOC_MOD_CLK_XTAL_X2_F32M, /*!< XTAL_X2_F32M_CLK is derived from XTAL_X2 (clock gating + fixed divider of 2), it has a fixed frequency of 32MHz */
SOC_MOD_CLK_PLL_F48M, /*!< PLL_F48M_CLK is derived from PLL (clock gating + fixed divider of 2), it has a fixed frequency of 48MHz */
SOC_MOD_CLK_XTAL_X2_F64M, /*!< XTAL_X2_F64M_CLK is derived from XTAL_X2 (clock gating), it has a fixed frequency of 64MHz */
// SOC_MOD_CLK_XTAL_X2_F64M, /*!< XTAL_X2_F64M_CLK is derived from XTAL_X2 (clock gating), it has a fixed frequency of 64MHz */
SOC_MOD_CLK_PLL_F96M, /*!< PLL_F96M_CLK is derived from PLL (clock gating), it has a fixed frequency of 96MHz */
SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */
SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */
@@ -256,7 +256,7 @@ typedef enum {
typedef enum {
FLASH_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
FLASH_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
FLASH_CLK_SRC_REF_F64M = SOC_MOD_CLK_XTAL_X2_F64M, /*!< Select XTAL_X2_F64M as the source clock */
// FLASH_CLK_SRC_REF_F64M = SOC_MOD_CLK_XTAL_X2_F64M, /*!< Select XTAL_X2_F64M as the source clock */
FLASH_CLK_SRC_REF_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M as the source clock */
FLASH_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */
FLASH_CLK_SRC_ROM_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as ROM default clock source */