Merge branch 'feature/esp_timer_add_ll_for_rc_fast_clk' into 'master'

hal: Adds hal/ll func for SYSTIMER to select clock source: XTAL or RC_FAST_CLK

Closes IDF-5323

See merge request espressif/esp-idf!21136

components/soc/esp32c6/include/soc/Kconfig.soc_caps.in

@@ -663,6 +663,10 @@ config SOC_SYSTIMER_FIXED_DIVIDER
     bool
     default y
 
+config SOC_SYSTIMER_SUPPORT_RC_FAST
+    bool
+    default y
+
 config SOC_SYSTIMER_INT_LEVEL
     bool
     default y

components/soc/esp32c6/include/soc/clk_tree_defs.h

@@ -116,6 +116,17 @@ typedef enum {
     SOC_MOD_CLK_XTAL,                          /*!< XTAL_CLK comes from the external 40MHz crystal */
 } soc_module_clk_t;
 
+//////////////////////////////////////////////////SYSTIMER///////////////////////////////////////////////////////////////
+
+/**
+ * @brief Type of SYSTIMER clock source
+ */
+typedef enum {
+    SYSTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,       /*!< SYSTIMER source clock is XTAL */
+    SYSTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< SYSTIMER source clock is RC_FAST */
+    SYSTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,    /*!< SYSTIMER source clock default choice is XTAL */
+} soc_periph_systimer_clk_src_t;
+
 //////////////////////////////////////////////////GPTimer///////////////////////////////////////////////////////////////
 
 /**

components/soc/esp32c6/include/soc/soc_caps.h

@@ -336,6 +336,7 @@
 #define SOC_SYSTIMER_BIT_WIDTH_LO           32 // Bit width of systimer low part
 #define SOC_SYSTIMER_BIT_WIDTH_HI           20 // Bit width of systimer high part
 #define SOC_SYSTIMER_FIXED_DIVIDER          1  // Clock source divider is fixed: 2.5
+#define SOC_SYSTIMER_SUPPORT_RC_FAST        1  // Systimer can use RC_FAST clock source
 #define SOC_SYSTIMER_INT_LEVEL              1  // Systimer peripheral uses level interrupt
 #define SOC_SYSTIMER_ALARM_MISS_COMPENSATE  1  // Systimer peripheral can generate interrupt immediately if t(target) > t(current)