alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2025-11-27 04:55:53 +00:00
Code Issues Packages Projects Releases Wiki Activity

mspi: move timing tuning to esp_hw_support

Browse Source
This commit is contained in:
Armando
2023-01-05 15:24:08 +08:00
parent c55d82d1fa
commit b46cfd15a2
15 changed files with 107 additions and 81 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
components/esp_psram/esp32s3/esp_psram_impl_quad.c
View File

@@ -18,6 +18,7 @@
#include "esp_rom_efuse.h"
#include "hal/gpio_hal.h"
#include "esp_private/spi_flash_os.h"
#include "esp_private/mspi_timing_tuning.h"
static const char* TAG = "quad_psram";
@@ -303,7 +304,7 @@ esp_err_t esp_psram_impl_enable(psram_vaddr_mode_t vaddrmode) //psram init
psram_set_cs_timing();
//enter MSPI slow mode to init PSRAM device registers
spi_timing_enter_mspi_low_speed_mode(true);
mspi_timing_enter_low_speed_mode(true);
//We use SPI1 to init PSRAM
psram_disable_qio_mode(SPI1_NUM);
@@ -335,12 +336,12 @@ esp_err_t esp_psram_impl_enable(psram_vaddr_mode_t vaddrmode) //psram init
psram_enable_qio_mode(SPI1_NUM);
//Do PSRAM timing tuning, we use SPI1 to do the tuning, and set the SPI0 PSRAM timing related registers accordingly
spi_timing_psram_tuning();
mspi_timing_psram_tuning();
//Configure SPI0 PSRAM related SPI Phases
config_psram_spi_phases();
//Back to the high speed mode. Flash/PSRAM clocks are set to the clock that user selected. SPI0/1 registers are all set correctly
spi_timing_enter_mspi_high_speed_mode(true);
mspi_timing_enter_high_speed_mode(true);
return ESP_OK;
}
@@ -364,7 +365,7 @@ static void config_psram_spi_phases(void)
//Dummy
/**
* We set the PSRAM chip required dummy here. If timing tuning is needed,
* the dummy length will be updated in `spi_timing_enter_mspi_high_speed_mode()`
* the dummy length will be updated in `mspi_timing_enter_high_speed_mode()`
*/
SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_RD_SRAM_DUMMY_M); //enable cache read dummy
SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_SRAM_RDUMMY_CYCLELEN_V, (PSRAM_FAST_READ_QUAD_DUMMY - 1), SPI_MEM_SRAM_RDUMMY_CYCLELEN_S); //dummy