feat(ana_cmpr): support analog comparator on C5

components/soc/esp32c5/ana_cmpr_periph.c

@@ -0,0 +1,26 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/ana_cmpr_periph.h"
+#include "soc/ana_cmpr_struct.h"
+
+const ana_cmpr_periph_t ana_cmpr_periph[SOC_ANA_CMPR_NUM] = {
+    [0] = {
+        .src_gpio = ANA_CMPR0_SRC_GPIO,
+        .ext_ref_gpio = ANA_CMPR0_EXT_REF_GPIO,
+        .intr_src = ETS_GPIO_NMI_SOURCE,
+    },
+};
+
+analog_cmpr_dev_t ANALOG_CMPR[SOC_ANA_CMPR_NUM] = {
+    [0] = {
+        .pad_comp_config = &GPIO_EXT.pad_comp_config_0,
+        .pad_comp_filter = &GPIO_EXT.pad_comp_filter_0,
+        .int_st = &GPIO_EXT.int_st,
+        .int_ena = &GPIO_EXT.int_ena,
+        .int_clr = &GPIO_EXT.int_clr,
+    },
+};

components/soc/esp32c5/include/soc/Kconfig.soc_caps.in

@@ -7,6 +7,10 @@ config SOC_ADC_SUPPORTED
     bool
     default y
 
+config SOC_ANA_CMPR_SUPPORTED
+    bool
+    default y
+
 config SOC_DEDICATED_GPIO_SUPPORTED
     bool
     default y
@@ -571,6 +575,18 @@ config SOC_DEDIC_PERIPH_ALWAYS_ENABLE
     bool
     default y
 
+config SOC_ANA_CMPR_NUM
+    int
+    default 1
+
+config SOC_ANA_CMPR_CAN_DISTINGUISH_EDGE
+    bool
+    default y
+
+config SOC_ANA_CMPR_SUPPORT_ETM
+    bool
+    default y
+
 config SOC_I2C_NUM
     int
     default 2

components/soc/esp32c5/include/soc/ana_cmpr_channel.h

@@ -0,0 +1,10 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#define ANA_CMPR0_EXT_REF_GPIO    8       /*!< The GPIO that can be used as external reference voltage */
+#define ANA_CMPR0_SRC_GPIO        9       /*!< The GPIO that used for inputting the source signal to compare */

components/soc/esp32c5/include/soc/ana_cmpr_struct.h

@@ -0,0 +1,36 @@
+/**
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+
+/* NOTE: this file is created manually for compatibility */
+
+#pragma once
+
+#include <stdint.h>
+#include "soc/gpio_ext_struct.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief The Analog Comparator Device struct
+ * @note  The field in it are register pointers, which point to the physical address
+ *        of the corresponding configuration register
+ * @note  see 'ana_cmpr_periph.c' for the device instance
+ */
+typedef struct {
+    volatile gpio_ext_pad_comp_config_0_reg_t *pad_comp_config;
+    volatile gpio_ext_pad_comp_filter_0_reg_t *pad_comp_filter;
+    volatile gpio_ext_int_st_reg_t *int_st;
+    volatile gpio_ext_int_ena_reg_t *int_ena;
+    volatile gpio_ext_int_clr_reg_t *int_clr;
+} analog_cmpr_dev_t;
+
+extern analog_cmpr_dev_t ANALOG_CMPR[1];
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32c5/include/soc/clk_tree_defs.h

@@ -402,6 +402,23 @@ typedef enum {
     GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M,  /*!< Select PLL_F80M clock as the default clock choice */
 } soc_periph_glitch_filter_clk_src_t;
 
+///////////////////////////////////////////////////Analog Comparator////////////////////////////////////////////////////
+
+/**
+ * @brief Array initializer for all supported clock sources of Analog Comparator
+ */
+#define SOC_ANA_CMPR_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
+
+/**
+ * @brief Analog Comparator clock source
+ */
+typedef enum {
+    ANA_CMPR_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,                   /*!< Select XTAL clock as the source clock */
+    ANA_CMPR_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,             /*!< Select RC_FAST clock as the source clock */
+    ANA_CMPR_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M,           /*!< Select PLL_F80M clock as the source clock */
+    ANA_CMPR_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M,            /*!< Select PLL_F80M as the default clock choice */
+} soc_periph_ana_cmpr_clk_src_t;
+
 //////////////////////////////////////////////////TWAI//////////////////////////////////////////////////////////////////
 
 /**

components/soc/esp32c5/include/soc/soc_caps.h

@@ -18,6 +18,7 @@
 
 /*-------------------------- COMMON CAPS ---------------------------------------*/
 #define SOC_ADC_SUPPORTED               1
+#define SOC_ANA_CMPR_SUPPORTED          1
 #define SOC_DEDICATED_GPIO_SUPPORTED    1
 #define SOC_UART_SUPPORTED              1
 #define SOC_GDMA_SUPPORTED              1
@@ -251,6 +252,11 @@
 #define SOC_DEDIC_GPIO_IN_CHANNELS_NUM  (8) /*!< 8 inward channels on each CPU core */
 #define SOC_DEDIC_PERIPH_ALWAYS_ENABLE  (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
 
+/*------------------------- Analog Comparator CAPS ---------------------------*/
+#define SOC_ANA_CMPR_NUM                       (1U)
+#define SOC_ANA_CMPR_CAN_DISTINGUISH_EDGE      (1)  // Support positive/negative/any cross interrupt
+#define SOC_ANA_CMPR_SUPPORT_ETM               (1)
+
 /*-------------------------- I2C CAPS ----------------------------------------*/
 #define SOC_I2C_NUM                 (2U)
 #define SOC_HP_I2C_NUM              (1U)