From c4aa4d47fc03985fbe336ded7510cf3407d88f8a Mon Sep 17 00:00:00 2001 From: muhaidong Date: Mon, 26 May 2025 20:43:46 +0800 Subject: [PATCH 1/3] feat(phy): support esp32c5 cert test --- components/esp_phy/include/esp_phy_cert_test.h | 12 ++++++++++-- examples/phy/.build-test-rules.yml | 2 +- examples/phy/cert_test/README.md | 4 ++-- examples/phy/cert_test/main/cmd_phy.c | 4 ++++ 4 files changed, 17 insertions(+), 5 deletions(-) diff --git a/components/esp_phy/include/esp_phy_cert_test.h b/components/esp_phy/include/esp_phy_cert_test.h index 47d27954dd..ab6041dcb5 100644 --- a/components/esp_phy/include/esp_phy_cert_test.h +++ b/components/esp_phy/include/esp_phy_cert_test.h @@ -38,7 +38,6 @@ typedef enum { PHY_RATE_MCS5 = 0x15, PHY_RATE_MCS6 = 0x16, PHY_RATE_MCS7 = 0x17, -#if CONFIG_SOC_WIFI_HE_SUPPORT // 11ax PHY_RATE_11AX_MCS0 = 0x20, PHY_RATE_11AX_MCS1 = 0x21, @@ -50,7 +49,16 @@ typedef enum { PHY_RATE_11AX_MCS7 = 0x27, PHY_RATE_11AX_MCS8 = 0x28, PHY_RATE_11AX_MCS9 = 0x29, -#endif//CONFIG_SOC_WIFI_HE_SUPPORT + //VHT + PHY_RATE_VHT_MCS0 = 0x30, + PHY_RATE_VHT_MCS1 = 0x31, + PHY_RATE_VHT_MCS2 = 0x32, + PHY_RATE_VHT_MCS3 = 0x33, + PHY_RATE_VHT_MCS4 = 0x34, + PHY_RATE_VHT_MCS5 = 0x35, + PHY_RATE_VHT_MCS6 = 0x36, + PHY_RATE_VHT_MCS7 = 0x37, + PHY_RATE_VHT_MCS8 = 0x38, PHY_WIFI_RATE_MAX } esp_phy_wifi_rate_t; diff --git a/examples/phy/.build-test-rules.yml b/examples/phy/.build-test-rules.yml index 520f3908e9..3e70012edf 100644 --- a/examples/phy/.build-test-rules.yml +++ b/examples/phy/.build-test-rules.yml @@ -11,6 +11,6 @@ examples/phy/cert_test: disable: - if: IDF_TARGET in ["esp32p4"] reason: not supported - - if: IDF_TARGET in ["esp32c5", "esp32c61", "esp32h21", "esp32h4"] + - if: IDF_TARGET in ["esp32c61", "esp32h21", "esp32h4"] temporary: true reason: not supported yet # TODO: [ESP32C5] IDF-8851, [esp32c61] IDF-9859, [esp32h21] IDF-12041, [ESP32H4] IDF-12716 diff --git a/examples/phy/cert_test/README.md b/examples/phy/cert_test/README.md index 42c3dc000e..e75ba038ec 100644 --- a/examples/phy/cert_test/README.md +++ b/examples/phy/cert_test/README.md @@ -1,5 +1,5 @@ -| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 | -| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | +| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-S2 | ESP32-S3 | +| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | # Certification Test Example diff --git a/examples/phy/cert_test/main/cmd_phy.c b/examples/phy/cert_test/main/cmd_phy.c index 92a05ea168..dc10afb5d7 100644 --- a/examples/phy/cert_test/main/cmd_phy.c +++ b/examples/phy/cert_test/main/cmd_phy.c @@ -42,6 +42,7 @@ static phy_gpio_output_set_t phy_gpio_output_set_args; #define arg_int1(_a, _b, _c, _d) arg_int1(NULL, NULL, _c, _d) #endif +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C6 static int esp_phy_tx_contin_en_func(int argc, char **argv) { int nerrors = arg_parse(argc, argv, (void **) &phy_args); @@ -57,6 +58,7 @@ static int esp_phy_tx_contin_en_func(int argc, char **argv) } return 0; } +#endif static int esp_phy_cmdstop_func(int argc, char **argv) { @@ -518,6 +520,7 @@ void register_phy_cmd(void) phy_args.enable = arg_int0(NULL, NULL, "", "enable"); phy_args.end = arg_end(1); +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C6 const esp_console_cmd_t tx_contin_cmd = { .command = "tx_contin_en", .help = "TX Continuous mode, 1: enable, 0: disable", @@ -526,6 +529,7 @@ void register_phy_cmd(void) .argtable = &phy_args }; ESP_ERROR_CHECK( esp_console_cmd_register(&tx_contin_cmd) ); +#endif const esp_console_cmd_t cmdstop_cmd = { .command = "cmdstop", From a58bae6812321b400e1da26af3069f664a6f93fd Mon Sep 17 00:00:00 2001 From: muhaidong Date: Fri, 27 Jun 2025 19:06:39 +0800 Subject: [PATCH 2/3] fix(phy): add tx_contain_en cmd for esp32c5 --- examples/phy/cert_test/main/cmd_phy.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/examples/phy/cert_test/main/cmd_phy.c b/examples/phy/cert_test/main/cmd_phy.c index dc10afb5d7..92a05ea168 100644 --- a/examples/phy/cert_test/main/cmd_phy.c +++ b/examples/phy/cert_test/main/cmd_phy.c @@ -42,7 +42,6 @@ static phy_gpio_output_set_t phy_gpio_output_set_args; #define arg_int1(_a, _b, _c, _d) arg_int1(NULL, NULL, _c, _d) #endif -#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C6 static int esp_phy_tx_contin_en_func(int argc, char **argv) { int nerrors = arg_parse(argc, argv, (void **) &phy_args); @@ -58,7 +57,6 @@ static int esp_phy_tx_contin_en_func(int argc, char **argv) } return 0; } -#endif static int esp_phy_cmdstop_func(int argc, char **argv) { @@ -520,7 +518,6 @@ void register_phy_cmd(void) phy_args.enable = arg_int0(NULL, NULL, "", "enable"); phy_args.end = arg_end(1); -#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C6 const esp_console_cmd_t tx_contin_cmd = { .command = "tx_contin_en", .help = "TX Continuous mode, 1: enable, 0: disable", @@ -529,7 +526,6 @@ void register_phy_cmd(void) .argtable = &phy_args }; ESP_ERROR_CHECK( esp_console_cmd_register(&tx_contin_cmd) ); -#endif const esp_console_cmd_t cmdstop_cmd = { .command = "cmdstop", From c64b751c509edfecd584b18a6032a4fa666d9ada Mon Sep 17 00:00:00 2001 From: muhaidong Date: Thu, 9 Oct 2025 16:48:52 +0800 Subject: [PATCH 3/3] fix(phy): fix cmd get_rx_result log error issue --- components/esp_phy/include/esp_phy_cert_test.h | 6 +++--- examples/phy/cert_test/README.md | 2 +- examples/phy/cert_test/main/cmd_phy.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/components/esp_phy/include/esp_phy_cert_test.h b/components/esp_phy/include/esp_phy_cert_test.h index ab6041dcb5..a354ab8547 100644 --- a/components/esp_phy/include/esp_phy_cert_test.h +++ b/components/esp_phy/include/esp_phy_cert_test.h @@ -20,7 +20,7 @@ typedef enum { PHY_RATE_2M = 0x1, PHY_RATE_5M5 = 0x2, PHY_RATE_11M = 0x3, - //11g + //11g,11a PHY_RATE_6M = 0xb, PHY_RATE_9M = 0xf, PHY_RATE_12M = 0xa, @@ -38,7 +38,7 @@ typedef enum { PHY_RATE_MCS5 = 0x15, PHY_RATE_MCS6 = 0x16, PHY_RATE_MCS7 = 0x17, - // 11ax + //11ax PHY_RATE_11AX_MCS0 = 0x20, PHY_RATE_11AX_MCS1 = 0x21, PHY_RATE_11AX_MCS2 = 0x22, @@ -49,7 +49,7 @@ typedef enum { PHY_RATE_11AX_MCS7 = 0x27, PHY_RATE_11AX_MCS8 = 0x28, PHY_RATE_11AX_MCS9 = 0x29, - //VHT + //11ac PHY_RATE_VHT_MCS0 = 0x30, PHY_RATE_VHT_MCS1 = 0x31, PHY_RATE_VHT_MCS2 = 0x32, diff --git a/examples/phy/cert_test/README.md b/examples/phy/cert_test/README.md index e75ba038ec..5564c13ce2 100644 --- a/examples/phy/cert_test/README.md +++ b/examples/phy/cert_test/README.md @@ -99,7 +99,7 @@ phy> cmdstop I (130260) phy: rx_num: 0 rx_rssi: 0 phy> phy> get_rx_result -I (139550) cmd_phy: Desired: 0, Correct: 0, RSSI: 0, flag: 2 +I (139550) cmd_phy: Correct: 0, Desired: 0, RSSI: 0, flag: 2 phy> phy> bt_tx_tone -e 1 -n 1 -p 0 I (151900) phy: BT TX TONE START! diff --git a/examples/phy/cert_test/main/cmd_phy.c b/examples/phy/cert_test/main/cmd_phy.c index 92a05ea168..4c28ddfb4a 100644 --- a/examples/phy/cert_test/main/cmd_phy.c +++ b/examples/phy/cert_test/main/cmd_phy.c @@ -82,7 +82,7 @@ static int esp_phy_get_rx_result_func(int argc, char **argv) esp_phy_get_rx_result(&rx_result); - ESP_LOGI(TAG, "Desired: %lu, Correct: %lu, RSSI: %d, flag: %lu", rx_result.phy_rx_total_count, + ESP_LOGI(TAG, "Correct: %lu, Desired: %lu, RSSI: %d, flag: %lu", rx_result.phy_rx_total_count, rx_result.phy_rx_correct_count, rx_result.phy_rx_rssi, rx_result.phy_rx_result_flag); return 0;