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ci(parlio_rx): enable target test for h2 and p4

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This commit is contained in:
laokaiyao
2024-06-19 17:20:37 +08:00
parent 1818bbaa79
commit b51fc7c390
8 changed files with 45 additions and 12 deletions
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12
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
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@@ -1095,10 +1095,22 @@ config SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH
int
default 16
config SOC_PARLIO_TX_CLK_SUPPORT_GATING
bool
default y
config SOC_PARLIO_RX_CLK_SUPPORT_GATING
bool
default y
config SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT
bool
default y
config SOC_PARLIO_TRANS_BIT_ALIGN
bool
default y
config SOC_PARLIO_TX_SIZE_BY_DMA
bool
default y

3
components/soc/esp32p4/include/soc/soc_caps.h
View File

@@ -417,7 +417,10 @@
#define SOC_PARLIO_RX_UNITS_PER_GROUP 1U /*!< number of RX units in each group */
#define SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH 16 /*!< Number of data lines of the TX unit */
#define SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH 16 /*!< Number of data lines of the RX unit */
#define SOC_PARLIO_TX_CLK_SUPPORT_GATING 1 /*!< Support gating TX clock */
#define SOC_PARLIO_RX_CLK_SUPPORT_GATING 1 /*!< Support gating RX clock */
#define SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT 1 /*!< Support output RX clock to a GPIO */
#define SOC_PARLIO_TRANS_BIT_ALIGN 1 /*!< Support bit alignment in transaction */
#define SOC_PARLIO_TX_SIZE_BY_DMA 1 /*!< Transaction length is controlled by DMA instead of indicated by register */
/*--------------------------- MPI CAPS ---------------------------------------*/