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https://github.com/espressif/esp-idf.git
synced 2025-08-26 18:14:11 +00:00
feat(sdio_slave): add reset and clock control functions
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -83,6 +83,7 @@ The driver of FIFOs works as below:
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#include "freertos/FreeRTOS.h"
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#include "soc/soc_memory_layout.h"
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#include "soc/gpio_periph.h"
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#include "soc/soc_caps.h"
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#include "esp_cpu.h"
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#include "freertos/semphr.h"
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#include "esp_private/periph_ctrl.h"
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@@ -100,6 +101,12 @@ static const char TAG[] = "sdio_slave";
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#define SDIO_SLAVE_LOGE(s, ...) ESP_LOGE(TAG, "%s(%d): "s, __FUNCTION__,__LINE__,##__VA_ARGS__)
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#define SDIO_SLAVE_LOGW(s, ...) ESP_LOGW(TAG, "%s: "s, __FUNCTION__,##__VA_ARGS__)
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#if !SOC_RCC_IS_INDEPENDENT
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#define SDIO_SLAVE_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
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#else
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#define SDIO_SLAVE_RCC_ATOMIC()
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#endif
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// sdio_slave_buf_handle_t is of type recv_desc_t*;
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typedef struct recv_desc_s {
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union {
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@@ -304,9 +311,11 @@ static inline esp_err_t sdio_slave_hw_init(sdio_slave_config_t *config)
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}
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configure_pin(slot->d3_gpio, slot->func, pullup);
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//enable module and config
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periph_module_reset(PERIPH_SDIO_SLAVE_MODULE);
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periph_module_enable(PERIPH_SDIO_SLAVE_MODULE);
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//enable register clock
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SDIO_SLAVE_RCC_ATOMIC() {
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sdio_slave_ll_enable_bus_clock(true);
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sdio_slave_ll_reset_register();
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}
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sdio_slave_hal_hw_init(context.hal);
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return ESP_OK;
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@@ -333,6 +342,11 @@ static void sdio_slave_hw_deinit(void)
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recover_pin(slot->d1_gpio, slot->func);
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recover_pin(slot->d2_gpio, slot->func);
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recover_pin(slot->d3_gpio, slot->func);
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//disable register clock
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SDIO_SLAVE_RCC_ATOMIC() {
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sdio_slave_ll_enable_bus_clock(false);
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}
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}
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esp_err_t sdio_slave_initialize(sdio_slave_config_t *config)
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