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Merge remote-tracking branch 'origin/master' into feature/mbedtls

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This commit is contained in:
Wu Jian Gang
2016-09-13 16:31:48 +08:00
parent 9c51f8a7a3 9027be98d1
commit b56098a612
37 changed files with 2711 additions and 889 deletions
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6
components/esp32/include/rom/aes.h
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@@ -18,6 +18,7 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ROM_AES_H_
#define _ROM_AES_H_
@@ -28,6 +29,7 @@
extern "C" {
#endif
//TODO, add comment for aes apis
enum AES_BITS {
AES128,
AES192,
@@ -39,8 +41,8 @@ void ets_aes_enable(void);
void ets_aes_disable(void);
void ets_aes_set_endian(bool key_word_swap, bool key_byte_swap,
bool in_word_swap, bool in_byte_swap,
bool out_word_swap, bool out_byte_swap);
bool in_word_swap, bool in_byte_swap,
bool out_word_swap, bool out_byte_swap);
bool ets_aes_setkey_enc(const uint8_t *key, enum AES_BITS bits);

2
components/esp32/include/rom/bigint.h
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@@ -18,6 +18,7 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ROM_BIGINT_H_
#define _ROM_BIGINT_H_
@@ -28,6 +29,7 @@
extern "C" {
#endif
//TODO: add comment here
void ets_bigint_enable(void);
void ets_bigint_disable(void);

143
components/esp32/include/rom/cache.h
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@@ -11,6 +11,7 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ROM_CACHE_H_
#define _ROM_CACHE_H_
@@ -18,50 +19,126 @@
extern "C" {
#endif
//===========================================
// function : cache_init
// description: initialise cache mmu, mark all entries as invalid.
// conditions:
// Call Cache_Read_Disable() before calling this function.
// inputs:
// cpu_no is CPU number,0(PRO CPU) or 1(APP CPU),
// output: NONE
//===========================================
/** \defgroup uart_apis, uart configuration and communication related apis
* @brief uart apis
*/
/** @addtogroup uart_apis
* @{
*/
/**
* @brief Initialise cache mmu, mark all entries as invalid.
* Please do not call this function in your SDK application.
*
* @param int cpu_no : 0 for PRO cpu, 1 for APP cpu.
*
* @return None
*/
void mmu_init(int cpu_no);
//===========================================
// function : cache_flash_mmu_set
// description: Configure MMU to cache a flash region.
// conditions:
// Call this function to configure the flash cache before enabling it.
// Check return value to verify MMU was set correctly.
// inputs:
// cpu_no is CPU number,0(PRO CPU) or 1(APP CPU),
// pid is process identifier. Range 0~7
// vaddr is "virtual" address in CPU address space. Can be IRam0, IRam1, IRom0 and DRom0 memory address.
// Should be aligned by psize
// paddr is "physical" address in flash controller's address space.
// ie for 16M flash the range is 0x000000~0xFFFFFF. Should be aligned by psize
// psize is page size of flash, in kilobytes. Can be 64, 32, 16.
// num is number of pages to be set, valid range 0 ~ (flash size)/(page size)
// output: error status
// 0 : mmu set success
// 1 : vaddr or paddr is not aligned
// 2 : pid error
// 3 : psize error
// 4 : mmu table to be written is out of range
// 5 : vaddr is out of range
//===========================================
/**
* @brief Set Flash-Cache mmu mapping.
* Please do not call this function in your SDK application.
*
* @param int cpu_no : CPU number, 0 for PRO cpu, 1 for APP cpu.
*
* @param int pod : process identifier. Range 0~7.
*
* @param unsigned int vaddr : virtual address in CPU address space.
* Can be IRam0, IRam1, IRom0 and DRom0 memory address.
* Should be aligned by psize.
*
* @param unsigned int paddr : physical address in Flash.
* Should be aligned by psize.
*
* @param int psize : page size of flash, in kilobytes. Should be 64 here.
*
* @param int num : pages to be set.
*
* @return unsigned int: error status
* 0 : mmu set success
* 1 : vaddr or paddr is not aligned
* 2 : pid error
* 3 : psize error
* 4 : mmu table to be written is out of range
* 5 : vaddr is out of range
*/
unsigned int cache_flash_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num);
unsigned int cache_sram_mmu_set(int cpu_no, int pid,unsigned int vaddr, unsigned int paddr, int psize, int num);
/**
* @brief Set Ext-SRAM-Cache mmu mapping.
* Please do not call this function in your SDK application.
*
* @param int cpu_no : CPU number, 0 for PRO cpu, 1 for APP cpu.
*
* @param int pod : process identifier. Range 0~7.
*
* @param unsigned int vaddr : virtual address in CPU address space.
* Can be IRam0, IRam1, IRom0 and DRom0 memory address.
* Should be aligned by psize.
*
* @param unsigned int paddr : physical address in Ext-SRAM.
* Should be aligned by psize.
*
* @param int psize : page size of flash, in kilobytes. Should be 32 here.
*
* @param int num : pages to be set.
*
* @return unsigned int: error status
* 0 : mmu set success
* 1 : vaddr or paddr is not aligned
* 2 : pid error
* 3 : psize error
* 4 : mmu table to be written is out of range
* 5 : vaddr is out of range
*/
unsigned int cache_sram_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num);
/**
* @brief Initialise cache access for the cpu.
* Please do not call this function in your SDK application.
*
* @param int cpu_no : 0 for PRO cpu, 1 for APP cpu.
*
* @return None
*/
void Cache_Read_Init(int cpu_no);
/**
* @brief Flush the cache value for the cpu.
* Please do not call this function in your SDK application.
*
* @param int cpu_no : 0 for PRO cpu, 1 for APP cpu.
*
* @return None
*/
void Cache_Flush(int cpu_no);
/**
* @brief Disable Cache access for the cpu.
* Please do not call this function in your SDK application.
*
* @param int cpu_no : 0 for PRO cpu, 1 for APP cpu.
*
* @return None
*/
void Cache_Read_Disable(int cpu_no);
/**
* @brief Enable Cache access for the cpu.
* Please do not call this function in your SDK application.
*
* @param int cpu_no : 0 for PRO cpu, 1 for APP cpu.
*
* @return None
*/
void Cache_Read_Enable(int cpu_no);
/**
* @}
*/
#ifdef __cplusplus
}
#endif

105
components/esp32/include/rom/crc.h
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@@ -11,20 +11,113 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef ROM_CRC_H
#define ROM_CRC_H
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup uart_apis, uart configuration and communication related apis
* @brief uart apis
*/
/** @addtogroup uart_apis
* @{
*/
/* Standard CRC8/16/32 algorithms. */
uint32_t crc32_le(uint32_t crc, uint8_t const * buf, uint32_t len);
uint32_t crc32_be(uint32_t crc, uint8_t const * buf, uint32_t len);
uint16_t crc16_le(uint16_t crc, uint8_t const * buf, uint32_t len);
uint16_t crc16_be(uint16_t crc, uint8_t const * buf, uint32_t len);
uint8_t crc8_le(uint8_t crc, uint8_t const * buf, uint32_t len);
uint8_t crc8_be(uint8_t crc, uint8_t const * buf, uint32_t len);
// CRC-8 x8+x2+x1+1 0x07
// CRC16-CCITT x16+x12+x5+1 1021 ISO HDLC, ITU X.25, V.34/V.41/V.42, PPP-FCS
// CRC32:
//G(x) = x32 +x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x1 + 1
//If your buf is not continuous, you can use the first result to be the second parameter.
/**
* @brief Crc32 value that is in little endian.
*
* @param uint32_t crc : init crc value, use 0 at the first use.
*
* @param uint8_t const *buf : buffer to start calculate crc.
*
* @param uint32_t len : buffer length in byte.
*
* @return None
*/
uint32_t crc32_le(uint32_t crc, uint8_t const *buf, uint32_t len);
/**
* @brief Crc32 value that is in big endian.
*
* @param uint32_t crc : init crc value, use 0 at the first use.
*
* @param uint8_t const *buf : buffer to start calculate crc.
*
* @param uint32_t len : buffer length in byte.
*
* @return None
*/
uint32_t crc32_be(uint32_t crc, uint8_t const *buf, uint32_t len);
/**
* @brief Crc16 value that is in little endian.
*
* @param uint16_t crc : init crc value, use 0 at the first use.
*
* @param uint8_t const *buf : buffer to start calculate crc.
*
* @param uint32_t len : buffer length in byte.
*
* @return None
*/
uint16_t crc16_le(uint16_t crc, uint8_t const *buf, uint32_t len);
/**
* @brief Crc16 value that is in big endian.
*
* @param uint16_t crc : init crc value, use 0 at the first use.
*
* @param uint8_t const *buf : buffer to start calculate crc.
*
* @param uint32_t len : buffer length in byte.
*
* @return None
*/
uint16_t crc16_be(uint16_t crc, uint8_t const *buf, uint32_t len);
/**
* @brief Crc8 value that is in little endian.
*
* @param uint8_t crc : init crc value, use 0 at the first use.
*
* @param uint8_t const *buf : buffer to start calculate crc.
*
* @param uint32_t len : buffer length in byte.
*
* @return None
*/
uint8_t crc8_le(uint8_t crc, uint8_t const *buf, uint32_t len);
/**
* @brief Crc8 value that is in big endian.
*
* @param uint32_t crc : init crc value, use 0 at the first use.
*
* @param uint8_t const *buf : buffer to start calculate crc.
*
* @param uint32_t len : buffer length in byte.
*
* @return None
*/
uint8_t crc8_be(uint8_t crc, uint8_t const *buf, uint32_t len);
/**
* @}
*/
#ifdef __cplusplus
}

83
components/esp32/include/rom/efuse.h
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@@ -11,17 +11,100 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ROM_EFUSE_H_
#define _ROM_EFUSE_H_
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup efuse_APIs efuse APIs
* @brief ESP32 efuse read/write APIs
* @attention
*
*/
/** @addtogroup efuse_APIs
* @{
*/
/**
* @brief Do a efuse read operation, to update the efuse value to efuse read registers.
*
* @param null
*
* @return null
*/
void ets_efuse_read_op(void);
/**
* @brief Do a efuse write operation, to update efuse write registers to efuse, then you need call ets_efuse_read_op again.
*
* @param null
*
* @return null
*/
void ets_efuse_program_op(void);
/**
* @brief Read 8M Analog Clock value(8 bit) in efuse, the analog clock will not change with temperature.
* It can be used to test the external xtal frequency, do not touch this efuse field.
*
* @param null
*
* @return u32: 1 for 100KHZ, range is 0 to 255.
*/
uint32_t ets_efuse_get_8M_clock(void);
/**
* @brief Read spi pad configuration, show gpio number of flash pad, includes 5 pads.
*
* @param null
*
* @return uint32_t: 0, invalid, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*/
uint32_t ets_efuse_get_spiconfig(void);
#define EFUSE_SPICONFIG_RET_SPICLK_MASK 0x3f
#define EFUSE_SPICONFIG_RET_SPICLK_SHIFT 0
#define EFUSE_SPICONFIG_RET_SPICLK(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPICLK_SHIFT) & EFUSE_SPICONFIG_RET_SPICLK_MASK)
#define EFUSE_SPICONFIG_RET_SPIQ_MASK 0x3f
#define EFUSE_SPICONFIG_RET_SPIQ_SHIFT 6
#define EFUSE_SPICONFIG_RET_SPIQ(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPIQ_SHIFT) & EFUSE_SPICONFIG_RET_SPIQ_MASK)
#define EFUSE_SPICONFIG_RET_SPID_MASK 0x3f
#define EFUSE_SPICONFIG_RET_SPID_SHIFT 12
#define EFUSE_SPICONFIG_RET_SPID(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPID_SHIFT) & EFUSE_SPICONFIG_RET_SPID_MASK)
#define EFUSE_SPICONFIG_RET_SPICS0_MASK 0x3f
#define EFUSE_SPICONFIG_RET_SPICS0_SHIFT 18
#define EFUSE_SPICONFIG_RET_SPICS0(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPICS0_SHIFT) & EFUSE_SPICONFIG_RET_SPICS0_MASK)
#define EFUSE_SPICONFIG_RET_SPIHD_MASK 0x3f
#define EFUSE_SPICONFIG_RET_SPIHD_SHIFT 24
#define EFUSE_SPICONFIG_RET_SPIHD(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPIHD_SHIFT) & EFUSE_SPICONFIG_RET_SPIHD_MASK)
/**
* @brief A crc8 algorithm used in efuse check.
*
* @param unsigned char const *p : Pointer to original data.
*
* @param unsigned int len : Data length in byte.
*
* @return unsigned char: Crc value.
*/
unsigned char esp_crc8(unsigned char const *p, unsigned int len);
/**
* @}
*/
#ifdef __cplusplus
}
#endif

675
components/esp32/include/rom/ets_sys.h
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@@ -24,82 +24,242 @@
extern "C" {
#endif
#define ETS_DEBUG
#define ETS_SERIAL_ENABLED() (1)
/** \defgroup ets_sys_apis, ets system related apis
* @brief ets system apis
*/
/** @addtogroup ets_sys_apis
* @{
*/
/************************************************************************
* NOTE
* Many functions in this header files can't be run in FreeRTOS.
* Please see the comment of the Functions.
* There are also some functions that doesn't work on FreeRTOS
* without listed in the header, such as:
* xtos functions start with "_xtos_" in ld file.
*
***********************************************************************
*/
/** \defgroup ets_apis, Espressif Task Scheduler related apis
* @brief ets apis
*/
/** @addtogroup ets_apis
* @{
*/
typedef enum {
ETS_OK = 0,
ETS_FAILED = 1
ETS_OK = 0, /**< return successful in ets*/
ETS_FAILED = 1 /**< return failed in ets*/
} ETS_STATUS;
typedef uint32_t ETSSignal;
typedef uint32_t ETSParam;
typedef struct ETSEventTag ETSEvent;
typedef struct ETSEventTag ETSEvent; /**< Event transmit/receive in ets*/
struct ETSEventTag {
ETSSignal sig;
ETSParam par;
ETSSignal sig; /**< Event signal, in same task, different Event with different signal*/
ETSParam par; /**< Event parameter, sometimes without usage, then will be set as 0*/
};
typedef void (*ETSTask)(ETSEvent *e);
enum ETS_User_Priorities {
/* task priorities... */
TICK_TASK_A_PRIO = 2,
KBD_TASK_PRIO = 5,
MAX_ETS_USER_PRIO = 16,
/* ISR priorities... */
MAX_ETS_USER_ISR_PRIO = 0xFF - 16
};
/* ETS interrupt entry and exit */
/* actually we don't need the following 2 macros any more since we won't exit
* isr until it is finised, more over, we don't do nest interrupt
*/
typedef void (*ETSTask)(ETSEvent *e); /**< Type of the Task processer*/
typedef void (* ets_idle_cb_t)(void *arg); /**< Type of the system idle callback*/
/**
* @brief Start the Espressif Task Scheduler, which is an infinit loop. Please do not add code after it.
*
* @param none
*
* @return none
*/
void ets_run(void);
/**
* @brief Set the Idle callback, when Tasks are processed, will call the callback before CPU goto sleep.
*
* @param ets_idle_cb_t func : The callback function.
*
* @param void *arg : Argument of the callback.
*
* @return None
*/
void ets_set_idle_cb(ets_idle_cb_t func, void *arg);
/**
* @brief Init a task with processer, priority, queue to receive Event, queue length.
*
* @param ETSTask task : The task processer.
*
* @param uint8_t prio : Task priority, 0-31, bigger num with high priority, one priority with one task.
*
* @param ETSEvent *queue : Queue belongs to the task, task always receives Events, Queue is circular used.
*
* @param uint8_t qlen : Queue length.
*
* @return None
*/
void ets_task(ETSTask task, uint8_t prio, ETSEvent *queue, uint8_t qlen);
ETS_STATUS ets_post(uint8_t prio, ETSSignal sig, ETSParam par);
/**
* @brief Post an event to an Task.
*
* @param uint8_t prio : Priority of the Task.
*
* @param ETSSignal sig : Event signal.
*
* @param ETSParam par : Event parameter
*
* @return ETS_OK : post successful
* @return ETS_FAILED : post failed
*/
ETS_STATUS ets_post(uint8_t prio, ETSSignal sig, ETSParam par);
/*
* now things become complicated, print could be directed to uart and/or SDIO
*/
/**
* @}
*/
/** \defgroup ets_boot_apis, Boot routing related apis
* @brief ets boot apis
*/
/** @addtogroup ets_apis
* @{
*/
extern const char *const exc_cause_table[40]; ///**< excption cause that defined by the core.*/
/**
* @brief Set Pro cpu Entry code, code can be called in PRO CPU when booting is not completed.
* When Pro CPU booting is completed, Pro CPU will call the Entry code if not NULL.
*
* @param uint32_t start : the PRO Entry code address value in uint32_t
*
* @return None
*/
void ets_set_user_start(uint32_t start);
/**
* @brief Set Pro cpu Startup code, code can be called when booting is not completed, or in Entry code.
* When Entry code completed, CPU will call the Startup code if not NULL, else call ets_run.
*
* @param uint32_t callback : the Startup code address value in uint32_t
*
* @return None : post successful
*/
void ets_set_startup_callback(uint32_t callback);
/**
* @brief Set App cpu Entry code, code can be called in PRO CPU.
* When APP booting is completed, APP CPU will call the Entry code if not NULL.
*
* @param uint32_t start : the APP Entry code address value in uint32_t, stored in register APPCPU_CTRL_REG_D.
*
* @return None
*/
void ets_set_appcpu_boot_addr(uint32_t start);
/**
* @brief unpack the image in flash to iram and dram, no using cache.
*
* @param uint32_t pos : Flash physical address.
*
* @param uint32_t *entry_addr: the pointer of an variable that can store Entry code address.
*
* @param bool jump : Jump into the code in the function or not.
*
* @param bool config : Config the flash when unpacking the image, config should be done only once.
*
* @return ETS_OK : unpack successful
* @return ETS_FAILED : unpack failed
*/
ETS_STATUS ets_unpack_flash_code_legacy(uint32_t pos, uint32_t *entry_addr, bool jump, bool config);
/**
* @brief unpack the image in flash to iram and dram, using cache, maybe decrypting.
*
* @param uint32_t pos : Flash physical address.
*
* @param uint32_t *entry_addr: the pointer of an variable that can store Entry code address.
*
* @param bool jump : Jump into the code in the function or not.
*
* @param bool sb_need_check : Do security boot check or not.
*
* @param bool config : Config the flash when unpacking the image, config should be done only once.
*
* @return ETS_OK : unpack successful
* @return ETS_FAILED : unpack failed
*/
ETS_STATUS ets_unpack_flash_code(uint32_t pos, uint32_t *entry_addr, bool jump, bool sb_need_check, bool config);
/**
* @}
*/
/** \defgroup ets_printf_apis, ets_printf related apis used in ets
* @brief ets printf apis
*/
/** @addtogroup ets_printf_apis
* @{
*/
/**
* @brief Printf the strings to uart or other devices, similar with printf, simple than printf.
* Can not print float point data format, or longlong data format.
* So we maybe only use this in ROM.
*
* @param const char *fmt : See printf.
*
* @param ... : See printf.
*
* @return int : the length printed to the output device.
*/
int ets_printf(const char *fmt, ...);
/* by default it's UART, just install_uart_printf, set putc1 to NULL to disable */
/**
* @brief Output a char to uart, which uart to output(which is in uart module in ROM) is not in scope of the function.
* Can not print float point data format, or longlong data format
*
* @param char c : char to output.
*
* @return None
*/
void ets_write_char_uart(char c);
/**
* @brief Ets_printf have two output functions： putc1 and putc2, both of which will be called if need ouput.
* To install putc1, which is defaulted installed as ets_write_char_uart in none silent boot mode, as NULL in silent mode.
*
* @param void (*)(char) p: Output function to install.
*
* @return None
*/
void ets_install_putc1(void (*p)(char c));
void ets_install_uart_printf(void);
/* no need to install, call directly */
int ets_uart_printf(const char *fmt, ...);
/* usually we don't need to call this, unless we want to disable SDIO print */
/**
* @brief Ets_printf have two output functions： putc1 and putc2, both of which will be called if need ouput.
* To install putc2, which is defaulted installed as NULL.
*
* @param void (*)(char) p: Output function to install.
*
* @return None
*/
void ets_install_putc2(void (*p)(char c));
/* @prepare_buf: allocate buffer for printf internal writting
* @putc: just set to NULL, let printf write to to buffer, unless if you want more fancy stuff
* @post_printf: will be called every time printf finish write buffer
*
* main idea of external printf is re-directing content to an external buffer.
* e.g. sip module allocates an event buffer in prepare_buf() and send the event to host in post_printf()
* moreover, you can check printf_buf_remain_len in post_printf(), send the event to host till buf is
* about to full.
*
* TBD: Another approach is sending printf parameter to host and let host to decode, which could save some bytes.
*/
void ets_install_external_printf(void (*prepare_buf)(char ** bufptr, uint16_t *buflen, uint32_t *cookie),
void (*putc)(char c),
void (*post_printf)(uint32_t cookie));
uint16_t est_get_printf_buf_remain_len(void);
void est_reset_printf_buf_len(void);
/* external (SDIO) printf only, still need to install*/
int ets_external_printf(const char *fmt, ...);
/**
* @brief Install putc1 as ets_write_char_uart.
* In silent boot mode(to void interfere the UART attached MCU), we can call this function, after booting ok.
*
* @param None
*
* @return None
*/
void ets_install_uart_printf(void);
#define ETS_PRINTF(...) ets_printf(...)
@@ -110,82 +270,251 @@ int ets_external_printf(const char *fmt, ...);
} \
} while (0);
/* memory and string support */
int8_t ets_char2xdigit(char ch);
uint8_t * ets_str2macaddr(uint8_t *macaddr, char *str);
void ets_getc(char *c);
void ets_putc(char c);
/**
* @}
*/
/* timer related */
typedef uint32_t ETSHandle;
typedef void ETSTimerFunc(void *timer_arg);
/** \defgroup ets_timer_apis, ets_timer related apis used in ets
* @brief ets timer apis
*/
/** @addtogroup ets_timer_apis
* @{
*/
typedef void ETSTimerFunc(void *timer_arg);/**< timer handler*/
typedef struct _ETSTIMER_ {
struct _ETSTIMER_ *timer_next;
uint32_t timer_expire;
uint32_t timer_period;
ETSTimerFunc *timer_func;
void *timer_arg;
struct _ETSTIMER_ *timer_next; /**< timer linker*/
uint32_t timer_expire; /**< abstruct time when timer expire*/
uint32_t timer_period; /**< timer period, 0 means timer is not periodic repeated*/
ETSTimerFunc *timer_func; /**< timer handler*/
void *timer_arg; /**< timer handler argument*/
} ETSTimer;
/**
* @brief Init ets timer, this timer range is 640 us to 429496 ms
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param None
*
* @return None
*/
void ets_timer_init(void);
/**
* @brief Arm an ets timer, this timer range is 640 us to 429496 ms.
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param ETSTimer *timer : Timer struct pointer.
*
* @param uint32_t tmout : Timer value in ms, range is 1 to 429496.
*
* @param bool repeat : Timer is periodic repeated.
*
* @return None
*/
void ets_timer_arm(ETSTimer *timer, uint32_t tmout, bool repeat);
/**
* @brief Arm an ets timer, this timer range is 640 us to 429496 ms.
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param ETSTimer *timer : Timer struct pointer.
*
* @param uint32_t tmout : Timer value in us, range is 1 to 429496729.
*
* @param bool repeat : Timer is periodic repeated.
*
* @return None
*/
void ets_timer_arm_us(ETSTimer *ptimer, uint32_t us, bool repeat);
/**
* @brief Disarm an ets timer.
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param ETSTimer *timer : Timer struct pointer.
*
* @return None
*/
void ets_timer_disarm(ETSTimer *timer);
void ets_timer_done(ETSTimer *ptimer);
/**
* @brief Set timer callback and argument.
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param ETSTimer *timer : Timer struct pointer.
*
* @param ETSTimerFunc *pfunction : Timer callback.
*
* @param void *parg : Timer callback argument.
*
* @return None
*/
void ets_timer_setfn(ETSTimer *ptimer, ETSTimerFunc *pfunction, void *parg);
/* watchdog related */
typedef enum {
WDT_NONE = -1,
WDT_DISABLED = 0,
WDT_CONTROL_RESET = 1,
WDT_CONTROL_INTR = 2, /* usually we use this mode? */
WDT_CONTROL_EXTERNAL_FEED = 3,
WDT_TESET_OVERFLOW = 4, // intend to make watchdog overflow to test
} WDT_MODE;
/**
* @brief Unset timer callback and argument to NULL.
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param ETSTimer *timer : Timer struct pointer.
*
* @return None
*/
void ets_timer_done(ETSTimer *ptimer);
typedef enum{
WDT_INTERVAL_THREE_SEC = 3,
WDT_INTERVAL_SIX_SEC = 6,
WDT_INTERVAL_TWELVE_SEC = 12,
} WDT_INTERVAL_TIME;
/**
* @brief CPU do while loop for some time.
* In FreeRTOS task, please call FreeRTOS apis.
*
* @param uint32_t us : Delay time in us.
*
* @return None
*/
void ets_delay_us(uint32_t us);
void ets_wdt_init(void);
WDT_MODE ets_wdt_get_mode(void);
void ets_wdt_enable(WDT_MODE mode, WDT_INTERVAL_TIME feed_interval,
WDT_INTERVAL_TIME expire_interval);
WDT_MODE ets_wdt_disable(void);
void ets_wdt_restore(WDT_MODE old_mode);
/**
* @brief Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate.
* Call this function when CPU frequency is changed.
*
* @param uint32_t ticks_per_us : CPU ticks per us.
*
* @return None
*/
void ets_update_cpu_frequency(uint32_t ticks_per_us);
/* interrupt related */
typedef void (* ets_isr_t)(void *);
/**
* @brief Get the real CPU ticks per us to the ets.
* This function do not return real CPU ticks per us, just the record in ets. It can be used to check with the real CPU frequency.
*
* @param None
*
* @return uint32_t : CPU ticks per us record in ets.
*/
uint32_t ets_get_cpu_frequency(void);
#define ETS_WMAC_SOURCE 0
#define ETS_SLC_SOURCE 1
#define ETS_UART_SOURCE 13
#define ETS_UART1_SOURCE 14
#define ETS_FRC_TIMER2_SOURCE 43
/**
* @brief Get xtal_freq/analog_8M*256 value calibrated in rtc module.
*
* @param None
*
* @return uint32_t : xtal_freq/analog_8M*256.
*/
uint32_t ets_get_xtal_scale(void);
#define ETS_WMAC_INUM 0
#define ETS_SLC_INUM 1
#define ETS_SPI_INUM 2
#define ETS_HSIP_INUM 2
#define ETS_I2S_INUM 2
#define ETS_RTC_INUM 3
#define ETS_FRC_TIMER1_INUM 9 /* use edge*/
#define ETS_FRC_TIMER2_INUM 10 /* use edge*/
#define ETS_WDT_INUM 8 /* use edge*/
#define ETS_GPIO_INUM 4
#define ETS_UART_INUM 5
#define ETS_UART1_INUM 5
#define ETS_MAX_INUM 6
/**
* @brief Get xtal_freq value, If value not stored in RTC_STORE5, than store.
*
* @param None
*
* @return uint32_t : if rtc store the value (RTC_STORE5 high 16 bits and low 16 bits with same value), read from rtc register.
* clock = (REG_READ(RTC_STORE5) & 0xffff) << 12;
* else if analog_8M in efuse
* clock = ets_get_xtal_scale() * 15625 * ets_efuse_get_8M_clock() / 40;
* else clock = 26M.
*/
uint32_t ets_get_detected_xtal_freq(void);
/**
* @}
*/
/** \defgroup ets_intr_apis, ets interrupt configure related apis
* @brief ets intr apis
*/
/** @addtogroup ets_intr_apis
* @{
*/
typedef void (* ets_isr_t)(void *);/**< interrupt handler type*/
/**
* @brief Attach a interrupt handler to a CPU interrupt number.
* This function equals to _xtos_set_interrupt_handler_arg(i, func, arg).
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param int i : CPU interrupt number.
*
* @param ets_isr_t func : Interrupt handler.
*
* @param void *arg : argument of the handler.
*
* @return None
*/
void ets_isr_attach(int i, ets_isr_t func, void *arg);
/**
* @brief Mask the interrupts which show in mask bits.
* This function equals to _xtos_ints_off(mask).
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param uint32_t mask : BIT(i) means mask CPU interrupt number i.
*
* @return None
*/
void ets_isr_mask(uint32_t mask);
/**
* @brief Unmask the interrupts which show in mask bits.
* This function equals to _xtos_ints_on(mask).
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param uint32_t mask : BIT(i) means mask CPU interrupt number i.
*
* @return None
*/
void ets_isr_unmask(uint32_t unmask);
/**
* @brief Lock the interrupt to level 2.
* This function direct set the CPU registers.
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param None
*
* @return None
*/
void ets_intr_lock(void);
/**
* @brief Unlock the interrupt to level 0.
* This function direct set the CPU registers.
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param None
*
* @return None
*/
void ets_intr_unlock(void);
/**
* @brief Unlock the interrupt to level 0, and CPU will go into power save mode(wait interrupt).
* This function direct set the CPU registers.
* In FreeRTOS, please call FreeRTOS apis, never call this api.
*
* @param None
*
* @return None
*/
void ets_waiti0(void);
/**
* @brief Attach an CPU interrupt to a hardware source.
* We have 4 steps to use an interrupt:
* 1.Attach hardware interrupt source to CPU. intr_matrix_set(0, ETS_WIFI_MAC_INTR_SOURCE, ETS_WMAC_INUM);
* 2.Set interrupt handler. xt_set_interrupt_handler(ETS_WMAC_INUM, func, NULL);
* 3.Enable interrupt for CPU. xt_ints_on(1 << ETS_WMAC_INUM);
* 4.Enable interrupt in the module.
*
* @param int cpu_no : The CPU which the interrupt number belongs.
*
* @param uint32_t model_num : The interrupt hardware source number, please see the interrupt hardware source table.
*
* @param uint32_t intr_num : The interrupt number CPU, please see the interrupt cpu using table.
*
* @return None
*/
void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num);
#define _ETSTR(v) # v
@@ -194,126 +523,80 @@ void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num);
: "=a" (__tmp) : : "memory" ); \
})
#ifdef CONFIG_NONE_OS
#define ETS_INTR_LOCK() \
ets_intr_lock()
ets_intr_lock()
#define ETS_INTR_UNLOCK() \
ets_intr_unlock()
#define ETS_CCOMPARE_INTR_ATTACH(func, arg) \
ets_isr_attach(ETS_CCOMPARE_INUM, (func), (void *)(arg))
#define ETS_PWM_INTR_ATTACH(func, arg) \
ets_isr_attach(ETS_PWM_INUM, (func), (void *)(arg))
#define ETS_WMAC_INTR_ATTACH(func, arg) \
ets_isr_attach(ETS_WMAC_INUM, (func), (void *)(arg))
#define ETS_FRC_TIMER1_INTR_ATTACH(func, arg) \
ets_isr_attach(ETS_FRC_TIMER1_INUM, (func), (void *)(arg))
#define ETS_FRC_TIMER2_INTR_ATTACH(func, arg) \
ets_isr_attach(ETS_FRC_TIMER2_INUM, (func), (void *)(arg))
#define ETS_GPIO_INTR_ATTACH(func, arg) \
ets_isr_attach(ETS_GPIO_INUM, (func), (void *)(arg))
#define ETS_UART_INTR_ATTACH(func, arg) \
ets_isr_attach(ETS_UART_INUM, (func), (void *)(arg))
#define ETS_WDT_INTR_ATTACH(func, arg) \
ets_isr_attach(ETS_WDT_INUM, (func), (void *)(arg))
#define ETS_RTC_INTR_ATTACH(func, arg) \
ets_isr_attach(ETS_RTC_INUM, (func), (void *)(arg))
#define ETS_SLC_INTR_ATTACH(func, arg) \
ets_isr_attach(ETS_SLC_INUM, (func), (void *)(arg))
ets_intr_unlock()
#define ETS_ISR_ATTACH \
ets_isr_attach
#define ETS_INTR_ENABLE(inum) \
xt_ints_on((1<<inum))
ets_isr_unmask((1<<inum))
#define ETS_INTR_DISABLE(inum) \
xt_ints_off((1<<inum))
ets_isr_mask((1<<inum))
#define ETS_CCOMPARE_INTR_ENBALE() \
ETS_INTR_ENABLE(ETS_CCOMPARE_INUM)
#define ETS_WMAC_INTR_ATTACH(func, arg) \
ETS_ISR_ATTACH(ETS_WMAC_INUM, (func), (void *)(arg))
#define ETS_CCOMPARE_INTR_DISBALE() \
ETS_INTR_DISABLE(ETS_CCOMPARE_INUM)
#define ETS_TG0_T0_INTR_ATTACH(func, arg) \
ETS_ISR_ATTACH(ETS_TG0_T0_INUM, (func), (void *)(arg))
#define ETS_PWM_INTR_ENABLE() \
ETS_INTR_ENABLE(ETS_PWM_INUM)
#define ETS_GPIO_INTR_ATTACH(func, arg) \
ETS_ISR_ATTACH(ETS_GPIO_INUM, (func), (void *)(arg))
#define ETS_PWM_INTR_DISABLE() \
ETS_INTR_DISABLE(ETS_PWM_INUM)
#define ETS_UART0_INTR_ATTACH(func, arg) \
ETS_ISR_ATTACH(ETS_UART0_INUM, (func), (void *)(arg))
#define ETS_WDT_INTR_ATTACH(func, arg) \
ETS_ISR_ATTACH(ETS_WDT_INUM, (func), (void *)(arg))
#define ETS_SLC_INTR_ATTACH(func, arg) \
ETS_ISR_ATTACH(ETS_SLC_INUM, (func), (void *)(arg))
#define ETS_BB_INTR_ENABLE() \
ETS_INTR_ENABLE(ETS_BB_INUM)
ETS_INTR_ENABLE(ETS_BB_INUM)
#define ETS_BB_INTR_DISABLE() \
ETS_INTR_DISABLE(ETS_BB_INUM)
ETS_INTR_DISABLE(ETS_BB_INUM)
#define ETS_UART_INTR_ENABLE() \
ETS_INTR_ENABLE(ETS_UART_INUM)
#define ETS_UART0_INTR_ENABLE() \
ETS_INTR_ENABLE(ETS_UART0_INUM)
#define ETS_UART_INTR_DISABLE() \
ETS_INTR_DISABLE(ETS_UART_INUM)
#define ETS_UART0_INTR_DISABLE() \
ETS_INTR_DISABLE(ETS_UART0_INUM)
#define ETS_GPIO_INTR_ENABLE() \
ETS_INTR_ENABLE(ETS_GPIO_INUM)
ETS_INTR_ENABLE(ETS_GPIO_INUM)
#define ETS_GPIO_INTR_DISABLE() \
ETS_INTR_DISABLE(ETS_GPIO_INUM)
ETS_INTR_DISABLE(ETS_GPIO_INUM)
#define ETS_WDT_INTR_ENABLE() \
ETS_INTR_ENABLE(ETS_WDT_INUM)
ETS_INTR_ENABLE(ETS_WDT_INUM)
#define ETS_WDT_INTR_DISABLE() \
ETS_INTR_DISABLE(ETS_WDT_INUM)
ETS_INTR_DISABLE(ETS_WDT_INUM)
#define ETS_FRC1_INTR_ENABLE() \
ETS_INTR_ENABLE(ETS_FRC_TIMER1_INUM)
#define ETS_TG0_T0_INTR_ENABLE() \
ETS_INTR_ENABLE(ETS_TG0_T0_INUM)
#define ETS_FRC1_INTR_DISABLE() \
ETS_INTR_DISABLE(ETS_FRC_TIMER1_INUM)
#define ETS_FRC2_INTR_ENABLE() \
ETS_INTR_ENABLE(ETS_FRC_TIMER2_INUM)
#define ETS_FRC2_INTR_DISABLE() \
ETS_INTR_DISABLE(ETS_FRC_TIMER2_INUM)
#define ETS_RTC_INTR_ENABLE() \
ETS_INTR_ENABLE(ETS_RTC_INUM)
#define ETS_RTC_INTR_DISABLE() \
ETS_INTR_DISABLE(ETS_RTC_INUM)
#define ETS_TG0_T0_INTR_DISABLE() \
ETS_INTR_DISABLE(ETS_TG0_T0_INUM)
#define ETS_SLC_INTR_ENABLE() \
ETS_INTR_ENABLE(ETS_SLC_INUM)
ETS_INTR_ENABLE(ETS_SLC_INUM)
#define ETS_SLC_INTR_DISABLE() \
ETS_INTR_DISABLE(ETS_SLC_INUM)
void ets_delay_us(uint32_t us);
void ets_update_cpu_frequency(uint32_t ticks_per_us);
uint32_t ets_get_xtal_scale();
uint32_t ets_get_detected_xtal_freq();
#if 0
#define isdigit(c) ((c >= '0') && (c <= '9'))
#define isxdigit(c) (((c >= '0') && (c <= '9')) || \
((c >= 'a') && (c <= 'f')) || \
((c >= 'A') && (c <= 'F')) )
#define isblank(c) ((c == ' ') || (c == '\t'))
#define isupper(c) ((c >= 'A') && (c <= 'Z'))
ETS_INTR_DISABLE(ETS_SLC_INUM)
#endif
/**
* @}
*/
#ifndef MAC2STR
#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5]
@@ -322,6 +605,10 @@ uint32_t ets_get_detected_xtal_freq();
#define ETS_MEM_BAR() asm volatile ( "" : : : "memory" )
/**
* @}
*/
#ifdef __cplusplus
}
#endif

308
components/esp32/include/rom/gpio.h
View File

@@ -25,6 +25,14 @@
extern "C" {
#endif
/** \defgroup gpio_apis, uart configuration and communication related apis
* @brief gpio apis
*/
/** @addtogroup gpio_apis
* @{
*/
#define GPIO_REG_READ(reg) READ_PERI_REG(reg)
#define GPIO_REG_WRITE(reg, val) WRITE_PERI_REG(reg, val)
#define GPIO_PIN_COUNT 40
@@ -37,17 +45,14 @@ extern "C" {
#define GPIO_REGID_TO_PINIDX(reg_id) ((reg_id) - GPIO_ID_PIN0)
typedef enum{
GPIO_PIN_INTR_DISABLE = 0,
GPIO_PIN_INTR_POSEDGE = 1,
GPIO_PIN_INTR_NEGEDGE = 2,
GPIO_PIN_INTR_ANYEGDE = 3,
GPIO_PIN_INTR_LOLEVEL = 4,
GPIO_PIN_INTR_HILEVEL = 5
}GPIO_INT_TYPE;
#define GREEN_LED_ON() GPIO_OUTPUT_SET(GPIO_ID_PIN(1) , 0)
#define GREEN_LED_OFF() GPIO_OUTPUT_SET(GPIO_ID_PIN(1) , 1)
typedef enum {
GPIO_PIN_INTR_DISABLE = 0,
GPIO_PIN_INTR_POSEDGE = 1,
GPIO_PIN_INTR_NEGEDGE = 2,
GPIO_PIN_INTR_ANYEGDE = 3,
GPIO_PIN_INTR_LOLEVEL = 4,
GPIO_PIN_INTR_HILEVEL = 5
} GPIO_INT_TYPE;
#define GPIO_OUTPUT_SET(gpio_no, bit_value) \
((gpio_no < 32) ? gpio_output_set(bit_value<<gpio_no, (bit_value ? 0 : 1)<<gpio_no, 1<<gpio_no,0) : \
@@ -58,82 +63,235 @@ typedef enum{
/* GPIO interrupt handler, registered through gpio_intr_handler_register */
typedef void (* gpio_intr_handler_fn_t)(uint32_t intr_mask, bool high, void *arg);
/**
* @brief Initialize GPIO. This includes reading the GPIO Configuration DataSet
* to initialize "output enables" and pin configurations for each gpio pin.
* Please do not call this function in SDK.
*
* @param None
*
* @return None
*/
void gpio_init(void);
/*
* Initialize GPIO. This includes reading the GPIO Configuration DataSet
* to initialize "output enables" and pin configurations for each gpio pin.
* Must be called once during startup.
*/
void gpio_init(void) ROMFN_ATTR;
/**
* @brief Change GPIO(0-31) pin output by setting, clearing, or disabling pins, GPIO0<->BIT(0).
* There is no particular ordering guaranteed; so if the order of writes is significant,
* calling code should divide a single call into multiple calls.
*
* @param uint32_t set_mask : the gpios that need high level.
*
* @param uint32_t clear_mask : the gpios that need low level.
*
* @param uint32_t enable_mask : the gpios that need be changed.
*
* @param uint32_t disable_mask : the gpios that need diable output.
*
* @return None
*/
void gpio_output_set(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask);
/*
* Change GPIO pin output by setting, clearing, or disabling pins.
* In general, it is expected that a bit will be set in at most one
* of these masks. If a bit is clear in all masks, the output state
* remains unchanged.
*
* There is no particular ordering guaranteed; so if the order of
* writes is significant, calling code should divide a single call
* into multiple calls.
*/
void gpio_output_set(uint32_t set_mask,
uint32_t clear_mask,
uint32_t enable_mask,
uint32_t disable_mask) ROMFN_ATTR;
void gpio_output_set_high(uint32_t set_mask,
uint32_t clear_mask,
uint32_t enable_mask,
uint32_t disable_mask) ROMFN_ATTR;
/*
* Sample the value of GPIO input pins and returns a bitmask.
*/
uint32_t gpio_input_get(void) ROMFN_ATTR;
uint32_t gpio_input_get_high(void) ROMFN_ATTR;
/**
* @brief Change GPIO(32-39) pin output by setting, clearing, or disabling pins, GPIO32<->BIT(0).
* There is no particular ordering guaranteed; so if the order of writes is significant,
* calling code should divide a single call into multiple calls.
*
* @param uint32_t set_mask : the gpios that need high level.
*
* @param uint32_t clear_mask : the gpios that need low level.
*
* @param uint32_t enable_mask : the gpios that need be changed.
*
* @param uint32_t disable_mask : the gpios that need diable output.
*
* @return None
*/
void gpio_output_set_high(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask);
/*
* Set the specified GPIO register to the specified value.
* This is a very general and powerful interface that is not
* expected to be used during normal operation. It is intended
* mainly for debug, or for unusual requirements.
*/
void gpio_register_set(uint32_t reg_id, uint32_t value) ROMFN_ATTR;
/**
* @brief Sample the value of GPIO input pins(0-31) and returns a bitmask.
*
* @param None
*
* @return uint32_t : bitmask for GPIO input pins, BIT(0) for GPIO0.
*/
uint32_t gpio_input_get(void);
/* Get the current value of the specified GPIO register. */
uint32_t gpio_register_get(uint32_t reg_id) ROMFN_ATTR;
/**
* @brief Sample the value of GPIO input pins(32-39) and returns a bitmask.
*
* @param None
*
* @return uint32_t : bitmask for GPIO input pins, BIT(0) for GPIO32.
*/
uint32_t gpio_input_get_high(void);
/*
* Register an application-specific interrupt handler for GPIO pin
* interrupts. Once the interrupt handler is called, it will not
* be called again until after a call to gpio_intr_ack. Any GPIO
* interrupts that occur during the interim are masked.
*
* The application-specific handler is called with a mask of
* pending GPIO interrupts. After processing pin interrupts, the
* application-specific handler may wish to use gpio_intr_pending
* to check for any additional pending interrupts before it returns.
*/
void gpio_intr_handler_register(gpio_intr_handler_fn_t fn, void *arg) ROMFN_ATTR;
/**
* @brief Register an application-specific interrupt handler for GPIO pin interrupts.
* Once the interrupt handler is called, it will not be called again until after a call to gpio_intr_ack.
* Please do not call this function in SDK.
*
* @param gpio_intr_handler_fn_t fn : gpio application-specific interrupt handler
*
* @param void *arg : gpio application-specific interrupt handler argument.
*
* @return None
*/
void gpio_intr_handler_register(gpio_intr_handler_fn_t fn, void *arg);
/* Determine which GPIO interrupts are pending. */
uint32_t gpio_intr_pending(void) ROMFN_ATTR;
uint32_t gpio_intr_pending_high(void) ROMFN_ATTR;
/**
* @brief Get gpio interrupts which happens but not processed.
* Please do not call this function in SDK.
*
* @param None
*
* @return uint32_t : bitmask for GPIO pending interrupts, BIT(0) for GPIO0.
*/
uint32_t gpio_intr_pending(void);
/*
* Acknowledge GPIO interrupts.
* Intended to be called from the gpio_intr_handler_fn.
*/
void gpio_intr_ack(uint32_t ack_mask) ROMFN_ATTR;
void gpio_intr_ack_high(uint32_t ack_mask) ROMFN_ATTR;
/**
* @brief Get gpio interrupts which happens but not processed.
* Please do not call this function in SDK.
*
* @param None
*
* @return uint32_t : bitmask for GPIO pending interrupts, BIT(0) for GPIO32.
*/
uint32_t gpio_intr_pending_high(void);
void gpio_pin_wakeup_enable(uint32_t i, GPIO_INT_TYPE intr_state) ROMFN_ATTR;
/**
* @brief Ack gpio interrupts to process pending interrupts.
* Please do not call this function in SDK.
*
* @param uint32_t ack_mask: bitmask for GPIO ack interrupts, BIT(0) for GPIO0.
*
* @return None
*/
void gpio_intr_ack(uint32_t ack_mask);
void gpio_pin_wakeup_disable() ROMFN_ATTR;
/**
* @brief Ack gpio interrupts to process pending interrupts.
* Please do not call this function in SDK.
*
* @param uint32_t ack_mask: bitmask for GPIO ack interrupts, BIT(0) for GPIO32.
*
* @return None
*/
void gpio_intr_ack_high(uint32_t ack_mask);
//extern void gpio_module_install(struct gpio_api *api);
/**
* @brief Set GPIO to wakeup the ESP32.
* Please do not call this function in SDK.
*
* @param uint32_t i: gpio number.
*
* @param GPIO_INT_TYPE intr_state : only GPIO_PIN_INTR_LOLEVEL\GPIO_PIN_INTR_HILEVEL can be used
*
* @return None
*/
void gpio_pin_wakeup_enable(uint32_t i, GPIO_INT_TYPE intr_state);
void gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv) ROMFN_ATTR;
/**
* @brief disable GPIOs to wakeup the ESP32.
* Please do not call this function in SDK.
*
* @param None
*
* @return None
*/
void gpio_pin_wakeup_disable(void);
void gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, bool out_inv, bool oen_inv) ROMFN_ATTR;
/**
* @brief set gpio input to a signal, one gpio can input to several signals.
*
* @param uint32_t gpio : gpio number, 0~0x27
* gpio == 0x30, input 0 to signal
* gpio == 0x34, ???
* gpio == 0x38, input 1 to signal
*
* @param uint32_t signal_idx : signal index.
*
* @param bool inv : the signal is inv or not
*
* @return None
*/
void gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv);
/**
* @brief set signal output to gpio, one signal can output to several gpios.
*
* @param uint32_t gpio : gpio number, 0~0x27
*
* @param uint32_t signal_idx : signal index.
* signal_idx == 0x100, cancel output put to the gpio
*
* @param bool out_inv : the signal output is inv or not
*
* @param bool oen_inv : the signal output enable is inv or not
*
* @return None
*/
void gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, bool out_inv, bool oen_inv);
/**
* @brief Select pad as a gpio function from IOMUX.
*
* @param uint32_t gpio_num : gpio number, 0~0x27
*
* @return None
*/
void gpio_pad_select_gpio(uint8_t gpio_num);
/**
* @brief Set pad driver capability.
*
* @param uint32_t gpio_num : gpio number, 0~0x27
*
* @param uint8_t drv : 0-3
*
* @return None
*/
void gpio_pad_set_drv(uint8_t gpio_num, uint8_t drv);
/**
* @brief Pull up the pad from gpio number.
*
* @param uint32_t gpio_num : gpio number, 0~0x27
*
* @return None
*/
void gpio_pad_pullup(uint8_t gpio_num);
/**
* @brief Pull down the pad from gpio number.
*
* @param uint32_t gpio_num : gpio number, 0~0x27
*
* @return None
*/
void gpio_pad_pulldown(uint8_t gpio_num);
/**
* @brief Unhold the pad from gpio number.
*
* @param uint32_t gpio_num : gpio number, 0~0x27
*
* @return None
*/
void gpio_pad_unhold(uint8_t gpio_num);
/**
* @brief Hold the pad from gpio number.
*
* @param uint32_t gpio_num : gpio number, 0~0x27
*
* @return None
*/
void gpio_pad_hold(uint8_t gpio_num);
/**
* @}
*/
#ifdef __cplusplus
}

184
components/esp32/include/rom/rtc.h
View File

@@ -26,30 +26,68 @@
extern "C" {
#endif
/** \defgroup rtc_apis, rtc registers and memory related apis
* @brief rtc apis
*/
/** @addtogroup rtc_apis
* @{
*/
/**************************************************************************************
* Note: *
* Some Rtc memory and registers are used, in ROM or in internal library. *
* Please do not use reserved or used rtc memory or registers. *
* *
*************************************************************************************
* RTC Memory & Store Register usage
*************************************************************************************
* rtc memory addr type size usage
* 0x3ff61000(0x50000000) Slow SIZE_CP Co-Processor code/Reset Entry
* 0x3ff61000+SIZE_CP Slow 6144-SIZE_CP
* 0x3ff62800 Slow 2048 Reserved
*
* 0x3ff80000(0x400c0000) Fast 8192 deep sleep entry code
*
*************************************************************************************
* Rtc store registers usage
* RTC_STORE0
* RTC_STORE1
* RTC_STORE2
* RTC_STORE3
* RTC_STORE4 Reserved
* RTC_STORE5 External Xtal Frequency
* RTC_STORE6 FAST_RTC_MEMORY_ENTRY
* RTC_STORE7 FAST_RTC_MEMORY_CRC
*************************************************************************************
*/
#define RTC_ENTRY_ADDR RTC_STORE6
#define RTC_MEMORY_CRC RTC_STORE7
typedef enum {
AWAKE = 0, //CPU ON
AWAKE = 0, //<CPU ON
LIGHT_SLEEP = BIT0, //CPU waiti, PLL ON. We don't need explicitly set this mode.
DEEP_SLEEP = BIT1 //CPU OFF, PLL OFF, only specific timer could wake up
} SLEEP_MODE;
typedef enum {
NO_MEAN = 0,
POWERON_RESET = 1, //1 Vbat power on reset, RTC reset
// EXT_SYS_RESET = 2, //4 External System reset, RTC reset
SW_RESET = 3, //6 Software warm reset
OWDT_RESET = 4, //5 Watch dog reset
DEEPSLEEP_RESET = 5, //2 Deep sleep timer reach reset.
SDIO_RESET = 6, //3 Deep sleep Pbint power on reset [boot]
TG0WDT_SYS_RESET = 7,
TG1WDT_SYS_RESET = 8,
RTCWDT_SYS_RESET = 9,
INTRUSION_RESET = 10,
TGWDT_CPU_RESET = 11,
SW_CPU_RESET = 12,
RTCWDT_CPU_RESET = 13,
EXT_CPU_RESET = 14,
RTCWDT_BROWN_OUT_RESET = 15,
RTCWDT_RTC_RESET = 16
POWERON_RESET = 1, /**<1, Vbat power on reset*/
SW_RESET = 3, /**<3, Software reset digital core*/
OWDT_RESET = 4, /**<4, Legacy watch dog reset digital core*/
DEEPSLEEP_RESET = 5, /**<3, Deep Sleep reset digital core*/
SDIO_RESET = 6, /**<6, Reset by SLC module, reset digital core*/
TG0WDT_SYS_RESET = 7, /**<7, Timer Group0 Watch dog reset digital core*/
TG1WDT_SYS_RESET = 8, /**<8, Timer Group1 Watch dog reset digital core*/
RTCWDT_SYS_RESET = 9, /**<9, RTC Watch dog Reset digital core*/
INTRUSION_RESET = 10, /**<10, Instrusion tested to reset CPU*/
TGWDT_CPU_RESET = 11, /**<11, Time Group reset CPU*/
SW_CPU_RESET = 12, /**<12, Software reset CPU*/
RTCWDT_CPU_RESET = 13, /**<13, RTC Watch dog Reset CPU*/
EXT_CPU_RESET = 14, /**<14, for APP CPU, reseted by PRO CPU*/
RTCWDT_BROWN_OUT_RESET = 15, /**<15, Reset when the vdd voltage is not stable*/
RTCWDT_RTC_RESET = 16 /**<16, RTC Watch dog reset digital core and rtc module*/
} RESET_REASON;
typedef enum {
@@ -98,67 +136,67 @@ typedef enum {
SDIO_IDLE_INT_EN = SDIO_IDLE_INT,
RTC_WDT_INT_EN = RTC_WDT_INT,
RTC_TIME_VALID_INT_EN = RTC_TIME_VALID_INT
}RTC_INT_EN;
// Alive memory is a special memory block which could restore data during system
// deep sleep. power management and wlan profile data may need put into this
// memory area.
// Should create a dram segment in link script.
#define ALIVE_MEMORY_ADDR
#define ALIVE_MEMORY_SIZE (1024 * 2)
void rtc_hw_init(void);
} RTC_INT_EN;
/**
* @brief Get the reset reason for CPU.
*
* @param int cpu_no : CPU no.
*
* @return RESET_REASON
*/
RESET_REASON rtc_get_reset_reason(int cpu_no);
/**
* @brief Get the wakeup cause for CPU.
*
* @param int cpu_no : CPU no.
*
* @return WAKEUP_REASON
*/
WAKEUP_REASON rtc_get_wakeup_cause(void);
/**
* @brief Get CRC for Fast RTC Memory.
*
* @param uint32_t start_addr : 0 - 0x7ff for Fast RTC Memory.
*
* @param uint32_t crc_len : 0 - 0x7ff, 0 for 1 byte, 0x7ff for 0x800 byte.
*
* @return uint32_t : CRC32 result
*/
uint32_t calc_rtc_memory_crc(uint32_t start_addr, uint32_t crc_len);
/**
* @brief Set CRC of Fast RTC memory 0-0x7ff into RTC STORE7.
*
* @param None
*
* @return None
*/
void set_rtc_memory_crc(void);
/**
* @brief Software Reset digital core.
*
* @param None
*
* @return None
*/
void software_reset(void);
/**
* @brief Software Reset digital core.
*
* @param int cpu_no : The CPU to reset, 0 for PRO CPU, 1 for APP CPU.
*
* @return None
*/
void software_reset_cpu(int cpu_no);
void rtc_select_apb_bridge(bool sel);
void rtc_set_sleep_mode(SLEEP_MODE mode, uint32_t sleep_sec, uint32_t wakeup_mode);
uint8_t ets_rtc_recovery(void);
#define MAX_DEEPSLEEP_DURATION (0xffffffff / RTC_CLK_FREQ)
#define SECOND_TO_RTC_TICK(second) ((second)*RTC_CLK_FREQ) //32KHz
#define CALIB_VALUE_TO_RTC_TICK(microsecond, clk_mkz, n_rtc,nclk) ((microsecond)*(clk_mkz)*(n_rtc)/(nclk)) //32KHz
#define RTC_TICK_TO_SECOND(tick) ((tick)/RTC_CLK_FREQ )
#define GET_CURRENT_TICK() (READ_PERI_REG(RTC_TIME))
#define SET_WAKEUP_TICK(tick) (WRITE_PERI_REG(RTC_TIMER0, tick))
//#define GET_WAKEUP_CAUSE() GET_PERI_REG_BITS2(RTC_STATE1, RTC_CNTL_WAKEUP_CAUSE, RTC_CNTL_WAKEUP_CAUSE_S)
#define DISABLE_RTC_INT(int_type) CLEAR_PERI_REG_MASK(RTC_INT_ENA, int_type)
#define ENABLE_RTC_INT(int_type) SET_PERI_REG_MASK(RTC_INT_ENA, int_type)
#define CLR_RTC_INT(int_type) SET_PERI_REG_MASK(RTC_INT_CLR, int_type)
#define GET_RTC_INT_CAUSE() GET_PERI_REG_BITS(RTC_INT_RAW, RTC_INT_RAW_MSB,RTC_INT_RAW_LSB)
void rtc_register_deepsleep_timer(ETSTimer *timer, uint32_t tmout);
void rtc_disable_deepsleep_timer(void);
void rtc_enter_sleep(void);
void ets_rtc_int_register(void);
void dtm_set_intr_mask(uint32_t mask);
uint32_t dtm_get_intr_mask(void);
void dtm_set_params(uint32_t sleep_mode, uint32_t sleep_tm_ms, uint32_t wakeup_tm_ms, uint32_t sleep_times, uint32_t rxbcn_len);
void save_rxbcn_mactime(uint32_t rxbcn_mactime);
void save_tsf_us(uint32_t tsf_us);
typedef void (* ets_idle_cb_t)(void *arg);
typedef uint32_t (* ETS_GET_MACTIME)(void);
typedef void (* ETS_WAKEUP_INIT)(void);
void dtm_params_init(ETS_GET_MACTIME get_mactime, ETS_WAKEUP_INIT wakeup_init);
void ets_set_idle_cb(ets_idle_cb_t func, void *arg);
void ets_enter_sleep(void);
void rtc_intr_handler(void *);
#define ETS_SLEEP_START(pfunc, parg) ets_set_idle_cb((pfunc), (parg));
#define ETS_SLEEP_END() ets_set_idle_cb(NULL, NULL);
/**
* @}
*/
#ifdef __cplusplus
}

5
components/esp32/include/rom/secure_boot.h
View File

@@ -11,6 +11,7 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ROM_SECURE_BOOT_H_
#define _ROM_SECURE_BOOT_H_
@@ -34,6 +35,10 @@ void ets_secure_boot_rd_iv(uint32_t *buf);
void ets_secure_boot_rd_abstract(uint32_t *buf);
bool ets_secure_boot_check_start(uint8_t abs_index, uint32_t iv_addr);
int ets_secure_boot_check_finish(uint32_t *abstract);
#ifdef __cplusplus
}
#endif

421
components/esp32/include/rom/spi_flash.h
View File

@@ -11,6 +11,7 @@
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ROM_SPI_FLASH_H_
#define _ROM_SPI_FLASH_H_
@@ -25,6 +26,45 @@
extern "C" {
#endif
/** \defgroup spi_flash_apis, spi flash operation related apis
* @brief spi_flash apis
*/
/** @addtogroup spi_flash_apis
* @{
*/
/*************************************************************
* Note
*************************************************************
* 1. ESP32 chip have 4 SPI slave/master, however, SPI0 is
* used as an SPI master to access Flash and ext-SRAM by
* Cache module. It will support Decryto read for Flash,
* read/write for ext-SRAM. And SPI1 is also used as an
* SPI master for Flash read/write and ext-SRAM read/write.
* It will support Encrypto write for Flash.
* 2. As an SPI master, SPI support Highest clock to 80M,
* however, Flash with 80M Clock should be configured
* for different Flash chips. If you want to use 80M
* clock We should use the SPI that is certified by
* Espressif. However, the certification is not started
* at the time, so please use 40M clock at the moment.
* 3. SPI Flash can use 2 lines or 4 lines mode. If you
* use 2 lines mode, you can save two pad SPIHD and
* SPIWP for gpio. ESP32 support configured SPI pad for
* Flash, the configuration is stored in efuse and flash.
* However, the configurations of pads should be certified
* by Espressif. If you use this function, please use 40M
* clock at the moment.
* 4. ESP32 support to use Common SPI command to configure
* Flash to QIO mode, if you failed to configure with fix
* command. With Common SPI Command, ESP32 can also provide
* a way to use same Common SPI command groups on different
* Flash chips.
* 5. This functions are not protected by packeting, Please use the
*************************************************************
*/
#define PERIPHS_SPI_FLASH_CMD SPI_CMD(1)
#define PERIPHS_SPI_FLASH_ADDR SPI_ADDR(1)
#define PERIPHS_SPI_FLASH_CTRL SPI_CTRL(1)
@@ -92,7 +132,7 @@ typedef enum {
SPI_FLASH_RESULT_TIMEOUT
} SpiFlashOpResult;
typedef struct{
typedef struct {
uint32_t deviceId;
uint32_t chip_size; // chip size in bytes
uint32_t block_size;
@@ -110,33 +150,362 @@ typedef struct {
uint16_t data;
} SpiCommonCmd;
void SelectSpiQIO(uint8_t wp_gpio_num, uint32_t ishspi) ROMFN_ATTR;
void SetSpiDrvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t* drvs) ROMFN_ATTR;
void SelectSpiFunction(uint32_t ishspi) ROMFN_ATTR;
SpiFlashOpResult SPIEraseChip(void) ROMFN_ATTR;
SpiFlashOpResult SPIEraseBlock(uint32_t block_num) ROMFN_ATTR;
SpiFlashOpResult SPIEraseSector(uint32_t sector_num) ROMFN_ATTR;
SpiFlashOpResult SPIWrite(uint32_t dest_addr, const uint32_t* src, int32_t len) ROMFN_ATTR;
void SPI_Write_Encrypt_Enable() ROMFN_ATTR;
SpiFlashOpResult SPI_Prepare_Encrypt_Data(uint32_t flash_addr, uint32_t* data) ROMFN_ATTR;
void SPI_Write_Encrypt_Disable() ROMFN_ATTR;
SpiFlashOpResult SPI_Encrypt_Write(uint32_t flash_addr, uint32_t* data, uint32_t len) ROMFN_ATTR;
SpiFlashOpResult SPIRead(uint32_t src_addr, uint32_t* dest, int32_t len) ROMFN_ATTR;
SpiFlashOpResult SPIReadModeCnfig(SpiFlashRdMode mode, bool legacy) ROMFN_ATTR;
SpiFlashOpResult SPIMasterReadModeCnfig(SpiFlashRdMode mode) ROMFN_ATTR;
SpiFlashOpResult SPIClkConfig(uint8_t freqdiv, uint8_t spi) ROMFN_ATTR;
uint16_t SPI_Common_Command(SpiCommonCmd * cmd) ROMFN_ATTR;
SpiFlashOpResult SPIUnlock() ROMFN_ATTR;
SpiFlashOpResult SPIEraseArea(uint32_t start_addr, uint32_t area_len) ROMFN_ATTR;
SpiFlashOpResult SPILock() ROMFN_ATTR;
SpiFlashOpResult SPIParamCfg(uint32_t deviceId, uint32_t chip_size, uint32_t block_size, uint32_t sector_size, uint32_t page_size, uint32_t status_mask) ROMFN_ATTR;
SpiFlashOpResult SPI_user_command_read(uint32_t * status, uint8_t cmd) ROMFN_ATTR;
void spi_cache_sram_init() ROMFN_ATTR;
/**
* @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed.
* Please do not call this function in SDK.
*
* @param uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write).
*
* @param uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M.
*
* @return None
*/
void spi_dummy_len_fix(uint8_t spi, uint8_t freqdiv);
//ETS_STATUS ets_unpack_flash_code(uint32_t pos, uint32_t *entry_addr, bool jump, bool sb_need_check, bool config) ROMFN_ATTR;
//ETS_STATUS ets_unpack_flash_code_legacy(uint32_t pos, uint32_t *entry_addr, bool jump, bool config) ROMFN_ATTR;
/**
* @brief Select SPI Flash to QIO mode when WP pad is read from Flash.
* Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
*/
void SelectSpiQIO(uint8_t wp_gpio_num, uint32_t ishspi);
void spi_flash_attach(uint32_t ishspi, bool legacy) ROMFN_ATTR;
/**
* @brief Set SPI Flash pad drivers.
* Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @param uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid
* drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp.
* Values usually read from falsh by rom code, function usually callde by rom code.
* if value with bit(3) set, the value is valid, bit[2:0] is the real value.
*
* @return None
*/
void SetSpiDrvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs);
/**
* @brief Select SPI Flash function for pads.
* Please do not call this function in SDK.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
*/
void SelectSpiFunction(uint32_t ishspi);
/**
* @brief SPI Flash init, clock divisor is 4, use 1 line Slow read mode.
* Please do not call this function in SDK.
*
* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @param uint8_t legacy: In legacy mode, more SPI command is used in line.
*
* @return None
*/
void spi_flash_attach(uint32_t ishspi, bool legacy);
/**
* @brief SPI Read Flash status register. We use CMD 0x05.
* Please do not call this function in SDK.
*
* @param SpiFlashChip *spi : The information for Flash, which is exported from ld file.
*
* @param uint32_t *status : The pointer to which to return the Flash status value.
*
* @return SPI_FLASH_RESULT_OK : read OK.
* SPI_FLASH_RESULT_ERR : read error.
* SPI_FLASH_RESULT_TIMEOUT : read timeout.
*/
SpiFlashOpResult SPI_read_status(SpiFlashChip *spi, uint32_t *status);
/**
* @brief SPI Read Flash status register high 16 bit. We use CMD 0x35.
* Please do not call this function in SDK.
*
* @param SpiFlashChip *spi : The information for Flash, which is exported from ld file.
*
* @param uint32_t *status : The pointer to which to return the Flash status value.
*
* @return SPI_FLASH_RESULT_OK : read OK.
* SPI_FLASH_RESULT_ERR : read error.
* SPI_FLASH_RESULT_TIMEOUT : read timeout.
*/
SpiFlashOpResult SPI_read_status_high(SpiFlashChip *spi, uint32_t *status);
/**
* @brief Write status to Falsh status register.
* Please do not call this function in SDK.
*
* @param SpiFlashChip *spi : The information for Flash, which is exported from ld file.
*
* @param uint32_t status_value : Value to .
*
* @return SPI_FLASH_RESULT_OK : write OK.
* SPI_FLASH_RESULT_ERR : write error.
* SPI_FLASH_RESULT_TIMEOUT : write timeout.
*/
SpiFlashOpResult SPI_write_status(SpiFlashChip *spi, uint32_t status_value);
/**
* @brief Use a command to Read Flash status register.
* Please do not call this function in SDK.
*
* @param SpiFlashChip *spi : The information for Flash, which is exported from ld file.
*
* @param uint32_t*status : The pointer to which to return the Flash status value.
*
* @return SPI_FLASH_RESULT_OK : read OK.
* SPI_FLASH_RESULT_ERR : read error.
* SPI_FLASH_RESULT_TIMEOUT : read timeout.
*/
SpiFlashOpResult SPI_user_command_read(uint32_t *status, uint8_t cmd);
/**
* @brief Config SPI Flash read mode when init.
* Please do not call this function in SDK.
*
* @param SpiFlashRdMode mode : QIO/QOUT/DIO/DOUT/FastRD/SlowRD.
*
* @param uint8_t legacy: In legacy mode, more SPI command is used in line.
*
* @return SPI_FLASH_RESULT_OK : config OK.
* SPI_FLASH_RESULT_ERR : config error.
* SPI_FLASH_RESULT_TIMEOUT : config timeout.
*/
SpiFlashOpResult SPIReadModeCnfig(SpiFlashRdMode mode, bool legacy);
/**
* @brief Config SPI Flash read mode when Flash is running in some mode.
* Please do not call this function in SDK.
*
* @param SpiFlashRdMode mode : QIO/QOUT/DIO/DOUT/FastRD/SlowRD.
*
* @return SPI_FLASH_RESULT_OK : config OK.
* SPI_FLASH_RESULT_ERR : config error.
* SPI_FLASH_RESULT_TIMEOUT : config timeout.
*/
SpiFlashOpResult SPIMasterReadModeCnfig(SpiFlashRdMode mode);
/**
* @brief Config SPI Flash clock divisor.
* Please do not call this function in SDK.
*
* @param uint8_t freqdiv: clock divisor.
*
* @param uint8_t spi: 0 for SPI0, 1 for SPI1.
*
* @return SPI_FLASH_RESULT_OK : config OK.
* SPI_FLASH_RESULT_ERR : config error.
* SPI_FLASH_RESULT_TIMEOUT : config timeout.
*/
SpiFlashOpResult SPIClkConfig(uint8_t freqdiv, uint8_t spi);
/**
* @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD.
* Please do not call this function in SDK.
*
* @param SpiCommonCmd *cmd : A struct to show the action of a command.
*
* @return uint16_t 0 : do not send command any more.
* 1 : go to the next command.
* n > 1 : skip (n - 1) commands.
*/
uint16_t SPI_Common_Command(SpiCommonCmd *cmd);
/**
* @brief Unlock SPI write protect.
* Please do not call this function in SDK.
*
* @param None.
*
* @return SPI_FLASH_RESULT_OK : Unlock OK.
* SPI_FLASH_RESULT_ERR : Unlock error.
* SPI_FLASH_RESULT_TIMEOUT : Unlock timeout.
*/
SpiFlashOpResult SPIUnlock(void);
/**
* @brief SPI write protect.
* Please do not call this function in SDK.
*
* @param None.
*
* @return SPI_FLASH_RESULT_OK : Lock OK.
* SPI_FLASH_RESULT_ERR : Lock error.
* SPI_FLASH_RESULT_TIMEOUT : Lock timeout.
*/
SpiFlashOpResult SPILock(void);
/**
* @brief Update SPI Flash parameter.
* Please do not call this function in SDK.
*
* @param uint32_t deviceId : Device ID read from SPI, the low 32 bit.
*
* @param uint32_t chip_size : The Flash size.
*
* @param uint32_t block_size : The Flash block size.
*
* @param uint32_t sector_size : The Flash sector size.
*
* @param uint32_t page_size : The Flash page size.
*
* @param uint32_t status_mask : The Mask used when read status from Flash(use single CMD).
*
* @return SPI_FLASH_RESULT_OK : Update OK.
* SPI_FLASH_RESULT_ERR : Update error.
* SPI_FLASH_RESULT_TIMEOUT : Update timeout.
*/
SpiFlashOpResult SPIParamCfg(uint32_t deviceId, uint32_t chip_size, uint32_t block_size, uint32_t sector_size, uint32_t page_size, uint32_t status_mask);
/**
* @brief Erase whole flash chip.
* Please do not call this function in SDK.
*
* @param None
*
* @return SPI_FLASH_RESULT_OK : Erase OK.
* SPI_FLASH_RESULT_ERR : Erase error.
* SPI_FLASH_RESULT_TIMEOUT : Erase timeout.
*/
SpiFlashOpResult SPIEraseChip(void);
/**
* @brief Erase a block of flash.
* Please do not call this function in SDK.
*
* @param uint32_t block_num : Which block to erase.
*
* @return SPI_FLASH_RESULT_OK : Erase OK.
* SPI_FLASH_RESULT_ERR : Erase error.
* SPI_FLASH_RESULT_TIMEOUT : Erase timeout.
*/
SpiFlashOpResult SPIEraseBlock(uint32_t block_num);
/**
* @brief Erase a sector of flash.
* Please do not call this function in SDK.
*
* @param uint32_t sector_num : Which sector to erase.
*
* @return SPI_FLASH_RESULT_OK : Erase OK.
* SPI_FLASH_RESULT_ERR : Erase error.
* SPI_FLASH_RESULT_TIMEOUT : Erase timeout.
*/
SpiFlashOpResult SPIEraseSector(uint32_t sector_num);
/**
* @brief Erase some sectors.
* Please do not call this function in SDK.
*
* @param uint32_t start_addr : Start addr to erase, should be sector aligned.
*
* @param uint32_t area_len : Length to erase, should be sector aligned.
*
* @return SPI_FLASH_RESULT_OK : Erase OK.
* SPI_FLASH_RESULT_ERR : Erase error.
* SPI_FLASH_RESULT_TIMEOUT : Erase timeout.
*/
SpiFlashOpResult SPIEraseArea(uint32_t start_addr, uint32_t area_len);
/**
* @brief Write Data to Flash, you should Erase it yourself if need.
* Please do not call this function in SDK.
*
* @param uint32_t dest_addr : Address to write, should be 4 bytes aligned.
*
* @param const uint32_t *src : The pointer to data which is to write.
*
* @param uint32_t len : Length to write, should be 4 bytes aligned.
*
* @return SPI_FLASH_RESULT_OK : Write OK.
* SPI_FLASH_RESULT_ERR : Write error.
* SPI_FLASH_RESULT_TIMEOUT : Write timeout.
*/
SpiFlashOpResult SPIWrite(uint32_t dest_addr, const uint32_t *src, int32_t len);
/**
* @brief Read Data from Flash, you should Erase it yourself if need.
* Please do not call this function in SDK.
*
* @param uint32_t src_addr : Address to read, should be 4 bytes aligned.
*
* @param uint32_t *dest : The buf to read the data.
*
* @param uint32_t len : Length to read, should be 4 bytes aligned.
*
* @return SPI_FLASH_RESULT_OK : Read OK.
* SPI_FLASH_RESULT_ERR : Read error.
* SPI_FLASH_RESULT_TIMEOUT : Read timeout.
*/
SpiFlashOpResult SPIRead(uint32_t src_addr, uint32_t *dest, int32_t len);
/**
* @brief SPI1 go into encrypto mode.
* Please do not call this function in SDK.
*
* @param None
*
* @return None
*/
void SPI_Write_Encrypt_Enable(void);
/**
* @brief Prepare 32 Bytes data to encrpto writing, you should Erase it yourself if need.
* Please do not call this function in SDK.
*
* @param uint32_t flash_addr : Address to write, should be 32 bytes aligned.
*
* @param uint32_t *data : The pointer to data which is to write.
*
* @return SPI_FLASH_RESULT_OK : Prepare OK.
* SPI_FLASH_RESULT_ERR : Prepare error.
* SPI_FLASH_RESULT_TIMEOUT : Prepare timeout.
*/
SpiFlashOpResult SPI_Prepare_Encrypt_Data(uint32_t flash_addr, uint32_t *data);
/**
* @brief SPI1 go out of encrypto mode.
* Please do not call this function in SDK.
*
* @param None
*
* @return None
*/
void SPI_Write_Encrypt_Disable(void);
/**
* @brief Encrpto writing data to flash, you should Erase it yourself if need.
* Please do not call this function in SDK.
*
* @param uint32_t flash_addr : Address to write, should be 32 bytes aligned.
*
* @param uint32_t *data : The pointer to data which is to write.
*
* @param uint32_t len : Length to write, should be 32 bytes aligned.
*
* @return SPI_FLASH_RESULT_OK : Encrypto write OK.
* SPI_FLASH_RESULT_ERR : Encrypto write error.
* SPI_FLASH_RESULT_TIMEOUT : Encrypto write timeout.
*/
SpiFlashOpResult SPI_Encrypt_Write(uint32_t flash_addr, uint32_t *data, uint32_t len);
/**
* @}
*/
#ifdef __cplusplus
}

85
components/esp32/include/rom/ssc.h
View File

@@ -1,85 +0,0 @@
// Copyright 2011-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ROM_SSC_H_
#define _ROM_SSC_H_
#include "esp_types.h"
#include "esp_attr.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct cmd_s {
char *cmd_str;
#define CMD_T_ASYNC 0x01
#define CMD_T_SYNC 0x02
uint8_t flag;
uint8_t id;
void (* cmd_func)(void);
void (* cmd_callback)(void *arg);
} ssc_cmd_t;
#define ssc_printf ets_printf
#define SSC_CMD_N 10 //since the command not added in ssc_cmd.c
#define MAX_LINE_N 40
#define PROMPT ":>"
#define SSC_EVT_N 4
#define SSC_PRIO 30
enum {
CMD_SET_SSID = 0,
CMD_SCAN,
CMD_CONNECT,
CMD_DISCONNECT,
CMD_SET_MACADDR,
CMD_PING,
CMD_PING_COUNT,
CMD_PING_LENGTH,
CMD_SET_IP,
// CMD_RD_I2C,
// CMD_SET_NULL, it's just for solving the old rom bug
// CMD_SET_I2C,
// CMD_RD_I2CM,
// CMD_SET_I2CM,
// CMD_SET_PBUS,
// CMD_SET_TXTONE,
// CMD_SET_STOPTONE,
CMD_END,
};
enum {
SIG_SSC_RUNCMD,
SIG_SSC_CMDDONE,
SIG_SSC_RESTART,
SIG_SSC_UART_RX_CHAR,
};
void ssc_attach(void) ROMFN_ATTR;
void ssc_cmd_done(int cmd_id, STATUS status) ROMFN_ATTR;
int ssc_param_len(void) ROMFN_ATTR;
char * ssc_param_str(void) ROMFN_ATTR;
void ssc_register(ssc_cmd_t *cmdset, uint8_t cmdnum, void (* help)(void)) ROMFN_ATTR;
extern ssc_cmd_t sscCmdSet[];
void ssc_help(void);
#ifdef __cplusplus
}
#endif
#endif /* _ROM_SSC_H_ */

282
components/esp32/include/rom/uart.h Executable file → Normal file
View File

@@ -22,6 +22,14 @@
extern "C" {
#endif
/** \defgroup uart_apis, uart configuration and communication related apis
* @brief uart apis
*/
/** @addtogroup uart_apis
* @{
*/
#define RX_BUFF_SIZE 0x100
#define TX_BUFF_SIZE 100
@@ -52,9 +60,9 @@ extern "C" {
#define UART_RCV_ERR_FLAG BIT7
//send and receive message frame head
#define FRAME_FLAG 0x7E
#define FRAME_FLAG 0x7E
typedef enum{
typedef enum {
UART_LINE_STATUS_INT_FLAG = 0x06,
UART_RCV_FIFO_INT_FLAG = 0x04,
UART_RCV_TMOUT_INT_FLAG = 0x0C,
@@ -82,9 +90,9 @@ typedef enum {
} UartStopBitsNum;
typedef enum {
NONE_BITS = 0,
ODD_BITS = 2,
EVEN_BITS = 3
NONE_BITS = 0,
ODD_BITS = 2,
EVEN_BITS = 3
} UartParityMode;
@@ -113,7 +121,7 @@ typedef enum {
typedef enum {
EMPTY,
UNDER_WRITE,
WRITE_OVER
WRITE_OVER
} RcvMsgBuffState;
typedef struct {
@@ -121,9 +129,9 @@ typedef struct {
uint8_t *pRcvMsgBuff;
uint8_t *pWritePos;
uint8_t *pReadPos;
uint8_t TrigLvl; //JLU: may need to pad
uint8_t TrigLvl;
RcvMsgBuffState BuffState;
}RcvMsgBuff;
} RcvMsgBuff;
typedef struct {
uint32_t TrxBuffSize;
@@ -138,7 +146,7 @@ typedef enum {
RCV_ESC_CHAR,
} RcvMsgState;
typedef struct{
typedef struct {
UartBautRate baut_rate;
UartBitsNum4Char data_bits;
UartExistParity exist_parity;
@@ -153,33 +161,249 @@ typedef struct{
int received;
} UartDevice;
void Uart_Init(uint8_t uart_no, uint32_t clock) ROMFN_ATTR;
STATUS UartTxString(uint8_t* pString) ROMFN_ATTR;
STATUS UartRxString(uint8_t* pString, uint8_t MaxStrlen) ROMFN_ATTR;
/**
* @brief Init uart device struct value and reset uart0/uart1 rx.
* Please do not call this function in SDK.
*
* @param None
*
* @return None
*/
void uartAttach(void);
STATUS uart_tx_one_char(uint8_t TxChar) ROMFN_ATTR;//for print
STATUS uart_tx_one_char2(uint8_t TxChar) ROMFN_ATTR;//for send message
STATUS uart_rx_one_char(uint8_t* pRxChar) ROMFN_ATTR;
char uart_rx_one_char_block(void) ROMFN_ATTR;
void uart_rx_intr_handler(void * para) ROMFN_ATTR;
STATUS uart_rx_readbuff( RcvMsgBuff* pRxBuff, uint8_t* pRxByte) ROMFN_ATTR;
STATUS UartGetCmdLn(uint8_t * pCmdLn) ROMFN_ATTR;
UartDevice * GetUartDevice() ROMFN_ATTR;
/**
* @brief Init uart0 or uart1 for UART download booting mode.
* Please do not call this function in SDK.
*
* @param uint8_t uart_no : 0 for UART0, else for UART1.
*
* @param uint32_t clock : clock used by uart module, to adjust baudrate.
*
* @return None
*/
void Uart_Init(uint8_t uart_no, uint32_t clock);
void uartToggleInterrupt(bool en) ROMFN_ATTR;
/**
* @brief Modify uart baudrate.
* This function will reset RX/TX fifo for uart.
*
* @param uint8_t uart_no : 0 for UART0, 1 for UART1.
*
* @param uint32_t DivLatchValue : (clock << 4)/baudrate.
*
* @return None
*/
void uart_div_modify(uint8_t uart_no, uint32_t DivLatchValue);
STATUS SendMsg(uint8_t *pData, uint16_t DataLen) ROMFN_ATTR;
/**
* @brief Init uart0 or uart1 for UART download booting mode.
* Please do not call this function in SDK.
*
* @param uint8_t uart_no : 0 for UART0, 1 for UART1.
*
* @param uint8_t is_sync : 0, only one UART module, easy to detect, wait until detected;
* 1, two UART modules, hard to detect, detect and return.
*
* @return None
*/
int uart_baudrate_detect(uint8_t uart_no, uint8_t is_sync);
STATUS RcvMsg(uint8_t *pData, uint16_t MaxDataLen, uint8_t is_sync) ROMFN_ATTR;
/**
* @brief Switch printf channel of uart_tx_one_char.
* Please do not call this function when printf.
*
* @param uint8_t uart_no : 0 for UART0, 1 for UART1.
*
* @return None
*/
void uart_tx_switch(uint8_t uart_no);
/**
* @brief Switch message exchange channel for UART download booting.
* Please do not call this function in SDK.
*
* @param uint8_t uart_no : 0 for UART0, 1 for UART1.
*
* @return None
*/
void uart_buff_switch(uint8_t uart_no);
/**
* @brief Output a char to printf channel, wait until fifo not full.
*
* @param None
*
* @return OK.
*/
STATUS uart_tx_one_char(uint8_t TxChar);
/**
* @brief Output a char to message exchange channel, wait until fifo not full.
* Please do not call this function in SDK.
*
* @param None
*
* @return OK.
*/
STATUS uart_tx_one_char2(uint8_t TxChar);//for send message
/**
* @brief Wait until uart tx full empty.
*
* @param uint8_t uart_no : 0 for UART0, 1 for UART1.
*
* @return None.
*/
void uart_tx_flush(uint8_t uart_no);
/**
* @brief Wait until uart tx full empty and the last char send ok.
*
* @param uint8_t uart_no : 0 for UART0, 1 for UART1.
*
* @return None.
*/
void uart_tx_wait_idle(uint8_t uart_no);
/**
* @brief Get an input char from message channel.
* Please do not call this function in SDK.
*
* @param uint8_t *pRxChar : the pointer to store the char.
*
* @return OK for successful.
* FAIL for failed.
*/
STATUS uart_rx_one_char(uint8_t *pRxChar);
/**
* @brief Get an input char to message channel, wait until successful.
* Please do not call this function in SDK.
*
* @param None
*
* @return char : input char value.
*/
char uart_rx_one_char_block(void);
/**
* @brief Get an input string line from message channel.
* Please do not call this function in SDK.
*
* @param uint8_t *pString : the pointer to store the string.
*
* @param uint8_t MaxStrlen : the max string length, incude '\0'.
*
* @return OK.
*/
STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen);
/**
* @brief Process uart recevied information in the interrupt handler.
* Please do not call this function in SDK.
*
* @param void *para : the message receive buffer.
*
* @return None
*/
void uart_rx_intr_handler(void *para);
/**
* @brief Get an char from receive buffer.
* Please do not call this function in SDK.
*
* @param RcvMsgBuff *pRxBuff : the pointer to the struct that include receive buffer.
*
* @param uint8_t *pRxByte : the pointer to store the char.
*
* @return OK for successful.
* FAIL for failed.
*/
STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte);
/**
* @brief Get all chars from receive buffer.
* Please do not call this function in SDK.
*
* @param uint8_t *pCmdLn : the pointer to store the string.
*
* @return OK for successful.
* FAIL for failed.
*/
STATUS UartGetCmdLn(uint8_t *pCmdLn);
/**
* @brief Get uart configuration struct.
* Please do not call this function in SDK.
*
* @param None
*
* @return UartDevice * : uart configuration struct pointer.
*/
UartDevice *GetUartDevice(void);
/**
* @brief Send an packet to download tool, with SLIP escaping.
* Please do not call this function in SDK.
*
* @param uint8_t *p : the pointer to output string.
*
* @param int len : the string length.
*
* @return None.
*/
void send_packet(uint8_t *p, int len);
/**
* @brief Receive an packet from download tool, with SLIP escaping.
* Please do not call this function in SDK.
*
* @param uint8_t *p : the pointer to input string.
*
* @param int len : If string length > len, the string will be truncated.
*
* @param uint8_t is_sync : 0, only one UART module;
* 1, two UART modules.
*
* @return int : the length of the string.
*/
int recv_packet(uint8_t *p, int len, uint8_t is_sync);
/**
* @brief Send an packet to download tool, with SLIP escaping.
* Please do not call this function in SDK.
*
* @param uint8_t *pData : the pointer to input string.
*
* @param uint16_t DataLen : the string length.
*
* @return OK for successful.
* FAIL for failed.
*/
STATUS SendMsg(uint8_t *pData, uint16_t DataLen);
/**
* @brief Receive an packet from download tool, with SLIP escaping.
* Please do not call this function in SDK.
*
* @param uint8_t *pData : the pointer to input string.
*
* @param uint16_t MaxDataLen : If string length > MaxDataLen, the string will be truncated.
*
* @param uint8_t is_sync : 0, only one UART module;
* 1, two UART modules.
*
* @return OK for successful.
* FAIL for failed.
*/
STATUS RcvMsg(uint8_t *pData, uint16_t MaxDataLen, uint8_t is_sync);
void uartAttach() ROMFN_ATTR;
void uart_div_modify(uint8_t uart_no, uint32_t DivLatchValue) ROMFN_ATTR;
int uart_baudrate_detect(uint8_t uart_no, uint8_t is_sync) ROMFN_ATTR;
void uart_buff_switch(uint8_t uart_no) ROMFN_ATTR;
void uart_tx_flush(uint8_t uart_no) ROMFN_ATTR;
void uart_tx_wait_idle(uint8_t uart_no) ROMFN_ATTR;
extern UartDevice UartDev;
/**
* @}
*/
#ifdef __cplusplus
}
#endif

40
components/esp32/include/rom/wdt.h
View File

@@ -1,40 +0,0 @@
// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _ROM_WDT_H_
#define _ROM_WDT_H_
#include "soc.h"
#include "ets_sys.h"
#define WDT_RESET_VALUE 0x73
#define WDT_RESET_LEN 7 //real time: (1<<(WDT_RESET_LEN+1))*pclk
#define WDT_CONTROL_ENABLED BIT0
#define WDT_MODE_SET(v) (v)
#define WDT_TARGET_SET(v) (v)
#define WDT_ADDRESS 0
#define SEC_TO_WDT_TICK(s) (s * WDT_CLK_FREQ) //it's Pclk clock,44MHz
typedef enum{
NEXT_OVERFLOW_RESET = 0,
NEXT_OVERFLOW_NO_RESET = 1,
EACH_OVERFLOW_RESET = 2,
} WDT_RESP_MODE;
#define WDT_DEFAULT_FEED_INTERVAL WDT_INTERVAL_SIX_SEC /* 6 seconds */
#define WDT_DEFAULT_EXPIRE_INTERVAL WDT_INTERVAL_TWELVE_SEC /* 12 seconds */
#endif /* _ROM_WDT_H_ */