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refactor(rng): refactor to use hal/ll apis for P4

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gaoxu
2025-05-13 09:09:06 +08:00
parent 719b1b2be0
commit b691eaba6d
7 changed files with 122 additions and 95 deletions
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62
components/hal/esp32p4/include/hal/adc_ll.h
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@@ -366,6 +366,18 @@ static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t patt
}
}
/**
* Rest pattern table to default value
*/
static inline void adc_ll_digi_reset_pattern_table(void)
{
for(int i = 0; i < 4; i++) {
ADC.sar1_patt_tab[i].sar1_patt_tab = 0xffffff;
ADC.sar2_patt_tab[i].sar2_patt_tab = 0xffffff;
}
}
/**
* Reset the pattern table pointer, then take the measurement rule from table header in next measurement.
*
@@ -514,24 +526,24 @@ static inline void _adc_ll_sar2_clock_force_en(bool enable)
* @brief Enable the ADC clock
* @param enable true to enable, false to disable
*/
static inline void adc_ll_enable_bus_clock(bool enable)
static inline void _adc_ll_enable_bus_clock(bool enable)
{
HP_SYS_CLKRST.soc_clk_ctrl2.reg_adc_apb_clk_en = enable;
HP_SYS_CLKRST.peri_clk_ctrl23.reg_adc_clk_en = enable;
}
// HP_SYS_CLKRST.soc_clk_ctrl2 are shared registers, so this function must be used in an atomic way
#define adc_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; adc_ll_enable_bus_clock(__VA_ARGS__)
#define adc_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _adc_ll_enable_bus_clock(__VA_ARGS__)
/**
* @brief Reset ADC module
*/
static inline void adc_ll_reset_register(void)
static inline void _adc_ll_reset_register(void)
{
HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_adc = 1;
HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_adc = 0;
}
// HP_SYS_CLKRST.hp_rst_en2 is a shared register, so this function must be used in an atomic way
#define adc_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; adc_ll_reset_register(__VA_ARGS__)
#define adc_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; _adc_ll_reset_register(__VA_ARGS__)
@@ -747,6 +759,48 @@ static inline void adc_ll_set_calibration_param(adc_unit_t adc_n, uint32_t param
}
}
/**
* Set the SAR DTEST param
*
* @param param DTEST value
*/
__attribute__((always_inline))
static inline void adc_ll_set_dtest_param(uint32_t param)
{
REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_DTEST_VDD_GRP1, param);
}
/**
* Set the SAR ENT param
*
* @param param ENT value
*/
__attribute__((always_inline))
static inline void adc_ll_set_ent_param(uint32_t param)
{
REGI2C_WRITE_MASK(I2C_SAR_ADC, I2C_SAR_ADC_ENT_VDD_GRP1, param);
}
/**
* Init regi2c SARADC registers
*/
__attribute__((always_inline))
static inline void adc_ll_regi2c_init(void)
{
adc_ll_set_dtest_param(0);
adc_ll_set_ent_param(1);
}
/**
* Deinit regi2c SARADC registers
*/
__attribute__((always_inline))
static inline void adc_ll_regi2c_adc_deinit(void)
{
adc_ll_set_dtest_param(0);
adc_ll_set_ent_param(0);
}
/*---------------------------------------------------------------
Oneshot Read
---------------------------------------------------------------*/