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panic: Add support for SoC-level panic

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SoC level exceptions such as watchdog timer and cache errors are now supported.
Such exceptions now triggers a panic, giving more information about how
and when it happened.
This commit is contained in:
Omar Chebib
2020-12-03 17:17:43 +08:00
parent e20833124e
commit b6a450f824
9 changed files with 346 additions and 20 deletions
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23
components/hal/esp32c3/include/hal/interrupt_controller_ll.h
View File

@@ -115,6 +115,29 @@ static inline void intr_cntrl_ll_enable_int_mask(uint32_t newmask)
RV_SET_CSR(mstatus, old_mstatus & MSTATUS_MIE);
}
/**
* @brief Set the interrupt type given an interrupt number.
*
* @param interrupt_number number of the interrupt
* @param type new type for this interrupt
*/
static inline void intr_cntrl_ll_set_type(int interrupt_number, int_type_t type)
{
esprv_intc_int_set_type(BIT(interrupt_number), type);
}
/**
* @brief Set the interrupt level (priority) given an interrupt number.
*
* @param interrupt_number number of the interrupt
* @param level new level for this interrupt
*/
static inline void intr_cntrl_ll_set_level(int interrupt_number, int level)
{
esprv_intc_int_set_priority(interrupt_number, level);
}
#ifdef __cplusplus
}
#endif

4
components/hal/esp32c3/interrupt_descriptor_table.c
View File

@@ -45,8 +45,8 @@ const int_desc_t interrupt_descriptor_table[32] = {
{ 2, INTTP_LEVEL, {INTDESC_NORMAL } }, //21
{ 3, INTTP_EDGE, {INTDESC_NORMAL } }, //22
{ 3, INTTP_LEVEL, {INTDESC_NORMAL } }, //23
{ 4, INTTP_LEVEL, {INTDESC_NORMAL } }, //24
{ 4, INTTP_LEVEL, {INTDESC_NORMAL } }, //25
{ 4, INTTP_LEVEL, {INTDESC_RESVD } }, //24
{ 4, INTTP_LEVEL, {INTDESC_RESVD } }, //25
{ 5, INTTP_LEVEL, {INTDESC_NORMAL } }, //26
{ 3, INTTP_LEVEL, {INTDESC_NORMAL } }, //27
{ 4, INTTP_EDGE, {INTDESC_NORMAL } }, //28