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ulp: added support to building code for riscv ULP coprocessor
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70
components/ulp/test/ulp_riscv/test_main.c
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70
components/ulp/test/ulp_riscv/test_main.c
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// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdio.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include "ulp_riscv/ulp_riscv.h"
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#include "ulp_riscv/ulp_riscv_utils.h"
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typedef enum{
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RISCV_READ_WRITE_TEST = 1,
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RISCV_DEEP_SLEEP_WAKEUP_TEST,
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RISCV_LIGHT_SLEEP_WAKEUP_TEST,
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RISCV_NO_COMMAND,
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} riscv_test_commands_t;
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typedef enum {
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RISCV_COMMAND_OK = 1,
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RISCV_COMMAND_NOK,
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RISCV_COMMAND_INVALID,
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} riscv_test_command_reply_t;
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#define XOR_MASK 0xDEADBEEF
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volatile riscv_test_commands_t main_cpu_command = RISCV_NO_COMMAND;
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volatile riscv_test_command_reply_t main_cpu_reply = RISCV_COMMAND_INVALID;
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volatile uint32_t riscv_test_data_in = 0;
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volatile uint32_t riscv_test_data_out = 0;
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void handle_commands(riscv_test_commands_t cmd)
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{
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switch (cmd) {
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case RISCV_READ_WRITE_TEST:
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riscv_test_data_out =riscv_test_data_in ^ XOR_MASK;
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main_cpu_reply = RISCV_COMMAND_OK;
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break;
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case RISCV_DEEP_SLEEP_WAKEUP_TEST:
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case RISCV_LIGHT_SLEEP_WAKEUP_TEST:
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main_cpu_reply = RISCV_COMMAND_OK;
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break;
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default:
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main_cpu_reply = RISCV_COMMAND_NOK;
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break;
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}
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ulp_riscv_wakeup_main_processor();
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}
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int main (void)
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{
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while (1) {
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handle_commands(main_cpu_command);
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break;
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}
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/* ulp_riscv_shutdown() is called automatically when main exits */
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return 0;
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}
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