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soc: Update esp32c3 soc headers
From internal commit 6d894813
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@@ -42,6 +42,8 @@
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#define DR_REG_SPI1_BASE 0x60002000
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#define DR_REG_SPI0_BASE 0x60003000
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#define DR_REG_GPIO_BASE 0x60004000
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#define DR_REG_FE2_BASE 0x60005000
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#define DR_REG_FE_BASE 0x60006000
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#define DR_REG_RTCCNTL_BASE 0x60008000
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#define DR_REG_IO_MUX_BASE 0x60009000
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#define DR_REG_RTC_I2C_BASE 0x6000e000
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@@ -51,6 +53,8 @@
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#define DR_REG_RMT_BASE 0x60016000
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#define DR_REG_LEDC_BASE 0x60019000
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#define DR_REG_EFUSE_BASE 0x60008800
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#define DR_REG_NRX_BASE 0x6001CC00
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#define DR_REG_BB_BASE 0x6001D000
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#define DR_REG_TIMERGROUP0_BASE 0x6001F000
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#define DR_REG_TIMERGROUP1_BASE 0x60020000
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#define DR_REG_SYS_TIMER_BASE 0x60023000
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@@ -312,6 +316,9 @@
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#define ETS_CACHEERR_INUM 25
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#define ETS_DPORT_INUM 28
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//CPU0 Max valid interrupt number
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#define ETS_MAX_INUM 31
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//CPU0 Interrupt number used in ROM, should be cancelled in SDK
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#define ETS_SLC_INUM 1
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#define ETS_UART0_INUM 5
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@@ -324,3 +331,6 @@
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//Invalid interrupt for number interrupt matrix
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#define ETS_INVALID_INUM 0
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//Interrupt medium level, used for INT WDT for example
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#define SOC_INTERRUPT_LEVEL_MEDIUM 4
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