dedicated gpio: add driver

components/hal/esp32s2/include/hal/clk_gate_ll.h

@@ -84,6 +84,8 @@ static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
         return DPORT_WIFI_CLK_WIFI_BT_COMMON_M;
     case PERIPH_SYSTIMER_MODULE:
         return DPORT_SYSTIMER_CLK_EN;
+    case PERIPH_DEDIC_GPIO_MODULE:
+        return DPORT_CLK_EN_DEDICATED_GPIO;
     case PERIPH_AES_MODULE:
         return DPORT_CRYPTO_AES_CLK_EN;
     case PERIPH_SHA_MODULE:
@@ -156,6 +158,8 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en
         return DPORT_TWAI_RST;
     case PERIPH_SYSTIMER_MODULE:
         return DPORT_SYSTIMER_RST;
+    case PERIPH_DEDIC_GPIO_MODULE:
+        return DPORT_RST_EN_DEDICATED_GPIO;
     case PERIPH_AES_MODULE:
         if (enable == true) {
             // Clear reset on digital signature, otherwise AES unit is held in reset also.
@@ -207,6 +211,8 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en
 static inline uint32_t periph_ll_get_clk_en_reg(periph_module_t periph)
 {
     switch (periph) {
+    case PERIPH_DEDIC_GPIO_MODULE:
+        return DPORT_CPU_PERI_CLK_EN_REG;
     case PERIPH_RNG_MODULE:
     case PERIPH_WIFI_MODULE:
     case PERIPH_WIFI_BT_COMMON_MODULE:
@@ -226,6 +232,8 @@ static inline uint32_t periph_ll_get_clk_en_reg(periph_module_t periph)
 static inline uint32_t periph_ll_get_rst_en_reg(periph_module_t periph)
 {
     switch (periph) {
+    case PERIPH_DEDIC_GPIO_MODULE:
+        return DPORT_CPU_PERI_RST_EN_REG;
     case PERIPH_RNG_MODULE:
     case PERIPH_WIFI_MODULE:
     case PERIPH_WIFI_BT_COMMON_MODULE:

components/hal/esp32s2/include/hal/cpu_ll.h

@@ -154,7 +154,7 @@ static inline bool cpu_ll_is_debugger_attached(void)
     uint32_t dcr = 0;
     uint32_t reg = DSRSET;
     RER(reg, dcr);
-    return (dcr&0x1);
+    return (dcr & 0x1);
 }
 
 
@@ -168,6 +168,30 @@ static inline void cpu_ll_set_vecbase(const void* vecbase)
     asm volatile ("wsr %0, vecbase" :: "r" (vecbase));
 }
 
+static inline uint32_t cpu_ll_read_dedic_gpio_in(void)
+{
+    uint32_t value = 0;
+    asm volatile("get_gpio_in %0" : "=r"(value) : :);
+    return value;
+}
+
+static inline uint32_t cpu_ll_read_dedic_gpio_out(void)
+{
+    uint32_t value = 0;
+    asm volatile("rur.gpio_out %0" : "=r"(value) : :);
+    return value;
+}
+
+static inline void cpu_ll_write_dedic_gpio_all(uint32_t value)
+{
+    asm volatile("wur.gpio_out %0"::"r"(value):);
+}
+
+static inline void cpu_ll_write_dedic_gpio_mask(uint32_t mask, uint32_t value)
+{
+    asm volatile("wr_mask_gpio_out %0, %1" : : "r"(value), "r"(mask):);
+}
+
 #ifdef __cplusplus
 }
 #endif

components/hal/esp32s2/include/hal/dedic_gpio_ll.h

@@ -0,0 +1,110 @@
+// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "soc/dedic_gpio_struct.h"
+
+static inline void dedic_gpio_ll_enable_instruction_access_out(dedic_dev_t *dev, uint32_t channel_mask, bool enable)
+{
+    if (enable) {
+        dev->gpio_out_cpu.val |= channel_mask;
+    } else {
+        dev->gpio_out_cpu.val &= ~channel_mask;
+    }
+}
+
+static inline void dedic_gpio_ll_write_all(dedic_dev_t *dev, uint32_t value)
+{
+    dev->gpio_out_drt.val = value;
+}
+
+static inline void dedic_gpio_ll_write_mask(dedic_dev_t *dev, uint32_t channel_mask, uint32_t value)
+{
+    dedic_gpio_out_msk_reg_t d = {
+        .gpio_out_msk = channel_mask,
+        .gpio_out_value = value
+    };
+    dev->gpio_out_msk.val = d.val;
+}
+
+static inline void dedic_gpio_ll_set_channel(dedic_dev_t *dev, uint32_t channel)
+{
+    dev->gpio_out_idv.val = 1 << (2 * channel);
+}
+
+static inline void dedic_gpio_ll_clear_channel(dedic_dev_t *dev, uint32_t channel)
+{
+    dev->gpio_out_idv.val = 2 << (2 * channel);
+}
+
+static inline void dedic_gpio_ll_toggle_channel(dedic_dev_t *dev, uint32_t channel)
+{
+    dev->gpio_out_idv.val = 3 << (2 * channel);
+}
+
+static inline uint32_t dedic_gpio_ll_read_out_all(dedic_dev_t *dev)
+{
+    return dev->gpio_out_scan.gpio_out_status;
+}
+
+static inline uint32_t dedic_gpio_ll_read_in_all(dedic_dev_t *dev)
+{
+    return dev->gpio_in_scan.gpio_in_status;
+}
+
+static inline void dedic_gpio_ll_set_input_delay(dedic_dev_t *dev, uint32_t channel, uint32_t delay_cpu_clks)
+{
+    dev->gpio_in_dly.val &= ~(3 << (2 * channel));
+    dev->gpio_in_dly.val |= (delay_cpu_clks & 0x03) << (2 * channel);
+}
+
+static inline uint32_t dedic_gpio_ll_get_input_delay(dedic_dev_t *dev, uint32_t channel)
+{
+    return (dev->gpio_in_dly.val & (3 << (2 * channel)) >> (2 * channel));
+}
+
+static inline void dedic_gpio_ll_set_interrupt_type(dedic_dev_t *dev, uint32_t channel, uint32_t type)
+{
+    dev->gpio_intr_rcgn.val &= ~(7 << (3 * channel));
+    dev->gpio_intr_rcgn.val |= (type & 0x07) << (3 * channel);
+}
+
+static inline void dedic_gpio_ll_enable_interrupt(dedic_dev_t *dev, uint32_t channel_mask, bool enable)
+{
+    if (enable) {
+        dev->gpio_intr_rls.val |= channel_mask;
+    } else {
+        dev->gpio_intr_rls.val &= ~channel_mask;
+    }
+}
+
+static inline uint32_t __attribute__((always_inline)) dedic_gpio_ll_get_interrupt_status(dedic_dev_t *dev)
+{
+    return dev->gpio_intr_st.val;
+}
+
+static inline void __attribute__((always_inline)) dedic_gpio_ll_clear_interrupt_status(dedic_dev_t *dev, uint32_t channel_mask)
+{
+    dev->gpio_intr_clr.val = channel_mask;
+}
+
+#ifdef __cplusplus
+}
+#endif