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dedicated gpio: add driver

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This commit is contained in:
morris
2020-05-11 19:50:17 +08:00
parent b3ce1db97a
commit bb1369b922
23 changed files with 2407 additions and 14 deletions
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8
components/hal/esp32s3/include/hal/clk_gate_ll.h
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@@ -92,6 +92,8 @@ static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
return SYSTEM_BT_LC_EN;
case PERIPH_SYSTIMER_MODULE:
return SYSTEM_SYSTIMER_CLK_EN;
case PERIPH_DEDIC_GPIO_MODULE:
return SYSTEM_CLK_EN_DEDICATED_GPIO;
case PERIPH_GDMA_MODULE:
return SYSTEM_DMA_CLK_EN;
case PERIPH_AES_MODULE:
@@ -163,6 +165,8 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en
return SYSTEM_TWAI_RST;
case PERIPH_SYSTIMER_MODULE:
return SYSTEM_SYSTIMER_RST;
case PERIPH_DEDIC_GPIO_MODULE:
return SYSTEM_RST_EN_DEDICATED_GPIO;
case PERIPH_GDMA_MODULE:
return SYSTEM_DMA_RST;
case PERIPH_AES_MODULE:
@@ -197,6 +201,8 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en
static uint32_t periph_ll_get_clk_en_reg(periph_module_t periph)
{
switch (periph) {
case PERIPH_DEDIC_GPIO_MODULE:
return SYSTEM_CPU_PERI_CLK_EN_REG;
case PERIPH_RNG_MODULE:
case PERIPH_WIFI_MODULE:
case PERIPH_BT_MODULE:
@@ -219,6 +225,8 @@ static uint32_t periph_ll_get_clk_en_reg(periph_module_t periph)
static uint32_t periph_ll_get_rst_en_reg(periph_module_t periph)
{
switch (periph) {
case PERIPH_DEDIC_GPIO_MODULE:
return SYSTEM_CPU_PERI_RST_EN_REG;
case PERIPH_RNG_MODULE:
case PERIPH_WIFI_MODULE:
case PERIPH_BT_MODULE:

49
components/hal/esp32s3/include/hal/cpu_ll.h
View File

@@ -44,7 +44,7 @@ static inline uint32_t cpu_ll_get_cycle_count(void)
return result;
}
static inline void* cpu_ll_get_sp(void)
static inline void *cpu_ll_get_sp(void)
{
void *sp;
asm volatile ("mov %0, sp;" : "=r" (sp));
@@ -94,21 +94,21 @@ static inline void cpu_ll_clear_breakpoint(int id)
WSR(IBREAKENABLE, en);
}
static inline uint32_t cpu_ll_ptr_to_pc(const void* addr)
static inline uint32_t cpu_ll_ptr_to_pc(const void *addr)
{
return ((uint32_t) addr);
}
static inline void* cpu_ll_pc_to_ptr(uint32_t pc)
static inline void *cpu_ll_pc_to_ptr(uint32_t pc)
{
return (void*) ((pc & 0x3fffffff) | 0x40000000);
return (void *) ((pc & 0x3fffffff) | 0x40000000);
}
static inline void cpu_ll_set_watchpoint(int id,
const void* addr,
size_t size,
bool on_read,
bool on_write)
const void *addr,
size_t size,
bool on_read,
bool on_write)
{
uint32_t dbreakc = 0x3F;
@@ -158,7 +158,7 @@ static inline bool cpu_ll_is_debugger_attached(void)
uint32_t dcr = 0;
uint32_t reg = DSRSET;
RER(reg, dcr);
return (dcr&0x1);
return (dcr & 0x1);
}
static inline void cpu_ll_break(void)
@@ -166,11 +166,40 @@ static inline void cpu_ll_break(void)
__asm__ ("break 0,0");
}
static inline void cpu_ll_set_vecbase(const void* vecbase)
static inline void cpu_ll_set_vecbase(const void *vecbase)
{
asm volatile ("wsr %0, vecbase" :: "r" (vecbase));
}
static inline uint32_t cpu_ll_read_dedic_gpio_in(void)
{
uint32_t value = 0;
asm volatile("get_gpio_in %0" : "=r"(value) : :);
return value;
}
static inline uint32_t cpu_ll_read_dedic_gpio_out(void)
{
uint32_t value = 0;
asm volatile("rur.gpio_out %0" : "=r"(value) : :);
return value;
}
static inline void cpu_ll_write_dedic_gpio_all(uint32_t value)
{
asm volatile("wur.gpio_out %0"::"r"(value):);
}
static inline void cpu_ll_write_dedic_gpio_mask(uint32_t mask, uint32_t value)
{
// ToDo: check if ESP32-S3 supports mask write instruction
uint32_t orig = 0;
asm volatile("rur.gpio_out %0" : "=r"(orig) : :);
orig &= ~mask;
orig |= value & mask;
asm volatile("wur.gpio_out %0"::"r"(orig):);
}
#ifdef __cplusplus
}
#endif