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feat(gdma): add GDMA support for ESP32C5 MP

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This commit is contained in:
Song Ruo Jing
2024-04-23 20:11:32 +08:00
parent 7c62ad5434
commit bbc44b486e
20 changed files with 1683 additions and 796 deletions
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44
components/hal/esp32p4/include/hal/ahb_dma_ll.h
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@@ -530,8 +530,8 @@ static inline void ahb_dma_ll_tx_enable_etm_task(ahb_dma_dev_t *dev, uint32_t ch
*/
static inline void ahb_dma_ll_tx_crc_clear(ahb_dma_dev_t *dev, uint32_t channel)
{
dev->out_crc[channel].crc_clear.out_crc_clear_chn_reg = 1;
dev->out_crc[channel].crc_clear.out_crc_clear_chn_reg = 0;
dev->out_crc_arb[channel].crc_clear.out_crc_clear_chn_reg = 1;
dev->out_crc_arb[channel].crc_clear.out_crc_clear_chn_reg = 0;
}
/**
@@ -540,7 +540,7 @@ static inline void ahb_dma_ll_tx_crc_clear(ahb_dma_dev_t *dev, uint32_t channel)
static inline void ahb_dma_ll_tx_crc_set_width(ahb_dma_dev_t *dev, uint32_t channel, uint32_t width)
{
HAL_ASSERT(width <= 32);
dev->out_crc[channel].crc_width.tx_crc_width_chn = (width - 1) / 8;
dev->out_crc_arb[channel].crc_width.tx_crc_width_chn = (width - 1) / 8;
}
/**
@@ -548,7 +548,7 @@ static inline void ahb_dma_ll_tx_crc_set_width(ahb_dma_dev_t *dev, uint32_t chan
*/
static inline void ahb_dma_ll_tx_crc_set_init_value(ahb_dma_dev_t *dev, uint32_t channel, uint32_t value)
{
dev->out_crc[channel].crc_init_data.out_crc_init_data_chn = value;
dev->out_crc_arb[channel].crc_init_data.out_crc_init_data_chn = value;
}
/**
@@ -556,7 +556,7 @@ static inline void ahb_dma_ll_tx_crc_set_init_value(ahb_dma_dev_t *dev, uint32_t
*/
static inline uint32_t ahb_dma_ll_tx_crc_get_result(ahb_dma_dev_t *dev, uint32_t channel)
{
return dev->out_crc[channel].crc_final_result.out_crc_final_result_chn;
return dev->out_crc_arb[channel].crc_final_result.out_crc_final_result_chn;
}
/**
@@ -564,8 +564,8 @@ static inline uint32_t ahb_dma_ll_tx_crc_get_result(ahb_dma_dev_t *dev, uint32_t
*/
static inline void ahb_dma_ll_tx_crc_latch_config(ahb_dma_dev_t *dev, uint32_t channel)
{
dev->out_crc[channel].crc_width.tx_crc_latch_flag_chn = 1;
dev->out_crc[channel].crc_width.tx_crc_latch_flag_chn = 0;
dev->out_crc_arb[channel].crc_width.tx_crc_latch_flag_chn = 1;
dev->out_crc_arb[channel].crc_width.tx_crc_latch_flag_chn = 0;
}
/**
@@ -574,14 +574,14 @@ static inline void ahb_dma_ll_tx_crc_latch_config(ahb_dma_dev_t *dev, uint32_t c
static inline void ahb_dma_ll_tx_crc_set_lfsr_data_mask(ahb_dma_dev_t *dev, uint32_t channel, uint32_t crc_bit,
uint32_t lfsr_mask, uint32_t data_mask, bool reverse_data_mask)
{
dev->out_crc[channel].crc_en_addr.tx_crc_en_addr_chn = crc_bit;
dev->out_crc[channel].crc_en_wr_data.tx_crc_en_wr_data_chn = lfsr_mask;
dev->out_crc[channel].crc_data_en_addr.tx_crc_data_en_addr_chn = crc_bit;
dev->out_crc_arb[channel].crc_en_addr.tx_crc_en_addr_chn = crc_bit;
dev->out_crc_arb[channel].crc_en_wr_data.tx_crc_en_wr_data_chn = lfsr_mask;
dev->out_crc_arb[channel].crc_data_en_addr.tx_crc_data_en_addr_chn = crc_bit;
if (reverse_data_mask) {
// "& 0xff" because the hardware only support 8-bit data
data_mask = hal_utils_bitwise_reverse8(data_mask & 0xFF);
}
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->out_crc[channel].crc_data_en_wr_data, tx_crc_data_en_wr_data_chn, data_mask);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->out_crc_arb[channel].crc_data_en_wr_data, tx_crc_data_en_wr_data_chn, data_mask);
}
///////////////////////////////////// CRC-RX /////////////////////////////////////////
@@ -591,8 +591,8 @@ static inline void ahb_dma_ll_tx_crc_set_lfsr_data_mask(ahb_dma_dev_t *dev, uint
*/
static inline void ahb_dma_ll_rx_crc_clear(ahb_dma_dev_t *dev, uint32_t channel)
{
dev->in_crc[channel].crc_clear.in_crc_clear_chn_reg = 1;
dev->in_crc[channel].crc_clear.in_crc_clear_chn_reg = 0;
dev->in_crc_arb[channel].crc_clear.in_crc_clear_chn_reg = 1;
dev->in_crc_arb[channel].crc_clear.in_crc_clear_chn_reg = 0;
}
/**
@@ -601,7 +601,7 @@ static inline void ahb_dma_ll_rx_crc_clear(ahb_dma_dev_t *dev, uint32_t channel)
static inline void ahb_dma_ll_rx_crc_set_width(ahb_dma_dev_t *dev, uint32_t channel, uint32_t width)
{
HAL_ASSERT(width <= 32);
dev->in_crc[channel].crc_width.rx_crc_width_chn = (width - 1) / 8;
dev->in_crc_arb[channel].crc_width.rx_crc_width_chn = (width - 1) / 8;
}
/**
@@ -609,7 +609,7 @@ static inline void ahb_dma_ll_rx_crc_set_width(ahb_dma_dev_t *dev, uint32_t chan
*/
static inline void ahb_dma_ll_rx_crc_set_init_value(ahb_dma_dev_t *dev, uint32_t channel, uint32_t value)
{
dev->in_crc[channel].crc_init_data.in_crc_init_data_chn = value;
dev->in_crc_arb[channel].crc_init_data.in_crc_init_data_chn = value;
}
/**
@@ -617,7 +617,7 @@ static inline void ahb_dma_ll_rx_crc_set_init_value(ahb_dma_dev_t *dev, uint32_t
*/
static inline uint32_t ahb_dma_ll_rx_crc_get_result(ahb_dma_dev_t *dev, uint32_t channel)
{
return dev->in_crc[channel].crc_final_result.in_crc_final_result_chn;
return dev->in_crc_arb[channel].crc_final_result.in_crc_final_result_chn;
}
/**
@@ -625,8 +625,8 @@ static inline uint32_t ahb_dma_ll_rx_crc_get_result(ahb_dma_dev_t *dev, uint32_t
*/
static inline void ahb_dma_ll_rx_crc_latch_config(ahb_dma_dev_t *dev, uint32_t channel)
{
dev->in_crc[channel].crc_width.rx_crc_latch_flag_chn = 1;
dev->in_crc[channel].crc_width.rx_crc_latch_flag_chn = 0;
dev->in_crc_arb[channel].crc_width.rx_crc_latch_flag_chn = 1;
dev->in_crc_arb[channel].crc_width.rx_crc_latch_flag_chn = 0;
}
/**
@@ -635,14 +635,14 @@ static inline void ahb_dma_ll_rx_crc_latch_config(ahb_dma_dev_t *dev, uint32_t c
static inline void ahb_dma_ll_rx_crc_set_lfsr_data_mask(ahb_dma_dev_t *dev, uint32_t channel, uint32_t crc_bit,
uint32_t lfsr_mask, uint32_t data_mask, bool reverse_data_mask)
{
dev->in_crc[channel].crc_en_addr.rx_crc_en_addr_chn = crc_bit;
dev->in_crc[channel].crc_en_wr_data.rx_crc_en_wr_data_chn = lfsr_mask;
dev->in_crc[channel].crc_data_en_addr.rx_crc_data_en_addr_chn = crc_bit;
dev->in_crc_arb[channel].crc_en_addr.rx_crc_en_addr_chn = crc_bit;
dev->in_crc_arb[channel].crc_en_wr_data.rx_crc_en_wr_data_chn = lfsr_mask;
dev->in_crc_arb[channel].crc_data_en_addr.rx_crc_data_en_addr_chn = crc_bit;
if (reverse_data_mask) {
// "& 0xff" because the hardware only support 8-bit data
data_mask = hal_utils_bitwise_reverse8(data_mask & 0xFF);
}
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->in_crc[channel].crc_data_en_wr_data, rx_crc_data_en_wr_data_chn, data_mask);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->in_crc_arb[channel].crc_data_en_wr_data, rx_crc_data_en_wr_data_chn, data_mask);
}
#ifdef __cplusplus