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feat(gdma): add GDMA support for ESP32C5 MP
This commit is contained in:
Song Ruo Jing
@@ -111,7 +111,7 @@ static const regdma_entries_config_t gdma_g0p2_regs_retention[] = {
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.owner = ENTRY(0) | ENTRY(2) },
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};
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const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[SOC_GDMA_PAIRS_PER_GROUP_MAX][SOC_GDMA_PAIRS_PER_GROUP_MAX] = {
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const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[SOC_GDMA_NUM_GROUPS_MAX][SOC_GDMA_PAIRS_PER_GROUP_MAX] = {
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[0] = {
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[0] = {gdma_g0p0_regs_retention, ARRAY_SIZE(gdma_g0p0_regs_retention)},
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[1] = {gdma_g0p1_regs_retention, ARRAY_SIZE(gdma_g0p1_regs_retention)},
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143
components/soc/esp32c5/mp/gdma_periph.c
Normal file
143
components/soc/esp32c5/mp/gdma_periph.c
Normal file
@@ -0,0 +1,143 @@
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/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc/gdma_periph.h"
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#include "soc/ahb_dma_reg.h"
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const gdma_signal_conn_t gdma_periph_signals = {
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.groups = {
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[0] = {
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.module = PERIPH_GDMA_MODULE,
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.pairs = {
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[0] = {
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.rx_irq_id = ETS_DMA_IN_CH0_INTR_SOURCE,
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.tx_irq_id = ETS_DMA_OUT_CH0_INTR_SOURCE,
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},
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[1] = {
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.rx_irq_id = ETS_DMA_IN_CH1_INTR_SOURCE,
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.tx_irq_id = ETS_DMA_OUT_CH1_INTR_SOURCE,
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},
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[2] = {
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.rx_irq_id = ETS_DMA_IN_CH2_INTR_SOURCE,
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.tx_irq_id = ETS_DMA_OUT_CH2_INTR_SOURCE,
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}
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}
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}
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}
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};
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#if SOC_GDMA_SUPPORT_SLEEP_RETENTION
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/* GDMA Channel (Group0, Pair0) Registers Context
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Include: GDMA_MISC_CONF_REG
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GDMA_IN_INT_ENA_CH0_REG / GDMA_OUT_INT_ENA_CH0_REG / GDMA_IN_PERI_SEL_CH0_REG / GDMA_OUT_PERI_SEL_CH0_REG
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GDMA_IN_CONF0_CH0_REG / GDMA_IN_CONF1_CH0_REG / GDMA_IN_LINK_CH0_REG / GDMA_IN_PRI_CH0_REG
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GDMA_OUT_CONF0_CH0_REG / GDMA_OUT_CONF1_CH0_REG / GDMA_OUT_LINK_CH0_REG /GDMA_OUT_PRI_CH0_REG
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AHB_DMA_TX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH0_REG
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AHB_DMA_RX_CH_ARB_WEIGH_CH0_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH0_REG
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AHB_DMA_IN_LINK_ADDR_CH0_REG / AHB_DMA_OUT_LINK_ADDR_CH0_REG
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AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
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AHB_DMA_ARB_TIMEOUT_TX_REG / AHB_DMA_ARB_TIMEOUT_RX_REG
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AHB_DMA_WEIGHT_EN_TX_REG / AHB_DMA_WEIGHT_EN_RX_REG
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*/
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#define G0P0_RETENTION_REGS_CNT_0 13
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#define G0P0_RETENTION_MAP_BASE_0 (REG_AHB_DMA_BASE + 0x8)
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#define G0P0_RETENTION_REGS_CNT_1 12
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#define G0P0_RETENTION_MAP_BASE_1 (REG_AHB_DMA_BASE + 0x2dc)
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static const uint32_t g0p0_regs_map0[4] = {0x4c801001, 0x604c0060, 0x0, 0x0};
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static const uint32_t g0p0_regs_map1[4] = {0xc0000003, 0xfc900000, 0x0, 0x0};
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static const regdma_entries_config_t gdma_g0p0_regs_retention[] = {
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[0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
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G0P0_RETENTION_MAP_BASE_0, G0P0_RETENTION_MAP_BASE_0, \
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G0P0_RETENTION_REGS_CNT_0, 0, 0, \
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g0p0_regs_map0[0], g0p0_regs_map0[1], \
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g0p0_regs_map0[2], g0p0_regs_map0[3]), \
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.owner = ENTRY(0) | ENTRY(2) }, \
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[1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
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G0P0_RETENTION_MAP_BASE_1, G0P0_RETENTION_MAP_BASE_1, \
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G0P0_RETENTION_REGS_CNT_1, 0, 0, \
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g0p0_regs_map1[0], g0p0_regs_map1[1], \
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g0p0_regs_map1[2], g0p0_regs_map1[3]), \
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.owner = ENTRY(0) | ENTRY(2) },
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};
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/* GDMA Channel (Group0, Pair1) Registers Context
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Include: GDMA_MISC_CONF_REG
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GDMA_IN_INT_ENA_CH1_REG / GDMA_OUT_INT_ENA_CH1_REG / GDMA_IN_PERI_SEL_CH1_REG / GDMA_OUT_PERI_SEL_CH1_REG
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GDMA_IN_CONF0_CH1_REG / GDMA_IN_CONF1_CH1_REG / GDMA_IN_LINK_CH1_REG / GDMA_IN_PRI_CH1_REG
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GDMA_OUT_CONF0_CH1_REG / GDMA_OUT_CONF1_CH1_REG / GDMA_OUT_LINK_CH1_REG /GDMA_OUT_PRI_CH1_REG
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AHB_DMA_TX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH1_REG
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AHB_DMA_RX_CH_ARB_WEIGH_CH1_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH1_REG
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AHB_DMA_IN_LINK_ADDR_CH1_REG / AHB_DMA_OUT_LINK_ADDR_CH1_REG
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AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
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AHB_DMA_ARB_TIMEOUT_TX_REG / AHB_DMA_ARB_TIMEOUT_RX_REG
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AHB_DMA_WEIGHT_EN_TX_REG / AHB_DMA_WEIGHT_EN_RX_REG
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*/
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#define G0P1_RETENTION_REGS_CNT_0 13
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#define G0P1_RETENTION_MAP_BASE_0 (REG_AHB_DMA_BASE + 0x18)
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#define G0P1_RETENTION_REGS_CNT_1 12
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#define G0P1_RETENTION_MAP_BASE_1 (REG_AHB_DMA_BASE + 0x304)
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static const uint32_t g0p1_regs_map0[4] = {0x81001, 0x0, 0xc00604c0, 0x604};
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static const uint32_t g0p1_regs_map1[4] = {0xc0000003, 0x3f4800, 0x0, 0x0};
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static const regdma_entries_config_t gdma_g0p1_regs_retention[] = {
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[0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
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G0P1_RETENTION_MAP_BASE_0, G0P1_RETENTION_MAP_BASE_0, \
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G0P1_RETENTION_REGS_CNT_0, 0, 0, \
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g0p1_regs_map0[0], g0p1_regs_map0[1], \
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g0p1_regs_map0[2], g0p1_regs_map0[3]), \
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.owner = ENTRY(0) | ENTRY(2) },
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[1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
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G0P1_RETENTION_MAP_BASE_1, G0P1_RETENTION_MAP_BASE_1, \
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G0P1_RETENTION_REGS_CNT_1, 0, 0, \
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g0p1_regs_map1[0], g0p1_regs_map1[1], \
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g0p1_regs_map1[2], g0p1_regs_map1[3]), \
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.owner = ENTRY(0) | ENTRY(2) },
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};
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/* GDMA Channel (Group0, Pair2) Registers Context
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Include: GDMA_MISC_CONF_REG
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GDMA_IN_INT_ENA_CH2_REG / GDMA_OUT_INT_ENA_CH2_REG
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GDMA_IN_PERI_SEL_CH2_REG / GDMA_OUT_PERI_SEL_CH2_REG
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GDMA_IN_CONF0_CH2_REG / GDMA_IN_CONF1_CH2_REG / GDMA_IN_LINK_CH2_REG / GDMA_IN_PRI_CH2_REG
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GDMA_OUT_CONF0_CH2_REG / GDMA_OUT_CONF1_CH2_REG / GDMA_OUT_LINK_CH2_REG /GDMA_OUT_PRI_CH2_REG
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AHB_DMA_TX_CH_ARB_WEIGH_CH2_REG / AHB_DMA_TX_ARB_WEIGH_OPT_DIR_CH2_REG
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AHB_DMA_RX_CH_ARB_WEIGH_CH2_REG / AHB_DMA_RX_ARB_WEIGH_OPT_DIR_CH2_REG
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AHB_DMA_IN_LINK_ADDR_CH2_REG / AHB_DMA_OUT_LINK_ADDR_CH2_REG
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AHB_DMA_INTR_MEM_START_ADDR_REG / AHB_DMA_INTR_MEM_END_ADDR_REG
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AHB_DMA_ARB_TIMEOUT_TX_REG / AHB_DMA_ARB_TIMEOUT_RX_REG
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AHB_DMA_WEIGHT_EN_TX_REG / AHB_DMA_WEIGHT_EN_RX_REG
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*/
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#define G0P2_RETENTION_REGS_CNT_0 3
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#define G0P2_RETENTION_MAP_BASE_0 (REG_AHB_DMA_BASE + 0x28)
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#define G0P2_RETENTION_REGS_CNT_1 22
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#define G0P2_RETENTION_MAP_BASE_1 (REG_AHB_DMA_BASE + 0x1f0)
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static const uint32_t g0p2_regs_map0[4] = {0x9001, 0x0, 0x0, 0x0};
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static const uint32_t g0p2_regs_map1[4] = {0x13001813, 0x18, 0x18000, 0x7f26000};
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static const regdma_entries_config_t gdma_g0p2_regs_retention[] = {
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[0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
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G0P2_RETENTION_MAP_BASE_0, G0P2_RETENTION_MAP_BASE_0, \
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G0P2_RETENTION_REGS_CNT_0, 0, 0, \
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g0p2_regs_map0[0], g0p2_regs_map0[1], \
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g0p2_regs_map0[2], g0p2_regs_map0[3]), \
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.owner = ENTRY(0) | ENTRY(2) },
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[1] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_AHB_DMA_LINK(0x00), \
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G0P2_RETENTION_MAP_BASE_1, G0P2_RETENTION_MAP_BASE_1, \
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G0P2_RETENTION_REGS_CNT_1, 0, 0, \
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g0p2_regs_map1[0], g0p2_regs_map1[1], \
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g0p2_regs_map1[2], g0p2_regs_map1[3]), \
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.owner = ENTRY(0) | ENTRY(2) },
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};
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const gdma_chx_reg_ctx_link_t gdma_chx_regs_retention[SOC_GDMA_NUM_GROUPS_MAX][SOC_GDMA_PAIRS_PER_GROUP_MAX] = {
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[0] = {
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[0] = {gdma_g0p0_regs_retention, ARRAY_SIZE(gdma_g0p0_regs_retention)},
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[1] = {gdma_g0p1_regs_retention, ARRAY_SIZE(gdma_g0p1_regs_retention)},
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[2] = {gdma_g0p2_regs_retention, ARRAY_SIZE(gdma_g0p2_regs_retention)}
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}
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};
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#endif
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@@ -7,10 +7,22 @@ config SOC_UART_SUPPORTED
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bool
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default y
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config SOC_GDMA_SUPPORTED
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bool
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default y
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config SOC_AHB_GDMA_SUPPORTED
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bool
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default y
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config SOC_GPTIMER_SUPPORTED
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bool
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default y
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config SOC_ASYNC_MEMCPY_SUPPORTED
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bool
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default y
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config SOC_SUPPORTS_SECURE_DL_MODE
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bool
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default y
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@@ -111,6 +123,22 @@ config SOC_CPU_IDRAM_SPLIT_USING_PMP
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bool
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default y
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config SOC_DMA_CAN_ACCESS_FLASH
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bool
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default y
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config SOC_AHB_GDMA_VERSION
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int
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default 2
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config SOC_GDMA_NUM_GROUPS_MAX
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int
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default 1
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config SOC_GDMA_PAIRS_PER_GROUP_MAX
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int
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default 3
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config SOC_GPIO_PORT
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int
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default 1
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@@ -1132,139 +1132,84 @@ typedef union {
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uint32_t val;
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} ahb_dma_out_peri_sel_chn_reg_t;
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typedef struct {
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volatile ahb_dma_in_int_raw_chn_reg_t raw;
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volatile ahb_dma_in_int_st_chn_reg_t st;
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volatile ahb_dma_in_int_ena_chn_reg_t ena;
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volatile ahb_dma_in_int_clr_chn_reg_t clr;
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} ahb_dma_in_int_chn_reg_t;
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typedef struct {
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volatile ahb_dma_in_int_raw_chn_reg_t in_int_raw_ch0;
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volatile ahb_dma_in_int_st_chn_reg_t in_int_st_ch0;
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volatile ahb_dma_in_int_ena_chn_reg_t in_int_ena_ch0;
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volatile ahb_dma_in_int_clr_chn_reg_t in_int_clr_ch0;
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volatile ahb_dma_in_int_raw_chn_reg_t in_int_raw_ch1;
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volatile ahb_dma_in_int_st_chn_reg_t in_int_st_ch1;
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volatile ahb_dma_in_int_ena_chn_reg_t in_int_ena_ch1;
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volatile ahb_dma_in_int_clr_chn_reg_t in_int_clr_ch1;
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volatile ahb_dma_in_int_raw_chn_reg_t in_int_raw_ch2;
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volatile ahb_dma_in_int_st_chn_reg_t in_int_st_ch2;
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volatile ahb_dma_in_int_ena_chn_reg_t in_int_ena_ch2;
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volatile ahb_dma_in_int_clr_chn_reg_t in_int_clr_ch2;
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volatile ahb_dma_out_int_raw_chn_reg_t out_int_raw_ch0;
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volatile ahb_dma_out_int_st_chn_reg_t out_int_st_ch0;
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volatile ahb_dma_out_int_ena_chn_reg_t out_int_ena_ch0;
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volatile ahb_dma_out_int_clr_chn_reg_t out_int_clr_ch0;
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volatile ahb_dma_out_int_raw_chn_reg_t out_int_raw_ch1;
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volatile ahb_dma_out_int_st_chn_reg_t out_int_st_ch1;
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volatile ahb_dma_out_int_ena_chn_reg_t out_int_ena_ch1;
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volatile ahb_dma_out_int_clr_chn_reg_t out_int_clr_ch1;
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volatile ahb_dma_out_int_raw_chn_reg_t out_int_raw_ch2;
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volatile ahb_dma_out_int_st_chn_reg_t out_int_st_ch2;
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volatile ahb_dma_out_int_ena_chn_reg_t out_int_ena_ch2;
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volatile ahb_dma_out_int_clr_chn_reg_t out_int_clr_ch2;
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volatile ahb_dma_out_int_raw_chn_reg_t raw;
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volatile ahb_dma_out_int_st_chn_reg_t st;
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volatile ahb_dma_out_int_ena_chn_reg_t ena;
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volatile ahb_dma_out_int_clr_chn_reg_t clr;
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} ahb_dma_out_int_chn_reg_t;
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typedef struct {
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volatile ahb_dma_in_conf0_chn_reg_t in_conf0;
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volatile ahb_dma_in_conf1_chn_reg_t in_conf1;
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volatile ahb_dma_infifo_status_chn_reg_t infifo_status;
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volatile ahb_dma_in_pop_chn_reg_t in_pop;
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volatile ahb_dma_in_link_chn_reg_t in_link;
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volatile ahb_dma_in_state_chn_reg_t in_state;
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volatile ahb_dma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr;
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volatile ahb_dma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr;
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volatile ahb_dma_in_dscr_chn_reg_t in_dscr;
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volatile ahb_dma_in_dscr_bf0_chn_reg_t in_dscr_bf0;
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volatile ahb_dma_in_dscr_bf1_chn_reg_t in_dscr_bf1;
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volatile ahb_dma_in_pri_chn_reg_t in_pri;
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volatile ahb_dma_in_peri_sel_chn_reg_t in_peri_sel;
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} ahb_dma_in_chn_reg_t;
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typedef struct {
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volatile ahb_dma_out_conf0_chn_reg_t out_conf0;
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volatile ahb_dma_out_conf1_chn_reg_t out_conf1;
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volatile ahb_dma_outfifo_status_chn_reg_t outfifo_status;
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volatile ahb_dma_out_push_chn_reg_t out_push;
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volatile ahb_dma_out_link_chn_reg_t out_link;
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volatile ahb_dma_out_state_chn_reg_t out_state;
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volatile ahb_dma_out_eof_des_addr_chn_reg_t out_eof_des_addr;
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volatile ahb_dma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr;
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volatile ahb_dma_out_dscr_chn_reg_t out_dscr;
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volatile ahb_dma_out_dscr_bf0_chn_reg_t out_dscr_bf0;
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volatile ahb_dma_out_dscr_bf1_chn_reg_t out_dscr_bf1;
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volatile ahb_dma_out_pri_chn_reg_t out_pri;
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volatile ahb_dma_out_peri_sel_chn_reg_t out_peri_sel;
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} ahb_dma_out_chn_reg_t;
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typedef struct {
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volatile ahb_dma_in_chn_reg_t in;
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uint32_t reserved_in[11];
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volatile ahb_dma_out_chn_reg_t out;
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uint32_t reserved_out[11];
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} ahb_dma_chn_reg_t;
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typedef struct {
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uint32_t reserved[8];
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ahb_dma_rx_ch_arb_weigh_chn_reg_t ch_arb_weigh;
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ahb_dma_rx_arb_weigh_opt_dir_chn_reg_t arb_weigh_opt;
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} ahb_dma_in_crc_arb_chn_reg_t;
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typedef struct {
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uint32_t reserved[8];
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ahb_dma_tx_ch_arb_weigh_chn_reg_t ch_arb_weigh;
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ahb_dma_tx_arb_weigh_opt_dir_chn_reg_t arb_weigh_opt;
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} ahb_dma_out_crc_arb_chn_reg_t;
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typedef struct {
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volatile ahb_dma_in_int_chn_reg_t in_intr[3];
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volatile ahb_dma_out_int_chn_reg_t out_intr[3];
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volatile ahb_dma_ahb_test_reg_t ahb_test;
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volatile ahb_dma_misc_conf_reg_t misc_conf;
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volatile ahb_dma_date_reg_t date;
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uint32_t reserved_06c;
|
||||
volatile ahb_dma_in_conf0_chn_reg_t in_conf0_ch0;
|
||||
volatile ahb_dma_in_conf1_chn_reg_t in_conf1_ch0;
|
||||
volatile ahb_dma_infifo_status_chn_reg_t infifo_status_ch0;
|
||||
volatile ahb_dma_in_pop_chn_reg_t in_pop_ch0;
|
||||
volatile ahb_dma_in_link_chn_reg_t in_link_ch0;
|
||||
volatile ahb_dma_in_state_chn_reg_t in_state_ch0;
|
||||
volatile ahb_dma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch0;
|
||||
volatile ahb_dma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch0;
|
||||
volatile ahb_dma_in_dscr_chn_reg_t in_dscr_ch0;
|
||||
volatile ahb_dma_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch0;
|
||||
volatile ahb_dma_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch0;
|
||||
volatile ahb_dma_in_pri_chn_reg_t in_pri_ch0;
|
||||
volatile ahb_dma_in_peri_sel_chn_reg_t in_peri_sel_ch0;
|
||||
uint32_t reserved_0a4[11];
|
||||
volatile ahb_dma_out_conf0_ch0_reg_t out_conf0_ch0;
|
||||
volatile ahb_dma_out_conf1_chn_reg_t out_conf1_ch0;
|
||||
volatile ahb_dma_outfifo_status_chn_reg_t outfifo_status_ch0;
|
||||
volatile ahb_dma_out_push_chn_reg_t out_push_ch0;
|
||||
volatile ahb_dma_out_link_chn_reg_t out_link_ch0;
|
||||
volatile ahb_dma_out_state_chn_reg_t out_state_ch0;
|
||||
volatile ahb_dma_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch0;
|
||||
volatile ahb_dma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr_ch0;
|
||||
volatile ahb_dma_out_dscr_chn_reg_t out_dscr_ch0;
|
||||
volatile ahb_dma_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch0;
|
||||
volatile ahb_dma_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch0;
|
||||
volatile ahb_dma_out_pri_chn_reg_t out_pri_ch0;
|
||||
volatile ahb_dma_out_peri_sel_chn_reg_t out_peri_sel_ch0;
|
||||
uint32_t reserved_104[11];
|
||||
volatile ahb_dma_in_conf0_chn_reg_t in_conf0_ch1;
|
||||
volatile ahb_dma_in_conf1_chn_reg_t in_conf1_ch1;
|
||||
volatile ahb_dma_infifo_status_chn_reg_t infifo_status_ch1;
|
||||
volatile ahb_dma_in_pop_chn_reg_t in_pop_ch1;
|
||||
volatile ahb_dma_in_link_chn_reg_t in_link_ch1;
|
||||
volatile ahb_dma_in_state_chn_reg_t in_state_ch1;
|
||||
volatile ahb_dma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch1;
|
||||
volatile ahb_dma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch1;
|
||||
volatile ahb_dma_in_dscr_chn_reg_t in_dscr_ch1;
|
||||
volatile ahb_dma_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch1;
|
||||
volatile ahb_dma_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch1;
|
||||
volatile ahb_dma_in_pri_chn_reg_t in_pri_ch1;
|
||||
volatile ahb_dma_in_peri_sel_chn_reg_t in_peri_sel_ch1;
|
||||
uint32_t reserved_164[11];
|
||||
volatile ahb_dma_out_conf0_chn_reg_t out_conf0_ch1;
|
||||
volatile ahb_dma_out_conf1_chn_reg_t out_conf1_ch1;
|
||||
volatile ahb_dma_outfifo_status_chn_reg_t outfifo_status_ch1;
|
||||
volatile ahb_dma_out_push_chn_reg_t out_push_ch1;
|
||||
volatile ahb_dma_out_link_chn_reg_t out_link_ch1;
|
||||
volatile ahb_dma_out_state_chn_reg_t out_state_ch1;
|
||||
volatile ahb_dma_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch1;
|
||||
volatile ahb_dma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr_ch1;
|
||||
volatile ahb_dma_out_dscr_chn_reg_t out_dscr_ch1;
|
||||
volatile ahb_dma_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch1;
|
||||
volatile ahb_dma_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch1;
|
||||
volatile ahb_dma_out_pri_chn_reg_t out_pri_ch1;
|
||||
volatile ahb_dma_out_peri_sel_chn_reg_t out_peri_sel_ch1;
|
||||
uint32_t reserved_1c4[11];
|
||||
volatile ahb_dma_in_conf0_chn_reg_t in_conf0_ch2;
|
||||
volatile ahb_dma_in_conf1_chn_reg_t in_conf1_ch2;
|
||||
volatile ahb_dma_infifo_status_chn_reg_t infifo_status_ch2;
|
||||
volatile ahb_dma_in_pop_chn_reg_t in_pop_ch2;
|
||||
volatile ahb_dma_in_link_chn_reg_t in_link_ch2;
|
||||
volatile ahb_dma_in_state_chn_reg_t in_state_ch2;
|
||||
volatile ahb_dma_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch2;
|
||||
volatile ahb_dma_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch2;
|
||||
volatile ahb_dma_in_dscr_chn_reg_t in_dscr_ch2;
|
||||
volatile ahb_dma_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch2;
|
||||
volatile ahb_dma_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch2;
|
||||
volatile ahb_dma_in_pri_chn_reg_t in_pri_ch2;
|
||||
volatile ahb_dma_in_peri_sel_chn_reg_t in_peri_sel_ch2;
|
||||
uint32_t reserved_224[11];
|
||||
volatile ahb_dma_out_conf0_chn_reg_t out_conf0_ch2;
|
||||
volatile ahb_dma_out_conf1_chn_reg_t out_conf1_ch2;
|
||||
volatile ahb_dma_outfifo_status_chn_reg_t outfifo_status_ch2;
|
||||
volatile ahb_dma_out_push_chn_reg_t out_push_ch2;
|
||||
volatile ahb_dma_out_link_chn_reg_t out_link_ch2;
|
||||
volatile ahb_dma_out_state_chn_reg_t out_state_ch2;
|
||||
volatile ahb_dma_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch2;
|
||||
volatile ahb_dma_out_eof_bfr_des_addr_chn_reg_t out_eof_bfr_des_addr_ch2;
|
||||
volatile ahb_dma_out_dscr_chn_reg_t out_dscr_ch2;
|
||||
volatile ahb_dma_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch2;
|
||||
volatile ahb_dma_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch2;
|
||||
volatile ahb_dma_out_pri_chn_reg_t out_pri_ch2;
|
||||
volatile ahb_dma_out_peri_sel_chn_reg_t out_peri_sel_ch2;
|
||||
uint32_t reserved_284[22];
|
||||
volatile ahb_dma_tx_ch_arb_weigh_chn_reg_t tx_ch_arb_weigh_ch0;
|
||||
volatile ahb_dma_tx_arb_weigh_opt_dir_chn_reg_t tx_arb_weigh_opt_dir_ch0;
|
||||
uint32_t reserved_2e4[8];
|
||||
volatile ahb_dma_tx_ch_arb_weigh_chn_reg_t tx_ch_arb_weigh_ch1;
|
||||
volatile ahb_dma_tx_arb_weigh_opt_dir_chn_reg_t tx_arb_weigh_opt_dir_ch1;
|
||||
uint32_t reserved_30c[8];
|
||||
volatile ahb_dma_tx_ch_arb_weigh_chn_reg_t tx_ch_arb_weigh_ch2;
|
||||
volatile ahb_dma_tx_arb_weigh_opt_dir_chn_reg_t tx_arb_weigh_opt_dir_ch2;
|
||||
uint32_t reserved_334[8];
|
||||
volatile ahb_dma_rx_ch_arb_weigh_chn_reg_t rx_ch_arb_weigh_ch0;
|
||||
volatile ahb_dma_rx_arb_weigh_opt_dir_chn_reg_t rx_arb_weigh_opt_dir_ch0;
|
||||
uint32_t reserved_35c[8];
|
||||
volatile ahb_dma_rx_ch_arb_weigh_chn_reg_t rx_ch_arb_weigh_ch1;
|
||||
volatile ahb_dma_rx_arb_weigh_opt_dir_chn_reg_t rx_arb_weigh_opt_dir_ch1;
|
||||
uint32_t reserved_384[8];
|
||||
volatile ahb_dma_rx_ch_arb_weigh_chn_reg_t rx_ch_arb_weigh_ch2;
|
||||
volatile ahb_dma_rx_arb_weigh_opt_dir_chn_reg_t rx_arb_weigh_opt_dir_ch2;
|
||||
volatile ahb_dma_in_link_addr_chn_reg_t in_link_addr_chn[3];
|
||||
volatile ahb_dma_out_link_addr_chn_reg_t out_link_addr_chn[3];
|
||||
volatile ahb_dma_chn_reg_t channel[3];
|
||||
uint32_t reserved_2b0[3];
|
||||
volatile ahb_dma_out_crc_arb_chn_reg_t out_crc_arb[3];
|
||||
volatile ahb_dma_in_crc_arb_chn_reg_t in_crc_arb[3];
|
||||
volatile ahb_dma_in_link_addr_chn_reg_t in_link_addr[3];
|
||||
volatile ahb_dma_out_link_addr_chn_reg_t out_link_addr[3];
|
||||
volatile ahb_dma_intr_mem_start_addr_reg_t intr_mem_start_addr;
|
||||
volatile ahb_dma_intr_mem_end_addr_reg_t intr_mem_end_addr;
|
||||
volatile ahb_dma_arb_timeout_tx_reg_t arb_timeout_tx;
|
||||
|
||||
@@ -0,0 +1,30 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
// The following macros have a format SOC_[periph][instance_id] to make it work with `GDMA_MAKE_TRIGGER`
|
||||
#define SOC_GDMA_TRIG_PERIPH_M2M0 (-1)
|
||||
#define SOC_GDMA_TRIG_PERIPH_SPI2 (1)
|
||||
#define SOC_GDMA_TRIG_PERIPH_UHCI0 (2)
|
||||
#define SOC_GDMA_TRIG_PERIPH_I2S0 (3)
|
||||
#define SOC_GDMA_TRIG_PERIPH_AES0 (6)
|
||||
#define SOC_GDMA_TRIG_PERIPH_SHA0 (7)
|
||||
#define SOC_GDMA_TRIG_PERIPH_ADC0 (8)
|
||||
#define SOC_GDMA_TRIG_PERIPH_PARLIO0 (9)
|
||||
|
||||
// On which system bus is the DMA instance of the peripheral connection mounted
|
||||
#define SOC_GDMA_BUS_ANY (-1)
|
||||
#define SOC_GDMA_BUS_AHB (0)
|
||||
|
||||
#define SOC_GDMA_TRIG_PERIPH_M2M0_BUS SOC_GDMA_BUS_ANY
|
||||
#define SOC_GDMA_TRIG_PERIPH_SPI2_BUS SOC_GDMA_BUS_AHB
|
||||
#define SOC_GDMA_TRIG_PERIPH_UHCI0_BUS SOC_GDMA_BUS_AHB
|
||||
#define SOC_GDMA_TRIG_PERIPH_I2S0_BUS SOC_GDMA_BUS_AHB
|
||||
#define SOC_GDMA_TRIG_PERIPH_AES0_BUS SOC_GDMA_BUS_AHB
|
||||
#define SOC_GDMA_TRIG_PERIPH_SHA0_BUS SOC_GDMA_BUS_AHB
|
||||
#define SOC_GDMA_TRIG_PERIPH_ADC0_BUS SOC_GDMA_BUS_AHB
|
||||
#define SOC_GDMA_TRIG_PERIPH_PARLIO0_BUS SOC_GDMA_BUS_AHB
|
||||
|
||||
@@ -63,6 +63,7 @@
|
||||
#define DR_REG_PCR_BASE 0x60096000
|
||||
#define DR_REG_TEE_BASE 0x60098000
|
||||
#define DR_REG_HP_APM_BASE 0x60099000
|
||||
#define DR_REG_LP_APM0_BASE 0x60099800
|
||||
#define DR_REG_MISC_BASE 0x6009F000
|
||||
|
||||
/**
|
||||
|
||||
@@ -0,0 +1,68 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "esp_bit_defs.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum periph_retention_module {
|
||||
SLEEP_RETENTION_MODULE_MIN = 0,
|
||||
/* clock module, which includes system and modem */
|
||||
SLEEP_RETENTION_MODULE_CLOCK_SYSTEM = 1,
|
||||
SLEEP_RETENTION_MODULE_CLOCK_MODEM = 2,
|
||||
|
||||
/* modem module, which includes WiFi, BLE and 802.15.4 */
|
||||
SLEEP_RETENTION_MODULE_WIFI_MAC = 10,
|
||||
SLEEP_RETENTION_MODULE_WIFI_BB = 11,
|
||||
SLEEP_RETENTION_MODULE_BLE_MAC = 12,
|
||||
SLEEP_RETENTION_MODULE_BT_BB = 13,
|
||||
SLEEP_RETENTION_MODULE_802154_MAC = 14,
|
||||
|
||||
/* digital peripheral module, which includes Interrupt Matrix, HP_SYSTEM,
|
||||
* TEE, APM, UART, Timer Group, IOMUX, SPIMEM, SysTimer, etc.. */
|
||||
SLEEP_RETENTION_MODULE_SYS_PERIPH = 16,
|
||||
|
||||
SLEEP_RETENTION_MODULE_ADC = 17,
|
||||
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH0 = 24,
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH1 = 25,
|
||||
SLEEP_RETENTION_MODULE_GDMA_CH2 = 26,
|
||||
|
||||
SLEEP_RETENTION_MODULE_MAX = 31
|
||||
} periph_retention_module_t;
|
||||
|
||||
typedef enum periph_retention_module_bitmap {
|
||||
/* clock module, which includes system and modem */
|
||||
SLEEP_RETENTION_MODULE_BM_CLOCK_SYSTEM = BIT(SLEEP_RETENTION_MODULE_CLOCK_SYSTEM),
|
||||
SLEEP_RETENTION_MODULE_BM_CLOCK_MODEM = BIT(SLEEP_RETENTION_MODULE_CLOCK_MODEM),
|
||||
|
||||
/* modem module, which includes WiFi, BLE and 802.15.4 */
|
||||
SLEEP_RETENTION_MODULE_BM_WIFI_MAC = BIT(SLEEP_RETENTION_MODULE_WIFI_MAC),
|
||||
SLEEP_RETENTION_MODULE_BM_WIFI_BB = BIT(SLEEP_RETENTION_MODULE_WIFI_BB),
|
||||
SLEEP_RETENTION_MODULE_BM_BLE_MAC = BIT(SLEEP_RETENTION_MODULE_BLE_MAC),
|
||||
SLEEP_RETENTION_MODULE_BM_BT_BB = BIT(SLEEP_RETENTION_MODULE_BT_BB),
|
||||
SLEEP_RETENTION_MODULE_BM_802154_MAC = BIT(SLEEP_RETENTION_MODULE_802154_MAC),
|
||||
|
||||
/* digital peripheral module, which includes Interrupt Matrix, HP_SYSTEM,
|
||||
* TEE, APM, UART, Timer Group, IOMUX, SPIMEM, SysTimer, etc.. */
|
||||
SLEEP_RETENTION_MODULE_BM_SYS_PERIPH = BIT(SLEEP_RETENTION_MODULE_SYS_PERIPH),
|
||||
|
||||
SLEEP_RETENTION_MODULE_BM_ADC = BIT(SLEEP_RETENTION_MODULE_ADC),
|
||||
|
||||
SLEEP_RETENTION_MODULE_BM_GDMA_CH0 = BIT(SLEEP_RETENTION_MODULE_GDMA_CH0),
|
||||
SLEEP_RETENTION_MODULE_BM_GDMA_CH1 = BIT(SLEEP_RETENTION_MODULE_GDMA_CH1),
|
||||
SLEEP_RETENTION_MODULE_BM_GDMA_CH2 = BIT(SLEEP_RETENTION_MODULE_GDMA_CH2),
|
||||
SLEEP_RETENTION_MODULE_BM_ALL = (uint32_t)-1
|
||||
} periph_retention_module_bitmap_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -20,15 +20,15 @@
|
||||
// #define SOC_ADC_SUPPORTED 1 // TODO: [ESP32C5] IDF-8701
|
||||
// #define SOC_DEDICATED_GPIO_SUPPORTED 1 // TODO: [ESP32C5] IDF-8725
|
||||
#define SOC_UART_SUPPORTED 1 // TODO: [ESP32C5] IDF-8722
|
||||
// #define SOC_GDMA_SUPPORTED 1 // TODO: [ESP32C5] IDF-8710
|
||||
// #define SOC_AHB_GDMA_SUPPORTED 1 // TODO: [ESP32C5] IDF-8710
|
||||
#define SOC_GDMA_SUPPORTED 1
|
||||
#define SOC_AHB_GDMA_SUPPORTED 1
|
||||
#define SOC_GPTIMER_SUPPORTED 1
|
||||
// #define SOC_PCNT_SUPPORTED 1 // TODO: [ESP32C5] IDF-8683
|
||||
// #define SOC_MCPWM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8709
|
||||
// #define SOC_TWAI_SUPPORTED 1 // TODO: [ESP32C5] IDF-8691
|
||||
// #define SOC_ETM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8693
|
||||
// #define SOC_PARLIO_SUPPORTED 1 // TODO: [ESP32C5] IDF-8685, IDF-8686
|
||||
// #define SOC_ASYNC_MEMCPY_SUPPORTED 1 // TODO: [ESP32C5] IDF-8716
|
||||
#define SOC_ASYNC_MEMCPY_SUPPORTED 1
|
||||
// #define SOC_USB_SERIAL_JTAG_SUPPORTED 1 // TODO: [ESP32C5] IDF-8721
|
||||
// #define SOC_TEMP_SENSOR_SUPPORTED 1 // TODO: [ESP32C5] IDF-8727
|
||||
// #define SOC_WIFI_SUPPORTED 1 // TODO: [ESP32C5] IDF-8851
|
||||
@@ -55,7 +55,7 @@
|
||||
#define SOC_FLASH_ENC_SUPPORTED 1 // TODO: [ESP32C5] IDF-8622
|
||||
// #define SOC_SECURE_BOOT_SUPPORTED 1 // TODO: [ESP32C5] IDF-8623
|
||||
// #define SOC_BOD_SUPPORTED 1 // TODO: [ESP32C5] IDF-8647
|
||||
// #define SOC_APM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8614
|
||||
// #define SOC_APM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8614, IDF-8615
|
||||
// #define SOC_PMU_SUPPORTED 1 // TODO: [ESP32C5] IDF-8667
|
||||
// #define SOC_PAU_SUPPORTED 1 // TODO: [ESP32C5] IDF-8638
|
||||
// #define SOC_LP_TIMER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8636
|
||||
@@ -164,11 +164,15 @@
|
||||
See TRM DS chapter for more details */
|
||||
// #define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100)
|
||||
|
||||
/*-------------------------- DMA Common CAPS ----------------------------------------*/
|
||||
#define SOC_DMA_CAN_ACCESS_FLASH 1 /*!< DMA can access Flash memory */
|
||||
|
||||
/*-------------------------- GDMA CAPS -------------------------------------*/
|
||||
// #define SOC_AHB_GDMA_VERSION 1U
|
||||
// #define SOC_GDMA_NUM_GROUPS_MAX 1U
|
||||
// #define SOC_GDMA_PAIRS_PER_GROUP_MAX 3
|
||||
// #define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule
|
||||
#define SOC_AHB_GDMA_VERSION 2
|
||||
#define SOC_GDMA_NUM_GROUPS_MAX 1U
|
||||
#define SOC_GDMA_PAIRS_PER_GROUP_MAX 3
|
||||
// #define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule TODO: IDF-9224
|
||||
// #define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1 // TODO: IDF-9225
|
||||
|
||||
/*-------------------------- ETM CAPS --------------------------------------*/
|
||||
// #define SOC_ETM_GROUPS 1U // Number of ETM groups
|
||||
|
||||
@@ -48,6 +48,7 @@ PROVIDE ( HP_SYSTEM = 0x60095000 );
|
||||
PROVIDE ( PCR = 0x60096000 );
|
||||
PROVIDE ( TEE = 0x60098000 );
|
||||
PROVIDE ( HP_APM = 0x60099000 );
|
||||
PROVIDE ( LP_APM0 = 0x60099800 );
|
||||
PROVIDE ( MISC = 0x6009F000 );
|
||||
|
||||
/* TODO: [ESP32C5] IDF-8845 Check the address */
|
||||
|
||||
Reference in New Issue
Block a user