diff --git a/components/hal/CMakeLists.txt b/components/hal/CMakeLists.txt index 48c74b8246..1e5010efd9 100644 --- a/components/hal/CMakeLists.txt +++ b/components/hal/CMakeLists.txt @@ -156,6 +156,7 @@ if(NOT BOOTLOADER_BUILD) if(${target} STREQUAL "esp32c2") list(APPEND srcs + "ecc_hal.c" "gdma_hal.c" "spi_flash_hal_gpspi.c" "spi_slave_hd_hal.c" diff --git a/components/hal/ecc_hal.c b/components/hal/ecc_hal.c new file mode 100644 index 0000000000..c4063e1357 --- /dev/null +++ b/components/hal/ecc_hal.c @@ -0,0 +1,82 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "hal/ecc_hal.h" +#include "hal/ecc_ll.h" + +void ecc_hal_set_mode(ecc_mode_t mode) +{ + ecc_ll_set_mode(mode); +} + +void ecc_hal_set_curve(ecc_curve_t curve) +{ + ecc_ll_set_curve(curve); +} + +void ecc_hal_start_calc(void) +{ + ecc_ll_clear_interrupt(); + ecc_ll_start_calc(); +} + +int ecc_hal_is_calc_finished(void) +{ + return ecc_ll_is_calc_finished(); +} + +static void clear_param_registers(void) +{ + uint8_t buf[32] = {0}; + + ecc_ll_write_param(ECC_PARAM_PX, buf, sizeof(buf)); + ecc_ll_write_param(ECC_PARAM_PY, buf, sizeof(buf)); + ecc_ll_write_param(ECC_PARAM_K, buf, sizeof(buf)); +} + +void ecc_hal_write_mul_param(const uint8_t *k, const uint8_t *px, const uint8_t *py, uint16_t len) +{ + ecc_curve_t curve = len == 32 ? ECC_CURVE_SECP256R1 : ECC_CURVE_SECP192R1; + ecc_ll_set_curve(curve); + + clear_param_registers(); + + ecc_ll_write_param(ECC_PARAM_K, k, len); + ecc_ll_write_param(ECC_PARAM_PX, px, len); + ecc_ll_write_param(ECC_PARAM_PY, py, len); +} + +void ecc_hal_write_verify_param(const uint8_t *px, const uint8_t *py, uint16_t len) +{ + ecc_curve_t curve = len == 32 ? ECC_CURVE_SECP256R1 : ECC_CURVE_SECP192R1; + ecc_ll_set_curve(curve); + + clear_param_registers(); + + ecc_ll_write_param(ECC_PARAM_PX, px, len); + ecc_ll_write_param(ECC_PARAM_PY, py, len); +} + +int ecc_hal_read_mul_result(uint8_t *rx, uint8_t *ry, uint16_t len) +{ + ecc_mode_t mode = ecc_ll_get_mode(); + + if (mode == ECC_MODE_VERIFY_THEN_POINT_MUL) { + if (!ecc_ll_get_verification_result()) { + memset(rx, 0x0, len); + memset(ry, 0x0, len); + return -1; + } + } + + ecc_ll_read_param(ECC_PARAM_PX, rx, len); + ecc_ll_read_param(ECC_PARAM_PY, ry, len); + return 0; +} + +int ecc_hal_read_verify_result(void) +{ + return ecc_ll_get_verification_result(); +} diff --git a/components/hal/esp32c2/include/hal/clk_gate_ll.h b/components/hal/esp32c2/include/hal/clk_gate_ll.h index 71e549b534..8a355d5fac 100644 --- a/components/hal/esp32c2/include/hal/clk_gate_ll.h +++ b/components/hal/esp32c2/include/hal/clk_gate_ll.h @@ -40,6 +40,8 @@ static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph) return SYSTEM_SPI2_CLK_EN; case PERIPH_GDMA_MODULE: return SYSTEM_DMA_CLK_EN; + case PERIPH_ECC_MODULE: + return SYSTEM_CRYPTO_ECC_CLK_EN; case PERIPH_SHA_MODULE: return SYSTEM_CRYPTO_SHA_CLK_EN; case PERIPH_RNG_MODULE: @@ -81,6 +83,8 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en return SYSTEM_SYSTIMER_RST; case PERIPH_GDMA_MODULE: return SYSTEM_DMA_RST; + case PERIPH_ECC_MODULE: + return SYSTEM_CRYPTO_ECC_RST; case PERIPH_SPI_MODULE: return SYSTEM_SPI01_RST; case PERIPH_SPI2_MODULE: @@ -111,6 +115,7 @@ static uint32_t periph_ll_get_clk_en_reg(periph_module_t periph) case PERIPH_SHA_MODULE: case PERIPH_GDMA_MODULE: + case PERIPH_ECC_MODULE: return SYSTEM_PERIP_CLK_EN1_REG; default: return SYSTEM_PERIP_CLK_EN0_REG; @@ -130,6 +135,7 @@ static uint32_t periph_ll_get_rst_en_reg(periph_module_t periph) case PERIPH_SHA_MODULE: case PERIPH_GDMA_MODULE: + case PERIPH_ECC_MODULE: return SYSTEM_PERIP_RST_EN1_REG; default: return SYSTEM_PERIP_RST_EN0_REG; diff --git a/components/hal/esp32c2/include/hal/ecc_ll.h b/components/hal/esp32c2/include/hal/ecc_ll.h new file mode 100644 index 0000000000..ce7829a432 --- /dev/null +++ b/components/hal/esp32c2/include/hal/ecc_ll.h @@ -0,0 +1,147 @@ +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include +#include "hal/assert.h" +#include "soc/ecc_mult_reg.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + ECC_PARAM_PX = 0x0, + ECC_PARAM_PY, + ECC_PARAM_K, +} ecc_ll_param_t; + +static inline void ecc_ll_enable_interrupt(void) +{ + REG_SET_FIELD(ECC_MULT_INT_ENA_REG, ECC_MULT_CALC_DONE_INT_ENA, 1); +} + +static inline void ecc_ll_disable_interrupt(void) +{ + REG_SET_FIELD(ECC_MULT_INT_ENA_REG, ECC_MULT_CALC_DONE_INT_ENA, 0); +} + +static inline void ecc_ll_clear_interrupt(void) +{ + REG_SET_FIELD(ECC_MULT_INT_CLR_REG, ECC_MULT_CALC_DONE_INT_CLR, 1); +} + +static inline void ecc_ll_set_mode(ecc_mode_t mode) +{ + switch(mode) { + case ECC_MODE_POINT_MUL: + REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 0); + break; + case ECC_MODE_INVERSE_MUL: + REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 1); + break; + case ECC_MODE_VERIFY: + REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 2); + break; + case ECC_MODE_VERIFY_THEN_POINT_MUL: + REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 3); + break; + default: + HAL_ASSERT(false && "Unsupported mode"); + break; + } +} + +static inline void ecc_ll_set_curve(ecc_curve_t curve) +{ + switch(curve) { + case ECC_CURVE_SECP256R1: + REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH); + break; + case ECC_CURVE_SECP192R1: + REG_CLR_BIT(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH); + break; + default: + HAL_ASSERT(false && "Unsupported curve"); + return; + } +} + +static inline void ecc_ll_write_param(ecc_ll_param_t param, const uint8_t *buf, uint16_t len) +{ + uint32_t reg; + uint32_t word; + switch (param) { + case ECC_PARAM_PX: + reg = ECC_MULT_PX_1_REG; + break; + case ECC_PARAM_PY: + reg = ECC_MULT_PY_1_REG; + break; + case ECC_PARAM_K: + reg = ECC_MULT_K_1_REG; + break; + default: + HAL_ASSERT(false && "Invalid parameter"); + return; + } + + for (int i = 0; i < len; i += 4) { + memcpy(&word, buf + i, 4); + REG_WRITE(reg + i, word); + } +} + +static inline void ecc_ll_start_calc(void) +{ + REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_START); +} + +static inline int ecc_ll_is_calc_finished(void) +{ + return REG_GET_FIELD(ECC_MULT_INT_RAW_REG, ECC_MULT_CALC_DONE_INT_RAW); +} + +static inline ecc_mode_t ecc_ll_get_mode(void) +{ + return REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE); +} + +static inline int ecc_ll_get_verification_result(void) +{ + return REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_VERIFICATION_RESULT); +} + +static inline ecc_curve_t ecc_ll_get_curve(void) +{ + return REG_GET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH); +} + +static inline void ecc_ll_read_param(ecc_ll_param_t param, uint8_t *buf, uint16_t len) +{ + uint32_t reg; + switch (param) { + case ECC_PARAM_PX: + reg = ECC_MULT_PX_1_REG; + break; + case ECC_PARAM_PY: + reg = ECC_MULT_PY_1_REG; + break; + case ECC_PARAM_K: + reg = ECC_MULT_K_1_REG; + break; + default: + HAL_ASSERT(false && "Invalid parameter"); + return; + } + + memcpy(buf, (void *)reg, len); +} + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/include/hal/ecc_hal.h b/components/hal/include/hal/ecc_hal.h new file mode 100644 index 0000000000..6b466718a0 --- /dev/null +++ b/components/hal/include/hal/ecc_hal.h @@ -0,0 +1,101 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/******************************************************************************* + * NOTICE + * The HAL is not public api, don't use in application code. + * See readme.md in soc/README.md + ******************************************************************************/ + +#pragma once + +#include "stdint.h" +#include "hal/ecc_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Set the work mode of the operation + * + * @param mode Mode of operation + */ +void ecc_hal_set_mode(ecc_mode_t mode); + +/** + * @brief Set the ECC curve of operation + * + * @param curve Curve to use for operation + */ +void ecc_hal_set_curve(ecc_curve_t curve); + +/** + * @brief Start calculation + * + */ +void ecc_hal_start_calc(void); + +/** + * @brief Check whether the calculation has finished + * + * @return - 1 if the hardware has finished calculating + * - 0 otherwise + */ +int ecc_hal_is_calc_finished(void); + +/** + * @brief Write parameters for point multiplication (K * (Px, Py)) + * + * @param k Scalar value + * @param px X coordinate of the ECC point + * @param py Y coordinate of the ECC point + * @param len Length (in bytes) of the ECC point + * - 32 bytes for SECP256R1 + * - 24 bytes for SECP192R1 + */ +void ecc_hal_write_mul_param(const uint8_t *k, const uint8_t *px, const uint8_t *py, uint16_t len); + +/** + * @brief Write parameters for point verification, + * i.e to check if the point lies on the curve + * + * @param px X coordinate of the ECC point + * @param py Y coordinate of the ECC point + * @param len Length (in bytes) of the ECC point + * - 32 for SECP256R1 + * - 24 for SECP192R1 + */ +void ecc_hal_write_verify_param(const uint8_t *px, const uint8_t *py, uint16_t len); + +/** + * @brief Read point multiplication result + * + * @param rx X coordinate of the multiplication result + * @param ry Y coordinate of the multiplication result + * @param len Length (in bytes) of the ECC point + * - 32 for SECP256R1 + * - 24 for SECP192R1 + * + * @return - 0 if the operation was successful + * - -1 if the operation was not successful + * + * In case the operation is not successful, rx and ry will contain + * all zeros + */ +int ecc_hal_read_mul_result(uint8_t *rx, uint8_t *ry, uint16_t len); + +/** + * @brief Read point verification result + * + * @return - 1 if point lies on curve + * - 0 otherwise + */ +int ecc_hal_read_verify_result(void); + +#ifdef __cplusplus +} +#endif diff --git a/components/hal/include/hal/ecc_types.h b/components/hal/include/hal/ecc_types.h new file mode 100644 index 0000000000..4abea16f6e --- /dev/null +++ b/components/hal/include/hal/ecc_types.h @@ -0,0 +1,18 @@ +/* + * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +typedef enum { + ECC_MODE_POINT_MUL = 0x0, // (Rx, Ry) = K * (Px, Py) + ECC_MODE_INVERSE_MUL, // R = K^(-1) * Py + ECC_MODE_VERIFY, // Check if (Px, Py) are points on the curve + ECC_MODE_VERIFY_THEN_POINT_MUL, // Verify and then perform point multiplication +} ecc_mode_t; + +typedef enum { + ECC_CURVE_SECP192R1 = 0x0, + ECC_CURVE_SECP256R1, +} ecc_curve_t; diff --git a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in index 751eed8737..155215df9b 100644 --- a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in @@ -31,6 +31,10 @@ config SOC_ASYNC_MEMCPY_SUPPORTED bool default y +config SOC_ECC_SUPPORTED + bool + default y + config SOC_SUPPORTS_SECURE_DL_MODE bool default y diff --git a/components/soc/esp32c2/include/soc/ecc_mult_reg.h b/components/soc/esp32c2/include/soc/ecc_mult_reg.h new file mode 100644 index 0000000000..906a91b7af --- /dev/null +++ b/components/soc/esp32c2/include/soc/ecc_mult_reg.h @@ -0,0 +1,292 @@ +/* + * SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define ECC_MULT_INT_RAW_REG (DR_REG_ECC_MULT_BASE + 0xC) +/* ECC_MULT_CALC_DONE_INT_RAW : RO/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the i2s_tx_hung_int interrupt.*/ +#define ECC_MULT_CALC_DONE_INT_RAW (BIT(0)) +#define ECC_MULT_CALC_DONE_INT_RAW_M (BIT(0)) +#define ECC_MULT_CALC_DONE_INT_RAW_V 0x1 +#define ECC_MULT_CALC_DONE_INT_RAW_S 0 + +#define ECC_MULT_INT_ST_REG (DR_REG_ECC_MULT_BASE + 0x10) +/* ECC_MULT_CALC_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The masked interrupt status bit for the i2s_rx_done_int interrupt.*/ +#define ECC_MULT_CALC_DONE_INT_ST (BIT(0)) +#define ECC_MULT_CALC_DONE_INT_ST_M (BIT(0)) +#define ECC_MULT_CALC_DONE_INT_ST_V 0x1 +#define ECC_MULT_CALC_DONE_INT_ST_S 0 + +#define ECC_MULT_INT_ENA_REG (DR_REG_ECC_MULT_BASE + 0x14) +/* ECC_MULT_CALC_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the i2s_rx_done_int interrupt.*/ +#define ECC_MULT_CALC_DONE_INT_ENA (BIT(0)) +#define ECC_MULT_CALC_DONE_INT_ENA_M (BIT(0)) +#define ECC_MULT_CALC_DONE_INT_ENA_V 0x1 +#define ECC_MULT_CALC_DONE_INT_ENA_S 0 + +#define ECC_MULT_INT_CLR_REG (DR_REG_ECC_MULT_BASE + 0x18) +/* ECC_MULT_CALC_DONE_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to clear the i2s_rx_done_int interrupt.*/ +#define ECC_MULT_CALC_DONE_INT_CLR (BIT(0)) +#define ECC_MULT_CALC_DONE_INT_CLR_M (BIT(0)) +#define ECC_MULT_CALC_DONE_INT_CLR_V 0x1 +#define ECC_MULT_CALC_DONE_INT_CLR_S 0 + +#define ECC_MULT_CONF_REG (DR_REG_ECC_MULT_BASE + 0x1C) +/* ECC_MULT_VERIFICATION_RESULT : RO/SS ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Reserve.*/ +#define ECC_MULT_VERIFICATION_RESULT (BIT(8)) +#define ECC_MULT_VERIFICATION_RESULT_M (BIT(8)) +#define ECC_MULT_VERIFICATION_RESULT_V 0x1 +#define ECC_MULT_VERIFICATION_RESULT_S 8 +/* ECC_MULT_WORK_MODE : R/W ;bitpos:[7:5] ;default: 3'b0 ; */ +/*description: Reserved.*/ +#define ECC_MULT_WORK_MODE 0x00000007 +#define ECC_MULT_WORK_MODE_M ((ECC_MULT_WORK_MODE_V)<<(ECC_MULT_WORK_MODE_S)) +#define ECC_MULT_WORK_MODE_V 0x7 +#define ECC_MULT_WORK_MODE_S 5 +/* ECC_MULT_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: clk gate.*/ +#define ECC_MULT_CLK_EN (BIT(4)) +#define ECC_MULT_CLK_EN_M (BIT(4)) +#define ECC_MULT_CLK_EN_V 0x1 +#define ECC_MULT_CLK_EN_S 4 +/* ECC_MULT_SECURITY_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to enable slave receiver mode.*/ +#define ECC_MULT_SECURITY_MODE (BIT(3)) +#define ECC_MULT_SECURITY_MODE_M (BIT(3)) +#define ECC_MULT_SECURITY_MODE_V 0x1 +#define ECC_MULT_SECURITY_MODE_S 3 +/* ECC_MULT_KEY_LENGTH : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to start receiving data.*/ +#define ECC_MULT_KEY_LENGTH (BIT(2)) +#define ECC_MULT_KEY_LENGTH_M (BIT(2)) +#define ECC_MULT_KEY_LENGTH_V 0x1 +#define ECC_MULT_KEY_LENGTH_S 2 +/* ECC_MULT_RESET : WT ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to reset Rx AFIFO.*/ +#define ECC_MULT_RESET (BIT(1)) +#define ECC_MULT_RESET_M (BIT(1)) +#define ECC_MULT_RESET_V 0x1 +#define ECC_MULT_RESET_S 1 +/* ECC_MULT_START : R/W/SC ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to reset receiver.*/ +#define ECC_MULT_START (BIT(0)) +#define ECC_MULT_START_M (BIT(0)) +#define ECC_MULT_START_V 0x1 +#define ECC_MULT_START_S 0 + +#define ECC_MULT_DATE_REG (DR_REG_ECC_MULT_BASE + 0xFC) +/* ECC_MULT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2012230 ; */ +/*description: ECC mult version control register.*/ +#define ECC_MULT_DATE 0x0FFFFFFF +#define ECC_MULT_DATE_M ((ECC_MULT_DATE_V)<<(ECC_MULT_DATE_S)) +#define ECC_MULT_DATE_V 0xFFFFFFF +#define ECC_MULT_DATE_S 0 + +#define ECC_MULT_K_1_REG (DR_REG_ECC_MULT_BASE + 0x0100) +/* ECC_MULT_MEM_K_1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: ECC Mem Parameter k.*/ +#define ECC_MULT_MEM_K_1 0xFFFFFFFF +#define ECC_MULT_MEM_K_1_M ((ECC_MULT_MEM_K_1_V)<<(ECC_MULT_MEM_K_1_S)) +#define ECC_MULT_MEM_K_1_V 0xFFFFFFFF +#define ECC_MULT_MEM_K_1_S 0 + +#define ECC_MULT_K_2_REG (DR_REG_ECC_MULT_BASE + 0x0104) +/* ECC_MULT_MEM_K_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: ECC Mem Parameter k.*/ +#define ECC_MULT_MEM_K_2 0xFFFFFFFF +#define ECC_MULT_MEM_K_2_M ((ECC_MULT_MEM_K_2_V)<<(ECC_MULT_MEM_K_2_S)) +#define ECC_MULT_MEM_K_2_V 0xFFFFFFFF +#define ECC_MULT_MEM_K_2_S 0 + +#define ECC_MULT_K_3_REG (DR_REG_ECC_MULT_BASE + 0x0108) +/* ECC_MULT_MEM_K_3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: ECC Mem Parameter k.*/ +#define ECC_MULT_MEM_K_3 0xFFFFFFFF +#define ECC_MULT_MEM_K_3_M ((ECC_MULT_MEM_K_3_V)<<(ECC_MULT_MEM_K_3_S)) +#define ECC_MULT_MEM_K_3_V 0xFFFFFFFF +#define ECC_MULT_MEM_K_3_S 0 + +#define ECC_MULT_K_4_REG (DR_REG_ECC_MULT_BASE + 0x010c) +/* ECC_MULT_MEM_K_4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: ECC Mem Parameter k.*/ +#define ECC_MULT_MEM_K_4 0xFFFFFFFF +#define ECC_MULT_MEM_K_4_M ((ECC_MULT_MEM_K_4_V)<<(ECC_MULT_MEM_K_4_S)) +#define ECC_MULT_MEM_K_4_V 0xFFFFFFFF +#define ECC_MULT_MEM_K_4_S 0 + +#define ECC_MULT_K_5_REG (DR_REG_ECC_MULT_BASE + 0x0110) +/* ECC_MULT_MEM_K_5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: ECC Mem Parameter k.*/ +#define ECC_MULT_MEM_K_5 0xFFFFFFFF +#define ECC_MULT_MEM_K_5_M ((ECC_MULT_MEM_K_5_V)<<(ECC_MULT_MEM_K_5_S)) +#define ECC_MULT_MEM_K_5_V 0xFFFFFFFF +#define ECC_MULT_MEM_K_5_S 0 + +#define ECC_MULT_K_6_REG (DR_REG_ECC_MULT_BASE + 0x0114) +/* ECC_MULT_MEM_K_6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: ECC Mem Parameter k.*/ +#define ECC_MULT_MEM_K_6 0xFFFFFFFF +#define ECC_MULT_MEM_K_6_M ((ECC_MULT_MEM_K_6_V)<<(ECC_MULT_MEM_K_6_S)) +#define ECC_MULT_MEM_K_6_V 0xFFFFFFFF +#define ECC_MULT_MEM_K_6_S 0 + +#define ECC_MULT_K_7_REG (DR_REG_ECC_MULT_BASE + 0x0118) +/* ECC_MULT_MEM_K_7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: ECC Mem Parameter k.*/ +#define ECC_MULT_MEM_K_7 0xFFFFFFFF +#define ECC_MULT_MEM_K_7_M ((ECC_MULT_MEM_K_7_V)<<(ECC_MULT_MEM_K_7_S)) +#define ECC_MULT_MEM_K_7_V 0xFFFFFFFF +#define ECC_MULT_MEM_K_7_S 0 + +#define ECC_MULT_K_8_REG (DR_REG_ECC_MULT_BASE + 0x011c) +/* ECC_MULT_MEM_K_8 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: ECC Mem Parameter k.*/ +#define ECC_MULT_MEM_K_8 0xFFFFFFFF +#define ECC_MULT_MEM_K_8_M ((ECC_MULT_MEM_K_8_V)<<(ECC_MULT_MEM_K_8_S)) +#define ECC_MULT_MEM_K_8_V 0xFFFFFFFF +#define ECC_MULT_MEM_K_8_S 0 + +#define ECC_MULT_PX_1_REG (DR_REG_ECC_MULT_BASE + 0x0120) +/* ECC_MULT_MEM_PX_1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: ECC Mem Parameter Px.*/ +#define ECC_MULT_MEM_PX_1 0xFFFFFFFF +#define ECC_MULT_MEM_PX_1_M ((ECC_MULT_MEM_PX_1_V)<<(ECC_MULT_MEM_PX_1_S)) +#define ECC_MULT_MEM_PX_1_V 0xFFFFFFFF +#define ECC_MULT_MEM_PX_1_S 0 + +#define ECC_MULT_PX_2_REG (DR_REG_ECC_MULT_BASE + 0x0124) +/* ECC_MULT_MEM_PX_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: ECC Mem Parameter Px.*/ +#define ECC_MULT_MEM_PX_2 0xFFFFFFFF +#define ECC_MULT_MEM_PX_2_M ((ECC_MULT_MEM_PX_2_V)<<(ECC_MULT_MEM_PX_2_S)) +#define ECC_MULT_MEM_PX_2_V 0xFFFFFFFF +#define ECC_MULT_MEM_PX_2_S 0 + +#define ECC_MULT_PX_3_REG (DR_REG_ECC_MULT_BASE + 0x0128) +/* ECC_MULT_MEM_PX_3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: ECC Mem Parameter Px.*/ +#define ECC_MULT_MEM_PX_3 0xFFFFFFFF +#define ECC_MULT_MEM_PX_3_M ((ECC_MULT_MEM_PX_3_V)<<(ECC_MULT_MEM_PX_3_S)) +#define ECC_MULT_MEM_PX_3_V 0xFFFFFFFF +#define ECC_MULT_MEM_PX_3_S 0 + +#define ECC_MULT_PX_4_REG (DR_REG_ECC_MULT_BASE + 0x012c) +/* ECC_MULT_MEM_PX_4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: ECC Mem Parameter Px.*/ +#define ECC_MULT_MEM_PX_4 0xFFFFFFFF +#define ECC_MULT_MEM_PX_4_M ((ECC_MULT_MEM_PX_4_V)<<(ECC_MULT_MEM_PX_4_S)) +#define ECC_MULT_MEM_PX_4_V 0xFFFFFFFF +#define ECC_MULT_MEM_PX_4_S 0 + +#define ECC_MULT_PX_5_REG (DR_REG_ECC_MULT_BASE + 0x0130) +/* ECC_MULT_MEM_PX_5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: ECC Mem Parameter Px.*/ +#define ECC_MULT_MEM_PX_5 0xFFFFFFFF +#define ECC_MULT_MEM_PX_5_M ((ECC_MULT_MEM_PX_5_V)<<(ECC_MULT_MEM_PX_5_S)) +#define ECC_MULT_MEM_PX_5_V 0xFFFFFFFF +#define ECC_MULT_MEM_PX_5_S 0 + +#define ECC_MULT_PX_6_REG (DR_REG_ECC_MULT_BASE + 0x0134) +/* ECC_MULT_MEM_PX_6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: ECC Mem Parameter Px.*/ +#define ECC_MULT_MEM_PX_6 0xFFFFFFFF +#define ECC_MULT_MEM_PX_6_M ((ECC_MULT_MEM_PX_6_V)<<(ECC_MULT_MEM_PX_6_S)) +#define ECC_MULT_MEM_PX_6_V 0xFFFFFFFF +#define ECC_MULT_MEM_PX_6_S 0 + +#define ECC_MULT_PX_7_REG (DR_REG_ECC_MULT_BASE + 0x0138) +/* ECC_MULT_MEM_PX_7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: ECC Mem Parameter Px.*/ +#define ECC_MULT_MEM_PX_7 0xFFFFFFFF +#define ECC_MULT_MEM_PX_7_M ((ECC_MULT_MEM_PX_7_V)<<(ECC_MULT_MEM_PX_7_S)) +#define ECC_MULT_MEM_PX_7_V 0xFFFFFFFF +#define ECC_MULT_MEM_PX_7_S 0 + +#define ECC_MULT_PX_8_REG (DR_REG_ECC_MULT_BASE + 0x013c) +/* ECC_MULT_MEM_PX_8 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: ECC Mem Parameter Px.*/ +#define ECC_MULT_MEM_PX_8 0xFFFFFFFF +#define ECC_MULT_MEM_PX_8_M ((ECC_MULT_MEM_PX_8_V)<<(ECC_MULT_MEM_PX_8_S)) +#define ECC_MULT_MEM_PX_8_V 0xFFFFFFFF +#define ECC_MULT_MEM_PX_8_S 0 + +#define ECC_MULT_PY_1_REG (DR_REG_ECC_MULT_BASE + 0x0140) +/* ECC_MULT_MEM_PY_1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: ECC Mem Parameter Py.*/ +#define ECC_MULT_MEM_PY_1 0xFFFFFFFF +#define ECC_MULT_MEM_PY_1_M ((ECC_MULT_MEM_PY_1_V)<<(ECC_MULT_MEM_PY_1_S)) +#define ECC_MULT_MEM_PY_1_V 0xFFFFFFFF +#define ECC_MULT_MEM_PY_1_S 0 + +#define ECC_MULT_PY_2_REG (DR_REG_ECC_MULT_BASE + 0x0144) +/* ECC_MULT_MEM_PY_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: ECC Mem Parameter Py.*/ +#define ECC_MULT_MEM_PY_2 0xFFFFFFFF +#define ECC_MULT_MEM_PY_2_M ((ECC_MULT_MEM_PY_2_V)<<(ECC_MULT_MEM_PY_2_S)) +#define ECC_MULT_MEM_PY_2_V 0xFFFFFFFF +#define ECC_MULT_MEM_PY_2_S 0 + +#define ECC_MULT_PY_3_REG (DR_REG_ECC_MULT_BASE + 0x0148) +/* ECC_MULT_MEM_PY_3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: ECC Mem Parameter Py.*/ +#define ECC_MULT_MEM_PY_3 0xFFFFFFFF +#define ECC_MULT_MEM_PY_3_M ((ECC_MULT_MEM_PY_3_V)<<(ECC_MULT_MEM_PY_3_S)) +#define ECC_MULT_MEM_PY_3_V 0xFFFFFFFF +#define ECC_MULT_MEM_PY_3_S 0 + +#define ECC_MULT_PY_4_REG (DR_REG_ECC_MULT_BASE + 0x014c) +/* ECC_MULT_MEM_PY_4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: ECC Mem Parameter Py.*/ +#define ECC_MULT_MEM_PY_4 0xFFFFFFFF +#define ECC_MULT_MEM_PY_4_M ((ECC_MULT_MEM_PY_4_V)<<(ECC_MULT_MEM_PY_4_S)) +#define ECC_MULT_MEM_PY_4_V 0xFFFFFFFF +#define ECC_MULT_MEM_PY_4_S 0 + +#define ECC_MULT_PY_5_REG (DR_REG_ECC_MULT_BASE + 0x0150) +/* ECC_MULT_MEM_PY_5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: ECC Mem Parameter Py.*/ +#define ECC_MULT_MEM_PY_5 0xFFFFFFFF +#define ECC_MULT_MEM_PY_5_M ((ECC_MULT_MEM_PY_5_V)<<(ECC_MULT_MEM_PY_5_S)) +#define ECC_MULT_MEM_PY_5_V 0xFFFFFFFF +#define ECC_MULT_MEM_PY_5_S 0 + +#define ECC_MULT_PY_6_REG (DR_REG_ECC_MULT_BASE + 0x0154) +/* ECC_MULT_MEM_PY_6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: ECC Mem Parameter Py.*/ +#define ECC_MULT_MEM_PY_6 0xFFFFFFFF +#define ECC_MULT_MEM_PY_6_M ((ECC_MULT_MEM_PY_6_V)<<(ECC_MULT_MEM_PY_6_S)) +#define ECC_MULT_MEM_PY_6_V 0xFFFFFFFF +#define ECC_MULT_MEM_PY_6_S 0 + +#define ECC_MULT_PY_7_REG (DR_REG_ECC_MULT_BASE + 0x0158) +/* ECC_MULT_MEM_PY_7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: ECC Mem Parameter Py.*/ +#define ECC_MULT_MEM_PY_7 0xFFFFFFFF +#define ECC_MULT_MEM_PY_7_M ((ECC_MULT_MEM_PY_7_V)<<(ECC_MULT_MEM_PY_7_S)) +#define ECC_MULT_MEM_PY_7_V 0xFFFFFFFF +#define ECC_MULT_MEM_PY_7_S 0 + +#define ECC_MULT_PY_8_REG (DR_REG_ECC_MULT_BASE + 0x015c) +/* ECC_MULT_MEM_PY_8 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: ECC Mem Parameter Py.*/ +#define ECC_MULT_MEM_PY_8 0xFFFFFFFF +#define ECC_MULT_MEM_PY_8_M ((ECC_MULT_MEM_PY_8_V)<<(ECC_MULT_MEM_PY_8_S)) +#define ECC_MULT_MEM_PY_8_V 0xFFFFFFFF +#define ECC_MULT_MEM_PY_8_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c2/include/soc/periph_defs.h b/components/soc/esp32c2/include/soc/periph_defs.h index 728bfcc7d1..97ffbefdc7 100644 --- a/components/soc/esp32c2/include/soc/periph_defs.h +++ b/components/soc/esp32c2/include/soc/periph_defs.h @@ -28,6 +28,7 @@ typedef enum { PERIPH_BT_LC_MODULE, PERIPH_AES_MODULE, PERIPH_SHA_MODULE, + PERIPH_ECC_MODULE, PERIPH_GDMA_MODULE, PERIPH_SYSTIMER_MODULE, PERIPH_SARADC_MODULE, diff --git a/components/soc/esp32c2/include/soc/reg_base.h b/components/soc/esp32c2/include/soc/reg_base.h index dede05420a..12165d61e7 100644 --- a/components/soc/esp32c2/include/soc/reg_base.h +++ b/components/soc/esp32c2/include/soc/reg_base.h @@ -9,6 +9,7 @@ #define DR_REG_EXTMEM_BASE 0x600c4000 // CACHE_CONFIG #define DR_REG_MMU_TABLE 0x600c5000 #define DR_REG_SHA_BASE 0x6003b000 +#define DR_REG_ECC_MULT_BASE 0x6003e000 #define DR_REG_GDMA_BASE 0x6003f000 #define DR_REG_ASSIST_DEBUG_BASE 0x600ce000 #define DR_REG_DEDICATED_GPIO_BASE 0x600cf000 diff --git a/components/soc/esp32c2/include/soc/soc_caps.h b/components/soc/esp32c2/include/soc/soc_caps.h index d07d769bd8..b1702f2799 100644 --- a/components/soc/esp32c2/include/soc/soc_caps.h +++ b/components/soc/esp32c2/include/soc/soc_caps.h @@ -32,6 +32,7 @@ #define SOC_BT_SUPPORTED 0 // Enable during bringup, IDF-4357 #define SOC_WIFI_SUPPORTED 0 // Enable during bringup, IDF-3905 #define SOC_ASYNC_MEMCPY_SUPPORTED 1 +#define SOC_ECC_SUPPORTED 1 #define SOC_SUPPORTS_SECURE_DL_MODE 1 #define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 1 #define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 0