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feat(uart): spilt LP and HP uart set_baudrate function

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This commit is contained in:
gaoxu
2023-09-26 17:42:03 +08:00
parent 4f24f805cc
commit bc2a6bd730
17 changed files with 155 additions and 119 deletions
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60
components/hal/esp32c6/include/hal/uart_ll.h
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@@ -85,6 +85,19 @@ typedef enum {
UART_INTR_WAKEUP = (0x1 << 19),
} uart_intr_t;
/**
* @brief Sync the update to UART core clock domain
*
* @param hw Beginning address of the peripheral registers.
*
* @return None.
*/
FORCE_INLINE_ATTR void uart_ll_update(uart_dev_t *hw)
{
hw->reg_update.reg_update = 1;
while (hw->reg_update.reg_update);
}
/****************************************** LP_UART Specific ********************************************/
/**
* @brief Get the LP_UART source clock.
@@ -131,6 +144,32 @@ static inline void lp_uart_ll_set_source_clk(uart_dev_t *hw, soc_periph_lp_uart_
/// LP_CLKRST.lpperi is a shared register, so this function must be used in an atomic way
#define lp_uart_ll_set_source_clk(...) (void)__DECLARE_RCC_ATOMIC_ENV; lp_uart_ll_set_source_clk(__VA_ARGS__)
/**
* @brief Configure the lp uart baud-rate.
*
* @param hw Beginning address of the peripheral registers.
* @param baud The baud rate to be set.
* @param sclk_freq Frequency of the clock source of UART, in Hz.
*
* @return None
*/
FORCE_INLINE_ATTR void lp_uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
{
#define DIV_UP(a, b) (((a) + (b) - 1) / (b))
const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits
uint32_t sclk_div = DIV_UP(sclk_freq, (uint64_t)max_div * baud);
if (sclk_div == 0) abort();
uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div);
// The baud rate configuration register is divided into
// an integer part and a fractional part.
hw->clkdiv_sync.clkdiv_int = clk_div >> 4;
hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, sclk_div - 1);
uart_ll_update(hw);
}
/**
* @brief Enable bus clock for the LP UART module
*
@@ -190,8 +229,7 @@ FORCE_INLINE_ATTR bool uart_ll_is_enabled(uint32_t uart_num)
*/
static inline void uart_ll_enable_bus_clock(uart_port_t uart_num, bool enable)
{
switch (uart_num)
{
switch (uart_num) {
case 0:
PCR.uart0_conf.uart0_clk_en = enable;
break;
@@ -211,8 +249,7 @@ static inline void uart_ll_enable_bus_clock(uart_port_t uart_num, bool enable)
*/
static inline void uart_ll_reset_register(uart_port_t uart_num)
{
switch (uart_num)
{
switch (uart_num) {
case 0:
PCR.uart0_conf.uart0_rst_en = 1;
PCR.uart0_conf.uart0_rst_en = 0;
@@ -228,19 +265,6 @@ static inline void uart_ll_reset_register(uart_port_t uart_num)
}
}
/**
* @brief Sync the update to UART core clock domain
*
* @param hw Beginning address of the peripheral registers.
*
* @return None.
*/
FORCE_INLINE_ATTR void uart_ll_update(uart_dev_t *hw)
{
hw->reg_update.reg_update = 1;
while (hw->reg_update.reg_update);
}
/**
* @brief Configure the UART core reset.
*
@@ -382,7 +406,7 @@ FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint3
hw->clkdiv_sync.clkdiv_int = clk_div >> 4;
hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf;
if ((hw) == &LP_UART) {
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, sclk_div - 1);
abort();
} else {
UART_LL_PCR_REG_U32_SET(hw, sclk_conf, sclk_div_num, sclk_div - 1);
}