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https://github.com/espressif/esp-idf.git
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Initial public version
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125
components/bootloader/src/main/secure_boot.c
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125
components/bootloader/src/main/secure_boot.c
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <string.h>
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#include "esp_attr.h"
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#include "esp_types.h"
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#include "rom/cache.h"
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#include "rom/ets_sys.h"
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#include "rom/spi_flash.h"
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#include "rom/secure_boot.h"
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#include "soc/dport_reg.h"
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#include "soc/io_mux_reg.h"
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#include "soc/efuse_reg.h"
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#include "soc/rtc_cntl_reg.h"
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#include "sdkconfig.h"
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#include "bootloader_log.h"
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#include "bootloader_config.h"
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/**
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* @function : secure_boot_generate
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* @description: generate boot abstruct & iv
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*
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* @inputs: bool
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*/
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bool secure_boot_generate(uint32_t bin_len){
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SpiFlashOpResult spiRet;
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uint16_t i;
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uint32_t buf[32];
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if (bin_len % 128 != 0) {
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bin_len = (bin_len / 128 + 1) * 128;
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}
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ets_secure_boot_start();
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ets_secure_boot_rd_iv(buf);
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ets_secure_boot_hash(NULL);
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Cache_Read_Disable(0);
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/* iv stored in sec 0 */
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spiRet = SPIEraseSector(0);
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if (spiRet != SPI_FLASH_RESULT_OK)
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{
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log_error(SPI_ERROR_LOG);
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return false;
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}
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/* write iv to flash, 0x0000, 128 bytes (1024 bits) */
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spiRet = SPIWrite(0, buf, 128);
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if (spiRet != SPI_FLASH_RESULT_OK)
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{
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log_error(SPI_ERROR_LOG);
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return false;
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}
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log_debug("write iv to flash.\n");
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Cache_Read_Enable(0);
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/* read 4K code image from flash, for test */
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for (i = 0; i < bin_len; i+=128) {
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ets_secure_boot_hash((uint32_t *)(0x3f400000 + 0x1000 + i));
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}
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ets_secure_boot_obtain();
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ets_secure_boot_rd_abstract(buf);
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ets_secure_boot_finish();
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Cache_Read_Disable(0);
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/* write abstract to flash, 0x0080, 64 bytes (512 bits) */
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spiRet = SPIWrite(0x80, buf, 64);
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if (spiRet != SPI_FLASH_RESULT_OK) {
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log_error(SPI_ERROR_LOG);
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return false;
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}
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log_debug("write abstract to flash.\n");
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Cache_Read_Enable(0);
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return true;
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}
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/**
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* @function : secure_boot
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* @description: protect boot code inflash
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*
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* @inputs: bool
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*/
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bool secure_boot(void){
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uint32_t bin_len = 0;
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if (REG_READ(EFUSE_BLK0_RDATA6) & EFUSE_RD_ABS_DONE_0)
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{
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log_info("already secure boot !\n");
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return true;
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} else {
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boot_cache_redirect( 0, 64*1024);
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bin_len = get_bin_len((uint32_t)MEM_CACHE(0x1000));
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if (bin_len == 0) {
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log_error("boot len is error");
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return false;
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}
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if (false == secure_boot_generate(bin_len)){
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log_error("secure boot generate failed");
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return false;
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}
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}
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REG_SET_BIT(EFUSE_BLK0_WDATA6, EFUSE_RD_ABS_DONE_0);
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REG_WRITE(EFUSE_CONF, 0x5A5A); /* efuse_pgm_op_ena, force no rd/wr disable */
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REG_WRITE(EFUSE_CMD, 0x02); /* efuse_pgm_cmd */
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while (REG_READ(EFUSE_CMD)); /* wait for efuse_pagm_cmd=0 */
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log_warn("burn abstract_done_0\n");
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REG_WRITE(EFUSE_CONF, 0x5AA5); /* efuse_read_op_ena, release force */
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REG_WRITE(EFUSE_CMD, 0x01); /* efuse_read_cmd */
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while (REG_READ(EFUSE_CMD)); /* wait for efuse_read_cmd=0 */
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log_debug("read EFUSE_BLK0_RDATA6 %x\n", REG_READ(EFUSE_BLK0_RDATA6));
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return true;
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}
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