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Initial public version
This commit is contained in:
Ivan Grokhotkov
145
components/esp32/include/rom/spi_flash.h
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145
components/esp32/include/rom/spi_flash.h
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// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _ROM_SPI_FLASH_H_
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#define _ROM_SPI_FLASH_H_
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#include <stdint.h>
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#include <stdbool.h>
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#include "esp_attr.h"
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#include "soc/spi_register.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define PERIPHS_SPI_FLASH_CMD SPI_CMD(1)
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#define PERIPHS_SPI_FLASH_ADDR SPI_ADDR(1)
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#define PERIPHS_SPI_FLASH_CTRL SPI_CTRL(1)
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#define PERIPHS_SPI_FLASH_CTRL1 SPI_CTRL1(1)
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#define PERIPHS_SPI_FLASH_STATUS SPI_RD_STATUS(1)
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#define PERIPHS_SPI_FLASH_USRREG SPI_USER(1)
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#define PERIPHS_SPI_FLASH_USRREG1 SPI_USER1(1)
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#define PERIPHS_SPI_FLASH_USRREG2 SPI_USER2(1)
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#define PERIPHS_SPI_FLASH_C0 SPI_W0(1)
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#define PERIPHS_SPI_FLASH_C1 SPI_W1(1)
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#define PERIPHS_SPI_FLASH_C2 SPI_W2(1)
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#define PERIPHS_SPI_FLASH_C3 SPI_W3(1)
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#define PERIPHS_SPI_FLASH_C4 SPI_W4(1)
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#define PERIPHS_SPI_FLASH_C5 SPI_W5(1)
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#define PERIPHS_SPI_FLASH_C6 SPI_W6(1)
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#define PERIPHS_SPI_FLASH_C7 SPI_W7(1)
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#define PERIPHS_SPI_FLASH_TX_CRC SPI_TX_CRC(1)
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#define SPI0_R_QIO_DUMMY_CYCLELEN 3
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#define SPI0_R_QIO_ADDR_BITSLEN 31
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#define SPI0_R_FAST_DUMMY_CYCLELEN 7
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#define SPI0_R_DIO_DUMMY_CYCLELEN 3
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#define SPI0_R_FAST_ADDR_BITSLEN 23
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#define SPI0_R_SIO_ADDR_BITSLEN 23
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#define SPI1_R_QIO_DUMMY_CYCLELEN 3
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#define SPI1_R_QIO_ADDR_BITSLEN 31
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#define SPI1_R_FAST_DUMMY_CYCLELEN 7
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#define SPI1_R_DIO_DUMMY_CYCLELEN 3
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#define SPI1_R_DIO_ADDR_BITSLEN 31
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#define SPI1_R_FAST_ADDR_BITSLEN 23
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#define SPI1_R_SIO_ADDR_BITSLEN 23
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#define SPI_W_SIO_ADDR_BITSLEN 23
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#define TWO_BYTE_STATUS_EN SPI_WRSR_2B
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//SPI address register
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#define SPI_FLASH_BYTES_LEN 24
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#define SPI_BUFF_BYTE_WRITE_NUM 32
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#define SPI_BUFF_BYTE_READ_NUM 64
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#define SPI_BUFF_BYTE_READ_BITS 0x3f
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//SPI status register
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#define SPI_FLASH_BUSY_FLAG BIT0
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#define SPI_FLASH_WRENABLE_FLAG BIT1
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#define SPI_FLASH_BP0 BIT2
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#define SPI_FLASH_BP1 BIT3
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#define SPI_FLASH_BP2 BIT4
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#define FLASH_WR_PROTECT (SPI_FLASH_BP0|SPI_FLASH_BP1|SPI_FLASH_BP2)
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#define SPI_FLASH_QE BIT9
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typedef enum {
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SPI_FLASH_QIO_MODE = 0,
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SPI_FLASH_QOUT_MODE,
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SPI_FLASH_DIO_MODE,
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SPI_FLASH_DOUT_MODE,
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SPI_FLASH_FASTRD_MODE,
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SPI_FLASH_SLOWRD_MODE
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} SpiFlashRdMode;
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typedef enum {
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SPI_FLASH_RESULT_OK,
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SPI_FLASH_RESULT_ERR,
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SPI_FLASH_RESULT_TIMEOUT
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} SpiFlashOpResult;
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typedef struct{
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uint32_t deviceId;
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uint32_t chip_size; // chip size in bytes
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uint32_t block_size;
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uint32_t sector_size;
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uint32_t page_size;
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uint32_t status_mask;
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} SpiFlashChip;
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typedef struct {
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uint8_t data_length;
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uint8_t read_cmd0;
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uint8_t read_cmd1;
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uint8_t write_cmd;
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uint16_t data_mask;
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uint16_t data;
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} SpiCommonCmd;
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void SelectSpiQIO(uint8_t wp_gpio_num, uint32_t ishspi) ROMFN_ATTR;
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void SetSpiDrvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t* drvs) ROMFN_ATTR;
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void SelectSpiFunction(uint32_t ishspi) ROMFN_ATTR;
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SpiFlashOpResult SPIEraseChip(void) ROMFN_ATTR;
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SpiFlashOpResult SPIEraseBlock(uint32_t block_num) ROMFN_ATTR;
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SpiFlashOpResult SPIEraseSector(uint32_t sector_num) ROMFN_ATTR;
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SpiFlashOpResult SPIWrite(uint32_t dest_addr, const uint32_t* src, int32_t len) ROMFN_ATTR;
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void SPI_Write_Encrypt_Enable() ROMFN_ATTR;
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SpiFlashOpResult SPI_Prepare_Encrypt_Data(uint32_t flash_addr, uint32_t* data) ROMFN_ATTR;
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void SPI_Write_Encrypt_Disable() ROMFN_ATTR;
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SpiFlashOpResult SPI_Encrypt_Write(uint32_t flash_addr, uint32_t* data, uint32_t len) ROMFN_ATTR;
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SpiFlashOpResult SPIRead(uint32_t src_addr, uint32_t* dest, int32_t len) ROMFN_ATTR;
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SpiFlashOpResult SPIReadModeCnfig(SpiFlashRdMode mode, bool legacy) ROMFN_ATTR;
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SpiFlashOpResult SPIMasterReadModeCnfig(SpiFlashRdMode mode) ROMFN_ATTR;
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SpiFlashOpResult SPIClkConfig(uint8_t freqdiv, uint8_t spi) ROMFN_ATTR;
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uint16_t SPI_Common_Command(SpiCommonCmd * cmd) ROMFN_ATTR;
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SpiFlashOpResult SPIUnlock() ROMFN_ATTR;
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SpiFlashOpResult SPIEraseArea(uint32_t start_addr, uint32_t area_len) ROMFN_ATTR;
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SpiFlashOpResult SPILock() ROMFN_ATTR;
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SpiFlashOpResult SPIParamCfg(uint32_t deviceId, uint32_t chip_size, uint32_t block_size, uint32_t sector_size, uint32_t page_size, uint32_t status_mask) ROMFN_ATTR;
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SpiFlashOpResult SPI_user_command_read(uint32_t * status, uint8_t cmd) ROMFN_ATTR;
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void spi_cache_sram_init() ROMFN_ATTR;
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//ETS_STATUS ets_unpack_flash_code(uint32_t pos, uint32_t *entry_addr, bool jump, bool sb_need_check, bool config) ROMFN_ATTR;
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//ETS_STATUS ets_unpack_flash_code_legacy(uint32_t pos, uint32_t *entry_addr, bool jump, bool config) ROMFN_ATTR;
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void spi_flash_attach(uint32_t ishspi, bool legacy) ROMFN_ATTR;
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#ifdef __cplusplus
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}
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#endif
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#endif /* _ROM_SPI_FLASH_H_ */
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