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soc: Add a soc cap, SOC_CLK_RC_FAST_D256_SUPPORTED, for whether the target has the RC_FAST_D256 clock

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This commit is contained in:
Song Ruo Jing
2022-10-27 17:18:17 +08:00
parent 2557e24a28
commit be0fdfa176
38 changed files with 170 additions and 145 deletions
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56
components/soc/esp32/include/soc/Kconfig.soc_caps.in
View File

@@ -207,10 +207,6 @@ config SOC_ADC_RTC_MAX_BITWIDTH
int
default 12
config SOC_RTC_SLOW_CLOCK_SUPPORT_8MD256
bool
default y
config SOC_SHARED_IDCACHE_SUPPORTED
bool
default y
@@ -291,26 +287,6 @@ config SOC_I2C_SUPPORT_APB
bool
default y
config SOC_CLK_APLL_SUPPORTED
bool
default y
config SOC_APLL_MULTIPLIER_OUT_MIN_HZ
int
default 350000000
config SOC_APLL_MULTIPLIER_OUT_MAX_HZ
int
default 500000000
config SOC_APLL_MIN_HZ
int
default 5303031
config SOC_APLL_MAX_HZ
int
default 125000000
config SOC_I2S_NUM
int
default 2
@@ -719,6 +695,34 @@ config SOC_PM_SUPPORT_RTC_SLOW_MEM_PD
bool
default y
config SOC_CLK_APLL_SUPPORTED
bool
default y
config SOC_APLL_MULTIPLIER_OUT_MIN_HZ
int
default 350000000
config SOC_APLL_MULTIPLIER_OUT_MAX_HZ
int
default 500000000
config SOC_APLL_MIN_HZ
int
default 5303031
config SOC_APLL_MAX_HZ
int
default 125000000
config SOC_CLK_RC_FAST_D256_SUPPORTED
bool
default y
config SOC_RTC_SLOW_CLK_SUPPORT_RC_FAST_D256
bool
default y
config SOC_SDMMC_USE_IOMUX
bool
default y
@@ -727,10 +731,6 @@ config SOC_SDMMC_NUM_SLOTS
int
default 2
config SOC_WIFI_HW_TSF
bool
default n
config SOC_WIFI_FTM_SUPPORT
bool
default n

21
components/soc/esp32/include/soc/soc_caps.h
View File

@@ -125,7 +125,6 @@
/*!< RTC */
#define SOC_ADC_RTC_MIN_BITWIDTH (9)
#define SOC_ADC_RTC_MAX_BITWIDTH (12)
#define SOC_RTC_SLOW_CLOCK_SUPPORT_8MD256 (1)
/*-------------------------- BROWNOUT CAPS -----------------------------------*/
#if SOC_CAPS_ECO_VER >= 1
@@ -181,14 +180,6 @@
#define SOC_I2C_SUPPORT_APB (1)
/*-------------------------- APLL CAPS ----------------------------------------*/
#define SOC_CLK_APLL_SUPPORTED (1)
// apll_multiplier_out = xtal_freq * (4 + sdm2 + sdm1/256 + sdm0/65536)
#define SOC_APLL_MULTIPLIER_OUT_MIN_HZ (350000000) // 350 MHz
#define SOC_APLL_MULTIPLIER_OUT_MAX_HZ (500000000) // 500 MHz
#define SOC_APLL_MIN_HZ (5303031) // 5.303031 MHz, refer to 'periph_rtc_apll_freq_set' for the calculation
#define SOC_APLL_MAX_HZ (125000000) // 125MHz, refer to 'periph_rtc_apll_freq_set' for the calculation
/*-------------------------- I2S CAPS ----------------------------------------*/
// ESP32 has 2 I2S
#define SOC_I2S_NUM (2U)
@@ -370,6 +361,17 @@
#define SOC_PM_SUPPORT_RTC_FAST_MEM_PD (1)
#define SOC_PM_SUPPORT_RTC_SLOW_MEM_PD (1)
/*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
#define SOC_CLK_APLL_SUPPORTED (1)
// apll_multiplier_out = xtal_freq * (4 + sdm2 + sdm1/256 + sdm0/65536)
#define SOC_APLL_MULTIPLIER_OUT_MIN_HZ (350000000) // 350 MHz
#define SOC_APLL_MULTIPLIER_OUT_MAX_HZ (500000000) // 500 MHz
#define SOC_APLL_MIN_HZ (5303031) // 5.303031 MHz, refer to 'periph_rtc_apll_freq_set' for the calculation
#define SOC_APLL_MAX_HZ (125000000) // 125MHz, refer to 'periph_rtc_apll_freq_set' for the calculation
#define SOC_CLK_RC_FAST_D256_SUPPORTED (1)
#define SOC_RTC_SLOW_CLK_SUPPORT_RC_FAST_D256 (1)
/*-------------------------- SDMMC CAPS -----------------------------------------*/
/* On ESP32, clock/cmd/data pins use IO MUX.
@@ -379,7 +381,6 @@
#define SOC_SDMMC_NUM_SLOTS 2
/*-------------------------- WI-FI HARDWARE CAPS -------------------------------*/
#define SOC_WIFI_HW_TSF (0) /*!< Hardware TSF is not supported */
#define SOC_WIFI_FTM_SUPPORT (0) /*!< FTM is not supported */
#define SOC_WIFI_GCMP_SUPPORT (0) /*!< GCMP is not supported(GCMP128 and GCMP256) */
#define SOC_WIFI_WAPI_SUPPORT (1) /*!< Support WAPI */