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fix(adc): fix adc do not enable/disable regi2c registers

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gaoxu
2025-04-25 14:39:01 +08:00
parent d6fb99b5ad
commit bf335a38f7
38 changed files with 215 additions and 366 deletions
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47
components/hal/esp32c6/include/hal/regi2c_ctrl_ll.h
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@@ -95,55 +95,26 @@ static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_bbpll_calibrati
}
/**
* @brief Enable the I2C internal bus to do I2C read/write operation to the SAR_ADC register
* @brief Enable the I2C internal bus to do I2C read/write operation to the SAR_ADC and TSENS registers
*/
static inline void regi2c_ctrl_ll_i2c_saradc_enable(void)
static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void)
{
CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_SAR_FORCE_PD);
SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PU);
//Enter regi2c reset mode
CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
//Enable REGI2C for SAR_ADC and TSENS
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
//Release regi2c reset mode, enter work mode
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
}
/**
* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register
*/
static inline void regi2c_ctrl_ll_i2c_saradc_disable(void)
{
CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_SAR_FORCE_PU);
SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PD);
}
/**
* @brief Enable regi2c controlled periph registers
*/
static inline void regi2c_ctrl_ll_i2c_periph_enable(void)
{
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
}
/**
* @brief Disable regi2c controlled periph registers
*/
static inline void regi2c_ctrl_ll_i2c_periph_disable(void)
static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void)
{
CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
}
/**
* @brief Enter / Exit reset state
*
* @param enter True to reset mode, false to normal working mode
*/
static inline void regi2c_ctrl_ll_reset(bool enter)
{
if (enter) {
// Reset mode
CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
} else {
// Normal working mode
SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
}
}
#ifdef __cplusplus
}
#endif