feat(esp32h4): ci enable public header check (stage7)

components/hal/esp32h4/include/hal/cache_ll.h

@@ -13,7 +13,7 @@
 #include "soc/ext_mem_defs.h"
 #include "hal/cache_types.h"
 #include "hal/assert.h"
-#include "esp32h4/rom/cache.h"
+#include "rom/cache.h"
 
 //TODO: [ESP32H4] IDF-12289 inherited from verification branch, need check
 

components/hal/esp32h4/include/hal/lpwdt_ll.h

@@ -24,7 +24,7 @@ extern "C" {
 #include "esp_attr.h"
 #include "esp_assert.h"
 
-#include "esp32h4/rom/ets_sys.h"
+#include "rom/ets_sys.h"
 
 /* The value that needs to be written to LP_WDT_WPROTECT_REG to write-enable the wdt registers */
 #define LP_WDT_WKEY_VALUE 0x50D83AA1

components/hal/include/hal/rtc_hal.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -11,11 +11,10 @@
 #include "hal/gpio_types.h"
 #include "sdkconfig.h"
 
-#if !CONFIG_IDF_TARGET_ESP32H21 //TODO: [ESP32H21] IDF-11512
-#if !SOC_LP_TIMER_SUPPORTED
+#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
 #include "hal/rtc_cntl_ll.h"
 #endif
-#endif  //#if !CONFIG_IDF_TARGET_ESP32H21
+
 #if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
 #include "hal/rtc_io_ll.h"
 #endif

components/hal/include/hal/sha_types.h

@@ -31,6 +31,8 @@
 #include "esp32h21/rom/sha.h"
 #elif CONFIG_IDF_TARGET_ESP32P4
 #include "esp32p4/rom/sha.h"
+#elif CONFIG_IDF_TARGET_ESP32H4
+#include "esp32h4/rom/sha.h"
 #endif
 
 #ifdef __cplusplus