mirror of
https://github.com/espressif/esp-idf.git
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refactor(soc): sort esp32c3 soc headers
This commit is contained in:
laokaiyao
committed by
Kevin (Lao Kaiyao)
Kevin (Lao Kaiyao)
parent
6a29351bd0
commit
c079f30295
@@ -1,569 +0,0 @@
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/*
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* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _SOC_APB_CTRL_REG_H_
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#define _SOC_APB_CTRL_REG_H_
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#warning "apb_ctrl_reg is deprecated due to duplicated with syscon_reg, please use syscon_reg instead, they are same"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "soc.h"
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#define APB_CTRL_SYSCLK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x000)
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/* APB_CTRL_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */
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/*description: */
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#define APB_CTRL_RST_TICK_CNT (BIT(12))
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#define APB_CTRL_RST_TICK_CNT_M (BIT(12))
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#define APB_CTRL_RST_TICK_CNT_V 0x1
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#define APB_CTRL_RST_TICK_CNT_S 12
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/* APB_CTRL_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
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/*description: */
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#define APB_CTRL_CLK_EN (BIT(11))
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#define APB_CTRL_CLK_EN_M (BIT(11))
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#define APB_CTRL_CLK_EN_V 0x1
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#define APB_CTRL_CLK_EN_S 11
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/* APB_CTRL_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
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/*description: */
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#define APB_CTRL_CLK_320M_EN (BIT(10))
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#define APB_CTRL_CLK_320M_EN_M (BIT(10))
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#define APB_CTRL_CLK_320M_EN_V 0x1
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#define APB_CTRL_CLK_320M_EN_S 10
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/* APB_CTRL_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */
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/*description: */
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#define APB_CTRL_PRE_DIV_CNT 0x000003FF
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#define APB_CTRL_PRE_DIV_CNT_M ((APB_CTRL_PRE_DIV_CNT_V)<<(APB_CTRL_PRE_DIV_CNT_S))
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#define APB_CTRL_PRE_DIV_CNT_V 0x3FF
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#define APB_CTRL_PRE_DIV_CNT_S 0
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#define APB_CTRL_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x004)
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/* APB_CTRL_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */
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/*description: */
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#define APB_CTRL_TICK_ENABLE (BIT(16))
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#define APB_CTRL_TICK_ENABLE_M (BIT(16))
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#define APB_CTRL_TICK_ENABLE_V 0x1
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#define APB_CTRL_TICK_ENABLE_S 16
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/* APB_CTRL_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */
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/*description: */
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#define APB_CTRL_CK8M_TICK_NUM 0x000000FF
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#define APB_CTRL_CK8M_TICK_NUM_M ((APB_CTRL_CK8M_TICK_NUM_V)<<(APB_CTRL_CK8M_TICK_NUM_S))
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#define APB_CTRL_CK8M_TICK_NUM_V 0xFF
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#define APB_CTRL_CK8M_TICK_NUM_S 8
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/* APB_CTRL_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */
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/*description: */
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#define APB_CTRL_XTAL_TICK_NUM 0x000000FF
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#define APB_CTRL_XTAL_TICK_NUM_M ((APB_CTRL_XTAL_TICK_NUM_V)<<(APB_CTRL_XTAL_TICK_NUM_S))
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#define APB_CTRL_XTAL_TICK_NUM_V 0xFF
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#define APB_CTRL_XTAL_TICK_NUM_S 0
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#define APB_CTRL_CLK_OUT_EN_REG (DR_REG_APB_CTRL_BASE + 0x008)
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/* APB_CTRL_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */
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/*description: */
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#define APB_CTRL_CLK_XTAL_OEN (BIT(10))
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#define APB_CTRL_CLK_XTAL_OEN_M (BIT(10))
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#define APB_CTRL_CLK_XTAL_OEN_V 0x1
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#define APB_CTRL_CLK_XTAL_OEN_S 10
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/* APB_CTRL_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */
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/*description: */
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#define APB_CTRL_CLK40X_BB_OEN (BIT(9))
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#define APB_CTRL_CLK40X_BB_OEN_M (BIT(9))
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#define APB_CTRL_CLK40X_BB_OEN_V 0x1
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#define APB_CTRL_CLK40X_BB_OEN_S 9
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/* APB_CTRL_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */
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/*description: */
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#define APB_CTRL_CLK_DAC_CPU_OEN (BIT(8))
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#define APB_CTRL_CLK_DAC_CPU_OEN_M (BIT(8))
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#define APB_CTRL_CLK_DAC_CPU_OEN_V 0x1
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#define APB_CTRL_CLK_DAC_CPU_OEN_S 8
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/* APB_CTRL_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */
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/*description: */
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#define APB_CTRL_CLK_ADC_INF_OEN (BIT(7))
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#define APB_CTRL_CLK_ADC_INF_OEN_M (BIT(7))
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#define APB_CTRL_CLK_ADC_INF_OEN_V 0x1
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#define APB_CTRL_CLK_ADC_INF_OEN_S 7
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/* APB_CTRL_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */
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/*description: */
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#define APB_CTRL_CLK_320M_OEN (BIT(6))
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#define APB_CTRL_CLK_320M_OEN_M (BIT(6))
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#define APB_CTRL_CLK_320M_OEN_V 0x1
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#define APB_CTRL_CLK_320M_OEN_S 6
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/* APB_CTRL_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */
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/*description: */
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#define APB_CTRL_CLK160_OEN (BIT(5))
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#define APB_CTRL_CLK160_OEN_M (BIT(5))
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#define APB_CTRL_CLK160_OEN_V 0x1
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#define APB_CTRL_CLK160_OEN_S 5
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/* APB_CTRL_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */
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/*description: */
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#define APB_CTRL_CLK80_OEN (BIT(4))
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#define APB_CTRL_CLK80_OEN_M (BIT(4))
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#define APB_CTRL_CLK80_OEN_V 0x1
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#define APB_CTRL_CLK80_OEN_S 4
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/* APB_CTRL_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */
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/*description: */
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#define APB_CTRL_CLK_BB_OEN (BIT(3))
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#define APB_CTRL_CLK_BB_OEN_M (BIT(3))
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#define APB_CTRL_CLK_BB_OEN_V 0x1
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#define APB_CTRL_CLK_BB_OEN_S 3
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/* APB_CTRL_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */
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/*description: */
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#define APB_CTRL_CLK44_OEN (BIT(2))
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#define APB_CTRL_CLK44_OEN_M (BIT(2))
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#define APB_CTRL_CLK44_OEN_V 0x1
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#define APB_CTRL_CLK44_OEN_S 2
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/* APB_CTRL_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */
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/*description: */
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#define APB_CTRL_CLK22_OEN (BIT(1))
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#define APB_CTRL_CLK22_OEN_M (BIT(1))
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#define APB_CTRL_CLK22_OEN_V 0x1
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#define APB_CTRL_CLK22_OEN_S 1
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/* APB_CTRL_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */
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/*description: */
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#define APB_CTRL_CLK20_OEN (BIT(0))
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#define APB_CTRL_CLK20_OEN_M (BIT(0))
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#define APB_CTRL_CLK20_OEN_V 0x1
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#define APB_CTRL_CLK20_OEN_S 0
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#define APB_CTRL_WIFI_BB_CFG_REG (DR_REG_APB_CTRL_BASE + 0x00C)
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/* APB_CTRL_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
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/*description: */
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#define APB_CTRL_WIFI_BB_CFG 0xFFFFFFFF
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#define APB_CTRL_WIFI_BB_CFG_M ((APB_CTRL_WIFI_BB_CFG_V)<<(APB_CTRL_WIFI_BB_CFG_S))
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#define APB_CTRL_WIFI_BB_CFG_V 0xFFFFFFFF
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#define APB_CTRL_WIFI_BB_CFG_S 0
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#define APB_CTRL_WIFI_BB_CFG_2_REG (DR_REG_APB_CTRL_BASE + 0x010)
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/* APB_CTRL_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
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/*description: */
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#define APB_CTRL_WIFI_BB_CFG_2 0xFFFFFFFF
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#define APB_CTRL_WIFI_BB_CFG_2_M ((APB_CTRL_WIFI_BB_CFG_2_V)<<(APB_CTRL_WIFI_BB_CFG_2_S))
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#define APB_CTRL_WIFI_BB_CFG_2_V 0xFFFFFFFF
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#define APB_CTRL_WIFI_BB_CFG_2_S 0
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#define APB_CTRL_WIFI_CLK_EN_REG (DR_REG_APB_CTRL_BASE + 0x014)
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/* APB_CTRL_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
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/*description: */
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#define APB_CTRL_WIFI_CLK_EN 0xFFFFFFFF
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#define APB_CTRL_WIFI_CLK_EN_M ((APB_CTRL_WIFI_CLK_EN_V)<<(APB_CTRL_WIFI_CLK_EN_S))
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#define APB_CTRL_WIFI_CLK_EN_V 0xFFFFFFFF
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#define APB_CTRL_WIFI_CLK_EN_S 0
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#define APB_CTRL_WIFI_RST_EN_REG (DR_REG_APB_CTRL_BASE + 0x018)
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/* APB_CTRL_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
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/*description: */
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#define APB_CTRL_WIFI_RST 0xFFFFFFFF
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#define APB_CTRL_WIFI_RST_M ((APB_CTRL_WIFI_RST_V)<<(APB_CTRL_WIFI_RST_S))
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#define APB_CTRL_WIFI_RST_V 0xFFFFFFFF
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#define APB_CTRL_WIFI_RST_S 0
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#define APB_CTRL_HOST_INF_SEL_REG (DR_REG_APB_CTRL_BASE + 0x01C)
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/* APB_CTRL_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
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/*description: */
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#define APB_CTRL_PERI_IO_SWAP 0x000000FF
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#define APB_CTRL_PERI_IO_SWAP_M ((APB_CTRL_PERI_IO_SWAP_V)<<(APB_CTRL_PERI_IO_SWAP_S))
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#define APB_CTRL_PERI_IO_SWAP_V 0xFF
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#define APB_CTRL_PERI_IO_SWAP_S 0
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#define APB_CTRL_EXT_MEM_PMS_LOCK_REG (DR_REG_APB_CTRL_BASE + 0x020)
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/* APB_CTRL_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
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/*description: */
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#define APB_CTRL_EXT_MEM_PMS_LOCK (BIT(0))
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#define APB_CTRL_EXT_MEM_PMS_LOCK_M (BIT(0))
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#define APB_CTRL_EXT_MEM_PMS_LOCK_V 0x1
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#define APB_CTRL_EXT_MEM_PMS_LOCK_S 0
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#define APB_CTRL_FLASH_ACE0_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x028)
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/* APB_CTRL_FLASH_ACE0_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
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/*description: */
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#define APB_CTRL_FLASH_ACE0_ATTR 0x00000003
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#define APB_CTRL_FLASH_ACE0_ATTR_M ((APB_CTRL_FLASH_ACE0_ATTR_V)<<(APB_CTRL_FLASH_ACE0_ATTR_S))
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#define APB_CTRL_FLASH_ACE0_ATTR_V 0x3
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#define APB_CTRL_FLASH_ACE0_ATTR_S 0
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#define APB_CTRL_FLASH_ACE1_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x02C)
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/* APB_CTRL_FLASH_ACE1_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
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/*description: */
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#define APB_CTRL_FLASH_ACE1_ATTR 0x00000003
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#define APB_CTRL_FLASH_ACE1_ATTR_M ((APB_CTRL_FLASH_ACE1_ATTR_V)<<(APB_CTRL_FLASH_ACE1_ATTR_S))
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#define APB_CTRL_FLASH_ACE1_ATTR_V 0x3
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#define APB_CTRL_FLASH_ACE1_ATTR_S 0
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#define APB_CTRL_FLASH_ACE2_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x030)
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/* APB_CTRL_FLASH_ACE2_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
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/*description: */
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#define APB_CTRL_FLASH_ACE2_ATTR 0x00000003
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#define APB_CTRL_FLASH_ACE2_ATTR_M ((APB_CTRL_FLASH_ACE2_ATTR_V)<<(APB_CTRL_FLASH_ACE2_ATTR_S))
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#define APB_CTRL_FLASH_ACE2_ATTR_V 0x3
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#define APB_CTRL_FLASH_ACE2_ATTR_S 0
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#define APB_CTRL_FLASH_ACE3_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x034)
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/* APB_CTRL_FLASH_ACE3_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
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/*description: */
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#define APB_CTRL_FLASH_ACE3_ATTR 0x00000003
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#define APB_CTRL_FLASH_ACE3_ATTR_M ((APB_CTRL_FLASH_ACE3_ATTR_V)<<(APB_CTRL_FLASH_ACE3_ATTR_S))
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#define APB_CTRL_FLASH_ACE3_ATTR_V 0x3
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#define APB_CTRL_FLASH_ACE3_ATTR_S 0
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#define APB_CTRL_FLASH_ACE0_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x038)
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/* APB_CTRL_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
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/*description: */
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#define APB_CTRL_FLASH_ACE0_ADDR_S 0xFFFFFFFF
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#define APB_CTRL_FLASH_ACE0_ADDR_S_M ((APB_CTRL_FLASH_ACE0_ADDR_S_V)<<(APB_CTRL_FLASH_ACE0_ADDR_S_S))
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#define APB_CTRL_FLASH_ACE0_ADDR_S_V 0xFFFFFFFF
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#define APB_CTRL_FLASH_ACE0_ADDR_S_S 0
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#define APB_CTRL_FLASH_ACE1_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x03C)
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/* APB_CTRL_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h400000 ; */
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/*description: */
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#define APB_CTRL_FLASH_ACE1_ADDR_S 0xFFFFFFFF
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#define APB_CTRL_FLASH_ACE1_ADDR_S_M ((APB_CTRL_FLASH_ACE1_ADDR_S_V)<<(APB_CTRL_FLASH_ACE1_ADDR_S_S))
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#define APB_CTRL_FLASH_ACE1_ADDR_S_V 0xFFFFFFFF
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#define APB_CTRL_FLASH_ACE1_ADDR_S_S 0
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#define APB_CTRL_FLASH_ACE2_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x040)
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/* APB_CTRL_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h800000 ; */
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/*description: */
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#define APB_CTRL_FLASH_ACE2_ADDR_S 0xFFFFFFFF
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#define APB_CTRL_FLASH_ACE2_ADDR_S_M ((APB_CTRL_FLASH_ACE2_ADDR_S_V)<<(APB_CTRL_FLASH_ACE2_ADDR_S_S))
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#define APB_CTRL_FLASH_ACE2_ADDR_S_V 0xFFFFFFFF
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#define APB_CTRL_FLASH_ACE2_ADDR_S_S 0
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#define APB_CTRL_FLASH_ACE3_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x044)
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/* APB_CTRL_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'hC00000 ; */
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/*description: */
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#define APB_CTRL_FLASH_ACE3_ADDR_S 0xFFFFFFFF
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#define APB_CTRL_FLASH_ACE3_ADDR_S_M ((APB_CTRL_FLASH_ACE3_ADDR_S_V)<<(APB_CTRL_FLASH_ACE3_ADDR_S_S))
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#define APB_CTRL_FLASH_ACE3_ADDR_S_V 0xFFFFFFFF
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#define APB_CTRL_FLASH_ACE3_ADDR_S_S 0
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#define APB_CTRL_FLASH_ACE0_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x048)
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/* APB_CTRL_FLASH_ACE0_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
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/*description: */
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#define APB_CTRL_FLASH_ACE0_SIZE 0x00001FFF
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#define APB_CTRL_FLASH_ACE0_SIZE_M ((APB_CTRL_FLASH_ACE0_SIZE_V)<<(APB_CTRL_FLASH_ACE0_SIZE_S))
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#define APB_CTRL_FLASH_ACE0_SIZE_V 0x1FFF
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#define APB_CTRL_FLASH_ACE0_SIZE_S 0
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#define APB_CTRL_FLASH_ACE1_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x04C)
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/* APB_CTRL_FLASH_ACE1_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
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/*description: */
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#define APB_CTRL_FLASH_ACE1_SIZE 0x00001FFF
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#define APB_CTRL_FLASH_ACE1_SIZE_M ((APB_CTRL_FLASH_ACE1_SIZE_V)<<(APB_CTRL_FLASH_ACE1_SIZE_S))
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#define APB_CTRL_FLASH_ACE1_SIZE_V 0x1FFF
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#define APB_CTRL_FLASH_ACE1_SIZE_S 0
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#define APB_CTRL_FLASH_ACE2_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x050)
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/* APB_CTRL_FLASH_ACE2_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
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/*description: */
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#define APB_CTRL_FLASH_ACE2_SIZE 0x00001FFF
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#define APB_CTRL_FLASH_ACE2_SIZE_M ((APB_CTRL_FLASH_ACE2_SIZE_V)<<(APB_CTRL_FLASH_ACE2_SIZE_S))
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#define APB_CTRL_FLASH_ACE2_SIZE_V 0x1FFF
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#define APB_CTRL_FLASH_ACE2_SIZE_S 0
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#define APB_CTRL_FLASH_ACE3_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x054)
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/* APB_CTRL_FLASH_ACE3_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
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/*description: */
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#define APB_CTRL_FLASH_ACE3_SIZE 0x00001FFF
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#define APB_CTRL_FLASH_ACE3_SIZE_M ((APB_CTRL_FLASH_ACE3_SIZE_V)<<(APB_CTRL_FLASH_ACE3_SIZE_S))
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#define APB_CTRL_FLASH_ACE3_SIZE_V 0x1FFF
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#define APB_CTRL_FLASH_ACE3_SIZE_S 0
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#define APB_CTRL_SPI_MEM_PMS_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x088)
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/* APB_CTRL_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */
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/*description: */
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#define APB_CTRL_SPI_MEM_REJECT_CDE 0x0000001F
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#define APB_CTRL_SPI_MEM_REJECT_CDE_M ((APB_CTRL_SPI_MEM_REJECT_CDE_V)<<(APB_CTRL_SPI_MEM_REJECT_CDE_S))
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#define APB_CTRL_SPI_MEM_REJECT_CDE_V 0x1F
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#define APB_CTRL_SPI_MEM_REJECT_CDE_S 2
|
||||
/* APB_CTRL_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_SPI_MEM_REJECT_CLR (BIT(1))
|
||||
#define APB_CTRL_SPI_MEM_REJECT_CLR_M (BIT(1))
|
||||
#define APB_CTRL_SPI_MEM_REJECT_CLR_V 0x1
|
||||
#define APB_CTRL_SPI_MEM_REJECT_CLR_S 1
|
||||
/* APB_CTRL_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_SPI_MEM_REJECT_INT (BIT(0))
|
||||
#define APB_CTRL_SPI_MEM_REJECT_INT_M (BIT(0))
|
||||
#define APB_CTRL_SPI_MEM_REJECT_INT_V 0x1
|
||||
#define APB_CTRL_SPI_MEM_REJECT_INT_S 0
|
||||
|
||||
#define APB_CTRL_SPI_MEM_REJECT_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x08C)
|
||||
/* APB_CTRL_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_SPI_MEM_REJECT_ADDR 0xFFFFFFFF
|
||||
#define APB_CTRL_SPI_MEM_REJECT_ADDR_M ((APB_CTRL_SPI_MEM_REJECT_ADDR_V)<<(APB_CTRL_SPI_MEM_REJECT_ADDR_S))
|
||||
#define APB_CTRL_SPI_MEM_REJECT_ADDR_V 0xFFFFFFFF
|
||||
#define APB_CTRL_SPI_MEM_REJECT_ADDR_S 0
|
||||
|
||||
#define APB_CTRL_SDIO_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x090)
|
||||
/* APB_CTRL_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_SDIO_WIN_ACCESS_EN (BIT(0))
|
||||
#define APB_CTRL_SDIO_WIN_ACCESS_EN_M (BIT(0))
|
||||
#define APB_CTRL_SDIO_WIN_ACCESS_EN_V 0x1
|
||||
#define APB_CTRL_SDIO_WIN_ACCESS_EN_S 0
|
||||
|
||||
#define APB_CTRL_REDCY_SIG0_REG (DR_REG_APB_CTRL_BASE + 0x094)
|
||||
/* APB_CTRL_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_REDCY_ANDOR (BIT(31))
|
||||
#define APB_CTRL_REDCY_ANDOR_M (BIT(31))
|
||||
#define APB_CTRL_REDCY_ANDOR_V 0x1
|
||||
#define APB_CTRL_REDCY_ANDOR_S 31
|
||||
/* APB_CTRL_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_REDCY_SIG0 0x7FFFFFFF
|
||||
#define APB_CTRL_REDCY_SIG0_M ((APB_CTRL_REDCY_SIG0_V)<<(APB_CTRL_REDCY_SIG0_S))
|
||||
#define APB_CTRL_REDCY_SIG0_V 0x7FFFFFFF
|
||||
#define APB_CTRL_REDCY_SIG0_S 0
|
||||
|
||||
#define APB_CTRL_REDCY_SIG1_REG (DR_REG_APB_CTRL_BASE + 0x098)
|
||||
/* APB_CTRL_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_REDCY_NANDOR (BIT(31))
|
||||
#define APB_CTRL_REDCY_NANDOR_M (BIT(31))
|
||||
#define APB_CTRL_REDCY_NANDOR_V 0x1
|
||||
#define APB_CTRL_REDCY_NANDOR_S 31
|
||||
/* APB_CTRL_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_REDCY_SIG1 0x7FFFFFFF
|
||||
#define APB_CTRL_REDCY_SIG1_M ((APB_CTRL_REDCY_SIG1_V)<<(APB_CTRL_REDCY_SIG1_S))
|
||||
#define APB_CTRL_REDCY_SIG1_V 0x7FFFFFFF
|
||||
#define APB_CTRL_REDCY_SIG1_S 0
|
||||
|
||||
#define APB_CTRL_FRONT_END_MEM_PD_REG (DR_REG_APB_CTRL_BASE + 0x09C)
|
||||
/* APB_CTRL_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_DC_MEM_FORCE_PD (BIT(5))
|
||||
#define APB_CTRL_DC_MEM_FORCE_PD_M (BIT(5))
|
||||
#define APB_CTRL_DC_MEM_FORCE_PD_V 0x1
|
||||
#define APB_CTRL_DC_MEM_FORCE_PD_S 5
|
||||
/* APB_CTRL_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_DC_MEM_FORCE_PU (BIT(4))
|
||||
#define APB_CTRL_DC_MEM_FORCE_PU_M (BIT(4))
|
||||
#define APB_CTRL_DC_MEM_FORCE_PU_V 0x1
|
||||
#define APB_CTRL_DC_MEM_FORCE_PU_S 4
|
||||
/* APB_CTRL_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_PBUS_MEM_FORCE_PD (BIT(3))
|
||||
#define APB_CTRL_PBUS_MEM_FORCE_PD_M (BIT(3))
|
||||
#define APB_CTRL_PBUS_MEM_FORCE_PD_V 0x1
|
||||
#define APB_CTRL_PBUS_MEM_FORCE_PD_S 3
|
||||
/* APB_CTRL_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_PBUS_MEM_FORCE_PU (BIT(2))
|
||||
#define APB_CTRL_PBUS_MEM_FORCE_PU_M (BIT(2))
|
||||
#define APB_CTRL_PBUS_MEM_FORCE_PU_V 0x1
|
||||
#define APB_CTRL_PBUS_MEM_FORCE_PU_S 2
|
||||
/* APB_CTRL_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_AGC_MEM_FORCE_PD (BIT(1))
|
||||
#define APB_CTRL_AGC_MEM_FORCE_PD_M (BIT(1))
|
||||
#define APB_CTRL_AGC_MEM_FORCE_PD_V 0x1
|
||||
#define APB_CTRL_AGC_MEM_FORCE_PD_S 1
|
||||
/* APB_CTRL_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_AGC_MEM_FORCE_PU (BIT(0))
|
||||
#define APB_CTRL_AGC_MEM_FORCE_PU_M (BIT(0))
|
||||
#define APB_CTRL_AGC_MEM_FORCE_PU_V 0x1
|
||||
#define APB_CTRL_AGC_MEM_FORCE_PU_S 0
|
||||
|
||||
#define APB_CTRL_RETENTION_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x0A0)
|
||||
/* APB_CTRL_NOBYPASS_CPU_ISO_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_NOBYPASS_CPU_ISO_RST (BIT(27))
|
||||
#define APB_CTRL_NOBYPASS_CPU_ISO_RST_M (BIT(27))
|
||||
#define APB_CTRL_NOBYPASS_CPU_ISO_RST_V 0x1
|
||||
#define APB_CTRL_NOBYPASS_CPU_ISO_RST_S 27
|
||||
/* APB_CTRL_RETENTION_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_RETENTION_LINK_ADDR 0x07FFFFFF
|
||||
#define APB_CTRL_RETENTION_LINK_ADDR_M ((APB_CTRL_RETENTION_LINK_ADDR_V)<<(APB_CTRL_RETENTION_LINK_ADDR_S))
|
||||
#define APB_CTRL_RETENTION_LINK_ADDR_V 0x7FFFFFF
|
||||
#define APB_CTRL_RETENTION_LINK_ADDR_S 0
|
||||
|
||||
#define APB_CTRL_CLKGATE_FORCE_ON_REG (DR_REG_APB_CTRL_BASE + 0x0A4)
|
||||
/* APB_CTRL_SRAM_CLKGATE_FORCE_ON : R/W ;bitpos:[5:2] ;default: ~4'b0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_SRAM_CLKGATE_FORCE_ON 0x0000000F
|
||||
#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_M ((APB_CTRL_SRAM_CLKGATE_FORCE_ON_V)<<(APB_CTRL_SRAM_CLKGATE_FORCE_ON_S))
|
||||
#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_V 0xF
|
||||
#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_S 2
|
||||
/* APB_CTRL_ROM_CLKGATE_FORCE_ON : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_ROM_CLKGATE_FORCE_ON 0x00000003
|
||||
#define APB_CTRL_ROM_CLKGATE_FORCE_ON_M ((APB_CTRL_ROM_CLKGATE_FORCE_ON_V)<<(APB_CTRL_ROM_CLKGATE_FORCE_ON_S))
|
||||
#define APB_CTRL_ROM_CLKGATE_FORCE_ON_V 0x3
|
||||
#define APB_CTRL_ROM_CLKGATE_FORCE_ON_S 0
|
||||
|
||||
#define APB_CTRL_MEM_POWER_DOWN_REG (DR_REG_APB_CTRL_BASE + 0x0A8)
|
||||
/* APB_CTRL_SRAM_POWER_DOWN : R/W ;bitpos:[5:2] ;default: 4'b0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_SRAM_POWER_DOWN 0x0000000F
|
||||
#define APB_CTRL_SRAM_POWER_DOWN_M ((APB_CTRL_SRAM_POWER_DOWN_V)<<(APB_CTRL_SRAM_POWER_DOWN_S))
|
||||
#define APB_CTRL_SRAM_POWER_DOWN_V 0xF
|
||||
#define APB_CTRL_SRAM_POWER_DOWN_S 2
|
||||
/* APB_CTRL_ROM_POWER_DOWN : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_ROM_POWER_DOWN 0x00000003
|
||||
#define APB_CTRL_ROM_POWER_DOWN_M ((APB_CTRL_ROM_POWER_DOWN_V)<<(APB_CTRL_ROM_POWER_DOWN_S))
|
||||
#define APB_CTRL_ROM_POWER_DOWN_V 0x3
|
||||
#define APB_CTRL_ROM_POWER_DOWN_S 0
|
||||
|
||||
#define APB_CTRL_MEM_POWER_UP_REG (DR_REG_APB_CTRL_BASE + 0x0AC)
|
||||
/* APB_CTRL_SRAM_POWER_UP : R/W ;bitpos:[5:2] ;default: ~4'b0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_SRAM_POWER_UP 0x0000000F
|
||||
#define APB_CTRL_SRAM_POWER_UP_M ((APB_CTRL_SRAM_POWER_UP_V)<<(APB_CTRL_SRAM_POWER_UP_S))
|
||||
#define APB_CTRL_SRAM_POWER_UP_V 0xF
|
||||
#define APB_CTRL_SRAM_POWER_UP_S 2
|
||||
/* APB_CTRL_ROM_POWER_UP : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_ROM_POWER_UP 0x00000003
|
||||
#define APB_CTRL_ROM_POWER_UP_M ((APB_CTRL_ROM_POWER_UP_V)<<(APB_CTRL_ROM_POWER_UP_S))
|
||||
#define APB_CTRL_ROM_POWER_UP_V 0x3
|
||||
#define APB_CTRL_ROM_POWER_UP_S 0
|
||||
|
||||
#define APB_CTRL_RND_DATA_REG (DR_REG_APB_CTRL_BASE + 0x0B0)
|
||||
/* APB_CTRL_RND_DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_RND_DATA 0xFFFFFFFF
|
||||
#define APB_CTRL_RND_DATA_M ((APB_CTRL_RND_DATA_V)<<(APB_CTRL_RND_DATA_S))
|
||||
#define APB_CTRL_RND_DATA_V 0xFFFFFFFF
|
||||
#define APB_CTRL_RND_DATA_S 0
|
||||
|
||||
#define APB_CTRL_PERI_BACKUP_CONFIG_REG (DR_REG_APB_CTRL_BASE + 0x0B4)
|
||||
/* APB_CTRL_PERI_BACKUP_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_PERI_BACKUP_ENA (BIT(31))
|
||||
#define APB_CTRL_PERI_BACKUP_ENA_M (BIT(31))
|
||||
#define APB_CTRL_PERI_BACKUP_ENA_V 0x1
|
||||
#define APB_CTRL_PERI_BACKUP_ENA_S 31
|
||||
/* APB_CTRL_PERI_BACKUP_TO_MEM : R/W ;bitpos:[30] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_PERI_BACKUP_TO_MEM (BIT(30))
|
||||
#define APB_CTRL_PERI_BACKUP_TO_MEM_M (BIT(30))
|
||||
#define APB_CTRL_PERI_BACKUP_TO_MEM_V 0x1
|
||||
#define APB_CTRL_PERI_BACKUP_TO_MEM_S 30
|
||||
/* APB_CTRL_PERI_BACKUP_START : WO ;bitpos:[29] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_PERI_BACKUP_START (BIT(29))
|
||||
#define APB_CTRL_PERI_BACKUP_START_M (BIT(29))
|
||||
#define APB_CTRL_PERI_BACKUP_START_V 0x1
|
||||
#define APB_CTRL_PERI_BACKUP_START_S 29
|
||||
/* APB_CTRL_PERI_BACKUP_SIZE : R/W ;bitpos:[28:19] ;default: 10'd0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_PERI_BACKUP_SIZE 0x000003FF
|
||||
#define APB_CTRL_PERI_BACKUP_SIZE_M ((APB_CTRL_PERI_BACKUP_SIZE_V)<<(APB_CTRL_PERI_BACKUP_SIZE_S))
|
||||
#define APB_CTRL_PERI_BACKUP_SIZE_V 0x3FF
|
||||
#define APB_CTRL_PERI_BACKUP_SIZE_S 19
|
||||
/* APB_CTRL_PERI_BACKUP_TOUT_THRES : R/W ;bitpos:[18:9] ;default: 10'd50 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_PERI_BACKUP_TOUT_THRES 0x000003FF
|
||||
#define APB_CTRL_PERI_BACKUP_TOUT_THRES_M ((APB_CTRL_PERI_BACKUP_TOUT_THRES_V)<<(APB_CTRL_PERI_BACKUP_TOUT_THRES_S))
|
||||
#define APB_CTRL_PERI_BACKUP_TOUT_THRES_V 0x3FF
|
||||
#define APB_CTRL_PERI_BACKUP_TOUT_THRES_S 9
|
||||
/* APB_CTRL_PERI_BACKUP_BURST_LIMIT : R/W ;bitpos:[8:4] ;default: 5'd8 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_PERI_BACKUP_BURST_LIMIT 0x0000001F
|
||||
#define APB_CTRL_PERI_BACKUP_BURST_LIMIT_M ((APB_CTRL_PERI_BACKUP_BURST_LIMIT_V)<<(APB_CTRL_PERI_BACKUP_BURST_LIMIT_S))
|
||||
#define APB_CTRL_PERI_BACKUP_BURST_LIMIT_V 0x1F
|
||||
#define APB_CTRL_PERI_BACKUP_BURST_LIMIT_S 4
|
||||
/* APB_CTRL_PERI_BACKUP_FLOW_ERR : RO ;bitpos:[2:1] ;default: 2'd0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_PERI_BACKUP_FLOW_ERR 0x00000003
|
||||
#define APB_CTRL_PERI_BACKUP_FLOW_ERR_M ((APB_CTRL_PERI_BACKUP_FLOW_ERR_V)<<(APB_CTRL_PERI_BACKUP_FLOW_ERR_S))
|
||||
#define APB_CTRL_PERI_BACKUP_FLOW_ERR_V 0x3
|
||||
#define APB_CTRL_PERI_BACKUP_FLOW_ERR_S 1
|
||||
|
||||
#define APB_CTRL_PERI_BACKUP_APB_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x0B8)
|
||||
/* APB_CTRL_BACKUP_APB_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_BACKUP_APB_START_ADDR 0xFFFFFFFF
|
||||
#define APB_CTRL_BACKUP_APB_START_ADDR_M ((APB_CTRL_BACKUP_APB_START_ADDR_V)<<(APB_CTRL_BACKUP_APB_START_ADDR_S))
|
||||
#define APB_CTRL_BACKUP_APB_START_ADDR_V 0xFFFFFFFF
|
||||
#define APB_CTRL_BACKUP_APB_START_ADDR_S 0
|
||||
|
||||
#define APB_CTRL_PERI_BACKUP_MEM_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x0BC)
|
||||
/* APB_CTRL_BACKUP_MEM_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_BACKUP_MEM_START_ADDR 0xFFFFFFFF
|
||||
#define APB_CTRL_BACKUP_MEM_START_ADDR_M ((APB_CTRL_BACKUP_MEM_START_ADDR_V)<<(APB_CTRL_BACKUP_MEM_START_ADDR_S))
|
||||
#define APB_CTRL_BACKUP_MEM_START_ADDR_V 0xFFFFFFFF
|
||||
#define APB_CTRL_BACKUP_MEM_START_ADDR_S 0
|
||||
|
||||
#define APB_CTRL_PERI_BACKUP_INT_RAW_REG (DR_REG_APB_CTRL_BASE + 0x0C0)
|
||||
/* APB_CTRL_PERI_BACKUP_ERR_INT_RAW : RO ;bitpos:[1] ;default: 1'd0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_RAW (BIT(1))
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_RAW_M (BIT(1))
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_RAW_V 0x1
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_RAW_S 1
|
||||
/* APB_CTRL_PERI_BACKUP_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'd0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_RAW (BIT(0))
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_RAW_M (BIT(0))
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_RAW_V 0x1
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_RAW_S 0
|
||||
|
||||
#define APB_CTRL_PERI_BACKUP_INT_ST_REG (DR_REG_APB_CTRL_BASE + 0x0C4)
|
||||
/* APB_CTRL_PERI_BACKUP_ERR_INT_ST : RO ;bitpos:[1] ;default: 1'd0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_ST (BIT(1))
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_ST_M (BIT(1))
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_ST_V 0x1
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_ST_S 1
|
||||
/* APB_CTRL_PERI_BACKUP_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'd0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_ST (BIT(0))
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_ST_M (BIT(0))
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_ST_V 0x1
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_ST_S 0
|
||||
|
||||
#define APB_CTRL_PERI_BACKUP_INT_ENA_REG (DR_REG_APB_CTRL_BASE + 0x0C8)
|
||||
/* APB_CTRL_PERI_BACKUP_ERR_INT_ENA : R/W ;bitpos:[1] ;default: 1'd0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_ENA (BIT(1))
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_ENA_M (BIT(1))
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_ENA_V 0x1
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_ENA_S 1
|
||||
/* APB_CTRL_PERI_BACKUP_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'd0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_ENA (BIT(0))
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_ENA_M (BIT(0))
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_ENA_V 0x1
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_ENA_S 0
|
||||
|
||||
#define APB_CTRL_PERI_BACKUP_INT_CLR_REG (DR_REG_APB_CTRL_BASE + 0x0D0)
|
||||
/* APB_CTRL_PERI_BACKUP_ERR_INT_CLR : WO ;bitpos:[1] ;default: 1'd0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_CLR (BIT(1))
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_CLR_M (BIT(1))
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_CLR_V 0x1
|
||||
#define APB_CTRL_PERI_BACKUP_ERR_INT_CLR_S 1
|
||||
/* APB_CTRL_PERI_BACKUP_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'd0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_CLR (BIT(0))
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_CLR_M (BIT(0))
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_CLR_V 0x1
|
||||
#define APB_CTRL_PERI_BACKUP_DONE_INT_CLR_S 0
|
||||
|
||||
#define APB_CTRL_DATE_REG (DR_REG_APB_CTRL_BASE + 0x3FC)
|
||||
/* APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h2007210 ; */
|
||||
/*description: Version control*/
|
||||
#define APB_CTRL_DATE 0xFFFFFFFF
|
||||
#define APB_CTRL_DATE_M ((APB_CTRL_DATE_V)<<(APB_CTRL_DATE_S))
|
||||
#define APB_CTRL_DATE_V 0xFFFFFFFF
|
||||
#define APB_CTRL_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /*_SOC_APB_CTRL_REG_H_ */
|
||||
@@ -1,477 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#warning "apb_ctrl_struct is deprecated due to duplicated with syscon_struct, please use syscon_struct instead, they are same"
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
typedef volatile struct apb_ctrl_dev_s {
|
||||
union {
|
||||
struct {
|
||||
uint32_t pre_div: 10;
|
||||
uint32_t clk_320m_en: 1;
|
||||
uint32_t clk_en: 1;
|
||||
uint32_t rst_tick: 1;
|
||||
uint32_t reserved13: 19;
|
||||
};
|
||||
uint32_t val;
|
||||
} clk_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t xtal_tick: 8;
|
||||
uint32_t ck8m_tick: 8;
|
||||
uint32_t tick_enable: 1;
|
||||
uint32_t reserved17: 15;
|
||||
};
|
||||
uint32_t val;
|
||||
} tick_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk20_oen: 1;
|
||||
uint32_t clk22_oen: 1;
|
||||
uint32_t clk44_oen: 1;
|
||||
uint32_t clk_bb_oen: 1;
|
||||
uint32_t clk80_oen: 1;
|
||||
uint32_t clk160_oen: 1;
|
||||
uint32_t clk_320m_oen: 1;
|
||||
uint32_t clk_adc_inf_oen: 1;
|
||||
uint32_t clk_dac_cpu_oen: 1;
|
||||
uint32_t clk40x_bb_oen: 1;
|
||||
uint32_t clk_xtal_oen: 1;
|
||||
uint32_t reserved11: 21;
|
||||
};
|
||||
uint32_t val;
|
||||
} clk_out_en;
|
||||
uint32_t wifi_bb_cfg; /**/
|
||||
uint32_t wifi_bb_cfg_2; /**/
|
||||
uint32_t wifi_clk_en; /**/
|
||||
uint32_t wifi_rst_en; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t peri_io_swap: 8;
|
||||
uint32_t reserved8: 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} host_inf_sel;
|
||||
union {
|
||||
struct {
|
||||
uint32_t ext_mem_pms_lock: 1;
|
||||
uint32_t reserved1: 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} ext_mem_pms_lock;
|
||||
uint32_t reserved_24;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace0_attr: 2;
|
||||
uint32_t reserved2: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace0_attr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace1_attr: 2;
|
||||
uint32_t reserved2: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace1_attr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace2_attr: 2;
|
||||
uint32_t reserved2: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace2_attr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace3_attr: 2;
|
||||
uint32_t reserved2: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace3_attr;
|
||||
uint32_t flash_ace0_addr; /**/
|
||||
uint32_t flash_ace1_addr; /**/
|
||||
uint32_t flash_ace2_addr; /**/
|
||||
uint32_t flash_ace3_addr; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace0_size:13;
|
||||
uint32_t reserved13: 19;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace0_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace1_size:13;
|
||||
uint32_t reserved13: 19;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace1_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace2_size:13;
|
||||
uint32_t reserved13: 19;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace2_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace3_size:13;
|
||||
uint32_t reserved13: 19;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace3_size;
|
||||
uint32_t reserved_58;
|
||||
uint32_t reserved_5c;
|
||||
uint32_t reserved_60;
|
||||
uint32_t reserved_64;
|
||||
uint32_t reserved_68;
|
||||
uint32_t reserved_6c;
|
||||
uint32_t reserved_70;
|
||||
uint32_t reserved_74;
|
||||
uint32_t reserved_78;
|
||||
uint32_t reserved_7c;
|
||||
uint32_t reserved_80;
|
||||
uint32_t reserved_84;
|
||||
union {
|
||||
struct {
|
||||
uint32_t spi_mem_reject_int: 1;
|
||||
uint32_t spi_mem_reject_clr: 1;
|
||||
uint32_t spi_mem_reject_cde: 5;
|
||||
uint32_t reserved7: 25;
|
||||
};
|
||||
uint32_t val;
|
||||
} spi_mem_pms_ctrl;
|
||||
uint32_t spi_mem_reject_addr; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t sdio_win_access_en: 1;
|
||||
uint32_t reserved1: 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} sdio_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t redcy_sig0: 31;
|
||||
uint32_t redcy_andor: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} redcy_sig0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t redcy_sig1: 31;
|
||||
uint32_t redcy_nandor: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} redcy_sig1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t agc_mem_force_pu: 1;
|
||||
uint32_t agc_mem_force_pd: 1;
|
||||
uint32_t pbus_mem_force_pu: 1;
|
||||
uint32_t pbus_mem_force_pd: 1;
|
||||
uint32_t dc_mem_force_pu: 1;
|
||||
uint32_t dc_mem_force_pd: 1;
|
||||
uint32_t reserved6: 26;
|
||||
};
|
||||
uint32_t val;
|
||||
} front_end_mem_pd;
|
||||
union {
|
||||
struct {
|
||||
uint32_t retention_link_addr: 27;
|
||||
uint32_t nobypass_cpu_iso_rst: 1;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} retention_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rom_clkgate_force_on: 2;
|
||||
uint32_t sram_clkgate_force_on: 4;
|
||||
uint32_t reserved6: 26;
|
||||
};
|
||||
uint32_t val;
|
||||
} clkgate_force_on;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rom_power_down: 2;
|
||||
uint32_t sram_power_down: 4;
|
||||
uint32_t reserved6: 26;
|
||||
};
|
||||
uint32_t val;
|
||||
} mem_power_down;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rom_power_up: 2;
|
||||
uint32_t sram_power_up: 4;
|
||||
uint32_t reserved6: 26;
|
||||
};
|
||||
uint32_t val;
|
||||
} mem_power_up;
|
||||
uint32_t rnd_data; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 1;
|
||||
uint32_t peri_backup_flow_err: 2;
|
||||
uint32_t reserved3: 1;
|
||||
uint32_t peri_backup_burst_limit: 5;
|
||||
uint32_t peri_backup_tout_thres: 10;
|
||||
uint32_t peri_backup_size: 10;
|
||||
uint32_t peri_backup_start: 1;
|
||||
uint32_t peri_backup_to_mem: 1;
|
||||
uint32_t peri_backup_ena: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} peri_backup_config;
|
||||
uint32_t peri_backup_addr; /**/
|
||||
uint32_t peri_backup_mem_addr; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t peri_backup_done: 1;
|
||||
uint32_t peri_backup_err: 1;
|
||||
uint32_t reserved2: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} peri_backup_int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t peri_backup_done: 1;
|
||||
uint32_t peri_backup_err: 1;
|
||||
uint32_t reserved2: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} peri_backup_int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t peri_backup_done: 1;
|
||||
uint32_t peri_backup_err: 1;
|
||||
uint32_t reserved2: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} peri_backup_int_ena;
|
||||
uint32_t reserved_cc;
|
||||
union {
|
||||
struct {
|
||||
uint32_t peri_backup_done: 1;
|
||||
uint32_t peri_backup_err: 1;
|
||||
uint32_t reserved2: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} peri_backup_int_clr;
|
||||
uint32_t reserved_d4;
|
||||
uint32_t reserved_d8;
|
||||
uint32_t reserved_dc;
|
||||
uint32_t reserved_e0;
|
||||
uint32_t reserved_e4;
|
||||
uint32_t reserved_e8;
|
||||
uint32_t reserved_ec;
|
||||
uint32_t reserved_f0;
|
||||
uint32_t reserved_f4;
|
||||
uint32_t reserved_f8;
|
||||
uint32_t reserved_fc;
|
||||
uint32_t reserved_100;
|
||||
uint32_t reserved_104;
|
||||
uint32_t reserved_108;
|
||||
uint32_t reserved_10c;
|
||||
uint32_t reserved_110;
|
||||
uint32_t reserved_114;
|
||||
uint32_t reserved_118;
|
||||
uint32_t reserved_11c;
|
||||
uint32_t reserved_120;
|
||||
uint32_t reserved_124;
|
||||
uint32_t reserved_128;
|
||||
uint32_t reserved_12c;
|
||||
uint32_t reserved_130;
|
||||
uint32_t reserved_134;
|
||||
uint32_t reserved_138;
|
||||
uint32_t reserved_13c;
|
||||
uint32_t reserved_140;
|
||||
uint32_t reserved_144;
|
||||
uint32_t reserved_148;
|
||||
uint32_t reserved_14c;
|
||||
uint32_t reserved_150;
|
||||
uint32_t reserved_154;
|
||||
uint32_t reserved_158;
|
||||
uint32_t reserved_15c;
|
||||
uint32_t reserved_160;
|
||||
uint32_t reserved_164;
|
||||
uint32_t reserved_168;
|
||||
uint32_t reserved_16c;
|
||||
uint32_t reserved_170;
|
||||
uint32_t reserved_174;
|
||||
uint32_t reserved_178;
|
||||
uint32_t reserved_17c;
|
||||
uint32_t reserved_180;
|
||||
uint32_t reserved_184;
|
||||
uint32_t reserved_188;
|
||||
uint32_t reserved_18c;
|
||||
uint32_t reserved_190;
|
||||
uint32_t reserved_194;
|
||||
uint32_t reserved_198;
|
||||
uint32_t reserved_19c;
|
||||
uint32_t reserved_1a0;
|
||||
uint32_t reserved_1a4;
|
||||
uint32_t reserved_1a8;
|
||||
uint32_t reserved_1ac;
|
||||
uint32_t reserved_1b0;
|
||||
uint32_t reserved_1b4;
|
||||
uint32_t reserved_1b8;
|
||||
uint32_t reserved_1bc;
|
||||
uint32_t reserved_1c0;
|
||||
uint32_t reserved_1c4;
|
||||
uint32_t reserved_1c8;
|
||||
uint32_t reserved_1cc;
|
||||
uint32_t reserved_1d0;
|
||||
uint32_t reserved_1d4;
|
||||
uint32_t reserved_1d8;
|
||||
uint32_t reserved_1dc;
|
||||
uint32_t reserved_1e0;
|
||||
uint32_t reserved_1e4;
|
||||
uint32_t reserved_1e8;
|
||||
uint32_t reserved_1ec;
|
||||
uint32_t reserved_1f0;
|
||||
uint32_t reserved_1f4;
|
||||
uint32_t reserved_1f8;
|
||||
uint32_t reserved_1fc;
|
||||
uint32_t reserved_200;
|
||||
uint32_t reserved_204;
|
||||
uint32_t reserved_208;
|
||||
uint32_t reserved_20c;
|
||||
uint32_t reserved_210;
|
||||
uint32_t reserved_214;
|
||||
uint32_t reserved_218;
|
||||
uint32_t reserved_21c;
|
||||
uint32_t reserved_220;
|
||||
uint32_t reserved_224;
|
||||
uint32_t reserved_228;
|
||||
uint32_t reserved_22c;
|
||||
uint32_t reserved_230;
|
||||
uint32_t reserved_234;
|
||||
uint32_t reserved_238;
|
||||
uint32_t reserved_23c;
|
||||
uint32_t reserved_240;
|
||||
uint32_t reserved_244;
|
||||
uint32_t reserved_248;
|
||||
uint32_t reserved_24c;
|
||||
uint32_t reserved_250;
|
||||
uint32_t reserved_254;
|
||||
uint32_t reserved_258;
|
||||
uint32_t reserved_25c;
|
||||
uint32_t reserved_260;
|
||||
uint32_t reserved_264;
|
||||
uint32_t reserved_268;
|
||||
uint32_t reserved_26c;
|
||||
uint32_t reserved_270;
|
||||
uint32_t reserved_274;
|
||||
uint32_t reserved_278;
|
||||
uint32_t reserved_27c;
|
||||
uint32_t reserved_280;
|
||||
uint32_t reserved_284;
|
||||
uint32_t reserved_288;
|
||||
uint32_t reserved_28c;
|
||||
uint32_t reserved_290;
|
||||
uint32_t reserved_294;
|
||||
uint32_t reserved_298;
|
||||
uint32_t reserved_29c;
|
||||
uint32_t reserved_2a0;
|
||||
uint32_t reserved_2a4;
|
||||
uint32_t reserved_2a8;
|
||||
uint32_t reserved_2ac;
|
||||
uint32_t reserved_2b0;
|
||||
uint32_t reserved_2b4;
|
||||
uint32_t reserved_2b8;
|
||||
uint32_t reserved_2bc;
|
||||
uint32_t reserved_2c0;
|
||||
uint32_t reserved_2c4;
|
||||
uint32_t reserved_2c8;
|
||||
uint32_t reserved_2cc;
|
||||
uint32_t reserved_2d0;
|
||||
uint32_t reserved_2d4;
|
||||
uint32_t reserved_2d8;
|
||||
uint32_t reserved_2dc;
|
||||
uint32_t reserved_2e0;
|
||||
uint32_t reserved_2e4;
|
||||
uint32_t reserved_2e8;
|
||||
uint32_t reserved_2ec;
|
||||
uint32_t reserved_2f0;
|
||||
uint32_t reserved_2f4;
|
||||
uint32_t reserved_2f8;
|
||||
uint32_t reserved_2fc;
|
||||
uint32_t reserved_300;
|
||||
uint32_t reserved_304;
|
||||
uint32_t reserved_308;
|
||||
uint32_t reserved_30c;
|
||||
uint32_t reserved_310;
|
||||
uint32_t reserved_314;
|
||||
uint32_t reserved_318;
|
||||
uint32_t reserved_31c;
|
||||
uint32_t reserved_320;
|
||||
uint32_t reserved_324;
|
||||
uint32_t reserved_328;
|
||||
uint32_t reserved_32c;
|
||||
uint32_t reserved_330;
|
||||
uint32_t reserved_334;
|
||||
uint32_t reserved_338;
|
||||
uint32_t reserved_33c;
|
||||
uint32_t reserved_340;
|
||||
uint32_t reserved_344;
|
||||
uint32_t reserved_348;
|
||||
uint32_t reserved_34c;
|
||||
uint32_t reserved_350;
|
||||
uint32_t reserved_354;
|
||||
uint32_t reserved_358;
|
||||
uint32_t reserved_35c;
|
||||
uint32_t reserved_360;
|
||||
uint32_t reserved_364;
|
||||
uint32_t reserved_368;
|
||||
uint32_t reserved_36c;
|
||||
uint32_t reserved_370;
|
||||
uint32_t reserved_374;
|
||||
uint32_t reserved_378;
|
||||
uint32_t reserved_37c;
|
||||
uint32_t reserved_380;
|
||||
uint32_t reserved_384;
|
||||
uint32_t reserved_388;
|
||||
uint32_t reserved_38c;
|
||||
uint32_t reserved_390;
|
||||
uint32_t reserved_394;
|
||||
uint32_t reserved_398;
|
||||
uint32_t reserved_39c;
|
||||
uint32_t reserved_3a0;
|
||||
uint32_t reserved_3a4;
|
||||
uint32_t reserved_3a8;
|
||||
uint32_t reserved_3ac;
|
||||
uint32_t reserved_3b0;
|
||||
uint32_t reserved_3b4;
|
||||
uint32_t reserved_3b8;
|
||||
uint32_t reserved_3bc;
|
||||
uint32_t reserved_3c0;
|
||||
uint32_t reserved_3c4;
|
||||
uint32_t reserved_3c8;
|
||||
uint32_t reserved_3cc;
|
||||
uint32_t reserved_3d0;
|
||||
uint32_t reserved_3d4;
|
||||
uint32_t reserved_3d8;
|
||||
uint32_t reserved_3dc;
|
||||
uint32_t reserved_3e0;
|
||||
uint32_t reserved_3e4;
|
||||
uint32_t reserved_3e8;
|
||||
uint32_t reserved_3ec;
|
||||
uint32_t reserved_3f0;
|
||||
uint32_t reserved_3f4;
|
||||
uint32_t reserved_3f8;
|
||||
uint32_t date; /*Version control*/
|
||||
} apb_ctrl_dev_t;
|
||||
extern apb_ctrl_dev_t APB_CTRL;
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,631 +0,0 @@
|
||||
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_APB_SARADC_REG_H_
|
||||
#define _SOC_APB_SARADC_REG_H_
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#include "soc.h"
|
||||
#define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x000)
|
||||
/* APB_SARADC_WAIT_ARB_CYCLE : R/W ;bitpos:[31:30] ;default: 2'd1 ; */
|
||||
/*description: wait arbit signal stable after sar_done*/
|
||||
#define APB_SARADC_WAIT_ARB_CYCLE 0x00000003
|
||||
#define APB_SARADC_WAIT_ARB_CYCLE_M ((APB_SARADC_WAIT_ARB_CYCLE_V)<<(APB_SARADC_WAIT_ARB_CYCLE_S))
|
||||
#define APB_SARADC_WAIT_ARB_CYCLE_V 0x3
|
||||
#define APB_SARADC_WAIT_ARB_CYCLE_S 30
|
||||
/* APB_SARADC_XPD_SAR_FORCE : R/W ;bitpos:[28:27] ;default: 2'd0 ; */
|
||||
/*description: force option to xpd sar blocks*/
|
||||
#define APB_SARADC_XPD_SAR_FORCE 0x00000003
|
||||
#define APB_SARADC_XPD_SAR_FORCE_M ((APB_SARADC_XPD_SAR_FORCE_V)<<(APB_SARADC_XPD_SAR_FORCE_S))
|
||||
#define APB_SARADC_XPD_SAR_FORCE_V 0x3
|
||||
#define APB_SARADC_XPD_SAR_FORCE_S 27
|
||||
/* APB_SARADC_SAR_PATT_P_CLEAR : R/W ;bitpos:[23] ;default: 1'd0 ; */
|
||||
/*description: clear the pointer of pattern table for DIG ADC1 CTRL*/
|
||||
#define APB_SARADC_SAR_PATT_P_CLEAR (BIT(23))
|
||||
#define APB_SARADC_SAR_PATT_P_CLEAR_M (BIT(23))
|
||||
#define APB_SARADC_SAR_PATT_P_CLEAR_V 0x1
|
||||
#define APB_SARADC_SAR_PATT_P_CLEAR_S 23
|
||||
/* APB_SARADC_SAR_PATT_LEN : R/W ;bitpos:[17:15] ;default: 3'd7 ; */
|
||||
/*description: 0 ~ 15 means length 1 ~ 16*/
|
||||
#define APB_SARADC_SAR_PATT_LEN 0x00000007
|
||||
#define APB_SARADC_SAR_PATT_LEN_M ((APB_SARADC_SAR_PATT_LEN_V)<<(APB_SARADC_SAR_PATT_LEN_S))
|
||||
#define APB_SARADC_SAR_PATT_LEN_V 0x7
|
||||
#define APB_SARADC_SAR_PATT_LEN_S 15
|
||||
/* APB_SARADC_SAR_CLK_DIV : R/W ;bitpos:[14:7] ;default: 8'd4 ; */
|
||||
/*description: SAR clock divider*/
|
||||
#define APB_SARADC_SAR_CLK_DIV 0x000000FF
|
||||
#define APB_SARADC_SAR_CLK_DIV_M ((APB_SARADC_SAR_CLK_DIV_V)<<(APB_SARADC_SAR_CLK_DIV_S))
|
||||
#define APB_SARADC_SAR_CLK_DIV_V 0xFF
|
||||
#define APB_SARADC_SAR_CLK_DIV_S 7
|
||||
/* APB_SARADC_SAR_CLK_GATED : R/W ;bitpos:[6] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_SAR_CLK_GATED (BIT(6))
|
||||
#define APB_SARADC_SAR_CLK_GATED_M (BIT(6))
|
||||
#define APB_SARADC_SAR_CLK_GATED_V 0x1
|
||||
#define APB_SARADC_SAR_CLK_GATED_S 6
|
||||
/* APB_SARADC_START : R/W ;bitpos:[1] ;default: 1'd0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_START (BIT(1))
|
||||
#define APB_SARADC_START_M (BIT(1))
|
||||
#define APB_SARADC_START_V 0x1
|
||||
#define APB_SARADC_START_S 1
|
||||
/* APB_SARADC_START_FORCE : R/W ;bitpos:[0] ;default: 1'd0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_START_FORCE (BIT(0))
|
||||
#define APB_SARADC_START_FORCE_M (BIT(0))
|
||||
#define APB_SARADC_START_FORCE_V 0x1
|
||||
#define APB_SARADC_START_FORCE_S 0
|
||||
|
||||
#define APB_SARADC_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x004)
|
||||
/* APB_SARADC_TIMER_EN : R/W ;bitpos:[24] ;default: 1'd0 ; */
|
||||
/*description: to enable saradc timer trigger*/
|
||||
#define APB_SARADC_TIMER_EN (BIT(24))
|
||||
#define APB_SARADC_TIMER_EN_M (BIT(24))
|
||||
#define APB_SARADC_TIMER_EN_V 0x1
|
||||
#define APB_SARADC_TIMER_EN_S 24
|
||||
/* APB_SARADC_TIMER_TARGET : R/W ;bitpos:[23:12] ;default: 12'd10 ; */
|
||||
/*description: to set saradc timer target*/
|
||||
#define APB_SARADC_TIMER_TARGET 0x00000FFF
|
||||
#define APB_SARADC_TIMER_TARGET_M ((APB_SARADC_TIMER_TARGET_V)<<(APB_SARADC_TIMER_TARGET_S))
|
||||
#define APB_SARADC_TIMER_TARGET_V 0xFFF
|
||||
#define APB_SARADC_TIMER_TARGET_S 12
|
||||
/* APB_SARADC_SAR2_INV : R/W ;bitpos:[10] ;default: 1'd0 ; */
|
||||
/*description: 1: data to DIG ADC2 CTRL is inverted otherwise not*/
|
||||
#define APB_SARADC_SAR2_INV (BIT(10))
|
||||
#define APB_SARADC_SAR2_INV_M (BIT(10))
|
||||
#define APB_SARADC_SAR2_INV_V 0x1
|
||||
#define APB_SARADC_SAR2_INV_S 10
|
||||
/* APB_SARADC_SAR1_INV : R/W ;bitpos:[9] ;default: 1'd0 ; */
|
||||
/*description: 1: data to DIG ADC1 CTRL is inverted otherwise not*/
|
||||
#define APB_SARADC_SAR1_INV (BIT(9))
|
||||
#define APB_SARADC_SAR1_INV_M (BIT(9))
|
||||
#define APB_SARADC_SAR1_INV_V 0x1
|
||||
#define APB_SARADC_SAR1_INV_S 9
|
||||
/* APB_SARADC_MAX_MEAS_NUM : R/W ;bitpos:[8:1] ;default: 8'd255 ; */
|
||||
/*description: max conversion number*/
|
||||
#define APB_SARADC_MAX_MEAS_NUM 0x000000FF
|
||||
#define APB_SARADC_MAX_MEAS_NUM_M ((APB_SARADC_MAX_MEAS_NUM_V)<<(APB_SARADC_MAX_MEAS_NUM_S))
|
||||
#define APB_SARADC_MAX_MEAS_NUM_V 0xFF
|
||||
#define APB_SARADC_MAX_MEAS_NUM_S 1
|
||||
/* APB_SARADC_MEAS_NUM_LIMIT : R/W ;bitpos:[0] ;default: 1'd0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_MEAS_NUM_LIMIT (BIT(0))
|
||||
#define APB_SARADC_MEAS_NUM_LIMIT_M (BIT(0))
|
||||
#define APB_SARADC_MEAS_NUM_LIMIT_V 0x1
|
||||
#define APB_SARADC_MEAS_NUM_LIMIT_S 0
|
||||
|
||||
#define APB_SARADC_FILTER_CTRL1_REG (DR_REG_APB_SARADC_BASE + 0x008)
|
||||
/* APB_SARADC_FILTER_FACTOR0 : R/W ;bitpos:[31:29] ;default: 3'd0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_FILTER_FACTOR0 0x00000007
|
||||
#define APB_SARADC_FILTER_FACTOR0_M ((APB_SARADC_FILTER_FACTOR0_V)<<(APB_SARADC_FILTER_FACTOR0_S))
|
||||
#define APB_SARADC_FILTER_FACTOR0_V 0x7
|
||||
#define APB_SARADC_FILTER_FACTOR0_S 29
|
||||
/* APB_SARADC_FILTER_FACTOR1 : R/W ;bitpos:[28:26] ;default: 3'd0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_FILTER_FACTOR1 0x00000007
|
||||
#define APB_SARADC_FILTER_FACTOR1_M ((APB_SARADC_FILTER_FACTOR1_V)<<(APB_SARADC_FILTER_FACTOR1_S))
|
||||
#define APB_SARADC_FILTER_FACTOR1_V 0x7
|
||||
#define APB_SARADC_FILTER_FACTOR1_S 26
|
||||
|
||||
#define APB_SARADC_FSM_WAIT_REG (DR_REG_APB_SARADC_BASE + 0x00C)
|
||||
/* APB_SARADC_STANDBY_WAIT : R/W ;bitpos:[23:16] ;default: 8'd255 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_STANDBY_WAIT 0x000000FF
|
||||
#define APB_SARADC_STANDBY_WAIT_M ((APB_SARADC_STANDBY_WAIT_V)<<(APB_SARADC_STANDBY_WAIT_S))
|
||||
#define APB_SARADC_STANDBY_WAIT_V 0xFF
|
||||
#define APB_SARADC_STANDBY_WAIT_S 16
|
||||
/* APB_SARADC_RSTB_WAIT : R/W ;bitpos:[15:8] ;default: 8'd8 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_RSTB_WAIT 0x000000FF
|
||||
#define APB_SARADC_RSTB_WAIT_M ((APB_SARADC_RSTB_WAIT_V)<<(APB_SARADC_RSTB_WAIT_S))
|
||||
#define APB_SARADC_RSTB_WAIT_V 0xFF
|
||||
#define APB_SARADC_RSTB_WAIT_S 8
|
||||
/* APB_SARADC_XPD_WAIT : R/W ;bitpos:[7:0] ;default: 8'd8 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_XPD_WAIT 0x000000FF
|
||||
#define APB_SARADC_XPD_WAIT_M ((APB_SARADC_XPD_WAIT_V)<<(APB_SARADC_XPD_WAIT_S))
|
||||
#define APB_SARADC_XPD_WAIT_V 0xFF
|
||||
#define APB_SARADC_XPD_WAIT_S 0
|
||||
|
||||
#define APB_SARADC_SAR1_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x010)
|
||||
/* APB_SARADC_SAR1_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_SAR1_STATUS 0xFFFFFFFF
|
||||
#define APB_SARADC_SAR1_STATUS_M ((APB_SARADC_SAR1_STATUS_V)<<(APB_SARADC_SAR1_STATUS_S))
|
||||
#define APB_SARADC_SAR1_STATUS_V 0xFFFFFFFF
|
||||
#define APB_SARADC_SAR1_STATUS_S 0
|
||||
|
||||
#define APB_SARADC_SAR2_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x014)
|
||||
/* APB_SARADC_SAR2_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_SAR2_STATUS 0xFFFFFFFF
|
||||
#define APB_SARADC_SAR2_STATUS_M ((APB_SARADC_SAR2_STATUS_V)<<(APB_SARADC_SAR2_STATUS_S))
|
||||
#define APB_SARADC_SAR2_STATUS_V 0xFFFFFFFF
|
||||
#define APB_SARADC_SAR2_STATUS_S 0
|
||||
|
||||
#define APB_SARADC_SAR_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x018)
|
||||
/* APB_SARADC_SAR_PATT_TAB1 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
|
||||
/*description: item 0 ~ 3 for pattern table 1 (each item one byte)*/
|
||||
#define APB_SARADC_SAR_PATT_TAB1 0x00FFFFFF
|
||||
#define APB_SARADC_SAR_PATT_TAB1_M ((APB_SARADC_SAR_PATT_TAB1_V)<<(APB_SARADC_SAR_PATT_TAB1_S))
|
||||
#define APB_SARADC_SAR_PATT_TAB1_V 0xFFFFFF
|
||||
#define APB_SARADC_SAR_PATT_TAB1_S 0
|
||||
|
||||
#define APB_SARADC_SAR_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x01C)
|
||||
/* APB_SARADC_SAR_PATT_TAB2 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
|
||||
/*description: Item 4 ~ 7 for pattern table 1 (each item one byte)*/
|
||||
#define APB_SARADC_SAR_PATT_TAB2 0x00FFFFFF
|
||||
#define APB_SARADC_SAR_PATT_TAB2_M ((APB_SARADC_SAR_PATT_TAB2_V)<<(APB_SARADC_SAR_PATT_TAB2_S))
|
||||
#define APB_SARADC_SAR_PATT_TAB2_V 0xFFFFFF
|
||||
#define APB_SARADC_SAR_PATT_TAB2_S 0
|
||||
|
||||
#define APB_SARADC_ONETIME_SAMPLE_REG (DR_REG_APB_SARADC_BASE + 0x020)
|
||||
/* APB_SARADC1_ONETIME_SAMPLE : R/W ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC1_ONETIME_SAMPLE (BIT(31))
|
||||
#define APB_SARADC1_ONETIME_SAMPLE_M (BIT(31))
|
||||
#define APB_SARADC1_ONETIME_SAMPLE_V 0x1
|
||||
#define APB_SARADC1_ONETIME_SAMPLE_S 31
|
||||
/* APB_SARADC2_ONETIME_SAMPLE : R/W ;bitpos:[30] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC2_ONETIME_SAMPLE (BIT(30))
|
||||
#define APB_SARADC2_ONETIME_SAMPLE_M (BIT(30))
|
||||
#define APB_SARADC2_ONETIME_SAMPLE_V 0x1
|
||||
#define APB_SARADC2_ONETIME_SAMPLE_S 30
|
||||
/* APB_SARADC_ONETIME_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_ONETIME_START (BIT(29))
|
||||
#define APB_SARADC_ONETIME_START_M (BIT(29))
|
||||
#define APB_SARADC_ONETIME_START_V 0x1
|
||||
#define APB_SARADC_ONETIME_START_S 29
|
||||
/* APB_SARADC_ONETIME_CHANNEL : R/W ;bitpos:[28:25] ;default: 4'd13 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_ONETIME_CHANNEL 0x0000000F
|
||||
#define APB_SARADC_ONETIME_CHANNEL_M ((APB_SARADC_ONETIME_CHANNEL_V)<<(APB_SARADC_ONETIME_CHANNEL_S))
|
||||
#define APB_SARADC_ONETIME_CHANNEL_V 0xF
|
||||
#define APB_SARADC_ONETIME_CHANNEL_S 25
|
||||
/* APB_SARADC_ONETIME_ATTEN : R/W ;bitpos:[24:23] ;default: 2'd0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_ONETIME_ATTEN 0x00000003
|
||||
#define APB_SARADC_ONETIME_ATTEN_M ((APB_SARADC_ONETIME_ATTEN_V)<<(APB_SARADC_ONETIME_ATTEN_S))
|
||||
#define APB_SARADC_ONETIME_ATTEN_V 0x3
|
||||
#define APB_SARADC_ONETIME_ATTEN_S 23
|
||||
|
||||
#define APB_SARADC_APB_ADC_ARB_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x024)
|
||||
/* APB_SARADC_ADC_ARB_FIX_PRIORITY : R/W ;bitpos:[12] ;default: 1'b0 ; */
|
||||
/*description: adc2 arbiter uses fixed priority*/
|
||||
#define APB_SARADC_ADC_ARB_FIX_PRIORITY (BIT(12))
|
||||
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_M (BIT(12))
|
||||
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_V 0x1
|
||||
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_S 12
|
||||
/* APB_SARADC_ADC_ARB_WIFI_PRIORITY : R/W ;bitpos:[11:10] ;default: 2'd2 ; */
|
||||
/*description: Set adc2 arbiter wifi priority*/
|
||||
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY 0x00000003
|
||||
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_M ((APB_SARADC_ADC_ARB_WIFI_PRIORITY_V)<<(APB_SARADC_ADC_ARB_WIFI_PRIORITY_S))
|
||||
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_V 0x3
|
||||
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_S 10
|
||||
/* APB_SARADC_ADC_ARB_RTC_PRIORITY : R/W ;bitpos:[9:8] ;default: 2'd1 ; */
|
||||
/*description: Set adc2 arbiter rtc priority*/
|
||||
#define APB_SARADC_ADC_ARB_RTC_PRIORITY 0x00000003
|
||||
#define APB_SARADC_ADC_ARB_RTC_PRIORITY_M ((APB_SARADC_ADC_ARB_RTC_PRIORITY_V)<<(APB_SARADC_ADC_ARB_RTC_PRIORITY_S))
|
||||
#define APB_SARADC_ADC_ARB_RTC_PRIORITY_V 0x3
|
||||
#define APB_SARADC_ADC_ARB_RTC_PRIORITY_S 8
|
||||
/* APB_SARADC_ADC_ARB_APB_PRIORITY : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
|
||||
/*description: Set adc2 arbiterapb priority*/
|
||||
#define APB_SARADC_ADC_ARB_APB_PRIORITY 0x00000003
|
||||
#define APB_SARADC_ADC_ARB_APB_PRIORITY_M ((APB_SARADC_ADC_ARB_APB_PRIORITY_V)<<(APB_SARADC_ADC_ARB_APB_PRIORITY_S))
|
||||
#define APB_SARADC_ADC_ARB_APB_PRIORITY_V 0x3
|
||||
#define APB_SARADC_ADC_ARB_APB_PRIORITY_S 6
|
||||
/* APB_SARADC_ADC_ARB_GRANT_FORCE : R/W ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: adc2 arbiter force grant*/
|
||||
#define APB_SARADC_ADC_ARB_GRANT_FORCE (BIT(5))
|
||||
#define APB_SARADC_ADC_ARB_GRANT_FORCE_M (BIT(5))
|
||||
#define APB_SARADC_ADC_ARB_GRANT_FORCE_V 0x1
|
||||
#define APB_SARADC_ADC_ARB_GRANT_FORCE_S 5
|
||||
/* APB_SARADC_ADC_ARB_WIFI_FORCE : R/W ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: adc2 arbiter force to enable wifi controller*/
|
||||
#define APB_SARADC_ADC_ARB_WIFI_FORCE (BIT(4))
|
||||
#define APB_SARADC_ADC_ARB_WIFI_FORCE_M (BIT(4))
|
||||
#define APB_SARADC_ADC_ARB_WIFI_FORCE_V 0x1
|
||||
#define APB_SARADC_ADC_ARB_WIFI_FORCE_S 4
|
||||
/* APB_SARADC_ADC_ARB_RTC_FORCE : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: adc2 arbiter force to enable rtc controller*/
|
||||
#define APB_SARADC_ADC_ARB_RTC_FORCE (BIT(3))
|
||||
#define APB_SARADC_ADC_ARB_RTC_FORCE_M (BIT(3))
|
||||
#define APB_SARADC_ADC_ARB_RTC_FORCE_V 0x1
|
||||
#define APB_SARADC_ADC_ARB_RTC_FORCE_S 3
|
||||
/* APB_SARADC_ADC_ARB_APB_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: adc2 arbiter force to enableapb controller*/
|
||||
#define APB_SARADC_ADC_ARB_APB_FORCE (BIT(2))
|
||||
#define APB_SARADC_ADC_ARB_APB_FORCE_M (BIT(2))
|
||||
#define APB_SARADC_ADC_ARB_APB_FORCE_V 0x1
|
||||
#define APB_SARADC_ADC_ARB_APB_FORCE_S 2
|
||||
|
||||
#define APB_SARADC_FILTER_CTRL0_REG (DR_REG_APB_SARADC_BASE + 0x028)
|
||||
/* APB_SARADC_FILTER_RESET : R/W ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: enable apb_adc1_filter*/
|
||||
#define APB_SARADC_FILTER_RESET (BIT(31))
|
||||
#define APB_SARADC_FILTER_RESET_M (BIT(31))
|
||||
#define APB_SARADC_FILTER_RESET_V 0x1
|
||||
#define APB_SARADC_FILTER_RESET_S 31
|
||||
/* APB_SARADC_FILTER_CHANNEL0 : R/W ;bitpos:[25:22] ;default: 4'd13 ; */
|
||||
/*description: apb_adc1_filter_factor*/
|
||||
#define APB_SARADC_FILTER_CHANNEL0 0x0000000F
|
||||
#define APB_SARADC_FILTER_CHANNEL0_M ((APB_SARADC_FILTER_CHANNEL0_V)<<(APB_SARADC_FILTER_CHANNEL0_S))
|
||||
#define APB_SARADC_FILTER_CHANNEL0_V 0xF
|
||||
#define APB_SARADC_FILTER_CHANNEL0_S 22
|
||||
/* APB_SARADC_FILTER_CHANNEL1 : R/W ;bitpos:[21:18] ;default: 4'd13 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_FILTER_CHANNEL1 0x0000000F
|
||||
#define APB_SARADC_FILTER_CHANNEL1_M ((APB_SARADC_FILTER_CHANNEL1_V)<<(APB_SARADC_FILTER_CHANNEL1_S))
|
||||
#define APB_SARADC_FILTER_CHANNEL1_V 0xF
|
||||
#define APB_SARADC_FILTER_CHANNEL1_S 18
|
||||
|
||||
#define APB_SARADC_1_DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x02C)
|
||||
/* APB_SARADC_ADC1_DATA : RO ;bitpos:[16:0] ;default: 17'd0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_ADC1_DATA 0x0001FFFF
|
||||
#define APB_SARADC_ADC1_DATA_M ((APB_SARADC_ADC1_DATA_V)<<(APB_SARADC_ADC1_DATA_S))
|
||||
#define APB_SARADC_ADC1_DATA_V 0x1FFFF
|
||||
#define APB_SARADC_ADC1_DATA_S 0
|
||||
|
||||
#define APB_SARADC_2_DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x030)
|
||||
/* APB_SARADC_ADC2_DATA : RO ;bitpos:[16:0] ;default: 17'd0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_ADC2_DATA 0x0001FFFF
|
||||
#define APB_SARADC_ADC2_DATA_M ((APB_SARADC_ADC2_DATA_V)<<(APB_SARADC_ADC2_DATA_S))
|
||||
#define APB_SARADC_ADC2_DATA_V 0x1FFFF
|
||||
#define APB_SARADC_ADC2_DATA_S 0
|
||||
|
||||
#define APB_SARADC_THRES0_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x034)
|
||||
/* APB_SARADC_THRES0_LOW : R/W ;bitpos:[30:18] ;default: 13'd0 ; */
|
||||
/*description: saradc1's thres0 monitor thres*/
|
||||
#define APB_SARADC_THRES0_LOW 0x00001FFF
|
||||
#define APB_SARADC_THRES0_LOW_M ((APB_SARADC_THRES0_LOW_V)<<(APB_SARADC_THRES0_LOW_S))
|
||||
#define APB_SARADC_THRES0_LOW_V 0x1FFF
|
||||
#define APB_SARADC_THRES0_LOW_S 18
|
||||
/* APB_SARADC_THRES0_HIGH : R/W ;bitpos:[17:5] ;default: 13'h1fff ; */
|
||||
/*description: saradc1's thres0 monitor thres*/
|
||||
#define APB_SARADC_THRES0_HIGH 0x00001FFF
|
||||
#define APB_SARADC_THRES0_HIGH_M ((APB_SARADC_THRES0_HIGH_V)<<(APB_SARADC_THRES0_HIGH_S))
|
||||
#define APB_SARADC_THRES0_HIGH_V 0x1FFF
|
||||
#define APB_SARADC_THRES0_HIGH_S 5
|
||||
/* APB_SARADC_THRES0_CHANNEL : R/W ;bitpos:[3:0] ;default: 4'd13 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_THRES0_CHANNEL 0x0000000F
|
||||
#define APB_SARADC_THRES0_CHANNEL_M ((APB_SARADC_THRES0_CHANNEL_V)<<(APB_SARADC_THRES0_CHANNEL_S))
|
||||
#define APB_SARADC_THRES0_CHANNEL_V 0xF
|
||||
#define APB_SARADC_THRES0_CHANNEL_S 0
|
||||
|
||||
#define APB_SARADC_THRES1_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x038)
|
||||
/* APB_SARADC_THRES1_LOW : R/W ;bitpos:[30:18] ;default: 13'd0 ; */
|
||||
/*description: saradc1's thres0 monitor thres*/
|
||||
#define APB_SARADC_THRES1_LOW 0x00001FFF
|
||||
#define APB_SARADC_THRES1_LOW_M ((APB_SARADC_THRES1_LOW_V)<<(APB_SARADC_THRES1_LOW_S))
|
||||
#define APB_SARADC_THRES1_LOW_V 0x1FFF
|
||||
#define APB_SARADC_THRES1_LOW_S 18
|
||||
/* APB_SARADC_THRES1_HIGH : R/W ;bitpos:[17:5] ;default: 13'h1fff ; */
|
||||
/*description: saradc1's thres0 monitor thres*/
|
||||
#define APB_SARADC_THRES1_HIGH 0x00001FFF
|
||||
#define APB_SARADC_THRES1_HIGH_M ((APB_SARADC_THRES1_HIGH_V)<<(APB_SARADC_THRES1_HIGH_S))
|
||||
#define APB_SARADC_THRES1_HIGH_V 0x1FFF
|
||||
#define APB_SARADC_THRES1_HIGH_S 5
|
||||
/* APB_SARADC_THRES1_CHANNEL : R/W ;bitpos:[3:0] ;default: 4'd13 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_THRES1_CHANNEL 0x0000000F
|
||||
#define APB_SARADC_THRES1_CHANNEL_M ((APB_SARADC_THRES1_CHANNEL_V)<<(APB_SARADC_THRES1_CHANNEL_S))
|
||||
#define APB_SARADC_THRES1_CHANNEL_V 0xF
|
||||
#define APB_SARADC_THRES1_CHANNEL_S 0
|
||||
|
||||
#define APB_SARADC_THRES_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x03C)
|
||||
/* APB_SARADC_THRES0_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_THRES0_EN (BIT(31))
|
||||
#define APB_SARADC_THRES0_EN_M (BIT(31))
|
||||
#define APB_SARADC_THRES0_EN_V 0x1
|
||||
#define APB_SARADC_THRES0_EN_S 31
|
||||
/* APB_SARADC_THRES1_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_THRES1_EN (BIT(30))
|
||||
#define APB_SARADC_THRES1_EN_M (BIT(30))
|
||||
#define APB_SARADC_THRES1_EN_V 0x1
|
||||
#define APB_SARADC_THRES1_EN_S 30
|
||||
/*description: */
|
||||
#define APB_SARADC_THRES_ALL_EN (BIT(27))
|
||||
#define APB_SARADC_THRES_ALL_EN_M (BIT(27))
|
||||
#define APB_SARADC_THRES_ALL_EN_V 0x1
|
||||
#define APB_SARADC_THRES_ALL_EN_S 27
|
||||
|
||||
#define APB_SARADC_INT_ENA_REG (DR_REG_APB_SARADC_BASE + 0x040)
|
||||
/* APB_SARADC_ADC1_DONE_INT_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_ADC1_DONE_INT_ENA (BIT(31))
|
||||
#define APB_SARADC_ADC1_DONE_INT_ENA_M (BIT(31))
|
||||
#define APB_SARADC_ADC1_DONE_INT_ENA_V 0x1
|
||||
#define APB_SARADC_ADC1_DONE_INT_ENA_S 31
|
||||
/* APB_SARADC_ADC2_DONE_INT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_ADC2_DONE_INT_ENA (BIT(30))
|
||||
#define APB_SARADC_ADC2_DONE_INT_ENA_M (BIT(30))
|
||||
#define APB_SARADC_ADC2_DONE_INT_ENA_V 0x1
|
||||
#define APB_SARADC_ADC2_DONE_INT_ENA_S 30
|
||||
/* APB_SARADC_THRES0_HIGH_INT_ENA : R/W ;bitpos:[29] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_THRES0_HIGH_INT_ENA (BIT(29))
|
||||
#define APB_SARADC_THRES0_HIGH_INT_ENA_M (BIT(29))
|
||||
#define APB_SARADC_THRES0_HIGH_INT_ENA_V 0x1
|
||||
#define APB_SARADC_THRES0_HIGH_INT_ENA_S 29
|
||||
/* APB_SARADC_THRES1_HIGH_INT_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_THRES1_HIGH_INT_ENA (BIT(28))
|
||||
#define APB_SARADC_THRES1_HIGH_INT_ENA_M (BIT(28))
|
||||
#define APB_SARADC_THRES1_HIGH_INT_ENA_V 0x1
|
||||
#define APB_SARADC_THRES1_HIGH_INT_ENA_S 28
|
||||
/* APB_SARADC_THRES0_LOW_INT_ENA : R/W ;bitpos:[27] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_THRES0_LOW_INT_ENA (BIT(27))
|
||||
#define APB_SARADC_THRES0_LOW_INT_ENA_M (BIT(27))
|
||||
#define APB_SARADC_THRES0_LOW_INT_ENA_V 0x1
|
||||
#define APB_SARADC_THRES0_LOW_INT_ENA_S 27
|
||||
/* APB_SARADC_THRES1_LOW_INT_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_THRES1_LOW_INT_ENA (BIT(26))
|
||||
#define APB_SARADC_THRES1_LOW_INT_ENA_M (BIT(26))
|
||||
#define APB_SARADC_THRES1_LOW_INT_ENA_V 0x1
|
||||
#define APB_SARADC_THRES1_LOW_INT_ENA_S 26
|
||||
|
||||
#define APB_SARADC_INT_RAW_REG (DR_REG_APB_SARADC_BASE + 0x044)
|
||||
/* APB_SARADC_ADC1_DONE_INT_RAW : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_ADC1_DONE_INT_RAW (BIT(31))
|
||||
#define APB_SARADC_ADC1_DONE_INT_RAW_M (BIT(31))
|
||||
#define APB_SARADC_ADC1_DONE_INT_RAW_V 0x1
|
||||
#define APB_SARADC_ADC1_DONE_INT_RAW_S 31
|
||||
/* APB_SARADC_ADC2_DONE_INT_RAW : RO ;bitpos:[30] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_ADC2_DONE_INT_RAW (BIT(30))
|
||||
#define APB_SARADC_ADC2_DONE_INT_RAW_M (BIT(30))
|
||||
#define APB_SARADC_ADC2_DONE_INT_RAW_V 0x1
|
||||
#define APB_SARADC_ADC2_DONE_INT_RAW_S 30
|
||||
/* APB_SARADC_THRES0_HIGH_INT_RAW : RO ;bitpos:[29] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_THRES0_HIGH_INT_RAW (BIT(29))
|
||||
#define APB_SARADC_THRES0_HIGH_INT_RAW_M (BIT(29))
|
||||
#define APB_SARADC_THRES0_HIGH_INT_RAW_V 0x1
|
||||
#define APB_SARADC_THRES0_HIGH_INT_RAW_S 29
|
||||
/* APB_SARADC_THRES1_HIGH_INT_RAW : RO ;bitpos:[28] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_THRES1_HIGH_INT_RAW (BIT(28))
|
||||
#define APB_SARADC_THRES1_HIGH_INT_RAW_M (BIT(28))
|
||||
#define APB_SARADC_THRES1_HIGH_INT_RAW_V 0x1
|
||||
#define APB_SARADC_THRES1_HIGH_INT_RAW_S 28
|
||||
/* APB_SARADC_THRES0_LOW_INT_RAW : RO ;bitpos:[27] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_THRES0_LOW_INT_RAW (BIT(27))
|
||||
#define APB_SARADC_THRES0_LOW_INT_RAW_M (BIT(27))
|
||||
#define APB_SARADC_THRES0_LOW_INT_RAW_V 0x1
|
||||
#define APB_SARADC_THRES0_LOW_INT_RAW_S 27
|
||||
/* APB_SARADC_THRES1_LOW_INT_RAW : RO ;bitpos:[26] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_THRES1_LOW_INT_RAW (BIT(26))
|
||||
#define APB_SARADC_THRES1_LOW_INT_RAW_M (BIT(26))
|
||||
#define APB_SARADC_THRES1_LOW_INT_RAW_V 0x1
|
||||
#define APB_SARADC_THRES1_LOW_INT_RAW_S 26
|
||||
|
||||
#define APB_SARADC_INT_ST_REG (DR_REG_APB_SARADC_BASE + 0x048)
|
||||
/* APB_SARADC_ADC1_DONE_INT_ST : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_ADC1_DONE_INT_ST (BIT(31))
|
||||
#define APB_SARADC_ADC1_DONE_INT_ST_M (BIT(31))
|
||||
#define APB_SARADC_ADC1_DONE_INT_ST_V 0x1
|
||||
#define APB_SARADC_ADC1_DONE_INT_ST_S 31
|
||||
/* APB_SARADC_ADC2_DONE_INT_ST : RO ;bitpos:[30] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_ADC2_DONE_INT_ST (BIT(30))
|
||||
#define APB_SARADC_ADC2_DONE_INT_ST_M (BIT(30))
|
||||
#define APB_SARADC_ADC2_DONE_INT_ST_V 0x1
|
||||
#define APB_SARADC_ADC2_DONE_INT_ST_S 30
|
||||
/* APB_SARADC_THRES0_HIGH_INT_ST : RO ;bitpos:[29] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_THRES0_HIGH_INT_ST (BIT(29))
|
||||
#define APB_SARADC_THRES0_HIGH_INT_ST_M (BIT(29))
|
||||
#define APB_SARADC_THRES0_HIGH_INT_ST_V 0x1
|
||||
#define APB_SARADC_THRES0_HIGH_INT_ST_S 29
|
||||
/* APB_SARADC_THRES1_HIGH_INT_ST : RO ;bitpos:[28] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_THRES1_HIGH_INT_ST (BIT(28))
|
||||
#define APB_SARADC_THRES1_HIGH_INT_ST_M (BIT(28))
|
||||
#define APB_SARADC_THRES1_HIGH_INT_ST_V 0x1
|
||||
#define APB_SARADC_THRES1_HIGH_INT_ST_S 28
|
||||
/* APB_SARADC_THRES0_LOW_INT_ST : RO ;bitpos:[27] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_THRES0_LOW_INT_ST (BIT(27))
|
||||
#define APB_SARADC_THRES0_LOW_INT_ST_M (BIT(27))
|
||||
#define APB_SARADC_THRES0_LOW_INT_ST_V 0x1
|
||||
#define APB_SARADC_THRES0_LOW_INT_ST_S 27
|
||||
/* APB_SARADC_THRES1_LOW_INT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_THRES1_LOW_INT_ST (BIT(26))
|
||||
#define APB_SARADC_THRES1_LOW_INT_ST_M (BIT(26))
|
||||
#define APB_SARADC_THRES1_LOW_INT_ST_V 0x1
|
||||
#define APB_SARADC_THRES1_LOW_INT_ST_S 26
|
||||
|
||||
#define APB_SARADC_INT_CLR_REG (DR_REG_APB_SARADC_BASE + 0x04C)
|
||||
/* APB_SARADC_ADC1_DONE_INT_CLR : WO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_ADC1_DONE_INT_CLR (BIT(31))
|
||||
#define APB_SARADC_ADC1_DONE_INT_CLR_M (BIT(31))
|
||||
#define APB_SARADC_ADC1_DONE_INT_CLR_V 0x1
|
||||
#define APB_SARADC_ADC1_DONE_INT_CLR_S 31
|
||||
/* APB_SARADC_ADC2_DONE_INT_CLR : WO ;bitpos:[30] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_ADC2_DONE_INT_CLR (BIT(30))
|
||||
#define APB_SARADC_ADC2_DONE_INT_CLR_M (BIT(30))
|
||||
#define APB_SARADC_ADC2_DONE_INT_CLR_V 0x1
|
||||
#define APB_SARADC_ADC2_DONE_INT_CLR_S 30
|
||||
/* APB_SARADC_THRES0_HIGH_INT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_THRES0_HIGH_INT_CLR (BIT(29))
|
||||
#define APB_SARADC_THRES0_HIGH_INT_CLR_M (BIT(29))
|
||||
#define APB_SARADC_THRES0_HIGH_INT_CLR_V 0x1
|
||||
#define APB_SARADC_THRES0_HIGH_INT_CLR_S 29
|
||||
/* APB_SARADC_THRES1_HIGH_INT_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_THRES1_HIGH_INT_CLR (BIT(28))
|
||||
#define APB_SARADC_THRES1_HIGH_INT_CLR_M (BIT(28))
|
||||
#define APB_SARADC_THRES1_HIGH_INT_CLR_V 0x1
|
||||
#define APB_SARADC_THRES1_HIGH_INT_CLR_S 28
|
||||
/* APB_SARADC_THRES0_LOW_INT_CLR : WO ;bitpos:[27] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_THRES0_LOW_INT_CLR (BIT(27))
|
||||
#define APB_SARADC_THRES0_LOW_INT_CLR_M (BIT(27))
|
||||
#define APB_SARADC_THRES0_LOW_INT_CLR_V 0x1
|
||||
#define APB_SARADC_THRES0_LOW_INT_CLR_S 27
|
||||
/* APB_SARADC_THRES1_LOW_INT_CLR : WO ;bitpos:[26] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_THRES1_LOW_INT_CLR (BIT(26))
|
||||
#define APB_SARADC_THRES1_LOW_INT_CLR_M (BIT(26))
|
||||
#define APB_SARADC_THRES1_LOW_INT_CLR_V 0x1
|
||||
#define APB_SARADC_THRES1_LOW_INT_CLR_S 26
|
||||
|
||||
#define APB_SARADC_DMA_CONF_REG (DR_REG_APB_SARADC_BASE + 0x050)
|
||||
/* APB_SARADC_APB_ADC_TRANS : R/W ;bitpos:[31] ;default: 1'd0 ; */
|
||||
/*description: enable apb_adc use spi_dma*/
|
||||
#define APB_SARADC_APB_ADC_TRANS (BIT(31))
|
||||
#define APB_SARADC_APB_ADC_TRANS_M (BIT(31))
|
||||
#define APB_SARADC_APB_ADC_TRANS_V 0x1
|
||||
#define APB_SARADC_APB_ADC_TRANS_S 31
|
||||
/* APB_SARADC_APB_ADC_RESET_FSM : R/W ;bitpos:[30] ;default: 1'b0 ; */
|
||||
/*description: reset_apb_adc_state*/
|
||||
#define APB_SARADC_APB_ADC_RESET_FSM (BIT(30))
|
||||
#define APB_SARADC_APB_ADC_RESET_FSM_M (BIT(30))
|
||||
#define APB_SARADC_APB_ADC_RESET_FSM_V 0x1
|
||||
#define APB_SARADC_APB_ADC_RESET_FSM_S 30
|
||||
/* APB_SARADC_APB_ADC_EOF_NUM : R/W ;bitpos:[15:0] ;default: 16'd255 ; */
|
||||
/*description: the dma_in_suc_eof gen when sample cnt = spi_eof_num*/
|
||||
#define APB_SARADC_APB_ADC_EOF_NUM 0x0000FFFF
|
||||
#define APB_SARADC_APB_ADC_EOF_NUM_M ((APB_SARADC_APB_ADC_EOF_NUM_V)<<(APB_SARADC_APB_ADC_EOF_NUM_S))
|
||||
#define APB_SARADC_APB_ADC_EOF_NUM_V 0xFFFF
|
||||
#define APB_SARADC_APB_ADC_EOF_NUM_S 0
|
||||
|
||||
#define APB_SARADC_APB_ADC_CLKM_CONF_REG (DR_REG_APB_SARADC_BASE + 0x054)
|
||||
/* APB_SARADC_CLK_SEL : R/W ;bitpos:[22:21] ;default: 2'b0 ; */
|
||||
/*description: Set this bit to enable clk_apll*/
|
||||
#define APB_SARADC_CLK_SEL 0x00000003
|
||||
#define APB_SARADC_CLK_SEL_M ((APB_SARADC_CLK_SEL_V)<<(APB_SARADC_CLK_SEL_S))
|
||||
#define APB_SARADC_CLK_SEL_V 0x3
|
||||
#define APB_SARADC_CLK_SEL_S 21
|
||||
/* APB_SARADC_CLK_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_CLK_EN (BIT(20))
|
||||
#define APB_SARADC_CLK_EN_M (BIT(20))
|
||||
#define APB_SARADC_CLK_EN_V 0x1
|
||||
#define APB_SARADC_CLK_EN_S 20
|
||||
/* APB_SARADC_CLKM_DIV_A : R/W ;bitpos:[19:14] ;default: 6'h0 ; */
|
||||
/*description: Fractional clock divider denominator value*/
|
||||
#define APB_SARADC_CLKM_DIV_A 0x0000003F
|
||||
#define APB_SARADC_CLKM_DIV_A_M ((APB_SARADC_CLKM_DIV_A_V)<<(APB_SARADC_CLKM_DIV_A_S))
|
||||
#define APB_SARADC_CLKM_DIV_A_V 0x3F
|
||||
#define APB_SARADC_CLKM_DIV_A_S 14
|
||||
/* APB_SARADC_CLKM_DIV_B : R/W ;bitpos:[13:8] ;default: 6'h0 ; */
|
||||
/*description: Fractional clock divider numerator value*/
|
||||
#define APB_SARADC_CLKM_DIV_B 0x0000003F
|
||||
#define APB_SARADC_CLKM_DIV_B_M ((APB_SARADC_CLKM_DIV_B_V)<<(APB_SARADC_CLKM_DIV_B_S))
|
||||
#define APB_SARADC_CLKM_DIV_B_V 0x3F
|
||||
#define APB_SARADC_CLKM_DIV_B_S 8
|
||||
/* APB_SARADC_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd4 ; */
|
||||
/*description: Integral I2S clock divider value*/
|
||||
#define APB_SARADC_CLKM_DIV_NUM 0x000000FF
|
||||
#define APB_SARADC_CLKM_DIV_NUM_M ((APB_SARADC_CLKM_DIV_NUM_V)<<(APB_SARADC_CLKM_DIV_NUM_S))
|
||||
#define APB_SARADC_CLKM_DIV_NUM_V 0xFF
|
||||
#define APB_SARADC_CLKM_DIV_NUM_S 0
|
||||
|
||||
#define APB_SARADC_APB_TSENS_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x058)
|
||||
/* APB_SARADC_TSENS_PU : R/W ;bitpos:[22] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_TSENS_PU (BIT(22))
|
||||
#define APB_SARADC_TSENS_PU_M (BIT(22))
|
||||
#define APB_SARADC_TSENS_PU_V 0x1
|
||||
#define APB_SARADC_TSENS_PU_S 22
|
||||
/* APB_SARADC_TSENS_CLK_DIV : R/W ;bitpos:[21:14] ;default: 8'd6 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_TSENS_CLK_DIV 0x000000FF
|
||||
#define APB_SARADC_TSENS_CLK_DIV_M ((APB_SARADC_TSENS_CLK_DIV_V)<<(APB_SARADC_TSENS_CLK_DIV_S))
|
||||
#define APB_SARADC_TSENS_CLK_DIV_V 0xFF
|
||||
#define APB_SARADC_TSENS_CLK_DIV_S 14
|
||||
/* APB_SARADC_TSENS_IN_INV : R/W ;bitpos:[13] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_TSENS_IN_INV (BIT(13))
|
||||
#define APB_SARADC_TSENS_IN_INV_M (BIT(13))
|
||||
#define APB_SARADC_TSENS_IN_INV_V 0x1
|
||||
#define APB_SARADC_TSENS_IN_INV_S 13
|
||||
/* APB_SARADC_TSENS_OUT : RO ;bitpos:[7:0] ;default: 8'h0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_TSENS_OUT 0x000000FF
|
||||
#define APB_SARADC_TSENS_OUT_M ((APB_SARADC_TSENS_OUT_V)<<(APB_SARADC_TSENS_OUT_S))
|
||||
#define APB_SARADC_TSENS_OUT_V 0xFF
|
||||
#define APB_SARADC_TSENS_OUT_S 0
|
||||
|
||||
#define APB_SARADC_APB_TSENS_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x05C)
|
||||
/* APB_SARADC_TSENS_CLK_SEL : R/W ;bitpos:[15] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_TSENS_CLK_SEL (BIT(15))
|
||||
#define APB_SARADC_TSENS_CLK_SEL_M (BIT(15))
|
||||
#define APB_SARADC_TSENS_CLK_SEL_V 0x1
|
||||
#define APB_SARADC_TSENS_CLK_SEL_S 15
|
||||
/* APB_SARADC_TSENS_CLK_INV : R/W ;bitpos:[14] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_TSENS_CLK_INV (BIT(14))
|
||||
#define APB_SARADC_TSENS_CLK_INV_M (BIT(14))
|
||||
#define APB_SARADC_TSENS_CLK_INV_V 0x1
|
||||
#define APB_SARADC_TSENS_CLK_INV_S 14
|
||||
/* APB_SARADC_TSENS_XPD_FORCE : R/W ;bitpos:[13:12] ;default: 2'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_TSENS_XPD_FORCE 0x00000003
|
||||
#define APB_SARADC_TSENS_XPD_FORCE_M ((APB_SARADC_TSENS_XPD_FORCE_V)<<(APB_SARADC_TSENS_XPD_FORCE_S))
|
||||
#define APB_SARADC_TSENS_XPD_FORCE_V 0x3
|
||||
#define APB_SARADC_TSENS_XPD_FORCE_S 12
|
||||
/* APB_SARADC_TSENS_XPD_WAIT : R/W ;bitpos:[11:0] ;default: 12'h2 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_TSENS_XPD_WAIT 0x00000FFF
|
||||
#define APB_SARADC_TSENS_XPD_WAIT_M ((APB_SARADC_TSENS_XPD_WAIT_V)<<(APB_SARADC_TSENS_XPD_WAIT_S))
|
||||
#define APB_SARADC_TSENS_XPD_WAIT_V 0xFFF
|
||||
#define APB_SARADC_TSENS_XPD_WAIT_S 0
|
||||
|
||||
#define APB_SARADC_CALI_REG (DR_REG_APB_SARADC_BASE + 0x060)
|
||||
/* APB_SARADC_CALI_CFG : R/W ;bitpos:[16:0] ;default: 17'h8000 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_CALI_CFG 0x0001FFFF
|
||||
#define APB_SARADC_CALI_CFG_M ((APB_SARADC_CALI_CFG_V)<<(APB_SARADC_CALI_CFG_S))
|
||||
#define APB_SARADC_CALI_CFG_V 0x1FFFF
|
||||
#define APB_SARADC_CALI_CFG_S 0
|
||||
|
||||
#define APB_SARADC_APB_CTRL_DATE_REG (DR_REG_APB_SARADC_BASE + 0x3fc)
|
||||
/* APB_SARADC_DATE : R/W ;bitpos:[31:0] ;default: 32'h02007171 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_DATE 0xFFFFFFFF
|
||||
#define APB_SARADC_DATE_M ((APB_SARADC_DATE_V)<<(APB_SARADC_DATE_S))
|
||||
#define APB_SARADC_DATE_V 0xFFFFFFFF
|
||||
#define APB_SARADC_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /*_SOC_APB_SARADC_REG_H_ */
|
||||
@@ -1,482 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct apb_saradc_dev_s {
|
||||
union {
|
||||
struct {
|
||||
uint32_t start_force: 1;
|
||||
uint32_t start: 1;
|
||||
uint32_t reserved2: 4; /*0: single mode 1: double mode 2: alternate mode*/
|
||||
uint32_t sar_clk_gated: 1;
|
||||
uint32_t sar_clk_div: 8; /*SAR clock divider*/
|
||||
uint32_t sar_patt_len: 3; /*0 ~ 15 means length 1 ~ 16*/
|
||||
uint32_t reserved18: 5;
|
||||
uint32_t sar_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC1 CTRL*/
|
||||
uint32_t reserved24: 3;
|
||||
uint32_t xpd_sar_force: 2; /*force option to xpd sar blocks*/
|
||||
uint32_t reserved29: 1;
|
||||
uint32_t wait_arb_cycle: 2; /*wait arbit signal stable after sar_done*/
|
||||
};
|
||||
uint32_t val;
|
||||
} ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t meas_num_limit: 1;
|
||||
uint32_t max_meas_num: 8; /*max conversion number*/
|
||||
uint32_t sar1_inv: 1; /*1: data to DIG ADC1 CTRL is inverted otherwise not*/
|
||||
uint32_t sar2_inv: 1; /*1: data to DIG ADC2 CTRL is inverted otherwise not*/
|
||||
uint32_t reserved11: 1; /*1: select saradc timer 0: i2s_ws trigger*/
|
||||
uint32_t timer_target: 12; /*to set saradc timer target*/
|
||||
uint32_t timer_en: 1; /*to enable saradc timer trigger*/
|
||||
uint32_t reserved25: 7;
|
||||
};
|
||||
uint32_t val;
|
||||
} ctrl2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 26;
|
||||
uint32_t filter_factor1: 3;
|
||||
uint32_t filter_factor0: 3;
|
||||
};
|
||||
uint32_t val;
|
||||
} filter_ctrl1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t xpd_wait: 8;
|
||||
uint32_t rstb_wait: 8;
|
||||
uint32_t standby_wait: 8;
|
||||
uint32_t reserved24: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} fsm_wait;
|
||||
uint32_t sar1_status; /**/
|
||||
uint32_t sar2_status; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar_patt_tab1: 24; /*item 0 ~ 3 for pattern table 1 (each item one byte)*/
|
||||
uint32_t reserved24: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_patt_tab[2];
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 23;
|
||||
uint32_t onetime_atten: 2;
|
||||
uint32_t onetime_channel: 4;
|
||||
uint32_t onetime_start: 1;
|
||||
uint32_t adc2_onetime_sample: 1;
|
||||
uint32_t adc1_onetime_sample: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} onetime_sample;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 2;
|
||||
uint32_t adc_arb_apb_force: 1; /*adc2 arbiter force to enableapb controller*/
|
||||
uint32_t adc_arb_rtc_force: 1; /*adc2 arbiter force to enable rtc controller*/
|
||||
uint32_t adc_arb_wifi_force: 1; /*adc2 arbiter force to enable wifi controller*/
|
||||
uint32_t adc_arb_grant_force: 1; /*adc2 arbiter force grant*/
|
||||
uint32_t adc_arb_apb_priority: 2; /*Set adc2 arbiterapb priority*/
|
||||
uint32_t adc_arb_rtc_priority: 2; /*Set adc2 arbiter rtc priority*/
|
||||
uint32_t adc_arb_wifi_priority: 2; /*Set adc2 arbiter wifi priority*/
|
||||
uint32_t adc_arb_fix_priority: 1; /*adc2 arbiter uses fixed priority*/
|
||||
uint32_t reserved13: 19;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_adc_arb_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 18;
|
||||
uint32_t filter_channel1: 4;
|
||||
uint32_t filter_channel0: 4; /*apb_adc1_filter_factor*/
|
||||
uint32_t reserved26: 5;
|
||||
uint32_t filter_reset: 1; /*enable apb_adc1_filter*/
|
||||
};
|
||||
uint32_t val;
|
||||
} filter_ctrl0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t adc1_data: 17;
|
||||
uint32_t reserved17:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_saradc1_data_status;
|
||||
union {
|
||||
struct {
|
||||
uint32_t adc2_data: 17;
|
||||
uint32_t reserved17:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_saradc2_data_status;
|
||||
union {
|
||||
struct {
|
||||
uint32_t thres0_channel: 4;
|
||||
uint32_t reserved4: 1;
|
||||
uint32_t thres0_high: 13; /*saradc1's thres0 monitor thres*/
|
||||
uint32_t thres0_low: 13; /*saradc1's thres0 monitor thres*/
|
||||
uint32_t reserved31: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} thres0_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t thres1_channel: 4;
|
||||
uint32_t reserved4: 1;
|
||||
uint32_t thres1_high: 13; /*saradc1's thres0 monitor thres*/
|
||||
uint32_t thres1_low: 13; /*saradc1's thres0 monitor thres*/
|
||||
uint32_t reserved31: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} thres1_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 27;
|
||||
uint32_t thres_all_en: 1;
|
||||
uint32_t reserved28: 2;
|
||||
uint32_t thres1_en: 1;
|
||||
uint32_t thres0_en: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} thres_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 26;
|
||||
uint32_t thres1_low: 1;
|
||||
uint32_t thres0_low: 1;
|
||||
uint32_t thres1_high: 1;
|
||||
uint32_t thres0_high: 1;
|
||||
uint32_t adc2_done: 1;
|
||||
uint32_t adc1_done: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 26;
|
||||
uint32_t thres1_low: 1;
|
||||
uint32_t thres0_low: 1;
|
||||
uint32_t thres1_high: 1;
|
||||
uint32_t thres0_high: 1;
|
||||
uint32_t adc2_done: 1;
|
||||
uint32_t adc1_done: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 26;
|
||||
uint32_t thres1_low: 1;
|
||||
uint32_t thres0_low: 1;
|
||||
uint32_t thres1_high: 1;
|
||||
uint32_t thres0_high: 1;
|
||||
uint32_t adc2_done: 1;
|
||||
uint32_t adc1_done: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 26;
|
||||
uint32_t thres1_low: 1;
|
||||
uint32_t thres0_low: 1;
|
||||
uint32_t thres1_high: 1;
|
||||
uint32_t thres0_high: 1;
|
||||
uint32_t adc2_done: 1;
|
||||
uint32_t adc1_done: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t apb_adc_eof_num: 16; /*the dma_in_suc_eof gen when sample cnt = spi_eof_num*/
|
||||
uint32_t reserved16: 14;
|
||||
uint32_t apb_adc_reset_fsm: 1; /*reset_apb_adc_state*/
|
||||
uint32_t apb_adc_trans: 1; /*enable apb_adc use spi_dma*/
|
||||
};
|
||||
uint32_t val;
|
||||
} dma_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clkm_div_num: 8; /*Integral I2S clock divider value*/
|
||||
uint32_t clkm_div_b: 6; /*Fractional clock divider numerator value*/
|
||||
uint32_t clkm_div_a: 6; /*Fractional clock divider denominator value*/
|
||||
uint32_t clk_en: 1;
|
||||
uint32_t clk_sel: 2; /*Set this bit to enable clk_apll*/
|
||||
uint32_t reserved23: 9;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_adc_clkm_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tsens_out: 8;
|
||||
uint32_t reserved8: 5;
|
||||
uint32_t tsens_in_inv: 1;
|
||||
uint32_t tsens_clk_div: 8;
|
||||
uint32_t tsens_pu: 1;
|
||||
uint32_t reserved23: 9;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_tsens_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tsens_xpd_wait: 12;
|
||||
uint32_t tsens_xpd_force: 2;
|
||||
uint32_t tsens_clk_inv: 1;
|
||||
uint32_t tsens_clk_sel: 1;
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_tsens_ctrl2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cali_cfg: 17;
|
||||
uint32_t reserved17:15;
|
||||
};
|
||||
uint32_t val;
|
||||
} cali;
|
||||
uint32_t reserved_64;
|
||||
uint32_t reserved_68;
|
||||
uint32_t reserved_6c;
|
||||
uint32_t reserved_70;
|
||||
uint32_t reserved_74;
|
||||
uint32_t reserved_78;
|
||||
uint32_t reserved_7c;
|
||||
uint32_t reserved_80;
|
||||
uint32_t reserved_84;
|
||||
uint32_t reserved_88;
|
||||
uint32_t reserved_8c;
|
||||
uint32_t reserved_90;
|
||||
uint32_t reserved_94;
|
||||
uint32_t reserved_98;
|
||||
uint32_t reserved_9c;
|
||||
uint32_t reserved_a0;
|
||||
uint32_t reserved_a4;
|
||||
uint32_t reserved_a8;
|
||||
uint32_t reserved_ac;
|
||||
uint32_t reserved_b0;
|
||||
uint32_t reserved_b4;
|
||||
uint32_t reserved_b8;
|
||||
uint32_t reserved_bc;
|
||||
uint32_t reserved_c0;
|
||||
uint32_t reserved_c4;
|
||||
uint32_t reserved_c8;
|
||||
uint32_t reserved_cc;
|
||||
uint32_t reserved_d0;
|
||||
uint32_t reserved_d4;
|
||||
uint32_t reserved_d8;
|
||||
uint32_t reserved_dc;
|
||||
uint32_t reserved_e0;
|
||||
uint32_t reserved_e4;
|
||||
uint32_t reserved_e8;
|
||||
uint32_t reserved_ec;
|
||||
uint32_t reserved_f0;
|
||||
uint32_t reserved_f4;
|
||||
uint32_t reserved_f8;
|
||||
uint32_t reserved_fc;
|
||||
uint32_t reserved_100;
|
||||
uint32_t reserved_104;
|
||||
uint32_t reserved_108;
|
||||
uint32_t reserved_10c;
|
||||
uint32_t reserved_110;
|
||||
uint32_t reserved_114;
|
||||
uint32_t reserved_118;
|
||||
uint32_t reserved_11c;
|
||||
uint32_t reserved_120;
|
||||
uint32_t reserved_124;
|
||||
uint32_t reserved_128;
|
||||
uint32_t reserved_12c;
|
||||
uint32_t reserved_130;
|
||||
uint32_t reserved_134;
|
||||
uint32_t reserved_138;
|
||||
uint32_t reserved_13c;
|
||||
uint32_t reserved_140;
|
||||
uint32_t reserved_144;
|
||||
uint32_t reserved_148;
|
||||
uint32_t reserved_14c;
|
||||
uint32_t reserved_150;
|
||||
uint32_t reserved_154;
|
||||
uint32_t reserved_158;
|
||||
uint32_t reserved_15c;
|
||||
uint32_t reserved_160;
|
||||
uint32_t reserved_164;
|
||||
uint32_t reserved_168;
|
||||
uint32_t reserved_16c;
|
||||
uint32_t reserved_170;
|
||||
uint32_t reserved_174;
|
||||
uint32_t reserved_178;
|
||||
uint32_t reserved_17c;
|
||||
uint32_t reserved_180;
|
||||
uint32_t reserved_184;
|
||||
uint32_t reserved_188;
|
||||
uint32_t reserved_18c;
|
||||
uint32_t reserved_190;
|
||||
uint32_t reserved_194;
|
||||
uint32_t reserved_198;
|
||||
uint32_t reserved_19c;
|
||||
uint32_t reserved_1a0;
|
||||
uint32_t reserved_1a4;
|
||||
uint32_t reserved_1a8;
|
||||
uint32_t reserved_1ac;
|
||||
uint32_t reserved_1b0;
|
||||
uint32_t reserved_1b4;
|
||||
uint32_t reserved_1b8;
|
||||
uint32_t reserved_1bc;
|
||||
uint32_t reserved_1c0;
|
||||
uint32_t reserved_1c4;
|
||||
uint32_t reserved_1c8;
|
||||
uint32_t reserved_1cc;
|
||||
uint32_t reserved_1d0;
|
||||
uint32_t reserved_1d4;
|
||||
uint32_t reserved_1d8;
|
||||
uint32_t reserved_1dc;
|
||||
uint32_t reserved_1e0;
|
||||
uint32_t reserved_1e4;
|
||||
uint32_t reserved_1e8;
|
||||
uint32_t reserved_1ec;
|
||||
uint32_t reserved_1f0;
|
||||
uint32_t reserved_1f4;
|
||||
uint32_t reserved_1f8;
|
||||
uint32_t reserved_1fc;
|
||||
uint32_t reserved_200;
|
||||
uint32_t reserved_204;
|
||||
uint32_t reserved_208;
|
||||
uint32_t reserved_20c;
|
||||
uint32_t reserved_210;
|
||||
uint32_t reserved_214;
|
||||
uint32_t reserved_218;
|
||||
uint32_t reserved_21c;
|
||||
uint32_t reserved_220;
|
||||
uint32_t reserved_224;
|
||||
uint32_t reserved_228;
|
||||
uint32_t reserved_22c;
|
||||
uint32_t reserved_230;
|
||||
uint32_t reserved_234;
|
||||
uint32_t reserved_238;
|
||||
uint32_t reserved_23c;
|
||||
uint32_t reserved_240;
|
||||
uint32_t reserved_244;
|
||||
uint32_t reserved_248;
|
||||
uint32_t reserved_24c;
|
||||
uint32_t reserved_250;
|
||||
uint32_t reserved_254;
|
||||
uint32_t reserved_258;
|
||||
uint32_t reserved_25c;
|
||||
uint32_t reserved_260;
|
||||
uint32_t reserved_264;
|
||||
uint32_t reserved_268;
|
||||
uint32_t reserved_26c;
|
||||
uint32_t reserved_270;
|
||||
uint32_t reserved_274;
|
||||
uint32_t reserved_278;
|
||||
uint32_t reserved_27c;
|
||||
uint32_t reserved_280;
|
||||
uint32_t reserved_284;
|
||||
uint32_t reserved_288;
|
||||
uint32_t reserved_28c;
|
||||
uint32_t reserved_290;
|
||||
uint32_t reserved_294;
|
||||
uint32_t reserved_298;
|
||||
uint32_t reserved_29c;
|
||||
uint32_t reserved_2a0;
|
||||
uint32_t reserved_2a4;
|
||||
uint32_t reserved_2a8;
|
||||
uint32_t reserved_2ac;
|
||||
uint32_t reserved_2b0;
|
||||
uint32_t reserved_2b4;
|
||||
uint32_t reserved_2b8;
|
||||
uint32_t reserved_2bc;
|
||||
uint32_t reserved_2c0;
|
||||
uint32_t reserved_2c4;
|
||||
uint32_t reserved_2c8;
|
||||
uint32_t reserved_2cc;
|
||||
uint32_t reserved_2d0;
|
||||
uint32_t reserved_2d4;
|
||||
uint32_t reserved_2d8;
|
||||
uint32_t reserved_2dc;
|
||||
uint32_t reserved_2e0;
|
||||
uint32_t reserved_2e4;
|
||||
uint32_t reserved_2e8;
|
||||
uint32_t reserved_2ec;
|
||||
uint32_t reserved_2f0;
|
||||
uint32_t reserved_2f4;
|
||||
uint32_t reserved_2f8;
|
||||
uint32_t reserved_2fc;
|
||||
uint32_t reserved_300;
|
||||
uint32_t reserved_304;
|
||||
uint32_t reserved_308;
|
||||
uint32_t reserved_30c;
|
||||
uint32_t reserved_310;
|
||||
uint32_t reserved_314;
|
||||
uint32_t reserved_318;
|
||||
uint32_t reserved_31c;
|
||||
uint32_t reserved_320;
|
||||
uint32_t reserved_324;
|
||||
uint32_t reserved_328;
|
||||
uint32_t reserved_32c;
|
||||
uint32_t reserved_330;
|
||||
uint32_t reserved_334;
|
||||
uint32_t reserved_338;
|
||||
uint32_t reserved_33c;
|
||||
uint32_t reserved_340;
|
||||
uint32_t reserved_344;
|
||||
uint32_t reserved_348;
|
||||
uint32_t reserved_34c;
|
||||
uint32_t reserved_350;
|
||||
uint32_t reserved_354;
|
||||
uint32_t reserved_358;
|
||||
uint32_t reserved_35c;
|
||||
uint32_t reserved_360;
|
||||
uint32_t reserved_364;
|
||||
uint32_t reserved_368;
|
||||
uint32_t reserved_36c;
|
||||
uint32_t reserved_370;
|
||||
uint32_t reserved_374;
|
||||
uint32_t reserved_378;
|
||||
uint32_t reserved_37c;
|
||||
uint32_t reserved_380;
|
||||
uint32_t reserved_384;
|
||||
uint32_t reserved_388;
|
||||
uint32_t reserved_38c;
|
||||
uint32_t reserved_390;
|
||||
uint32_t reserved_394;
|
||||
uint32_t reserved_398;
|
||||
uint32_t reserved_39c;
|
||||
uint32_t reserved_3a0;
|
||||
uint32_t reserved_3a4;
|
||||
uint32_t reserved_3a8;
|
||||
uint32_t reserved_3ac;
|
||||
uint32_t reserved_3b0;
|
||||
uint32_t reserved_3b4;
|
||||
uint32_t reserved_3b8;
|
||||
uint32_t reserved_3bc;
|
||||
uint32_t reserved_3c0;
|
||||
uint32_t reserved_3c4;
|
||||
uint32_t reserved_3c8;
|
||||
uint32_t reserved_3cc;
|
||||
uint32_t reserved_3d0;
|
||||
uint32_t reserved_3d4;
|
||||
uint32_t reserved_3d8;
|
||||
uint32_t reserved_3dc;
|
||||
uint32_t reserved_3e0;
|
||||
uint32_t reserved_3e4;
|
||||
uint32_t reserved_3e8;
|
||||
uint32_t reserved_3ec;
|
||||
uint32_t reserved_3f0;
|
||||
uint32_t reserved_3f4;
|
||||
uint32_t reserved_3f8;
|
||||
uint32_t apb_ctrl_date; /**/
|
||||
} apb_saradc_dev_t;
|
||||
extern apb_saradc_dev_t APB_SARADC;
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,691 +0,0 @@
|
||||
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_ASSIST_DEBUG_REG_H_
|
||||
#define _SOC_ASSIST_DEBUG_REG_H_
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#include "soc.h"
|
||||
#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x000)
|
||||
/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA (BIT(11))
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_M (BIT(11))
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S 11
|
||||
/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA (BIT(10))
|
||||
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_M (BIT(10))
|
||||
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S 10
|
||||
/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA (BIT(9))
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M (BIT(9))
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S 9
|
||||
/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA (BIT(8))
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M (BIT(8))
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S 8
|
||||
/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA (BIT(7))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_M (BIT(7))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S 7
|
||||
/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA (BIT(6))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_M (BIT(6))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S 6
|
||||
/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA (BIT(5))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_M (BIT(5))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S 5
|
||||
/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA (BIT(4))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_M (BIT(4))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S 4
|
||||
/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA (BIT(3))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_M (BIT(3))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S 3
|
||||
/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA (BIT(2))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_M (BIT(2))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S 2
|
||||
/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA (BIT(1))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_M (BIT(1))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S 1
|
||||
/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA (BIT(0))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_M (BIT(0))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S 0
|
||||
|
||||
#define ASSIST_DEBUG_CORE_0_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x004)
|
||||
/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW (BIT(11))
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_M (BIT(11))
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S 11
|
||||
/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW (BIT(10))
|
||||
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_M (BIT(10))
|
||||
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S 10
|
||||
/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW (BIT(9))
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M (BIT(9))
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S 9
|
||||
/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW (BIT(8))
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M (BIT(8))
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S 8
|
||||
/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW (BIT(7))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_M (BIT(7))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S 7
|
||||
/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW (BIT(6))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_M (BIT(6))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S 6
|
||||
/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW (BIT(5))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_M (BIT(5))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S 5
|
||||
/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW (BIT(4))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_M (BIT(4))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S 4
|
||||
/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW (BIT(3))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_M (BIT(3))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S 3
|
||||
/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW (BIT(2))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_M (BIT(2))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S 2
|
||||
/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW (BIT(1))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_M (BIT(1))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S 1
|
||||
/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW (BIT(0))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M (BIT(0))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S 0
|
||||
|
||||
#define ASSIST_DEBUG_CORE_0_INTR_RLS_REG (DR_REG_ASSIST_DEBUG_BASE + 0x008)
|
||||
/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS : R/W ;bitpos:[11] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS (BIT(11))
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_M (BIT(11))
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_S 11
|
||||
/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS : R/W ;bitpos:[10] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS (BIT(10))
|
||||
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_M (BIT(10))
|
||||
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_S 10
|
||||
/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS : R/W ;bitpos:[9] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS (BIT(9))
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_M (BIT(9))
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S 9
|
||||
/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS : R/W ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS (BIT(8))
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_M (BIT(8))
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S 8
|
||||
/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS : R/W ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS (BIT(7))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_M (BIT(7))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S 7
|
||||
/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS : R/W ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS (BIT(6))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_M (BIT(6))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S 6
|
||||
/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS : R/W ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS (BIT(5))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_M (BIT(5))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S 5
|
||||
/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS : R/W ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS (BIT(4))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_M (BIT(4))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S 4
|
||||
/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS (BIT(3))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_M (BIT(3))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S 3
|
||||
/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS (BIT(2))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_M (BIT(2))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S 2
|
||||
/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS (BIT(1))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_M (BIT(1))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S 1
|
||||
/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS (BIT(0))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_M (BIT(0))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S 0
|
||||
|
||||
#define ASSIST_DEBUG_CORE_0_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0x00C)
|
||||
/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR : R/W ;bitpos:[11] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR (BIT(11))
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_M (BIT(11))
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S 11
|
||||
/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR : R/W ;bitpos:[10] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR (BIT(10))
|
||||
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_M (BIT(10))
|
||||
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S 10
|
||||
/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : R/W ;bitpos:[9] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR (BIT(9))
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M (BIT(9))
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S 9
|
||||
/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : R/W ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR (BIT(8))
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M (BIT(8))
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S 8
|
||||
/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR (BIT(7))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_M (BIT(7))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S 7
|
||||
/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR (BIT(6))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_M (BIT(6))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S 6
|
||||
/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR : R/W ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR (BIT(5))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_M (BIT(5))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S 5
|
||||
/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR (BIT(4))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_M (BIT(4))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S 4
|
||||
/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR (BIT(3))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_M (BIT(3))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S 3
|
||||
/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR (BIT(2))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_M (BIT(2))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S 2
|
||||
/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR (BIT(1))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_M (BIT(1))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S 1
|
||||
/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR (BIT(0))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_M (BIT(0))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S 0
|
||||
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x010)
|
||||
/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_M ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S 0
|
||||
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x014)
|
||||
/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_M ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S 0
|
||||
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x018)
|
||||
/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_M ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S 0
|
||||
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x01C)
|
||||
/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_M ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S 0
|
||||
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x020)
|
||||
/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_M ((ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S 0
|
||||
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x024)
|
||||
/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_M ((ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S 0
|
||||
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x028)
|
||||
/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_M ((ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S 0
|
||||
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x02C)
|
||||
/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_M ((ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V)<<(ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S 0
|
||||
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x030)
|
||||
/* ASSIST_DEBUG_CORE_0_AREA_PC : RO ;bitpos:[31:0] ;default: 32'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PC 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PC_M ((ASSIST_DEBUG_CORE_0_AREA_PC_V)<<(ASSIST_DEBUG_CORE_0_AREA_PC_S))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PC_V 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_PC_S 0
|
||||
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x034)
|
||||
/* ASSIST_DEBUG_CORE_0_AREA_SP : RO ;bitpos:[31:0] ;default: 32'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_SP 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_SP_M ((ASSIST_DEBUG_CORE_0_AREA_SP_V)<<(ASSIST_DEBUG_CORE_0_AREA_SP_S))
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_SP_V 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_CORE_0_AREA_SP_S 0
|
||||
|
||||
#define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x038)
|
||||
/* ASSIST_DEBUG_CORE_0_SP_MIN : RW ;bitpos:[31:0] ;default: 32'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_SP_MIN 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_CORE_0_SP_MIN_M ((ASSIST_DEBUG_CORE_0_SP_MIN_V)<<(ASSIST_DEBUG_CORE_0_SP_MIN_S))
|
||||
#define ASSIST_DEBUG_CORE_0_SP_MIN_V 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_CORE_0_SP_MIN_S 0
|
||||
|
||||
#define ASSIST_DEBUG_CORE_0_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x03C)
|
||||
/* ASSIST_DEBUG_CORE_0_SP_MAX : RW ;bitpos:[31:0] ;default: ~32'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_SP_MAX 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_CORE_0_SP_MAX_M ((ASSIST_DEBUG_CORE_0_SP_MAX_V)<<(ASSIST_DEBUG_CORE_0_SP_MAX_S))
|
||||
#define ASSIST_DEBUG_CORE_0_SP_MAX_V 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_CORE_0_SP_MAX_S 0
|
||||
|
||||
#define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x040)
|
||||
/* ASSIST_DEBUG_CORE_0_SP_PC : RO ;bitpos:[31:0] ;default: 32'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_SP_PC 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_CORE_0_SP_PC_M ((ASSIST_DEBUG_CORE_0_SP_PC_V)<<(ASSIST_DEBUG_CORE_0_SP_PC_S))
|
||||
#define ASSIST_DEBUG_CORE_0_SP_PC_V 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_CORE_0_SP_PC_S 0
|
||||
|
||||
#define ASSIST_DEBUG_CORE_0_RCD_EN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x044)
|
||||
/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN : RW ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: enable CPU Pdebug function if enable CPU will update PdebugPC*/
|
||||
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN (BIT(1))
|
||||
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_M (BIT(1))
|
||||
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S 1
|
||||
/* ASSIST_DEBUG_CORE_0_RCD_RECORDEN : RW ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: enable recording function if enable assist_debug will update
|
||||
PdebugPC so you can read it*/
|
||||
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN (BIT(0))
|
||||
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_M (BIT(0))
|
||||
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S 0
|
||||
|
||||
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x048)
|
||||
/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V)<<(ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S))
|
||||
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S 0
|
||||
|
||||
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x04C)
|
||||
/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_M ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V)<<(ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S))
|
||||
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S 0
|
||||
|
||||
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x050)
|
||||
/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 : RO ;bitpos:[25] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 (BIT(25))
|
||||
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_M (BIT(25))
|
||||
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S 25
|
||||
/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 : RO ;bitpos:[24] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 (BIT(24))
|
||||
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_M (BIT(24))
|
||||
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S 24
|
||||
/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 : RO ;bitpos:[23:0] ;default: 24'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 0x00FFFFFF
|
||||
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_M ((ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V)<<(ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S))
|
||||
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V 0xFFFFFF
|
||||
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S 0
|
||||
|
||||
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x054)
|
||||
/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 : RO ;bitpos:[25] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 (BIT(25))
|
||||
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_M (BIT(25))
|
||||
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S 25
|
||||
/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 : RO ;bitpos:[24] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 (BIT(24))
|
||||
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_M (BIT(24))
|
||||
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S 24
|
||||
/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 : RO ;bitpos:[23:0] ;default: 24'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 0x00FFFFFF
|
||||
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_M ((ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V)<<(ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S))
|
||||
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V 0xFFFFFF
|
||||
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S 0
|
||||
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x058)
|
||||
/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 : RO ;bitpos:[28:25] ;default: 4'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 0x0000000F
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S))
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V 0xF
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S 25
|
||||
/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 : RO ;bitpos:[24] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 (BIT(24))
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_M (BIT(24))
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S 24
|
||||
/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 : RO ;bitpos:[23:0] ;default: 24'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 0x00FFFFFF
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S))
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V 0xFFFFFF
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S 0
|
||||
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x05C)
|
||||
/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S))
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S 0
|
||||
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG (DR_REG_ASSIST_DEBUG_BASE + 0x060)
|
||||
/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 : RO ;bitpos:[28:25] ;default: 4'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 0x0000000F
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S))
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V 0xF
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S 25
|
||||
/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 : RO ;bitpos:[24] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 (BIT(24))
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_M (BIT(24))
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S 24
|
||||
/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 : RO ;bitpos:[23:0] ;default: 24'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 0x00FFFFFF
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S))
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V 0xFFFFFF
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S 0
|
||||
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG (DR_REG_ASSIST_DEBUG_BASE + 0x064)
|
||||
/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V)<<(ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S))
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S 0
|
||||
|
||||
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x068)
|
||||
/* ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 : R/W ;bitpos:[19:0] ;default: 20'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 0x000FFFFF
|
||||
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_M ((ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V)<<(ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S))
|
||||
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V 0xFFFFF
|
||||
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S 0
|
||||
|
||||
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x06C)
|
||||
/* ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 : R/W ;bitpos:[19:0] ;default: 20'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 0x000FFFFF
|
||||
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_M ((ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V)<<(ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S))
|
||||
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V 0xFFFFF
|
||||
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S 0
|
||||
|
||||
#define ASSIST_DEBUG_LOG_SETTING_REG (DR_REG_ASSIST_DEBUG_BASE + 0x070)
|
||||
/* ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE : R/W ;bitpos:[7] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE (BIT(7))
|
||||
#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_M (BIT(7))
|
||||
#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_V 0x1
|
||||
#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_S 7
|
||||
/* ASSIST_DEBUG_LOG_MODE : R/W ;bitpos:[6:3] ;default: 4'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_LOG_MODE 0x0000000F
|
||||
#define ASSIST_DEBUG_LOG_MODE_M ((ASSIST_DEBUG_LOG_MODE_V)<<(ASSIST_DEBUG_LOG_MODE_S))
|
||||
#define ASSIST_DEBUG_LOG_MODE_V 0xF
|
||||
#define ASSIST_DEBUG_LOG_MODE_S 3
|
||||
/* ASSIST_DEBUG_LOG_ENA : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_LOG_ENA 0x00000007
|
||||
#define ASSIST_DEBUG_LOG_ENA_M ((ASSIST_DEBUG_LOG_ENA_V)<<(ASSIST_DEBUG_LOG_ENA_S))
|
||||
#define ASSIST_DEBUG_LOG_ENA_V 0x7
|
||||
#define ASSIST_DEBUG_LOG_ENA_S 0
|
||||
|
||||
#define ASSIST_DEBUG_LOG_DATA_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x074)
|
||||
/* ASSIST_DEBUG_LOG_DATA_0 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_LOG_DATA_0 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_LOG_DATA_0_M ((ASSIST_DEBUG_LOG_DATA_0_V)<<(ASSIST_DEBUG_LOG_DATA_0_S))
|
||||
#define ASSIST_DEBUG_LOG_DATA_0_V 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_LOG_DATA_0_S 0
|
||||
|
||||
#define ASSIST_DEBUG_LOG_DATA_MASK_REG (DR_REG_ASSIST_DEBUG_BASE + 0x078)
|
||||
/* ASSIST_DEBUG_LOG_DATA_SIZE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_LOG_DATA_SIZE 0x0000FFFF
|
||||
#define ASSIST_DEBUG_LOG_DATA_SIZE_M ((ASSIST_DEBUG_LOG_DATA_SIZE_V)<<(ASSIST_DEBUG_LOG_DATA_SIZE_S))
|
||||
#define ASSIST_DEBUG_LOG_DATA_SIZE_V 0xFFFF
|
||||
#define ASSIST_DEBUG_LOG_DATA_SIZE_S 0
|
||||
|
||||
#define ASSIST_DEBUG_LOG_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x07C)
|
||||
/* ASSIST_DEBUG_LOG_MIN : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_LOG_MIN 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_LOG_MIN_M ((ASSIST_DEBUG_LOG_MIN_V)<<(ASSIST_DEBUG_LOG_MIN_S))
|
||||
#define ASSIST_DEBUG_LOG_MIN_V 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_LOG_MIN_S 0
|
||||
|
||||
#define ASSIST_DEBUG_LOG_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x080)
|
||||
/* ASSIST_DEBUG_LOG_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_LOG_MAX 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_LOG_MAX_M ((ASSIST_DEBUG_LOG_MAX_V)<<(ASSIST_DEBUG_LOG_MAX_S))
|
||||
#define ASSIST_DEBUG_LOG_MAX_V 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_LOG_MAX_S 0
|
||||
|
||||
#define ASSIST_DEBUG_LOG_MEM_START_REG (DR_REG_ASSIST_DEBUG_BASE + 0x084)
|
||||
/* ASSIST_DEBUG_LOG_MEM_START : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_LOG_MEM_START 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_LOG_MEM_START_M ((ASSIST_DEBUG_LOG_MEM_START_V)<<(ASSIST_DEBUG_LOG_MEM_START_S))
|
||||
#define ASSIST_DEBUG_LOG_MEM_START_V 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_LOG_MEM_START_S 0
|
||||
|
||||
#define ASSIST_DEBUG_LOG_MEM_END_REG (DR_REG_ASSIST_DEBUG_BASE + 0x088)
|
||||
/* ASSIST_DEBUG_LOG_MEM_END : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_LOG_MEM_END 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_LOG_MEM_END_M ((ASSIST_DEBUG_LOG_MEM_END_V)<<(ASSIST_DEBUG_LOG_MEM_END_S))
|
||||
#define ASSIST_DEBUG_LOG_MEM_END_V 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_LOG_MEM_END_S 0
|
||||
|
||||
#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_REG (DR_REG_ASSIST_DEBUG_BASE + 0x08C)
|
||||
/* ASSIST_DEBUG_LOG_MEM_WRITING_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_M ((ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_V)<<(ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_S))
|
||||
#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_V 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_S 0
|
||||
|
||||
#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_REG (DR_REG_ASSIST_DEBUG_BASE + 0x090)
|
||||
/* ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG (BIT(1))
|
||||
#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_M (BIT(1))
|
||||
#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_V 0x1
|
||||
#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_S 1
|
||||
/* ASSIST_DEBUG_LOG_MEM_FULL_FLAG : RO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG (BIT(0))
|
||||
#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_M (BIT(0))
|
||||
#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_V 0x1
|
||||
#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_S 0
|
||||
|
||||
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_DEBUG_BASE + 0x094)
|
||||
/* ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC : RO ;bitpos:[31:0] ;default: 32'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_M ((ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V)<<(ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S))
|
||||
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V 0xFFFFFFFF
|
||||
#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S 0
|
||||
|
||||
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x098)
|
||||
/* ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE : RO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE (BIT(1))
|
||||
#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_M (BIT(1))
|
||||
#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S 1
|
||||
/* ASSIST_DEBUG_CORE_0_DEBUG_MODE : RO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE (BIT(0))
|
||||
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_M (BIT(0))
|
||||
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_V 0x1
|
||||
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_S 0
|
||||
|
||||
#define ASSIST_DEBUG_DATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1FC)
|
||||
/* ASSIST_DEBUG_DATE : R/W ;bitpos:[27:0] ;default: 28'h2008010 ; */
|
||||
/*description: */
|
||||
#define ASSIST_DEBUG_DATE 0x0FFFFFFF
|
||||
#define ASSIST_DEBUG_DATE_M ((ASSIST_DEBUG_DATE_V)<<(ASSIST_DEBUG_DATE_S))
|
||||
#define ASSIST_DEBUG_DATE_V 0xFFFFFFF
|
||||
#define ASSIST_DEBUG_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /*_SOC_ASSIST_DEBUG_REG_H_ */
|
||||
@@ -8,8 +8,7 @@
|
||||
#define _DPORT_ACCESS_H_
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc.h"
|
||||
#include "uart_reg.h"
|
||||
#include "soc/soc.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,992 +0,0 @@
|
||||
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_EXTMEM_REG_H_
|
||||
#define _SOC_EXTMEM_REG_H_
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#include "soc.h"
|
||||
#define EXTMEM_ICACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x000)
|
||||
/* EXTMEM_ICACHE_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to activate the data cache. 0: disable 1: enable*/
|
||||
#define EXTMEM_ICACHE_ENABLE (BIT(0))
|
||||
#define EXTMEM_ICACHE_ENABLE_M (BIT(0))
|
||||
#define EXTMEM_ICACHE_ENABLE_V 0x1
|
||||
#define EXTMEM_ICACHE_ENABLE_S 0
|
||||
|
||||
#define EXTMEM_ICACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x004)
|
||||
/* EXTMEM_ICACHE_SHUT_DBUS : R/W ;bitpos:[1] ;default: 1'b1 ; */
|
||||
/*description: The bit is used to disable core1 ibus 0: enable 1: disable*/
|
||||
#define EXTMEM_ICACHE_SHUT_DBUS (BIT(1))
|
||||
#define EXTMEM_ICACHE_SHUT_DBUS_M (BIT(1))
|
||||
#define EXTMEM_ICACHE_SHUT_DBUS_V 0x1
|
||||
#define EXTMEM_ICACHE_SHUT_DBUS_S 1
|
||||
/* EXTMEM_ICACHE_SHUT_IBUS : R/W ;bitpos:[0] ;default: 1'b1 ; */
|
||||
/*description: The bit is used to disable core0 ibus 0: enable 1: disable*/
|
||||
#define EXTMEM_ICACHE_SHUT_IBUS (BIT(0))
|
||||
#define EXTMEM_ICACHE_SHUT_IBUS_M (BIT(0))
|
||||
#define EXTMEM_ICACHE_SHUT_IBUS_V 0x1
|
||||
#define EXTMEM_ICACHE_SHUT_IBUS_S 0
|
||||
|
||||
#define EXTMEM_ICACHE_TAG_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x008)
|
||||
/* EXTMEM_ICACHE_TAG_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
|
||||
/*description: The bit is used to power icache tag memory up 0: follow rtc_lslp 1: power up*/
|
||||
#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU (BIT(2))
|
||||
#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_M (BIT(2))
|
||||
#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_V 0x1
|
||||
#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_S 2
|
||||
/* EXTMEM_ICACHE_TAG_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to power icache tag memory down 0: follow rtc_lslp
|
||||
1: power down*/
|
||||
#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD (BIT(1))
|
||||
#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_M (BIT(1))
|
||||
#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_V 0x1
|
||||
#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_S 1
|
||||
/* EXTMEM_ICACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
|
||||
/*description: The bit is used to close clock gating of icache tag memory.
|
||||
1: close gating 0: open clock gating.*/
|
||||
#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON (BIT(0))
|
||||
#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_M (BIT(0))
|
||||
#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_V 0x1
|
||||
#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_S 0
|
||||
|
||||
#define EXTMEM_ICACHE_PRELOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x00C)
|
||||
/* EXTMEM_ICACHE_PRELOCK_SCT1_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */
|
||||
/*description: The bit is used to enable the second section of prelock function.*/
|
||||
#define EXTMEM_ICACHE_PRELOCK_SCT1_EN (BIT(1))
|
||||
#define EXTMEM_ICACHE_PRELOCK_SCT1_EN_M (BIT(1))
|
||||
#define EXTMEM_ICACHE_PRELOCK_SCT1_EN_V 0x1
|
||||
#define EXTMEM_ICACHE_PRELOCK_SCT1_EN_S 1
|
||||
/* EXTMEM_ICACHE_PRELOCK_SCT0_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
|
||||
/*description: The bit is used to enable the first section of prelock function.*/
|
||||
#define EXTMEM_ICACHE_PRELOCK_SCT0_EN (BIT(0))
|
||||
#define EXTMEM_ICACHE_PRELOCK_SCT0_EN_M (BIT(0))
|
||||
#define EXTMEM_ICACHE_PRELOCK_SCT0_EN_V 0x1
|
||||
#define EXTMEM_ICACHE_PRELOCK_SCT0_EN_S 0
|
||||
|
||||
#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x010)
|
||||
/* EXTMEM_ICACHE_PRELOCK_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: The bits are used to configure the first start virtual address
|
||||
of data prelock which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG*/
|
||||
#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR 0xFFFFFFFF
|
||||
#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_M ((EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_V)<<(EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_S))
|
||||
#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_V 0xFFFFFFFF
|
||||
#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_S 0
|
||||
|
||||
#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x014)
|
||||
/* EXTMEM_ICACHE_PRELOCK_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: The bits are used to configure the second start virtual address
|
||||
of data prelock which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG*/
|
||||
#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR 0xFFFFFFFF
|
||||
#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_M ((EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_V)<<(EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_S))
|
||||
#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_V 0xFFFFFFFF
|
||||
#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_S 0
|
||||
|
||||
#define EXTMEM_ICACHE_PRELOCK_SCT_SIZE_REG (DR_REG_EXTMEM_BASE + 0x018)
|
||||
/* EXTMEM_ICACHE_PRELOCK_SCT0_SIZE : R/W ;bitpos:[31:16] ;default: 16'h0 ; */
|
||||
/*description: The bits are used to configure the first length of data locking
|
||||
which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG*/
|
||||
#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE 0x0000FFFF
|
||||
#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_M ((EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_V)<<(EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_S))
|
||||
#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_V 0xFFFF
|
||||
#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_S 16
|
||||
/* EXTMEM_ICACHE_PRELOCK_SCT1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
|
||||
/*description: The bits are used to configure the second length of data locking
|
||||
which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG*/
|
||||
#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE 0x0000FFFF
|
||||
#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_M ((EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_V)<<(EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_S))
|
||||
#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_V 0xFFFF
|
||||
#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_S 0
|
||||
|
||||
#define EXTMEM_ICACHE_LOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x01C)
|
||||
/* EXTMEM_ICACHE_LOCK_DONE : RO ;bitpos:[2] ;default: 1'b1 ; */
|
||||
/*description: The bit is used to indicate unlock/lock operation is finished.*/
|
||||
#define EXTMEM_ICACHE_LOCK_DONE (BIT(2))
|
||||
#define EXTMEM_ICACHE_LOCK_DONE_M (BIT(2))
|
||||
#define EXTMEM_ICACHE_LOCK_DONE_V 0x1
|
||||
#define EXTMEM_ICACHE_LOCK_DONE_S 2
|
||||
/* EXTMEM_ICACHE_UNLOCK_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to enable unlock operation. It will be cleared
|
||||
by hardware after unlock operation done.*/
|
||||
#define EXTMEM_ICACHE_UNLOCK_ENA (BIT(1))
|
||||
#define EXTMEM_ICACHE_UNLOCK_ENA_M (BIT(1))
|
||||
#define EXTMEM_ICACHE_UNLOCK_ENA_V 0x1
|
||||
#define EXTMEM_ICACHE_UNLOCK_ENA_S 1
|
||||
/* EXTMEM_ICACHE_LOCK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to enable lock operation. It will be cleared
|
||||
by hardware after lock operation done.*/
|
||||
#define EXTMEM_ICACHE_LOCK_ENA (BIT(0))
|
||||
#define EXTMEM_ICACHE_LOCK_ENA_M (BIT(0))
|
||||
#define EXTMEM_ICACHE_LOCK_ENA_V 0x1
|
||||
#define EXTMEM_ICACHE_LOCK_ENA_S 0
|
||||
|
||||
#define EXTMEM_ICACHE_LOCK_ADDR_REG (DR_REG_EXTMEM_BASE + 0x020)
|
||||
/* EXTMEM_ICACHE_LOCK_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
|
||||
/*description: The bits are used to configure the start virtual address for
|
||||
lock operations. It should be combined with ICACHE_LOCK_SIZE_REG.*/
|
||||
#define EXTMEM_ICACHE_LOCK_ADDR 0xFFFFFFFF
|
||||
#define EXTMEM_ICACHE_LOCK_ADDR_M ((EXTMEM_ICACHE_LOCK_ADDR_V)<<(EXTMEM_ICACHE_LOCK_ADDR_S))
|
||||
#define EXTMEM_ICACHE_LOCK_ADDR_V 0xFFFFFFFF
|
||||
#define EXTMEM_ICACHE_LOCK_ADDR_S 0
|
||||
|
||||
#define EXTMEM_ICACHE_LOCK_SIZE_REG (DR_REG_EXTMEM_BASE + 0x024)
|
||||
/* EXTMEM_ICACHE_LOCK_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
|
||||
/*description: The bits are used to configure the length for lock operations.
|
||||
The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG.*/
|
||||
#define EXTMEM_ICACHE_LOCK_SIZE 0x0000FFFF
|
||||
#define EXTMEM_ICACHE_LOCK_SIZE_M ((EXTMEM_ICACHE_LOCK_SIZE_V)<<(EXTMEM_ICACHE_LOCK_SIZE_S))
|
||||
#define EXTMEM_ICACHE_LOCK_SIZE_V 0xFFFF
|
||||
#define EXTMEM_ICACHE_LOCK_SIZE_S 0
|
||||
|
||||
#define EXTMEM_ICACHE_SYNC_CTRL_REG (DR_REG_EXTMEM_BASE + 0x028)
|
||||
/* EXTMEM_ICACHE_SYNC_DONE : RO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to indicate invalidate operation is finished.*/
|
||||
#define EXTMEM_ICACHE_SYNC_DONE (BIT(1))
|
||||
#define EXTMEM_ICACHE_SYNC_DONE_M (BIT(1))
|
||||
#define EXTMEM_ICACHE_SYNC_DONE_V 0x1
|
||||
#define EXTMEM_ICACHE_SYNC_DONE_S 1
|
||||
/* EXTMEM_ICACHE_INVALIDATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
|
||||
/*description: The bit is used to enable invalidate operation. It will be cleared
|
||||
by hardware after invalidate operation done.*/
|
||||
#define EXTMEM_ICACHE_INVALIDATE_ENA (BIT(0))
|
||||
#define EXTMEM_ICACHE_INVALIDATE_ENA_M (BIT(0))
|
||||
#define EXTMEM_ICACHE_INVALIDATE_ENA_V 0x1
|
||||
#define EXTMEM_ICACHE_INVALIDATE_ENA_S 0
|
||||
|
||||
#define EXTMEM_ICACHE_SYNC_ADDR_REG (DR_REG_EXTMEM_BASE + 0x02C)
|
||||
/* EXTMEM_ICACHE_SYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
|
||||
/*description: The bits are used to configure the start virtual address for
|
||||
clean operations. It should be combined with ICACHE_SYNC_SIZE_REG.*/
|
||||
#define EXTMEM_ICACHE_SYNC_ADDR 0xFFFFFFFF
|
||||
#define EXTMEM_ICACHE_SYNC_ADDR_M ((EXTMEM_ICACHE_SYNC_ADDR_V)<<(EXTMEM_ICACHE_SYNC_ADDR_S))
|
||||
#define EXTMEM_ICACHE_SYNC_ADDR_V 0xFFFFFFFF
|
||||
#define EXTMEM_ICACHE_SYNC_ADDR_S 0
|
||||
|
||||
#define EXTMEM_ICACHE_SYNC_SIZE_REG (DR_REG_EXTMEM_BASE + 0x030)
|
||||
/* EXTMEM_ICACHE_SYNC_SIZE : R/W ;bitpos:[22:0] ;default: 23'h0 ; */
|
||||
/*description: The bits are used to configure the length for sync operations.
|
||||
The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG.*/
|
||||
#define EXTMEM_ICACHE_SYNC_SIZE 0x007FFFFF
|
||||
#define EXTMEM_ICACHE_SYNC_SIZE_M ((EXTMEM_ICACHE_SYNC_SIZE_V)<<(EXTMEM_ICACHE_SYNC_SIZE_S))
|
||||
#define EXTMEM_ICACHE_SYNC_SIZE_V 0x7FFFFF
|
||||
#define EXTMEM_ICACHE_SYNC_SIZE_S 0
|
||||
|
||||
#define EXTMEM_ICACHE_PRELOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0x034)
|
||||
/* EXTMEM_ICACHE_PRELOAD_ORDER : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to configure the direction of preload operation.
|
||||
1: descending 0: ascending.*/
|
||||
#define EXTMEM_ICACHE_PRELOAD_ORDER (BIT(2))
|
||||
#define EXTMEM_ICACHE_PRELOAD_ORDER_M (BIT(2))
|
||||
#define EXTMEM_ICACHE_PRELOAD_ORDER_V 0x1
|
||||
#define EXTMEM_ICACHE_PRELOAD_ORDER_S 2
|
||||
/* EXTMEM_ICACHE_PRELOAD_DONE : RO ;bitpos:[1] ;default: 1'b1 ; */
|
||||
/*description: The bit is used to indicate preload operation is finished.*/
|
||||
#define EXTMEM_ICACHE_PRELOAD_DONE (BIT(1))
|
||||
#define EXTMEM_ICACHE_PRELOAD_DONE_M (BIT(1))
|
||||
#define EXTMEM_ICACHE_PRELOAD_DONE_V 0x1
|
||||
#define EXTMEM_ICACHE_PRELOAD_DONE_S 1
|
||||
/* EXTMEM_ICACHE_PRELOAD_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to enable preload operation. It will be cleared
|
||||
by hardware after preload operation done.*/
|
||||
#define EXTMEM_ICACHE_PRELOAD_ENA (BIT(0))
|
||||
#define EXTMEM_ICACHE_PRELOAD_ENA_M (BIT(0))
|
||||
#define EXTMEM_ICACHE_PRELOAD_ENA_V 0x1
|
||||
#define EXTMEM_ICACHE_PRELOAD_ENA_S 0
|
||||
|
||||
#define EXTMEM_ICACHE_PRELOAD_ADDR_REG (DR_REG_EXTMEM_BASE + 0x038)
|
||||
/* EXTMEM_ICACHE_PRELOAD_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
|
||||
/*description: The bits are used to configure the start virtual address for
|
||||
preload operation. It should be combined with ICACHE_PRELOAD_SIZE_REG.*/
|
||||
#define EXTMEM_ICACHE_PRELOAD_ADDR 0xFFFFFFFF
|
||||
#define EXTMEM_ICACHE_PRELOAD_ADDR_M ((EXTMEM_ICACHE_PRELOAD_ADDR_V)<<(EXTMEM_ICACHE_PRELOAD_ADDR_S))
|
||||
#define EXTMEM_ICACHE_PRELOAD_ADDR_V 0xFFFFFFFF
|
||||
#define EXTMEM_ICACHE_PRELOAD_ADDR_S 0
|
||||
|
||||
#define EXTMEM_ICACHE_PRELOAD_SIZE_REG (DR_REG_EXTMEM_BASE + 0x03C)
|
||||
/* EXTMEM_ICACHE_PRELOAD_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
|
||||
/*description: The bits are used to configure the length for preload operation.
|
||||
The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG..*/
|
||||
#define EXTMEM_ICACHE_PRELOAD_SIZE 0x0000FFFF
|
||||
#define EXTMEM_ICACHE_PRELOAD_SIZE_M ((EXTMEM_ICACHE_PRELOAD_SIZE_V)<<(EXTMEM_ICACHE_PRELOAD_SIZE_S))
|
||||
#define EXTMEM_ICACHE_PRELOAD_SIZE_V 0xFFFF
|
||||
#define EXTMEM_ICACHE_PRELOAD_SIZE_S 0
|
||||
|
||||
#define EXTMEM_ICACHE_AUTOLOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0x040)
|
||||
/* EXTMEM_ICACHE_AUTOLOAD_RQST : R/W ;bitpos:[6:5] ;default: 2'b0 ; */
|
||||
/*description: The bits are used to configure trigger conditions for autoload.
|
||||
0/3: cache miss 1: cache hit 2: both cache miss and hit.*/
|
||||
#define EXTMEM_ICACHE_AUTOLOAD_RQST 0x00000003
|
||||
#define EXTMEM_ICACHE_AUTOLOAD_RQST_M ((EXTMEM_ICACHE_AUTOLOAD_RQST_V)<<(EXTMEM_ICACHE_AUTOLOAD_RQST_S))
|
||||
#define EXTMEM_ICACHE_AUTOLOAD_RQST_V 0x3
|
||||
#define EXTMEM_ICACHE_AUTOLOAD_RQST_S 5
|
||||
/* EXTMEM_ICACHE_AUTOLOAD_ORDER : R/W ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: The bits are used to configure the direction of autoload. 1:
|
||||
descending 0: ascending.*/
|
||||
#define EXTMEM_ICACHE_AUTOLOAD_ORDER (BIT(4))
|
||||
#define EXTMEM_ICACHE_AUTOLOAD_ORDER_M (BIT(4))
|
||||
#define EXTMEM_ICACHE_AUTOLOAD_ORDER_V 0x1
|
||||
#define EXTMEM_ICACHE_AUTOLOAD_ORDER_S 4
|
||||
/* EXTMEM_ICACHE_AUTOLOAD_DONE : RO ;bitpos:[3] ;default: 1'b1 ; */
|
||||
/*description: The bit is used to indicate autoload operation is finished.*/
|
||||
#define EXTMEM_ICACHE_AUTOLOAD_DONE (BIT(3))
|
||||
#define EXTMEM_ICACHE_AUTOLOAD_DONE_M (BIT(3))
|
||||
#define EXTMEM_ICACHE_AUTOLOAD_DONE_V 0x1
|
||||
#define EXTMEM_ICACHE_AUTOLOAD_DONE_S 3
|
||||
/* EXTMEM_ICACHE_AUTOLOAD_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to enable and disable autoload operation. It
|
||||
is combined with icache_autoload_done. 1: enable 0: disable.*/
|
||||
#define EXTMEM_ICACHE_AUTOLOAD_ENA (BIT(2))
|
||||
#define EXTMEM_ICACHE_AUTOLOAD_ENA_M (BIT(2))
|
||||
#define EXTMEM_ICACHE_AUTOLOAD_ENA_V 0x1
|
||||
#define EXTMEM_ICACHE_AUTOLOAD_ENA_S 2
|
||||
/* EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: The bits are used to enable the second section for autoload operation.*/
|
||||
#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA (BIT(1))
|
||||
#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_M (BIT(1))
|
||||
#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_V 0x1
|
||||
#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_S 1
|
||||
/* EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: The bits are used to enable the first section for autoload operation.*/
|
||||
#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA (BIT(0))
|
||||
#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_M (BIT(0))
|
||||
#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_V 0x1
|
||||
#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_S 0
|
||||
|
||||
#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x044)
|
||||
/* EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
|
||||
/*description: The bits are used to configure the start virtual address of the
|
||||
first section for autoload operation. It should be combined with icache_autoload_sct0_ena.*/
|
||||
#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR 0xFFFFFFFF
|
||||
#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_M ((EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_S))
|
||||
#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFF
|
||||
#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_S 0
|
||||
|
||||
#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_EXTMEM_BASE + 0x048)
|
||||
/* EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE : R/W ;bitpos:[26:0] ;default: 27'h0 ; */
|
||||
/*description: The bits are used to configure the length of the first section
|
||||
for autoload operation. It should be combined with icache_autoload_sct0_ena.*/
|
||||
#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE 0x07FFFFFF
|
||||
#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_M ((EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_S))
|
||||
#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_V 0x7FFFFFF
|
||||
#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_S 0
|
||||
|
||||
#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x04C)
|
||||
/* EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
|
||||
/*description: The bits are used to configure the start virtual address of the
|
||||
second section for autoload operation. It should be combined with icache_autoload_sct1_ena.*/
|
||||
#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR 0xFFFFFFFF
|
||||
#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_M ((EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_S))
|
||||
#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFF
|
||||
#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_S 0
|
||||
|
||||
#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_EXTMEM_BASE + 0x050)
|
||||
/* EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE : R/W ;bitpos:[26:0] ;default: 27'h0 ; */
|
||||
/*description: The bits are used to configure the length of the second section
|
||||
for autoload operation. It should be combined with icache_autoload_sct1_ena.*/
|
||||
#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE 0x07FFFFFF
|
||||
#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_M ((EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_S))
|
||||
#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_V 0x7FFFFFF
|
||||
#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_S 0
|
||||
|
||||
#define EXTMEM_IBUS_TO_FLASH_START_VADDR_REG (DR_REG_EXTMEM_BASE + 0x054)
|
||||
/* EXTMEM_IBUS_TO_FLASH_START_VADDR : R/W ;bitpos:[31:0] ;default: 32'h42000000 ; */
|
||||
/*description: The bits are used to configure the start virtual address of ibus
|
||||
to access flash. The register is used to give constraints to ibus access counter.*/
|
||||
#define EXTMEM_IBUS_TO_FLASH_START_VADDR 0xFFFFFFFF
|
||||
#define EXTMEM_IBUS_TO_FLASH_START_VADDR_M ((EXTMEM_IBUS_TO_FLASH_START_VADDR_V)<<(EXTMEM_IBUS_TO_FLASH_START_VADDR_S))
|
||||
#define EXTMEM_IBUS_TO_FLASH_START_VADDR_V 0xFFFFFFFF
|
||||
#define EXTMEM_IBUS_TO_FLASH_START_VADDR_S 0
|
||||
|
||||
#define EXTMEM_IBUS_TO_FLASH_END_VADDR_REG (DR_REG_EXTMEM_BASE + 0x058)
|
||||
/* EXTMEM_IBUS_TO_FLASH_END_VADDR : R/W ;bitpos:[31:0] ;default: 32'h427FFFFF ; */
|
||||
/*description: The bits are used to configure the end virtual address of ibus
|
||||
to access flash. The register is used to give constraints to ibus access counter.*/
|
||||
#define EXTMEM_IBUS_TO_FLASH_END_VADDR 0xFFFFFFFF
|
||||
#define EXTMEM_IBUS_TO_FLASH_END_VADDR_M ((EXTMEM_IBUS_TO_FLASH_END_VADDR_V)<<(EXTMEM_IBUS_TO_FLASH_END_VADDR_S))
|
||||
#define EXTMEM_IBUS_TO_FLASH_END_VADDR_V 0xFFFFFFFF
|
||||
#define EXTMEM_IBUS_TO_FLASH_END_VADDR_S 0
|
||||
|
||||
#define EXTMEM_DBUS_TO_FLASH_START_VADDR_REG (DR_REG_EXTMEM_BASE + 0x05C)
|
||||
/* EXTMEM_DBUS_TO_FLASH_START_VADDR : R/W ;bitpos:[31:0] ;default: 32'h3C000000 ; */
|
||||
/*description: The bits are used to configure the start virtual address of dbus
|
||||
to access flash. The register is used to give constraints to dbus access counter.*/
|
||||
#define EXTMEM_DBUS_TO_FLASH_START_VADDR 0xFFFFFFFF
|
||||
#define EXTMEM_DBUS_TO_FLASH_START_VADDR_M ((EXTMEM_DBUS_TO_FLASH_START_VADDR_V)<<(EXTMEM_DBUS_TO_FLASH_START_VADDR_S))
|
||||
#define EXTMEM_DBUS_TO_FLASH_START_VADDR_V 0xFFFFFFFF
|
||||
#define EXTMEM_DBUS_TO_FLASH_START_VADDR_S 0
|
||||
|
||||
#define EXTMEM_DBUS_TO_FLASH_END_VADDR_REG (DR_REG_EXTMEM_BASE + 0x060)
|
||||
/* EXTMEM_DBUS_TO_FLASH_END_VADDR : R/W ;bitpos:[31:0] ;default: 32'h3C7FFFFF ; */
|
||||
/*description: The bits are used to configure the end virtual address of dbus
|
||||
to access flash. The register is used to give constraints to dbus access counter.*/
|
||||
#define EXTMEM_DBUS_TO_FLASH_END_VADDR 0xFFFFFFFF
|
||||
#define EXTMEM_DBUS_TO_FLASH_END_VADDR_M ((EXTMEM_DBUS_TO_FLASH_END_VADDR_V)<<(EXTMEM_DBUS_TO_FLASH_END_VADDR_S))
|
||||
#define EXTMEM_DBUS_TO_FLASH_END_VADDR_V 0xFFFFFFFF
|
||||
#define EXTMEM_DBUS_TO_FLASH_END_VADDR_S 0
|
||||
|
||||
#define EXTMEM_CACHE_ACS_CNT_CLR_REG (DR_REG_EXTMEM_BASE + 0x064)
|
||||
/* EXTMEM_DBUS_ACS_CNT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to clear dbus counter.*/
|
||||
#define EXTMEM_DBUS_ACS_CNT_CLR (BIT(1))
|
||||
#define EXTMEM_DBUS_ACS_CNT_CLR_M (BIT(1))
|
||||
#define EXTMEM_DBUS_ACS_CNT_CLR_V 0x1
|
||||
#define EXTMEM_DBUS_ACS_CNT_CLR_S 1
|
||||
/* EXTMEM_IBUS_ACS_CNT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to clear ibus counter.*/
|
||||
#define EXTMEM_IBUS_ACS_CNT_CLR (BIT(0))
|
||||
#define EXTMEM_IBUS_ACS_CNT_CLR_M (BIT(0))
|
||||
#define EXTMEM_IBUS_ACS_CNT_CLR_V 0x1
|
||||
#define EXTMEM_IBUS_ACS_CNT_CLR_S 0
|
||||
|
||||
#define EXTMEM_IBUS_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x068)
|
||||
/* EXTMEM_IBUS_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: The bits are used to count the number of the cache miss caused
|
||||
by ibus access flash.*/
|
||||
#define EXTMEM_IBUS_ACS_MISS_CNT 0xFFFFFFFF
|
||||
#define EXTMEM_IBUS_ACS_MISS_CNT_M ((EXTMEM_IBUS_ACS_MISS_CNT_V)<<(EXTMEM_IBUS_ACS_MISS_CNT_S))
|
||||
#define EXTMEM_IBUS_ACS_MISS_CNT_V 0xFFFFFFFF
|
||||
#define EXTMEM_IBUS_ACS_MISS_CNT_S 0
|
||||
|
||||
#define EXTMEM_IBUS_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0x06C)
|
||||
/* EXTMEM_IBUS_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: The bits are used to count the number of ibus access flash through icache.*/
|
||||
#define EXTMEM_IBUS_ACS_CNT 0xFFFFFFFF
|
||||
#define EXTMEM_IBUS_ACS_CNT_M ((EXTMEM_IBUS_ACS_CNT_V)<<(EXTMEM_IBUS_ACS_CNT_S))
|
||||
#define EXTMEM_IBUS_ACS_CNT_V 0xFFFFFFFF
|
||||
#define EXTMEM_IBUS_ACS_CNT_S 0
|
||||
|
||||
#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x070)
|
||||
/* EXTMEM_DBUS_ACS_FLASH_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: The bits are used to count the number of the cache miss caused
|
||||
by dbus access flash.*/
|
||||
#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT 0xFFFFFFFF
|
||||
#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_M ((EXTMEM_DBUS_ACS_FLASH_MISS_CNT_V)<<(EXTMEM_DBUS_ACS_FLASH_MISS_CNT_S))
|
||||
#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_V 0xFFFFFFFF
|
||||
#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_S 0
|
||||
|
||||
#define EXTMEM_DBUS_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0x074)
|
||||
/* EXTMEM_DBUS_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: The bits are used to count the number of dbus access flash through icache.*/
|
||||
#define EXTMEM_DBUS_ACS_CNT 0xFFFFFFFF
|
||||
#define EXTMEM_DBUS_ACS_CNT_M ((EXTMEM_DBUS_ACS_CNT_V)<<(EXTMEM_DBUS_ACS_CNT_S))
|
||||
#define EXTMEM_DBUS_ACS_CNT_V 0xFFFFFFFF
|
||||
#define EXTMEM_DBUS_ACS_CNT_S 0
|
||||
|
||||
#define EXTMEM_CACHE_ILG_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x078)
|
||||
/* EXTMEM_DBUS_CNT_OVF_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to enable interrupt by dbus counter overflow.*/
|
||||
#define EXTMEM_DBUS_CNT_OVF_INT_ENA (BIT(8))
|
||||
#define EXTMEM_DBUS_CNT_OVF_INT_ENA_M (BIT(8))
|
||||
#define EXTMEM_DBUS_CNT_OVF_INT_ENA_V 0x1
|
||||
#define EXTMEM_DBUS_CNT_OVF_INT_ENA_S 8
|
||||
/* EXTMEM_IBUS_CNT_OVF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to enable interrupt by ibus counter overflow.*/
|
||||
#define EXTMEM_IBUS_CNT_OVF_INT_ENA (BIT(7))
|
||||
#define EXTMEM_IBUS_CNT_OVF_INT_ENA_M (BIT(7))
|
||||
#define EXTMEM_IBUS_CNT_OVF_INT_ENA_V 0x1
|
||||
#define EXTMEM_IBUS_CNT_OVF_INT_ENA_S 7
|
||||
/* EXTMEM_MMU_ENTRY_FAULT_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to enable interrupt by mmu entry fault.*/
|
||||
#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA (BIT(5))
|
||||
#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_M (BIT(5))
|
||||
#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_V 0x1
|
||||
#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_S 5
|
||||
/* EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to enable interrupt by preload configurations fault.*/
|
||||
#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA (BIT(1))
|
||||
#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_M (BIT(1))
|
||||
#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_V 0x1
|
||||
#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_S 1
|
||||
/* EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to enable interrupt by sync configurations fault.*/
|
||||
#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA (BIT(0))
|
||||
#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_M (BIT(0))
|
||||
#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_V 0x1
|
||||
#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_S 0
|
||||
|
||||
#define EXTMEM_CACHE_ILG_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x07C)
|
||||
/* EXTMEM_DBUS_CNT_OVF_INT_CLR : WOD ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to clear interrupt by dbus counter overflow.*/
|
||||
#define EXTMEM_DBUS_CNT_OVF_INT_CLR (BIT(8))
|
||||
#define EXTMEM_DBUS_CNT_OVF_INT_CLR_M (BIT(8))
|
||||
#define EXTMEM_DBUS_CNT_OVF_INT_CLR_V 0x1
|
||||
#define EXTMEM_DBUS_CNT_OVF_INT_CLR_S 8
|
||||
/* EXTMEM_IBUS_CNT_OVF_INT_CLR : WOD ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to clear interrupt by ibus counter overflow.*/
|
||||
#define EXTMEM_IBUS_CNT_OVF_INT_CLR (BIT(7))
|
||||
#define EXTMEM_IBUS_CNT_OVF_INT_CLR_M (BIT(7))
|
||||
#define EXTMEM_IBUS_CNT_OVF_INT_CLR_V 0x1
|
||||
#define EXTMEM_IBUS_CNT_OVF_INT_CLR_S 7
|
||||
/* EXTMEM_MMU_ENTRY_FAULT_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to clear interrupt by mmu entry fault.*/
|
||||
#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR (BIT(5))
|
||||
#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_M (BIT(5))
|
||||
#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_V 0x1
|
||||
#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_S 5
|
||||
/* EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to clear interrupt by preload configurations fault.*/
|
||||
#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR (BIT(1))
|
||||
#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_M (BIT(1))
|
||||
#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_V 0x1
|
||||
#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_S 1
|
||||
/* EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to clear interrupt by sync configurations fault.*/
|
||||
#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR (BIT(0))
|
||||
#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_M (BIT(0))
|
||||
#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_V 0x1
|
||||
#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_S 0
|
||||
|
||||
#define EXTMEM_CACHE_ILG_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x080)
|
||||
/* EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to indicate interrupt by dbus access flash miss
|
||||
counter overflow.*/
|
||||
#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST (BIT(10))
|
||||
#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_M (BIT(10))
|
||||
#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_V 0x1
|
||||
#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_S 10
|
||||
/* EXTMEM_DBUS_ACS_CNT_OVF_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to indicate interrupt by dbus access flash/spiram
|
||||
counter overflow.*/
|
||||
#define EXTMEM_DBUS_ACS_CNT_OVF_ST (BIT(9))
|
||||
#define EXTMEM_DBUS_ACS_CNT_OVF_ST_M (BIT(9))
|
||||
#define EXTMEM_DBUS_ACS_CNT_OVF_ST_V 0x1
|
||||
#define EXTMEM_DBUS_ACS_CNT_OVF_ST_S 9
|
||||
/* EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to indicate interrupt by ibus access flash/spiram
|
||||
miss counter overflow.*/
|
||||
#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST (BIT(8))
|
||||
#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_M (BIT(8))
|
||||
#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_V 0x1
|
||||
#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_S 8
|
||||
/* EXTMEM_IBUS_ACS_CNT_OVF_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to indicate interrupt by ibus access flash/spiram
|
||||
counter overflow.*/
|
||||
#define EXTMEM_IBUS_ACS_CNT_OVF_ST (BIT(7))
|
||||
#define EXTMEM_IBUS_ACS_CNT_OVF_ST_M (BIT(7))
|
||||
#define EXTMEM_IBUS_ACS_CNT_OVF_ST_V 0x1
|
||||
#define EXTMEM_IBUS_ACS_CNT_OVF_ST_S 7
|
||||
/* EXTMEM_MMU_ENTRY_FAULT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to indicate interrupt by mmu entry fault.*/
|
||||
#define EXTMEM_MMU_ENTRY_FAULT_ST (BIT(5))
|
||||
#define EXTMEM_MMU_ENTRY_FAULT_ST_M (BIT(5))
|
||||
#define EXTMEM_MMU_ENTRY_FAULT_ST_V 0x1
|
||||
#define EXTMEM_MMU_ENTRY_FAULT_ST_S 5
|
||||
/* EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to indicate interrupt by preload configurations fault.*/
|
||||
#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST (BIT(1))
|
||||
#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_M (BIT(1))
|
||||
#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_V 0x1
|
||||
#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_S 1
|
||||
/* EXTMEM_ICACHE_SYNC_OP_FAULT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to indicate interrupt by sync configurations fault.*/
|
||||
#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST (BIT(0))
|
||||
#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_M (BIT(0))
|
||||
#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_V 0x1
|
||||
#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_S 0
|
||||
|
||||
#define EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x084)
|
||||
/* EXTMEM_CORE0_DBUS_WR_IC_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to enable interrupt by dbus trying to write icache*/
|
||||
#define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA (BIT(5))
|
||||
#define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA_M (BIT(5))
|
||||
#define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA_V 0x1
|
||||
#define EXTMEM_CORE0_DBUS_WR_IC_INT_ENA_S 5
|
||||
/* EXTMEM_CORE0_DBUS_REJECT_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to enable interrupt by authentication fail.*/
|
||||
#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA (BIT(4))
|
||||
#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_M (BIT(4))
|
||||
#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_V 0x1
|
||||
#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_S 4
|
||||
/* EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to enable interrupt by cpu access icache while
|
||||
the corresponding dbus is disabled which include speculative access.*/
|
||||
#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA (BIT(3))
|
||||
#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA_M (BIT(3))
|
||||
#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA_V 0x1
|
||||
#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_ENA_S 3
|
||||
/* EXTMEM_CORE0_IBUS_REJECT_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to enable interrupt by authentication fail.*/
|
||||
#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA (BIT(2))
|
||||
#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_M (BIT(2))
|
||||
#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_V 0x1
|
||||
#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_S 2
|
||||
/* EXTMEM_CORE0_IBUS_WR_IC_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to enable interrupt by ibus trying to write icache*/
|
||||
#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA (BIT(1))
|
||||
#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_M (BIT(1))
|
||||
#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_V 0x1
|
||||
#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_S 1
|
||||
/* EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to enable interrupt by cpu access icache while
|
||||
the corresponding ibus is disabled which include speculative access.*/
|
||||
#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA (BIT(0))
|
||||
#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_M (BIT(0))
|
||||
#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_V 0x1
|
||||
#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_S 0
|
||||
|
||||
#define EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x088)
|
||||
/* EXTMEM_CORE0_DBUS_WR_IC_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to clear interrupt by dbus trying to write icache*/
|
||||
#define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR (BIT(5))
|
||||
#define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR_M (BIT(5))
|
||||
#define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR_V 0x1
|
||||
#define EXTMEM_CORE0_DBUS_WR_IC_INT_CLR_S 5
|
||||
/* EXTMEM_CORE0_DBUS_REJECT_INT_CLR : WOD ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to clear interrupt by authentication fail.*/
|
||||
#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR (BIT(4))
|
||||
#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_M (BIT(4))
|
||||
#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_V 0x1
|
||||
#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_S 4
|
||||
/* EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR : WOD ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to clear interrupt by cpu access icache while
|
||||
the corresponding dbus is disabled or icache is disabled which include speculative access.*/
|
||||
#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR (BIT(3))
|
||||
#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR_M (BIT(3))
|
||||
#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR_V 0x1
|
||||
#define EXTMEM_CORE0_DBUS_ACS_MSK_IC_INT_CLR_S 3
|
||||
/* EXTMEM_CORE0_IBUS_REJECT_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to clear interrupt by authentication fail.*/
|
||||
#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR (BIT(2))
|
||||
#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_M (BIT(2))
|
||||
#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_V 0x1
|
||||
#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_S 2
|
||||
/* EXTMEM_CORE0_IBUS_WR_IC_INT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to clear interrupt by ibus trying to write icache*/
|
||||
#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR (BIT(1))
|
||||
#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_M (BIT(1))
|
||||
#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_V 0x1
|
||||
#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_S 1
|
||||
/* EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to clear interrupt by cpu access icache while
|
||||
the corresponding ibus is disabled or icache is disabled which include speculative access.*/
|
||||
#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR (BIT(0))
|
||||
#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_M (BIT(0))
|
||||
#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_V 0x1
|
||||
#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_S 0
|
||||
|
||||
#define EXTMEM_CORE0_ACS_CACHE_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x08C)
|
||||
/* EXTMEM_CORE0_DBUS_WR_ICACHE_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to indicate interrupt by dbus trying to write icache*/
|
||||
#define EXTMEM_CORE0_DBUS_WR_ICACHE_ST (BIT(5))
|
||||
#define EXTMEM_CORE0_DBUS_WR_ICACHE_ST_M (BIT(5))
|
||||
#define EXTMEM_CORE0_DBUS_WR_ICACHE_ST_V 0x1
|
||||
#define EXTMEM_CORE0_DBUS_WR_ICACHE_ST_S 5
|
||||
/* EXTMEM_CORE0_DBUS_REJECT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to indicate interrupt by authentication fail.*/
|
||||
#define EXTMEM_CORE0_DBUS_REJECT_ST (BIT(4))
|
||||
#define EXTMEM_CORE0_DBUS_REJECT_ST_M (BIT(4))
|
||||
#define EXTMEM_CORE0_DBUS_REJECT_ST_V 0x1
|
||||
#define EXTMEM_CORE0_DBUS_REJECT_ST_S 4
|
||||
/* EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to indicate interrupt by cpu access icache while
|
||||
the core0_dbus is disabled or icache is disabled which include speculative access.*/
|
||||
#define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST (BIT(3))
|
||||
#define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST_M (BIT(3))
|
||||
#define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST_V 0x1
|
||||
#define EXTMEM_CORE0_DBUS_ACS_MSK_ICACHE_ST_S 3
|
||||
/* EXTMEM_CORE0_IBUS_REJECT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to indicate interrupt by authentication fail.*/
|
||||
#define EXTMEM_CORE0_IBUS_REJECT_ST (BIT(2))
|
||||
#define EXTMEM_CORE0_IBUS_REJECT_ST_M (BIT(2))
|
||||
#define EXTMEM_CORE0_IBUS_REJECT_ST_V 0x1
|
||||
#define EXTMEM_CORE0_IBUS_REJECT_ST_S 2
|
||||
/* EXTMEM_CORE0_IBUS_WR_ICACHE_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to indicate interrupt by ibus trying to write icache*/
|
||||
#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST (BIT(1))
|
||||
#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_M (BIT(1))
|
||||
#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_V 0x1
|
||||
#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_S 1
|
||||
/* EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to indicate interrupt by cpu access icache while
|
||||
the core0_ibus is disabled or icache is disabled which include speculative access.*/
|
||||
#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST (BIT(0))
|
||||
#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_M (BIT(0))
|
||||
#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_V 0x1
|
||||
#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_S 0
|
||||
|
||||
#define EXTMEM_CORE0_DBUS_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x090)
|
||||
/* EXTMEM_CORE0_DBUS_WORLD : RO ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to indicate the world of CPU access dbus when
|
||||
authentication fail. 0: WORLD0 1: WORLD1*/
|
||||
#define EXTMEM_CORE0_DBUS_WORLD (BIT(3))
|
||||
#define EXTMEM_CORE0_DBUS_WORLD_M (BIT(3))
|
||||
#define EXTMEM_CORE0_DBUS_WORLD_V 0x1
|
||||
#define EXTMEM_CORE0_DBUS_WORLD_S 3
|
||||
/* EXTMEM_CORE0_DBUS_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */
|
||||
/*description: The bits are used to indicate the attribute of CPU access dbus
|
||||
when authentication fail. 0: invalidate 1: execute-able 2: read-able 4: write-able.*/
|
||||
#define EXTMEM_CORE0_DBUS_ATTR 0x00000007
|
||||
#define EXTMEM_CORE0_DBUS_ATTR_M ((EXTMEM_CORE0_DBUS_ATTR_V)<<(EXTMEM_CORE0_DBUS_ATTR_S))
|
||||
#define EXTMEM_CORE0_DBUS_ATTR_V 0x7
|
||||
#define EXTMEM_CORE0_DBUS_ATTR_S 0
|
||||
|
||||
#define EXTMEM_CORE0_DBUS_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x094)
|
||||
/* EXTMEM_CORE0_DBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */
|
||||
/*description: The bits are used to indicate the virtual address of CPU access
|
||||
dbus when authentication fail.*/
|
||||
#define EXTMEM_CORE0_DBUS_VADDR 0xFFFFFFFF
|
||||
#define EXTMEM_CORE0_DBUS_VADDR_M ((EXTMEM_CORE0_DBUS_VADDR_V)<<(EXTMEM_CORE0_DBUS_VADDR_S))
|
||||
#define EXTMEM_CORE0_DBUS_VADDR_V 0xFFFFFFFF
|
||||
#define EXTMEM_CORE0_DBUS_VADDR_S 0
|
||||
|
||||
#define EXTMEM_CORE0_IBUS_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x098)
|
||||
/* EXTMEM_CORE0_IBUS_WORLD : RO ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to indicate the world of CPU access ibus when
|
||||
authentication fail. 0: WORLD0 1: WORLD1*/
|
||||
#define EXTMEM_CORE0_IBUS_WORLD (BIT(3))
|
||||
#define EXTMEM_CORE0_IBUS_WORLD_M (BIT(3))
|
||||
#define EXTMEM_CORE0_IBUS_WORLD_V 0x1
|
||||
#define EXTMEM_CORE0_IBUS_WORLD_S 3
|
||||
/* EXTMEM_CORE0_IBUS_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */
|
||||
/*description: The bits are used to indicate the attribute of CPU access ibus
|
||||
when authentication fail. 0: invalidate 1: execute-able 2: read-able*/
|
||||
#define EXTMEM_CORE0_IBUS_ATTR 0x00000007
|
||||
#define EXTMEM_CORE0_IBUS_ATTR_M ((EXTMEM_CORE0_IBUS_ATTR_V)<<(EXTMEM_CORE0_IBUS_ATTR_S))
|
||||
#define EXTMEM_CORE0_IBUS_ATTR_V 0x7
|
||||
#define EXTMEM_CORE0_IBUS_ATTR_S 0
|
||||
|
||||
#define EXTMEM_CORE0_IBUS_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x09C)
|
||||
/* EXTMEM_CORE0_IBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */
|
||||
/*description: The bits are used to indicate the virtual address of CPU access
|
||||
ibus when authentication fail.*/
|
||||
#define EXTMEM_CORE0_IBUS_VADDR 0xFFFFFFFF
|
||||
#define EXTMEM_CORE0_IBUS_VADDR_M ((EXTMEM_CORE0_IBUS_VADDR_V)<<(EXTMEM_CORE0_IBUS_VADDR_S))
|
||||
#define EXTMEM_CORE0_IBUS_VADDR_V 0xFFFFFFFF
|
||||
#define EXTMEM_CORE0_IBUS_VADDR_S 0
|
||||
|
||||
#define EXTMEM_CACHE_MMU_FAULT_CONTENT_REG (DR_REG_EXTMEM_BASE + 0x0A0)
|
||||
/* EXTMEM_CACHE_MMU_FAULT_CODE : RO ;bitpos:[13:10] ;default: 4'h0 ; */
|
||||
/*description: The right-most 3 bits are used to indicate the operations which
|
||||
cause mmu fault occurrence. 0: default 1: cpu miss 2: preload miss 3: writeback 4: cpu miss evict recovery address 5: load miss evict recovery address 6: external dma tx 7: external dma rx. The most significant bit is used to indicate this operation occurs in which one icache.*/
|
||||
#define EXTMEM_CACHE_MMU_FAULT_CODE 0x0000000F
|
||||
#define EXTMEM_CACHE_MMU_FAULT_CODE_M ((EXTMEM_CACHE_MMU_FAULT_CODE_V)<<(EXTMEM_CACHE_MMU_FAULT_CODE_S))
|
||||
#define EXTMEM_CACHE_MMU_FAULT_CODE_V 0xF
|
||||
#define EXTMEM_CACHE_MMU_FAULT_CODE_S 10
|
||||
/* EXTMEM_CACHE_MMU_FAULT_CONTENT : RO ;bitpos:[9:0] ;default: 10'h0 ; */
|
||||
/*description: The bits are used to indicate the content of mmu entry which cause mmu fault..*/
|
||||
#define EXTMEM_CACHE_MMU_FAULT_CONTENT 0x000003FF
|
||||
#define EXTMEM_CACHE_MMU_FAULT_CONTENT_M ((EXTMEM_CACHE_MMU_FAULT_CONTENT_V)<<(EXTMEM_CACHE_MMU_FAULT_CONTENT_S))
|
||||
#define EXTMEM_CACHE_MMU_FAULT_CONTENT_V 0x3FF
|
||||
#define EXTMEM_CACHE_MMU_FAULT_CONTENT_S 0
|
||||
|
||||
#define EXTMEM_CACHE_MMU_FAULT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x0A4)
|
||||
/* EXTMEM_CACHE_MMU_FAULT_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: The bits are used to indicate the virtual address which cause mmu fault..*/
|
||||
#define EXTMEM_CACHE_MMU_FAULT_VADDR 0xFFFFFFFF
|
||||
#define EXTMEM_CACHE_MMU_FAULT_VADDR_M ((EXTMEM_CACHE_MMU_FAULT_VADDR_V)<<(EXTMEM_CACHE_MMU_FAULT_VADDR_S))
|
||||
#define EXTMEM_CACHE_MMU_FAULT_VADDR_V 0xFFFFFFFF
|
||||
#define EXTMEM_CACHE_MMU_FAULT_VADDR_S 0
|
||||
|
||||
#define EXTMEM_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_EXTMEM_BASE + 0x0A8)
|
||||
/* EXTMEM_CACHE_FLASH_WRAP_AROUND : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to enable wrap around mode when read data from flash.*/
|
||||
#define EXTMEM_CACHE_FLASH_WRAP_AROUND (BIT(0))
|
||||
#define EXTMEM_CACHE_FLASH_WRAP_AROUND_M (BIT(0))
|
||||
#define EXTMEM_CACHE_FLASH_WRAP_AROUND_V 0x1
|
||||
#define EXTMEM_CACHE_FLASH_WRAP_AROUND_S 0
|
||||
|
||||
#define EXTMEM_CACHE_MMU_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x0AC)
|
||||
/* EXTMEM_CACHE_MMU_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
|
||||
/*description: The bit is used to power mmu memory down 0: follow_rtc_lslp_pd 1: power up*/
|
||||
#define EXTMEM_CACHE_MMU_MEM_FORCE_PU (BIT(2))
|
||||
#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_M (BIT(2))
|
||||
#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_V 0x1
|
||||
#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_S 2
|
||||
/* EXTMEM_CACHE_MMU_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to power mmu memory down 0: follow_rtc_lslp_pd 1: power down*/
|
||||
#define EXTMEM_CACHE_MMU_MEM_FORCE_PD (BIT(1))
|
||||
#define EXTMEM_CACHE_MMU_MEM_FORCE_PD_M (BIT(1))
|
||||
#define EXTMEM_CACHE_MMU_MEM_FORCE_PD_V 0x1
|
||||
#define EXTMEM_CACHE_MMU_MEM_FORCE_PD_S 1
|
||||
/* EXTMEM_CACHE_MMU_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
|
||||
/*description: The bit is used to enable clock gating to save power when access
|
||||
mmu memory 0: enable 1: disable*/
|
||||
#define EXTMEM_CACHE_MMU_MEM_FORCE_ON (BIT(0))
|
||||
#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_M (BIT(0))
|
||||
#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_V 0x1
|
||||
#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_S 0
|
||||
|
||||
#define EXTMEM_CACHE_STATE_REG (DR_REG_EXTMEM_BASE + 0x0B0)
|
||||
/* EXTMEM_ICACHE_STATE : RO ;bitpos:[11:0] ;default: 12'h1 ; */
|
||||
/*description: The bit is used to indicate whether icache main fsm is in idle
|
||||
state or not. 1: in idle state 0: not in idle state*/
|
||||
#define EXTMEM_ICACHE_STATE 0x00000FFF
|
||||
#define EXTMEM_ICACHE_STATE_M ((EXTMEM_ICACHE_STATE_V)<<(EXTMEM_ICACHE_STATE_S))
|
||||
#define EXTMEM_ICACHE_STATE_V 0xFFF
|
||||
#define EXTMEM_ICACHE_STATE_S 0
|
||||
|
||||
#define EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_REG (DR_REG_EXTMEM_BASE + 0x0B4)
|
||||
/* EXTMEM_RECORD_DISABLE_G0CB_DECRYPT : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: Reserved.*/
|
||||
#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT (BIT(1))
|
||||
#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_M (BIT(1))
|
||||
#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_V 0x1
|
||||
#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_S 1
|
||||
/* EXTMEM_RECORD_DISABLE_DB_ENCRYPT : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: Reserved.*/
|
||||
#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT (BIT(0))
|
||||
#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_M (BIT(0))
|
||||
#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_V 0x1
|
||||
#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_S 0
|
||||
|
||||
#define EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_REG (DR_REG_EXTMEM_BASE + 0x0B8)
|
||||
/* EXTMEM_CLK_FORCE_ON_CRYPT : R/W ;bitpos:[2] ;default: 1'b1 ; */
|
||||
/*description: The bit is used to close clock gating of external memory encrypt
|
||||
and decrypt clock. 1: close gating 0: open clock gating.*/
|
||||
#define EXTMEM_CLK_FORCE_ON_CRYPT (BIT(2))
|
||||
#define EXTMEM_CLK_FORCE_ON_CRYPT_M (BIT(2))
|
||||
#define EXTMEM_CLK_FORCE_ON_CRYPT_V 0x1
|
||||
#define EXTMEM_CLK_FORCE_ON_CRYPT_S 2
|
||||
/* EXTMEM_CLK_FORCE_ON_AUTO_CRYPT : R/W ;bitpos:[1] ;default: 1'b1 ; */
|
||||
/*description: The bit is used to close clock gating of automatic crypt clock.
|
||||
1: close gating 0: open clock gating.*/
|
||||
#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT (BIT(1))
|
||||
#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_M (BIT(1))
|
||||
#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_V 0x1
|
||||
#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_S 1
|
||||
/* EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT : R/W ;bitpos:[0] ;default: 1'b1 ; */
|
||||
/*description: The bit is used to close clock gating of manual crypt clock.
|
||||
1: close gating 0: open clock gating.*/
|
||||
#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT (BIT(0))
|
||||
#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_M (BIT(0))
|
||||
#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_V 0x1
|
||||
#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_S 0
|
||||
|
||||
#define EXTMEM_CACHE_PRELOAD_INT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x0BC)
|
||||
/* EXTMEM_ICACHE_PRELOAD_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to clear the interrupt by icache pre-load done.*/
|
||||
#define EXTMEM_ICACHE_PRELOAD_INT_CLR (BIT(2))
|
||||
#define EXTMEM_ICACHE_PRELOAD_INT_CLR_M (BIT(2))
|
||||
#define EXTMEM_ICACHE_PRELOAD_INT_CLR_V 0x1
|
||||
#define EXTMEM_ICACHE_PRELOAD_INT_CLR_S 2
|
||||
/* EXTMEM_ICACHE_PRELOAD_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to enable the interrupt by icache pre-load done.*/
|
||||
#define EXTMEM_ICACHE_PRELOAD_INT_ENA (BIT(1))
|
||||
#define EXTMEM_ICACHE_PRELOAD_INT_ENA_M (BIT(1))
|
||||
#define EXTMEM_ICACHE_PRELOAD_INT_ENA_V 0x1
|
||||
#define EXTMEM_ICACHE_PRELOAD_INT_ENA_S 1
|
||||
/* EXTMEM_ICACHE_PRELOAD_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to indicate the interrupt by icache pre-load done.*/
|
||||
#define EXTMEM_ICACHE_PRELOAD_INT_ST (BIT(0))
|
||||
#define EXTMEM_ICACHE_PRELOAD_INT_ST_M (BIT(0))
|
||||
#define EXTMEM_ICACHE_PRELOAD_INT_ST_V 0x1
|
||||
#define EXTMEM_ICACHE_PRELOAD_INT_ST_S 0
|
||||
|
||||
#define EXTMEM_CACHE_SYNC_INT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x0C0)
|
||||
/* EXTMEM_ICACHE_SYNC_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to clear the interrupt by icache sync done.*/
|
||||
#define EXTMEM_ICACHE_SYNC_INT_CLR (BIT(2))
|
||||
#define EXTMEM_ICACHE_SYNC_INT_CLR_M (BIT(2))
|
||||
#define EXTMEM_ICACHE_SYNC_INT_CLR_V 0x1
|
||||
#define EXTMEM_ICACHE_SYNC_INT_CLR_S 2
|
||||
/* EXTMEM_ICACHE_SYNC_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to enable the interrupt by icache sync done.*/
|
||||
#define EXTMEM_ICACHE_SYNC_INT_ENA (BIT(1))
|
||||
#define EXTMEM_ICACHE_SYNC_INT_ENA_M (BIT(1))
|
||||
#define EXTMEM_ICACHE_SYNC_INT_ENA_V 0x1
|
||||
#define EXTMEM_ICACHE_SYNC_INT_ENA_S 1
|
||||
/* EXTMEM_ICACHE_SYNC_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to indicate the interrupt by icache sync done.*/
|
||||
#define EXTMEM_ICACHE_SYNC_INT_ST (BIT(0))
|
||||
#define EXTMEM_ICACHE_SYNC_INT_ST_M (BIT(0))
|
||||
#define EXTMEM_ICACHE_SYNC_INT_ST_V 0x1
|
||||
#define EXTMEM_ICACHE_SYNC_INT_ST_S 0
|
||||
|
||||
#define EXTMEM_CACHE_MMU_OWNER_REG (DR_REG_EXTMEM_BASE + 0x0C4)
|
||||
/* EXTMEM_CACHE_MMU_OWNER : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
|
||||
/*description: The bits are used to specify the owner of MMU.bit0/bit2: ibus bit1/bit3: dbus*/
|
||||
#define EXTMEM_CACHE_MMU_OWNER 0x0000000F
|
||||
#define EXTMEM_CACHE_MMU_OWNER_M ((EXTMEM_CACHE_MMU_OWNER_V)<<(EXTMEM_CACHE_MMU_OWNER_S))
|
||||
#define EXTMEM_CACHE_MMU_OWNER_V 0xF
|
||||
#define EXTMEM_CACHE_MMU_OWNER_S 0
|
||||
|
||||
#define EXTMEM_CACHE_CONF_MISC_REG (DR_REG_EXTMEM_BASE + 0x0C8)
|
||||
/* EXTMEM_CACHE_TRACE_ENA : R/W ;bitpos:[2] ;default: 1'b1 ; */
|
||||
/*description: The bit is used to enable cache trace function.*/
|
||||
#define EXTMEM_CACHE_TRACE_ENA (BIT(2))
|
||||
#define EXTMEM_CACHE_TRACE_ENA_M (BIT(2))
|
||||
#define EXTMEM_CACHE_TRACE_ENA_V 0x1
|
||||
#define EXTMEM_CACHE_TRACE_ENA_S 2
|
||||
/* EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT : R/W ;bitpos:[1] ;default: 1'b1 ; */
|
||||
/*description: The bit is used to disable checking mmu entry fault by sync operation.*/
|
||||
#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT (BIT(1))
|
||||
#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_M (BIT(1))
|
||||
#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_V 0x1
|
||||
#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_S 1
|
||||
/* EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT : R/W ;bitpos:[0] ;default: 1'b1 ; */
|
||||
/*description: The bit is used to disable checking mmu entry fault by preload operation.*/
|
||||
#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT (BIT(0))
|
||||
#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_M (BIT(0))
|
||||
#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_V 0x1
|
||||
#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_S 0
|
||||
|
||||
#define EXTMEM_ICACHE_FREEZE_REG (DR_REG_EXTMEM_BASE + 0x0CC)
|
||||
/* EXTMEM_ICACHE_FREEZE_DONE : RO ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to indicate icache freeze success*/
|
||||
#define EXTMEM_ICACHE_FREEZE_DONE (BIT(2))
|
||||
#define EXTMEM_ICACHE_FREEZE_DONE_M (BIT(2))
|
||||
#define EXTMEM_ICACHE_FREEZE_DONE_V 0x1
|
||||
#define EXTMEM_ICACHE_FREEZE_DONE_S 2
|
||||
/* EXTMEM_ICACHE_FREEZE_MODE : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to configure freeze mode 0: assert busy if
|
||||
CPU miss 1: assert hit if CPU miss*/
|
||||
#define EXTMEM_ICACHE_FREEZE_MODE (BIT(1))
|
||||
#define EXTMEM_ICACHE_FREEZE_MODE_M (BIT(1))
|
||||
#define EXTMEM_ICACHE_FREEZE_MODE_V 0x1
|
||||
#define EXTMEM_ICACHE_FREEZE_MODE_S 1
|
||||
/* EXTMEM_ICACHE_FREEZE_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to enable icache freeze mode*/
|
||||
#define EXTMEM_ICACHE_FREEZE_ENA (BIT(0))
|
||||
#define EXTMEM_ICACHE_FREEZE_ENA_M (BIT(0))
|
||||
#define EXTMEM_ICACHE_FREEZE_ENA_V 0x1
|
||||
#define EXTMEM_ICACHE_FREEZE_ENA_S 0
|
||||
|
||||
#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_REG (DR_REG_EXTMEM_BASE + 0x0D0)
|
||||
/* EXTMEM_ICACHE_ATOMIC_OPERATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
|
||||
/*description: The bit is used to activate icache atomic operation protection.
|
||||
In this case sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation.*/
|
||||
#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA (BIT(0))
|
||||
#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_M (BIT(0))
|
||||
#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_V 0x1
|
||||
#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_S 0
|
||||
|
||||
#define EXTMEM_CACHE_REQUEST_REG (DR_REG_EXTMEM_BASE + 0x0D4)
|
||||
/* EXTMEM_CACHE_REQUEST_BYPASS : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to disable request recording which could cause performance issue*/
|
||||
#define EXTMEM_CACHE_REQUEST_BYPASS (BIT(0))
|
||||
#define EXTMEM_CACHE_REQUEST_BYPASS_M (BIT(0))
|
||||
#define EXTMEM_CACHE_REQUEST_BYPASS_V 0x1
|
||||
#define EXTMEM_CACHE_REQUEST_BYPASS_S 0
|
||||
|
||||
#define EXTMEM_IBUS_PMS_TBL_LOCK_REG (DR_REG_EXTMEM_BASE + 0x0D8)
|
||||
/* EXTMEM_IBUS_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to configure the ibus permission control section boundary0*/
|
||||
#define EXTMEM_IBUS_PMS_LOCK (BIT(0))
|
||||
#define EXTMEM_IBUS_PMS_LOCK_M (BIT(0))
|
||||
#define EXTMEM_IBUS_PMS_LOCK_V 0x1
|
||||
#define EXTMEM_IBUS_PMS_LOCK_S 0
|
||||
|
||||
#define EXTMEM_IBUS_PMS_TBL_BOUNDARY0_REG (DR_REG_EXTMEM_BASE + 0x0DC)
|
||||
/* EXTMEM_IBUS_PMS_BOUNDARY0 : R/W ;bitpos:[11:0] ;default: 12'h0 ; */
|
||||
/*description: The bit is used to configure the ibus permission control section boundary0*/
|
||||
#define EXTMEM_IBUS_PMS_BOUNDARY0 0x00000FFF
|
||||
#define EXTMEM_IBUS_PMS_BOUNDARY0_M ((EXTMEM_IBUS_PMS_BOUNDARY0_V)<<(EXTMEM_IBUS_PMS_BOUNDARY0_S))
|
||||
#define EXTMEM_IBUS_PMS_BOUNDARY0_V 0xFFF
|
||||
#define EXTMEM_IBUS_PMS_BOUNDARY0_S 0
|
||||
|
||||
#define EXTMEM_IBUS_PMS_TBL_BOUNDARY1_REG (DR_REG_EXTMEM_BASE + 0x0E0)
|
||||
/* EXTMEM_IBUS_PMS_BOUNDARY1 : R/W ;bitpos:[11:0] ;default: 12'h800 ; */
|
||||
/*description: The bit is used to configure the ibus permission control section boundary1*/
|
||||
#define EXTMEM_IBUS_PMS_BOUNDARY1 0x00000FFF
|
||||
#define EXTMEM_IBUS_PMS_BOUNDARY1_M ((EXTMEM_IBUS_PMS_BOUNDARY1_V)<<(EXTMEM_IBUS_PMS_BOUNDARY1_S))
|
||||
#define EXTMEM_IBUS_PMS_BOUNDARY1_V 0xFFF
|
||||
#define EXTMEM_IBUS_PMS_BOUNDARY1_S 0
|
||||
|
||||
#define EXTMEM_IBUS_PMS_TBL_BOUNDARY2_REG (DR_REG_EXTMEM_BASE + 0x0E4)
|
||||
/* EXTMEM_IBUS_PMS_BOUNDARY2 : R/W ;bitpos:[11:0] ;default: 12'h800 ; */
|
||||
/*description: The bit is used to configure the ibus permission control section boundary2*/
|
||||
#define EXTMEM_IBUS_PMS_BOUNDARY2 0x00000FFF
|
||||
#define EXTMEM_IBUS_PMS_BOUNDARY2_M ((EXTMEM_IBUS_PMS_BOUNDARY2_V)<<(EXTMEM_IBUS_PMS_BOUNDARY2_S))
|
||||
#define EXTMEM_IBUS_PMS_BOUNDARY2_V 0xFFF
|
||||
#define EXTMEM_IBUS_PMS_BOUNDARY2_S 0
|
||||
|
||||
#define EXTMEM_IBUS_PMS_TBL_ATTR_REG (DR_REG_EXTMEM_BASE + 0x0E8)
|
||||
/* EXTMEM_IBUS_PMS_SCT2_ATTR : R/W ;bitpos:[7:4] ;default: 4'hF ; */
|
||||
/*description: The bit is used to configure attribute of the ibus permission
|
||||
control section2 bit0: fetch in world0 bit1: load in world0 bit2: fetch in world1 bit3: load in world1*/
|
||||
#define EXTMEM_IBUS_PMS_SCT2_ATTR 0x0000000F
|
||||
#define EXTMEM_IBUS_PMS_SCT2_ATTR_M ((EXTMEM_IBUS_PMS_SCT2_ATTR_V)<<(EXTMEM_IBUS_PMS_SCT2_ATTR_S))
|
||||
#define EXTMEM_IBUS_PMS_SCT2_ATTR_V 0xF
|
||||
#define EXTMEM_IBUS_PMS_SCT2_ATTR_S 4
|
||||
/* EXTMEM_IBUS_PMS_SCT1_ATTR : R/W ;bitpos:[3:0] ;default: 4'hF ; */
|
||||
/*description: The bit is used to configure attribute of the ibus permission
|
||||
control section1 bit0: fetch in world0 bit1: load in world0 bit2: fetch in world1 bit3: load in world1*/
|
||||
#define EXTMEM_IBUS_PMS_SCT1_ATTR 0x0000000F
|
||||
#define EXTMEM_IBUS_PMS_SCT1_ATTR_M ((EXTMEM_IBUS_PMS_SCT1_ATTR_V)<<(EXTMEM_IBUS_PMS_SCT1_ATTR_S))
|
||||
#define EXTMEM_IBUS_PMS_SCT1_ATTR_V 0xF
|
||||
#define EXTMEM_IBUS_PMS_SCT1_ATTR_S 0
|
||||
|
||||
#define EXTMEM_DBUS_PMS_TBL_LOCK_REG (DR_REG_EXTMEM_BASE + 0x0EC)
|
||||
/* EXTMEM_DBUS_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: The bit is used to configure the ibus permission control section boundary0*/
|
||||
#define EXTMEM_DBUS_PMS_LOCK (BIT(0))
|
||||
#define EXTMEM_DBUS_PMS_LOCK_M (BIT(0))
|
||||
#define EXTMEM_DBUS_PMS_LOCK_V 0x1
|
||||
#define EXTMEM_DBUS_PMS_LOCK_S 0
|
||||
|
||||
#define EXTMEM_DBUS_PMS_TBL_BOUNDARY0_REG (DR_REG_EXTMEM_BASE + 0x0F0)
|
||||
/* EXTMEM_DBUS_PMS_BOUNDARY0 : R/W ;bitpos:[11:0] ;default: 12'h0 ; */
|
||||
/*description: The bit is used to configure the dbus permission control section boundary0*/
|
||||
#define EXTMEM_DBUS_PMS_BOUNDARY0 0x00000FFF
|
||||
#define EXTMEM_DBUS_PMS_BOUNDARY0_M ((EXTMEM_DBUS_PMS_BOUNDARY0_V)<<(EXTMEM_DBUS_PMS_BOUNDARY0_S))
|
||||
#define EXTMEM_DBUS_PMS_BOUNDARY0_V 0xFFF
|
||||
#define EXTMEM_DBUS_PMS_BOUNDARY0_S 0
|
||||
|
||||
#define EXTMEM_DBUS_PMS_TBL_BOUNDARY1_REG (DR_REG_EXTMEM_BASE + 0x0F4)
|
||||
/* EXTMEM_DBUS_PMS_BOUNDARY1 : R/W ;bitpos:[11:0] ;default: 12'h800 ; */
|
||||
/*description: The bit is used to configure the dbus permission control section boundary1*/
|
||||
#define EXTMEM_DBUS_PMS_BOUNDARY1 0x00000FFF
|
||||
#define EXTMEM_DBUS_PMS_BOUNDARY1_M ((EXTMEM_DBUS_PMS_BOUNDARY1_V)<<(EXTMEM_DBUS_PMS_BOUNDARY1_S))
|
||||
#define EXTMEM_DBUS_PMS_BOUNDARY1_V 0xFFF
|
||||
#define EXTMEM_DBUS_PMS_BOUNDARY1_S 0
|
||||
|
||||
#define EXTMEM_DBUS_PMS_TBL_BOUNDARY2_REG (DR_REG_EXTMEM_BASE + 0x0F8)
|
||||
/* EXTMEM_DBUS_PMS_BOUNDARY2 : R/W ;bitpos:[11:0] ;default: 12'h800 ; */
|
||||
/*description: The bit is used to configure the dbus permission control section boundary2*/
|
||||
#define EXTMEM_DBUS_PMS_BOUNDARY2 0x00000FFF
|
||||
#define EXTMEM_DBUS_PMS_BOUNDARY2_M ((EXTMEM_DBUS_PMS_BOUNDARY2_V)<<(EXTMEM_DBUS_PMS_BOUNDARY2_S))
|
||||
#define EXTMEM_DBUS_PMS_BOUNDARY2_V 0xFFF
|
||||
#define EXTMEM_DBUS_PMS_BOUNDARY2_S 0
|
||||
|
||||
#define EXTMEM_DBUS_PMS_TBL_ATTR_REG (DR_REG_EXTMEM_BASE + 0x0FC)
|
||||
/* EXTMEM_DBUS_PMS_SCT2_ATTR : R/W ;bitpos:[3:2] ;default: 2'd3 ; */
|
||||
/*description: The bit is used to configure attribute of the dbus permission
|
||||
control section2 bit0: load in world0 bit2: load in world1*/
|
||||
#define EXTMEM_DBUS_PMS_SCT2_ATTR 0x00000003
|
||||
#define EXTMEM_DBUS_PMS_SCT2_ATTR_M ((EXTMEM_DBUS_PMS_SCT2_ATTR_V)<<(EXTMEM_DBUS_PMS_SCT2_ATTR_S))
|
||||
#define EXTMEM_DBUS_PMS_SCT2_ATTR_V 0x3
|
||||
#define EXTMEM_DBUS_PMS_SCT2_ATTR_S 2
|
||||
/* EXTMEM_DBUS_PMS_SCT1_ATTR : R/W ;bitpos:[1:0] ;default: 2'd3 ; */
|
||||
/*description: The bit is used to configure attribute of the dbus permission
|
||||
control section1 bit0: load in world0 bit2: load in world1*/
|
||||
#define EXTMEM_DBUS_PMS_SCT1_ATTR 0x00000003
|
||||
#define EXTMEM_DBUS_PMS_SCT1_ATTR_M ((EXTMEM_DBUS_PMS_SCT1_ATTR_V)<<(EXTMEM_DBUS_PMS_SCT1_ATTR_S))
|
||||
#define EXTMEM_DBUS_PMS_SCT1_ATTR_V 0x3
|
||||
#define EXTMEM_DBUS_PMS_SCT1_ATTR_S 0
|
||||
|
||||
#define EXTMEM_CLOCK_GATE_REG (DR_REG_EXTMEM_BASE + 0x100)
|
||||
/* EXTMEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
|
||||
/*description: Reserved.*/
|
||||
#define EXTMEM_CLK_EN (BIT(0))
|
||||
#define EXTMEM_CLK_EN_M (BIT(0))
|
||||
#define EXTMEM_CLK_EN_V 0x1
|
||||
#define EXTMEM_CLK_EN_S 0
|
||||
|
||||
#define EXTMEM_DATE_REG (DR_REG_EXTMEM_BASE + 0x3FC)
|
||||
/* EXTMEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2007160 ; */
|
||||
/*description: Reserved.*/
|
||||
#define EXTMEM_DATE 0x0FFFFFFF
|
||||
#define EXTMEM_DATE_M ((EXTMEM_DATE_V)<<(EXTMEM_DATE_S))
|
||||
#define EXTMEM_DATE_V 0xFFFFFFF
|
||||
#define EXTMEM_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /*_SOC_EXTMEM_REG_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,323 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct gdma_dev_s {
|
||||
struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t in_done: 1; /*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0.*/
|
||||
uint32_t in_suc_eof: 1; /*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0.*/
|
||||
uint32_t in_err_eof: 1; /*The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved.*/
|
||||
uint32_t out_done: 1; /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0.*/
|
||||
uint32_t out_eof: 1; /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0.*/
|
||||
uint32_t in_dscr_err: 1; /*The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error the second and third word error of inlink descriptor for Rx channel 0.*/
|
||||
uint32_t out_dscr_err: 1; /*The raw interrupt bit turns to high level when detecting outlink descriptor error including owner error the second and third word error of outlink descriptor for Tx channel 0.*/
|
||||
uint32_t in_dscr_empty: 1; /*The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0.*/
|
||||
uint32_t out_total_eof: 1; /*The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0.*/
|
||||
uint32_t infifo_ovf: 1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow.*/
|
||||
uint32_t infifo_udf: 1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow.*/
|
||||
uint32_t outfifo_ovf: 1; /*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow.*/
|
||||
uint32_t outfifo_udf: 1; /*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow.*/
|
||||
uint32_t reserved13: 19; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t in_done: 1; /*The raw interrupt status bit for the IN_DONE_CH_INT interrupt.*/
|
||||
uint32_t in_suc_eof: 1; /*The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.*/
|
||||
uint32_t in_err_eof: 1; /*The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.*/
|
||||
uint32_t out_done: 1; /*The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.*/
|
||||
uint32_t out_eof: 1; /*The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.*/
|
||||
uint32_t in_dscr_err: 1; /*The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.*/
|
||||
uint32_t out_dscr_err: 1; /*The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.*/
|
||||
uint32_t in_dscr_empty: 1; /*The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/
|
||||
uint32_t out_total_eof: 1; /*The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/
|
||||
uint32_t infifo_ovf: 1; /*The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.*/
|
||||
uint32_t infifo_udf: 1; /*The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.*/
|
||||
uint32_t outfifo_ovf: 1; /*The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/
|
||||
uint32_t outfifo_udf: 1; /*The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/
|
||||
uint32_t reserved13: 19; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t in_done: 1; /*The interrupt enable bit for the IN_DONE_CH_INT interrupt.*/
|
||||
uint32_t in_suc_eof: 1; /*The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.*/
|
||||
uint32_t in_err_eof: 1; /*The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.*/
|
||||
uint32_t out_done: 1; /*The interrupt enable bit for the OUT_DONE_CH_INT interrupt.*/
|
||||
uint32_t out_eof: 1; /*The interrupt enable bit for the OUT_EOF_CH_INT interrupt.*/
|
||||
uint32_t in_dscr_err: 1; /*The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.*/
|
||||
uint32_t out_dscr_err: 1; /*The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.*/
|
||||
uint32_t in_dscr_empty: 1; /*The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/
|
||||
uint32_t out_total_eof: 1; /*The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/
|
||||
uint32_t infifo_ovf: 1; /*The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.*/
|
||||
uint32_t infifo_udf: 1; /*The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.*/
|
||||
uint32_t outfifo_ovf: 1; /*The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/
|
||||
uint32_t outfifo_udf: 1; /*The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/
|
||||
uint32_t reserved13: 19; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t in_done: 1; /*Set this bit to clear the IN_DONE_CH_INT interrupt.*/
|
||||
uint32_t in_suc_eof: 1; /*Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.*/
|
||||
uint32_t in_err_eof: 1; /*Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.*/
|
||||
uint32_t out_done: 1; /*Set this bit to clear the OUT_DONE_CH_INT interrupt.*/
|
||||
uint32_t out_eof: 1; /*Set this bit to clear the OUT_EOF_CH_INT interrupt.*/
|
||||
uint32_t in_dscr_err: 1; /*Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.*/
|
||||
uint32_t out_dscr_err: 1; /*Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.*/
|
||||
uint32_t in_dscr_empty: 1; /*Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.*/
|
||||
uint32_t out_total_eof: 1; /*Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.*/
|
||||
uint32_t infifo_ovf: 1; /*Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.*/
|
||||
uint32_t infifo_udf: 1; /*Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.*/
|
||||
uint32_t outfifo_ovf: 1; /*Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.*/
|
||||
uint32_t outfifo_udf: 1; /*Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.*/
|
||||
uint32_t reserved13: 19; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} clr;
|
||||
} intr[3];
|
||||
uint32_t reserved_30;
|
||||
uint32_t reserved_34;
|
||||
uint32_t reserved_38;
|
||||
uint32_t reserved_3c;
|
||||
union {
|
||||
struct {
|
||||
uint32_t ahb_testmode: 3; /*reserved*/
|
||||
uint32_t reserved3: 1; /*reserved*/
|
||||
uint32_t ahb_testaddr: 2; /*reserved*/
|
||||
uint32_t reserved6: 26; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} ahb_test;
|
||||
union {
|
||||
struct {
|
||||
uint32_t ahbm_rst_inter: 1; /*Set this bit then clear this bit to reset the internal ahb FSM.*/
|
||||
uint32_t reserved1: 1;
|
||||
uint32_t arb_pri_dis: 1; /*Set this bit to disable priority arbitration function.*/
|
||||
uint32_t clk_en: 1;
|
||||
uint32_t reserved4: 28;
|
||||
};
|
||||
uint32_t val;
|
||||
} misc_conf;
|
||||
uint32_t date; /**/
|
||||
uint32_t reserved_4c;
|
||||
uint32_t reserved_50;
|
||||
uint32_t reserved_54;
|
||||
uint32_t reserved_58;
|
||||
uint32_t reserved_5c;
|
||||
uint32_t reserved_60;
|
||||
uint32_t reserved_64;
|
||||
uint32_t reserved_68;
|
||||
uint32_t reserved_6c;
|
||||
struct {
|
||||
struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t in_rst: 1; /*This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.*/
|
||||
uint32_t in_loop_test: 1; /*reserved*/
|
||||
uint32_t indscr_burst_en: 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM.*/
|
||||
uint32_t in_data_burst_en: 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM.*/
|
||||
uint32_t mem_trans_en: 1; /*Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.*/
|
||||
uint32_t reserved5: 27; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} in_conf0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 12;
|
||||
uint32_t in_check_owner: 1; /*Set this bit to enable checking the owner attribute of the link descriptor.*/
|
||||
uint32_t reserved13: 19; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} in_conf1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t infifo_full: 1; /*L1 Rx FIFO full signal for Rx channel 0.*/
|
||||
uint32_t infifo_empty: 1; /*L1 Rx FIFO empty signal for Rx channel 0.*/
|
||||
uint32_t infifo_cnt: 6; /*The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.*/
|
||||
uint32_t reserved8: 15; /*reserved*/
|
||||
uint32_t in_remain_under_1b: 1; /*reserved*/
|
||||
uint32_t in_remain_under_2b: 1; /*reserved*/
|
||||
uint32_t in_remain_under_3b: 1; /*reserved*/
|
||||
uint32_t in_remain_under_4b: 1; /*reserved*/
|
||||
uint32_t in_buf_hungry: 1; /*reserved*/
|
||||
uint32_t reserved28: 4; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} infifo_status;
|
||||
union {
|
||||
struct {
|
||||
uint32_t infifo_rdata: 12; /*This register stores the data popping from DMA FIFO.*/
|
||||
uint32_t infifo_pop: 1; /*Set this bit to pop data from DMA FIFO.*/
|
||||
uint32_t reserved13: 19; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} in_pop;
|
||||
union {
|
||||
struct {
|
||||
uint32_t addr: 20; /*This register stores the 20 least significant bits of the first inlink descriptor's address.*/
|
||||
uint32_t auto_ret: 1; /*Set this bit to return to current inlink descriptor's address when there are some errors in current receiving data.*/
|
||||
uint32_t stop: 1; /*Set this bit to stop dealing with the inlink descriptors.*/
|
||||
uint32_t start: 1; /*Set this bit to start dealing with the inlink descriptors.*/
|
||||
uint32_t restart: 1; /*Set this bit to mount a new inlink descriptor.*/
|
||||
uint32_t park: 1; /*1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working.*/
|
||||
uint32_t reserved25: 7;
|
||||
};
|
||||
uint32_t val;
|
||||
} in_link;
|
||||
union {
|
||||
struct {
|
||||
uint32_t inlink_dscr_addr: 18; /*This register stores the current inlink descriptor's address.*/
|
||||
uint32_t in_dscr_state: 2; /*reserved*/
|
||||
uint32_t in_state: 3; /*reserved*/
|
||||
uint32_t reserved23: 9; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} in_state;
|
||||
uint32_t in_suc_eof_des_addr; /**/
|
||||
uint32_t in_err_eof_des_addr; /**/
|
||||
uint32_t in_dscr; /**/
|
||||
uint32_t in_dscr_bf0; /**/
|
||||
uint32_t in_dscr_bf1; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_pri: 4; /*The priority of Rx channel 0. The larger of the value the higher of the priority.*/
|
||||
uint32_t reserved4: 28;
|
||||
};
|
||||
uint32_t val;
|
||||
} in_pri;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sel: 6; /*This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.*/
|
||||
uint32_t reserved6: 26;
|
||||
};
|
||||
uint32_t val;
|
||||
} in_peri_sel;
|
||||
} in;
|
||||
uint32_t reserved_a4;
|
||||
uint32_t reserved_a8;
|
||||
uint32_t reserved_ac;
|
||||
uint32_t reserved_b0;
|
||||
uint32_t reserved_b4;
|
||||
uint32_t reserved_b8;
|
||||
uint32_t reserved_bc;
|
||||
uint32_t reserved_c0;
|
||||
uint32_t reserved_c4;
|
||||
uint32_t reserved_c8;
|
||||
uint32_t reserved_cc;
|
||||
struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t out_rst: 1; /*This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.*/
|
||||
uint32_t out_loop_test: 1; /*reserved*/
|
||||
uint32_t out_auto_wrback: 1; /*Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.*/
|
||||
uint32_t out_eof_mode: 1; /*EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA*/
|
||||
uint32_t outdscr_burst_en: 1; /*Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM.*/
|
||||
uint32_t out_data_burst_en: 1; /*Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM.*/
|
||||
uint32_t reserved6: 26;
|
||||
};
|
||||
uint32_t val;
|
||||
} out_conf0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 12;
|
||||
uint32_t out_check_owner: 1; /*Set this bit to enable checking the owner attribute of the link descriptor.*/
|
||||
uint32_t reserved13: 19; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} out_conf1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t outfifo_full: 1; /*L1 Tx FIFO full signal for Tx channel 0.*/
|
||||
uint32_t outfifo_empty: 1; /*L1 Tx FIFO empty signal for Tx channel 0.*/
|
||||
uint32_t outfifo_cnt: 6; /*The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.*/
|
||||
uint32_t reserved8: 15; /*reserved*/
|
||||
uint32_t out_remain_under_1b: 1; /*reserved*/
|
||||
uint32_t out_remain_under_2b: 1; /*reserved*/
|
||||
uint32_t out_remain_under_3b: 1; /*reserved*/
|
||||
uint32_t out_remain_under_4b: 1; /*reserved*/
|
||||
uint32_t reserved27: 5; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} outfifo_status;
|
||||
union {
|
||||
struct {
|
||||
uint32_t outfifo_wdata: 9; /*This register stores the data that need to be pushed into DMA FIFO.*/
|
||||
uint32_t outfifo_push: 1; /*Set this bit to push data into DMA FIFO.*/
|
||||
uint32_t reserved10: 22; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} out_push;
|
||||
union {
|
||||
struct {
|
||||
uint32_t addr: 20; /*This register stores the 20 least significant bits of the first outlink descriptor's address.*/
|
||||
uint32_t stop: 1; /*Set this bit to stop dealing with the outlink descriptors.*/
|
||||
uint32_t start: 1; /*Set this bit to start dealing with the outlink descriptors.*/
|
||||
uint32_t restart: 1; /*Set this bit to restart a new outlink from the last address.*/
|
||||
uint32_t park: 1; /*1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working.*/
|
||||
uint32_t reserved24: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} out_link;
|
||||
union {
|
||||
struct {
|
||||
uint32_t outlink_dscr_addr: 18; /*This register stores the current outlink descriptor's address.*/
|
||||
uint32_t out_dscr_state: 2; /*reserved*/
|
||||
uint32_t out_state: 3; /*reserved*/
|
||||
uint32_t reserved23: 9; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} out_state;
|
||||
uint32_t out_eof_des_addr; /**/
|
||||
uint32_t out_eof_bfr_des_addr; /**/
|
||||
uint32_t out_dscr; /**/
|
||||
uint32_t out_dscr_bf0; /**/
|
||||
uint32_t out_dscr_bf1; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t tx_pri: 4; /*The priority of Tx channel 0. The larger of the value the higher of the priority.*/
|
||||
uint32_t reserved4: 28;
|
||||
};
|
||||
uint32_t val;
|
||||
} out_pri;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sel: 6; /*This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.*/
|
||||
uint32_t reserved6: 26;
|
||||
};
|
||||
uint32_t val;
|
||||
} out_peri_sel;
|
||||
} out;
|
||||
uint32_t reserved_104;
|
||||
uint32_t reserved_108;
|
||||
uint32_t reserved_10c;
|
||||
uint32_t reserved_110;
|
||||
uint32_t reserved_114;
|
||||
uint32_t reserved_118;
|
||||
uint32_t reserved_11c;
|
||||
uint32_t reserved_120;
|
||||
uint32_t reserved_124;
|
||||
uint32_t reserved_128;
|
||||
uint32_t reserved_12c;
|
||||
} channel[3];
|
||||
} gdma_dev_t;
|
||||
|
||||
extern gdma_dev_t GDMA;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,102 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "soc.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#define GPIO_SIGMADELTA0_REG (DR_REG_GPIO_SD_BASE + 0x0000)
|
||||
/* GPIO_SD0_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
|
||||
/*description: */
|
||||
#define GPIO_SD0_PRESCALE 0x000000FF
|
||||
#define GPIO_SD0_PRESCALE_M ((GPIO_SD0_PRESCALE_V)<<(GPIO_SD0_PRESCALE_S))
|
||||
#define GPIO_SD0_PRESCALE_V 0xFF
|
||||
#define GPIO_SD0_PRESCALE_S 8
|
||||
/* GPIO_SD0_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
|
||||
/*description: */
|
||||
#define GPIO_SD0_IN 0x000000FF
|
||||
#define GPIO_SD0_IN_M ((GPIO_SD0_IN_V)<<(GPIO_SD0_IN_S))
|
||||
#define GPIO_SD0_IN_V 0xFF
|
||||
#define GPIO_SD0_IN_S 0
|
||||
|
||||
#define GPIO_SIGMADELTA1_REG (DR_REG_GPIO_SD_BASE + 0x0004)
|
||||
/* GPIO_SD1_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
|
||||
/*description: */
|
||||
#define GPIO_SD1_PRESCALE 0x000000FF
|
||||
#define GPIO_SD1_PRESCALE_M ((GPIO_SD1_PRESCALE_V)<<(GPIO_SD1_PRESCALE_S))
|
||||
#define GPIO_SD1_PRESCALE_V 0xFF
|
||||
#define GPIO_SD1_PRESCALE_S 8
|
||||
/* GPIO_SD1_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
|
||||
/*description: */
|
||||
#define GPIO_SD1_IN 0x000000FF
|
||||
#define GPIO_SD1_IN_M ((GPIO_SD1_IN_V)<<(GPIO_SD1_IN_S))
|
||||
#define GPIO_SD1_IN_V 0xFF
|
||||
#define GPIO_SD1_IN_S 0
|
||||
|
||||
#define GPIO_SIGMADELTA2_REG (DR_REG_GPIO_SD_BASE + 0x0008)
|
||||
/* GPIO_SD2_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
|
||||
/*description: */
|
||||
#define GPIO_SD2_PRESCALE 0x000000FF
|
||||
#define GPIO_SD2_PRESCALE_M ((GPIO_SD2_PRESCALE_V)<<(GPIO_SD2_PRESCALE_S))
|
||||
#define GPIO_SD2_PRESCALE_V 0xFF
|
||||
#define GPIO_SD2_PRESCALE_S 8
|
||||
/* GPIO_SD2_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
|
||||
/*description: */
|
||||
#define GPIO_SD2_IN 0x000000FF
|
||||
#define GPIO_SD2_IN_M ((GPIO_SD2_IN_V)<<(GPIO_SD2_IN_S))
|
||||
#define GPIO_SD2_IN_V 0xFF
|
||||
#define GPIO_SD2_IN_S 0
|
||||
|
||||
#define GPIO_SIGMADELTA3_REG (DR_REG_GPIO_SD_BASE + 0x000c)
|
||||
/* GPIO_SD3_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
|
||||
/*description: */
|
||||
#define GPIO_SD3_PRESCALE 0x000000FF
|
||||
#define GPIO_SD3_PRESCALE_M ((GPIO_SD3_PRESCALE_V)<<(GPIO_SD3_PRESCALE_S))
|
||||
#define GPIO_SD3_PRESCALE_V 0xFF
|
||||
#define GPIO_SD3_PRESCALE_S 8
|
||||
/* GPIO_SD3_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
|
||||
/*description: */
|
||||
#define GPIO_SD3_IN 0x000000FF
|
||||
#define GPIO_SD3_IN_M ((GPIO_SD3_IN_V)<<(GPIO_SD3_IN_S))
|
||||
#define GPIO_SD3_IN_V 0xFF
|
||||
#define GPIO_SD3_IN_S 0
|
||||
|
||||
#define GPIO_SIGMADELTA_CG_REG (DR_REG_GPIO_SD_BASE + 0x0020)
|
||||
/* GPIO_SD_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
|
||||
/*description: */
|
||||
#define GPIO_SD_CLK_EN (BIT(31))
|
||||
#define GPIO_SD_CLK_EN_M (BIT(31))
|
||||
#define GPIO_SD_CLK_EN_V 0x1
|
||||
#define GPIO_SD_CLK_EN_S 31
|
||||
|
||||
#define GPIO_SIGMADELTA_MISC_REG (DR_REG_GPIO_SD_BASE + 0x0024)
|
||||
/* GPIO_SPI_SWAP : R/W ;bitpos:[31] ;default: 1'h0 ; */
|
||||
/*description: */
|
||||
#define GPIO_SPI_SWAP (BIT(31))
|
||||
#define GPIO_SPI_SWAP_M (BIT(31))
|
||||
#define GPIO_SPI_SWAP_V 0x1
|
||||
#define GPIO_SPI_SWAP_S 31
|
||||
/* GPIO_FUNCTION_CLK_EN : R/W ;bitpos:[30] ;default: 1'd0 ; */
|
||||
/*description: */
|
||||
#define GPIO_FUNCTION_CLK_EN (BIT(30))
|
||||
#define GPIO_FUNCTION_CLK_EN_M (BIT(30))
|
||||
#define GPIO_FUNCTION_CLK_EN_V 0x1
|
||||
#define GPIO_FUNCTION_CLK_EN_S 30
|
||||
|
||||
#define GPIO_SIGMADELTA_VERSION_REG (DR_REG_GPIO_SD_BASE + 0x0028)
|
||||
/* GPIO_SD_DATE : R/W ;bitpos:[27:0] ;default: 28'h2006230 ; */
|
||||
/*description: */
|
||||
#define GPIO_SD_DATE 0x0FFFFFFF
|
||||
#define GPIO_SD_DATE_M ((GPIO_SD_DATE_V)<<(GPIO_SD_DATE_S))
|
||||
#define GPIO_SD_DATE_V 0xFFFFFFF
|
||||
#define GPIO_SD_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,56 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef struct gpio_sd_dev_t {
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t duty: 8;
|
||||
uint32_t prescale: 8;
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} channel[4];
|
||||
uint32_t reserved_10;
|
||||
uint32_t reserved_14;
|
||||
uint32_t reserved_18;
|
||||
uint32_t reserved_1c;
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t reserved0: 31;
|
||||
uint32_t clk_en: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} cg;
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t reserved0: 30;
|
||||
uint32_t function_clk_en: 1;
|
||||
uint32_t spi_swap: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} misc;
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t date: 28;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} version;
|
||||
} gpio_sd_dev_t;
|
||||
|
||||
extern gpio_sd_dev_t SDM;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,437 +0,0 @@
|
||||
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_GPIO_STRUCT_H_
|
||||
#define _SOC_GPIO_STRUCT_H_
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct gpio_dev_s {
|
||||
uint32_t bt_select; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t data: 26;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} out;
|
||||
union {
|
||||
struct {
|
||||
uint32_t out_w1ts: 26;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} out_w1ts;
|
||||
union {
|
||||
struct {
|
||||
uint32_t out_w1tc: 26;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} out_w1tc;
|
||||
uint32_t reserved_10;
|
||||
uint32_t reserved_14;
|
||||
uint32_t reserved_18;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sel: 8;
|
||||
uint32_t reserved8: 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} sdio_select;
|
||||
union {
|
||||
struct {
|
||||
uint32_t data: 26;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} enable;
|
||||
union {
|
||||
struct {
|
||||
uint32_t enable_w1ts:26;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} enable_w1ts;
|
||||
union {
|
||||
struct {
|
||||
uint32_t enable_w1tc:26;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} enable_w1tc;
|
||||
uint32_t reserved_2c;
|
||||
uint32_t reserved_30;
|
||||
uint32_t reserved_34;
|
||||
union {
|
||||
struct {
|
||||
uint32_t strapping: 16;
|
||||
uint32_t reserved16:16;
|
||||
};
|
||||
uint32_t val;
|
||||
} strap;
|
||||
union {
|
||||
struct {
|
||||
uint32_t data: 26;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} in;
|
||||
uint32_t reserved_40;
|
||||
union {
|
||||
struct {
|
||||
uint32_t intr_st: 26;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} status;
|
||||
union {
|
||||
struct {
|
||||
uint32_t status_w1ts:26;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} status_w1ts;
|
||||
union {
|
||||
struct {
|
||||
uint32_t status_w1tc:26;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} status_w1tc;
|
||||
uint32_t reserved_50;
|
||||
uint32_t reserved_54;
|
||||
uint32_t reserved_58;
|
||||
union {
|
||||
struct {
|
||||
uint32_t intr: 26;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} pcpu_int;
|
||||
union {
|
||||
struct {
|
||||
uint32_t intr: 26;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} pcpu_nmi_int;
|
||||
union {
|
||||
struct {
|
||||
uint32_t intr: 26;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} cpusdio_int;
|
||||
uint32_t reserved_68;
|
||||
uint32_t reserved_6c;
|
||||
uint32_t reserved_70;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sync2_bypass: 2;
|
||||
uint32_t pad_driver: 1;
|
||||
uint32_t sync1_bypass: 2;
|
||||
uint32_t reserved5: 2;
|
||||
uint32_t int_type: 3;
|
||||
uint32_t wakeup_enable: 1;
|
||||
uint32_t config: 2;
|
||||
uint32_t int_ena: 5;
|
||||
uint32_t reserved18: 14;
|
||||
};
|
||||
uint32_t val;
|
||||
} pin[26];
|
||||
uint32_t reserved_dc;
|
||||
uint32_t reserved_e0;
|
||||
uint32_t reserved_e4;
|
||||
uint32_t reserved_e8;
|
||||
uint32_t reserved_ec;
|
||||
uint32_t reserved_f0;
|
||||
uint32_t reserved_f4;
|
||||
uint32_t reserved_f8;
|
||||
uint32_t reserved_fc;
|
||||
uint32_t reserved_100;
|
||||
uint32_t reserved_104;
|
||||
uint32_t reserved_108;
|
||||
uint32_t reserved_10c;
|
||||
uint32_t reserved_110;
|
||||
uint32_t reserved_114;
|
||||
uint32_t reserved_118;
|
||||
uint32_t reserved_11c;
|
||||
uint32_t reserved_120;
|
||||
uint32_t reserved_124;
|
||||
uint32_t reserved_128;
|
||||
uint32_t reserved_12c;
|
||||
uint32_t reserved_130;
|
||||
uint32_t reserved_134;
|
||||
uint32_t reserved_138;
|
||||
uint32_t reserved_13c;
|
||||
uint32_t reserved_140;
|
||||
uint32_t reserved_144;
|
||||
uint32_t reserved_148;
|
||||
union {
|
||||
struct {
|
||||
uint32_t intr_st_next: 26;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} status_next;
|
||||
uint32_t reserved_150;
|
||||
union {
|
||||
struct {
|
||||
uint32_t func_sel: 5;
|
||||
uint32_t sig_in_inv: 1;
|
||||
uint32_t sig_in_sel: 1;
|
||||
uint32_t reserved7: 25;
|
||||
};
|
||||
uint32_t val;
|
||||
} func_in_sel_cfg[128];
|
||||
uint32_t reserved_354;
|
||||
uint32_t reserved_358;
|
||||
uint32_t reserved_35c;
|
||||
uint32_t reserved_360;
|
||||
uint32_t reserved_364;
|
||||
uint32_t reserved_368;
|
||||
uint32_t reserved_36c;
|
||||
uint32_t reserved_370;
|
||||
uint32_t reserved_374;
|
||||
uint32_t reserved_378;
|
||||
uint32_t reserved_37c;
|
||||
uint32_t reserved_380;
|
||||
uint32_t reserved_384;
|
||||
uint32_t reserved_388;
|
||||
uint32_t reserved_38c;
|
||||
uint32_t reserved_390;
|
||||
uint32_t reserved_394;
|
||||
uint32_t reserved_398;
|
||||
uint32_t reserved_39c;
|
||||
uint32_t reserved_3a0;
|
||||
uint32_t reserved_3a4;
|
||||
uint32_t reserved_3a8;
|
||||
uint32_t reserved_3ac;
|
||||
uint32_t reserved_3b0;
|
||||
uint32_t reserved_3b4;
|
||||
uint32_t reserved_3b8;
|
||||
uint32_t reserved_3bc;
|
||||
uint32_t reserved_3c0;
|
||||
uint32_t reserved_3c4;
|
||||
uint32_t reserved_3c8;
|
||||
uint32_t reserved_3cc;
|
||||
uint32_t reserved_3d0;
|
||||
uint32_t reserved_3d4;
|
||||
uint32_t reserved_3d8;
|
||||
uint32_t reserved_3dc;
|
||||
uint32_t reserved_3e0;
|
||||
uint32_t reserved_3e4;
|
||||
uint32_t reserved_3e8;
|
||||
uint32_t reserved_3ec;
|
||||
uint32_t reserved_3f0;
|
||||
uint32_t reserved_3f4;
|
||||
uint32_t reserved_3f8;
|
||||
uint32_t reserved_3fc;
|
||||
uint32_t reserved_400;
|
||||
uint32_t reserved_404;
|
||||
uint32_t reserved_408;
|
||||
uint32_t reserved_40c;
|
||||
uint32_t reserved_410;
|
||||
uint32_t reserved_414;
|
||||
uint32_t reserved_418;
|
||||
uint32_t reserved_41c;
|
||||
uint32_t reserved_420;
|
||||
uint32_t reserved_424;
|
||||
uint32_t reserved_428;
|
||||
uint32_t reserved_42c;
|
||||
uint32_t reserved_430;
|
||||
uint32_t reserved_434;
|
||||
uint32_t reserved_438;
|
||||
uint32_t reserved_43c;
|
||||
uint32_t reserved_440;
|
||||
uint32_t reserved_444;
|
||||
uint32_t reserved_448;
|
||||
uint32_t reserved_44c;
|
||||
uint32_t reserved_450;
|
||||
uint32_t reserved_454;
|
||||
uint32_t reserved_458;
|
||||
uint32_t reserved_45c;
|
||||
uint32_t reserved_460;
|
||||
uint32_t reserved_464;
|
||||
uint32_t reserved_468;
|
||||
uint32_t reserved_46c;
|
||||
uint32_t reserved_470;
|
||||
uint32_t reserved_474;
|
||||
uint32_t reserved_478;
|
||||
uint32_t reserved_47c;
|
||||
uint32_t reserved_480;
|
||||
uint32_t reserved_484;
|
||||
uint32_t reserved_488;
|
||||
uint32_t reserved_48c;
|
||||
uint32_t reserved_490;
|
||||
uint32_t reserved_494;
|
||||
uint32_t reserved_498;
|
||||
uint32_t reserved_49c;
|
||||
uint32_t reserved_4a0;
|
||||
uint32_t reserved_4a4;
|
||||
uint32_t reserved_4a8;
|
||||
uint32_t reserved_4ac;
|
||||
uint32_t reserved_4b0;
|
||||
uint32_t reserved_4b4;
|
||||
uint32_t reserved_4b8;
|
||||
uint32_t reserved_4bc;
|
||||
uint32_t reserved_4c0;
|
||||
uint32_t reserved_4c4;
|
||||
uint32_t reserved_4c8;
|
||||
uint32_t reserved_4cc;
|
||||
uint32_t reserved_4d0;
|
||||
uint32_t reserved_4d4;
|
||||
uint32_t reserved_4d8;
|
||||
uint32_t reserved_4dc;
|
||||
uint32_t reserved_4e0;
|
||||
uint32_t reserved_4e4;
|
||||
uint32_t reserved_4e8;
|
||||
uint32_t reserved_4ec;
|
||||
uint32_t reserved_4f0;
|
||||
uint32_t reserved_4f4;
|
||||
uint32_t reserved_4f8;
|
||||
uint32_t reserved_4fc;
|
||||
uint32_t reserved_500;
|
||||
uint32_t reserved_504;
|
||||
uint32_t reserved_508;
|
||||
uint32_t reserved_50c;
|
||||
uint32_t reserved_510;
|
||||
uint32_t reserved_514;
|
||||
uint32_t reserved_518;
|
||||
uint32_t reserved_51c;
|
||||
uint32_t reserved_520;
|
||||
uint32_t reserved_524;
|
||||
uint32_t reserved_528;
|
||||
uint32_t reserved_52c;
|
||||
uint32_t reserved_530;
|
||||
uint32_t reserved_534;
|
||||
uint32_t reserved_538;
|
||||
uint32_t reserved_53c;
|
||||
uint32_t reserved_540;
|
||||
uint32_t reserved_544;
|
||||
uint32_t reserved_548;
|
||||
uint32_t reserved_54c;
|
||||
uint32_t reserved_550;
|
||||
union {
|
||||
struct {
|
||||
uint32_t func_sel: 8;
|
||||
uint32_t inv_sel: 1;
|
||||
uint32_t oen_sel: 1;
|
||||
uint32_t oen_inv_sel: 1;
|
||||
uint32_t reserved11: 21;
|
||||
};
|
||||
uint32_t val;
|
||||
} func_out_sel_cfg[26];
|
||||
uint32_t reserved_5bc;
|
||||
uint32_t reserved_5c0;
|
||||
uint32_t reserved_5c4;
|
||||
uint32_t reserved_5c8;
|
||||
uint32_t reserved_5cc;
|
||||
uint32_t reserved_5d0;
|
||||
uint32_t reserved_5d4;
|
||||
uint32_t reserved_5d8;
|
||||
uint32_t reserved_5dc;
|
||||
uint32_t reserved_5e0;
|
||||
uint32_t reserved_5e4;
|
||||
uint32_t reserved_5e8;
|
||||
uint32_t reserved_5ec;
|
||||
uint32_t reserved_5f0;
|
||||
uint32_t reserved_5f4;
|
||||
uint32_t reserved_5f8;
|
||||
uint32_t reserved_5fc;
|
||||
uint32_t reserved_600;
|
||||
uint32_t reserved_604;
|
||||
uint32_t reserved_608;
|
||||
uint32_t reserved_60c;
|
||||
uint32_t reserved_610;
|
||||
uint32_t reserved_614;
|
||||
uint32_t reserved_618;
|
||||
uint32_t reserved_61c;
|
||||
uint32_t reserved_620;
|
||||
uint32_t reserved_624;
|
||||
uint32_t reserved_628;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_en: 1;
|
||||
uint32_t reserved1: 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} clock_gate;
|
||||
uint32_t reserved_630;
|
||||
uint32_t reserved_634;
|
||||
uint32_t reserved_638;
|
||||
uint32_t reserved_63c;
|
||||
uint32_t reserved_640;
|
||||
uint32_t reserved_644;
|
||||
uint32_t reserved_648;
|
||||
uint32_t reserved_64c;
|
||||
uint32_t reserved_650;
|
||||
uint32_t reserved_654;
|
||||
uint32_t reserved_658;
|
||||
uint32_t reserved_65c;
|
||||
uint32_t reserved_660;
|
||||
uint32_t reserved_664;
|
||||
uint32_t reserved_668;
|
||||
uint32_t reserved_66c;
|
||||
uint32_t reserved_670;
|
||||
uint32_t reserved_674;
|
||||
uint32_t reserved_678;
|
||||
uint32_t reserved_67c;
|
||||
uint32_t reserved_680;
|
||||
uint32_t reserved_684;
|
||||
uint32_t reserved_688;
|
||||
uint32_t reserved_68c;
|
||||
uint32_t reserved_690;
|
||||
uint32_t reserved_694;
|
||||
uint32_t reserved_698;
|
||||
uint32_t reserved_69c;
|
||||
uint32_t reserved_6a0;
|
||||
uint32_t reserved_6a4;
|
||||
uint32_t reserved_6a8;
|
||||
uint32_t reserved_6ac;
|
||||
uint32_t reserved_6b0;
|
||||
uint32_t reserved_6b4;
|
||||
uint32_t reserved_6b8;
|
||||
uint32_t reserved_6bc;
|
||||
uint32_t reserved_6c0;
|
||||
uint32_t reserved_6c4;
|
||||
uint32_t reserved_6c8;
|
||||
uint32_t reserved_6cc;
|
||||
uint32_t reserved_6d0;
|
||||
uint32_t reserved_6d4;
|
||||
uint32_t reserved_6d8;
|
||||
uint32_t reserved_6dc;
|
||||
uint32_t reserved_6e0;
|
||||
uint32_t reserved_6e4;
|
||||
uint32_t reserved_6e8;
|
||||
uint32_t reserved_6ec;
|
||||
uint32_t reserved_6f0;
|
||||
uint32_t reserved_6f4;
|
||||
uint32_t reserved_6f8;
|
||||
union {
|
||||
struct {
|
||||
uint32_t date: 28;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} date;
|
||||
} gpio_dev_t;
|
||||
extern gpio_dev_t GPIO;
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _SOC_GPIO_STRUCT_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,368 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#ifndef _SOC_I2C_STRUCT_H_
|
||||
#define _SOC_I2C_STRUCT_H_
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#include "soc.h"
|
||||
|
||||
typedef volatile struct i2c_dev_s {
|
||||
union {
|
||||
struct {
|
||||
uint32_t period : 9;
|
||||
uint32_t reserved9 : 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} scl_low_period;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sda_force_out : 1;
|
||||
uint32_t scl_force_out : 1;
|
||||
uint32_t sample_scl_level : 1;
|
||||
uint32_t rx_full_ack_level : 1;
|
||||
uint32_t ms_mode : 1;
|
||||
uint32_t trans_start : 1;
|
||||
uint32_t tx_lsb_first : 1;
|
||||
uint32_t rx_lsb_first : 1;
|
||||
uint32_t clk_en : 1;
|
||||
uint32_t arbitration_en : 1;
|
||||
uint32_t fsm_rst : 1;
|
||||
uint32_t conf_upgate : 1;
|
||||
uint32_t slv_tx_auto_start_en : 1;
|
||||
uint32_t addr_10bit_rw_check_en : 1;
|
||||
uint32_t addr_broadcasting_en : 1;
|
||||
uint32_t reserved15 : 17;
|
||||
};
|
||||
uint32_t val;
|
||||
} ctr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t resp_rec : 1;
|
||||
uint32_t slave_rw : 1;
|
||||
uint32_t reserved2 : 1;
|
||||
uint32_t arb_lost : 1;
|
||||
uint32_t bus_busy : 1;
|
||||
uint32_t slave_addressed : 1;
|
||||
uint32_t reserved6 : 1;
|
||||
uint32_t reserved7 : 1;
|
||||
uint32_t rx_fifo_cnt : 6;
|
||||
uint32_t stretch_cause : 2;
|
||||
uint32_t reserved16 : 2;
|
||||
uint32_t tx_fifo_cnt : 6;
|
||||
uint32_t scl_main_state_last : 3;
|
||||
uint32_t reserved27 : 1;
|
||||
uint32_t scl_state_last : 3;
|
||||
uint32_t reserved31 : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} sr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t time_out_value : 5;
|
||||
uint32_t time_out_en : 1;
|
||||
uint32_t reserved6 : 26;
|
||||
};
|
||||
uint32_t val;
|
||||
} timeout;
|
||||
union {
|
||||
struct {
|
||||
uint32_t addr : 15;
|
||||
uint32_t reserved15 : 16;
|
||||
uint32_t en_10bit : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} slave_addr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_fifo_raddr : 5;
|
||||
uint32_t rx_fifo_waddr : 5;
|
||||
uint32_t tx_fifo_raddr : 5;
|
||||
uint32_t tx_fifo_waddr : 5;
|
||||
uint32_t reserved20 : 1;
|
||||
uint32_t reserved21 : 1;
|
||||
uint32_t slave_rw_point : 8;
|
||||
uint32_t reserved30 : 2;
|
||||
};
|
||||
uint32_t val;
|
||||
} fifo_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_fifo_wm_thrhd : 5;
|
||||
uint32_t tx_fifo_wm_thrhd : 5;
|
||||
uint32_t nonfifo_en : 1;
|
||||
uint32_t fifo_addr_cfg_en : 1;
|
||||
uint32_t rx_fifo_rst : 1;
|
||||
uint32_t tx_fifo_rst : 1;
|
||||
uint32_t fifo_prt_en : 1;
|
||||
uint32_t reserved15 : 5;
|
||||
uint32_t reserved20 : 6;
|
||||
uint32_t reserved26 : 1;
|
||||
uint32_t reserved27 : 5;
|
||||
};
|
||||
uint32_t val;
|
||||
} fifo_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t data : 8;
|
||||
uint32_t reserved8 : 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} fifo_data;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_fifo_wm : 1;
|
||||
uint32_t tx_fifo_wm : 1;
|
||||
uint32_t rx_fifo_ovf : 1;
|
||||
uint32_t end_detect : 1;
|
||||
uint32_t byte_trans_done : 1;
|
||||
uint32_t arbitration_lost : 1;
|
||||
uint32_t mst_tx_fifo_udf : 1;
|
||||
uint32_t trans_complete : 1;
|
||||
uint32_t time_out : 1;
|
||||
uint32_t trans_start : 1;
|
||||
uint32_t nack : 1;
|
||||
uint32_t tx_fifo_ovf : 1;
|
||||
uint32_t rx_fifo_udf : 1;
|
||||
uint32_t scl_st_to : 1;
|
||||
uint32_t scl_main_st_to : 1;
|
||||
uint32_t det_start : 1;
|
||||
uint32_t slave_stretch : 1;
|
||||
uint32_t general_call : 1;
|
||||
uint32_t reserved18 : 14;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_fifo_wm : 1;
|
||||
uint32_t tx_fifo_wm : 1;
|
||||
uint32_t rx_fifo_ovf : 1;
|
||||
uint32_t end_detect : 1;
|
||||
uint32_t byte_trans_done : 1;
|
||||
uint32_t arbitration_lost : 1;
|
||||
uint32_t mst_tx_fifo_udf : 1;
|
||||
uint32_t trans_complete : 1;
|
||||
uint32_t time_out : 1;
|
||||
uint32_t trans_start : 1;
|
||||
uint32_t nack : 1;
|
||||
uint32_t tx_fifo_ovf : 1;
|
||||
uint32_t rx_fifo_udf : 1;
|
||||
uint32_t scl_st_to : 1;
|
||||
uint32_t scl_main_st_to : 1;
|
||||
uint32_t det_start : 1;
|
||||
uint32_t slave_stretch : 1;
|
||||
uint32_t general_call : 1;
|
||||
uint32_t reserved18 : 14;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_fifo_wm : 1;
|
||||
uint32_t tx_fifo_wm : 1;
|
||||
uint32_t rx_fifo_ovf : 1;
|
||||
uint32_t end_detect : 1;
|
||||
uint32_t byte_trans_done : 1;
|
||||
uint32_t arbitration_lost : 1;
|
||||
uint32_t mst_tx_fifo_udf : 1;
|
||||
uint32_t trans_complete : 1;
|
||||
uint32_t time_out : 1;
|
||||
uint32_t trans_start : 1;
|
||||
uint32_t nack : 1;
|
||||
uint32_t tx_fifo_ovf : 1;
|
||||
uint32_t rx_fifo_udf : 1;
|
||||
uint32_t scl_st_to : 1;
|
||||
uint32_t scl_main_st_to : 1;
|
||||
uint32_t det_start : 1;
|
||||
uint32_t slave_stretch : 1;
|
||||
uint32_t general_call : 1;
|
||||
uint32_t reserved18 : 14;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_fifo_wm : 1;
|
||||
uint32_t tx_fifo_wm : 1;
|
||||
uint32_t rx_fifo_ovf : 1;
|
||||
uint32_t end_detect : 1;
|
||||
uint32_t byte_trans_done : 1;
|
||||
uint32_t arbitration_lost : 1;
|
||||
uint32_t mst_tx_fifo_udf : 1;
|
||||
uint32_t trans_complete : 1;
|
||||
uint32_t time_out : 1;
|
||||
uint32_t trans_start : 1;
|
||||
uint32_t nack : 1;
|
||||
uint32_t tx_fifo_ovf : 1;
|
||||
uint32_t rx_fifo_udf : 1;
|
||||
uint32_t scl_st_to : 1;
|
||||
uint32_t scl_main_st_to : 1;
|
||||
uint32_t det_start : 1;
|
||||
uint32_t slave_stretch : 1;
|
||||
uint32_t general_call : 1;
|
||||
uint32_t reserved18 : 14;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_status;
|
||||
union {
|
||||
struct {
|
||||
uint32_t time : 9;
|
||||
uint32_t reserved9 : 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} sda_hold;
|
||||
union {
|
||||
struct {
|
||||
uint32_t time : 9;
|
||||
uint32_t reserved9 : 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} sda_sample;
|
||||
union {
|
||||
struct {
|
||||
uint32_t period : 9;
|
||||
uint32_t scl_wait_high_period : 7;
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} scl_high_period;
|
||||
uint32_t reserved_3c;
|
||||
union {
|
||||
struct {
|
||||
uint32_t time : 9;
|
||||
uint32_t reserved9 : 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} scl_start_hold;
|
||||
union {
|
||||
struct {
|
||||
uint32_t time : 9;
|
||||
uint32_t reserved9 : 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} scl_rstart_setup;
|
||||
union {
|
||||
struct {
|
||||
uint32_t time : 9;
|
||||
uint32_t reserved9 : 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} scl_stop_hold;
|
||||
union {
|
||||
struct {
|
||||
uint32_t time : 9;
|
||||
uint32_t reserved9 : 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} scl_stop_setup;
|
||||
union {
|
||||
struct {
|
||||
uint32_t scl_thres : 4;
|
||||
uint32_t sda_thres : 4;
|
||||
uint32_t scl_en : 1;
|
||||
uint32_t sda_en : 1;
|
||||
uint32_t reserved10 : 22;
|
||||
};
|
||||
uint32_t val;
|
||||
} filter_cfg;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sclk_div_num : 8;
|
||||
uint32_t sclk_div_a : 6;
|
||||
uint32_t sclk_div_b : 6;
|
||||
uint32_t sclk_sel : 1;
|
||||
uint32_t sclk_active : 1;
|
||||
uint32_t reserved22 : 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} clk_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t command0 : 14;
|
||||
uint32_t reserved14 : 17;
|
||||
uint32_t command0_done : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} command[8];
|
||||
union {
|
||||
struct {
|
||||
uint32_t scl_st_to : 5; /*no more than 23*/
|
||||
uint32_t reserved5 : 27;
|
||||
};
|
||||
uint32_t val;
|
||||
} scl_st_time_out;
|
||||
union {
|
||||
struct {
|
||||
uint32_t scl_main_st_to : 5; /*no more than 23*/
|
||||
uint32_t reserved5 : 27;
|
||||
};
|
||||
uint32_t val;
|
||||
} scl_main_st_time_out;
|
||||
union {
|
||||
struct {
|
||||
uint32_t scl_rst_slv_en : 1;
|
||||
uint32_t scl_rst_slv_num : 5;
|
||||
uint32_t scl_pd_en : 1;
|
||||
uint32_t sda_pd_en : 1;
|
||||
uint32_t reserved8 : 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} scl_sp_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t stretch_protect_num : 10;
|
||||
uint32_t slave_scl_stretch_en : 1;
|
||||
uint32_t slave_scl_stretch_clr : 1;
|
||||
uint32_t slave_byte_ack_ctl_en : 1;
|
||||
uint32_t slave_byte_ack_level : 1;
|
||||
uint32_t reserved14 : 18;
|
||||
};
|
||||
uint32_t val;
|
||||
} scl_stretch_conf;
|
||||
uint32_t reserved_88;
|
||||
uint32_t reserved_8c;
|
||||
uint32_t reserved_90;
|
||||
uint32_t reserved_94;
|
||||
uint32_t reserved_98;
|
||||
uint32_t reserved_9c;
|
||||
uint32_t reserved_a0;
|
||||
uint32_t reserved_a4;
|
||||
uint32_t reserved_a8;
|
||||
uint32_t reserved_ac;
|
||||
uint32_t reserved_b0;
|
||||
uint32_t reserved_b4;
|
||||
uint32_t reserved_b8;
|
||||
uint32_t reserved_bc;
|
||||
uint32_t reserved_c0;
|
||||
uint32_t reserved_c4;
|
||||
uint32_t reserved_c8;
|
||||
uint32_t reserved_cc;
|
||||
uint32_t reserved_d0;
|
||||
uint32_t reserved_d4;
|
||||
uint32_t reserved_d8;
|
||||
uint32_t reserved_dc;
|
||||
uint32_t reserved_e0;
|
||||
uint32_t reserved_e4;
|
||||
uint32_t reserved_e8;
|
||||
uint32_t reserved_ec;
|
||||
uint32_t reserved_f0;
|
||||
uint32_t reserved_f4;
|
||||
uint32_t date;
|
||||
uint32_t reserved_fc;
|
||||
uint32_t txfifo_mem[32];
|
||||
uint32_t rxfifo_mem[32];
|
||||
} i2c_dev_t;
|
||||
extern i2c_dev_t I2C0;
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /*_SOC_I2C_STRUCT_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,328 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct i2s_dev_s {
|
||||
uint32_t reserved_0;
|
||||
uint32_t reserved_4;
|
||||
uint32_t reserved_8;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_done: 1; /*The raw interrupt status bit for the i2s_rx_done_int interrupt*/
|
||||
uint32_t tx_done: 1; /*The raw interrupt status bit for the i2s_tx_done_int interrupt*/
|
||||
uint32_t rx_hung: 1; /*The raw interrupt status bit for the i2s_rx_hung_int interrupt*/
|
||||
uint32_t tx_hung: 1; /*The raw interrupt status bit for the i2s_tx_hung_int interrupt*/
|
||||
uint32_t reserved4: 28; /*Reserve*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_done: 1; /*The masked interrupt status bit for the i2s_rx_done_int interrupt*/
|
||||
uint32_t tx_done: 1; /*The masked interrupt status bit for the i2s_tx_done_int interrupt*/
|
||||
uint32_t rx_hung: 1; /*The masked interrupt status bit for the i2s_rx_hung_int interrupt*/
|
||||
uint32_t tx_hung: 1; /*The masked interrupt status bit for the i2s_tx_hung_int interrupt*/
|
||||
uint32_t reserved4: 28; /*Reserve*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_done: 1; /*The interrupt enable bit for the i2s_rx_done_int interrupt*/
|
||||
uint32_t tx_done: 1; /*The interrupt enable bit for the i2s_tx_done_int interrupt*/
|
||||
uint32_t rx_hung: 1; /*The interrupt enable bit for the i2s_rx_hung_int interrupt*/
|
||||
uint32_t tx_hung: 1; /*The interrupt enable bit for the i2s_tx_hung_int interrupt*/
|
||||
uint32_t reserved4: 28; /*Reserve*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_done: 1; /*Set this bit to clear the i2s_rx_done_int interrupt*/
|
||||
uint32_t tx_done: 1; /*Set this bit to clear the i2s_tx_done_int interrupt*/
|
||||
uint32_t rx_hung: 1; /*Set this bit to clear the i2s_rx_hung_int interrupt*/
|
||||
uint32_t tx_hung: 1; /*Set this bit to clear the i2s_tx_hung_int interrupt*/
|
||||
uint32_t reserved4: 28; /*Reserve*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_clr;
|
||||
uint32_t reserved_1c;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_reset: 1; /*Set this bit to reset receiver*/
|
||||
uint32_t rx_fifo_reset: 1; /*Set this bit to reset Rx AFIFO*/
|
||||
uint32_t rx_start: 1; /*Set this bit to start receiving data*/
|
||||
uint32_t rx_slave_mod: 1; /*Set this bit to enable slave receiver mode*/
|
||||
uint32_t reserved4: 1; /*Reserved*/
|
||||
uint32_t rx_mono: 1; /*Set this bit to enable receiver in mono mode*/
|
||||
uint32_t reserved6: 1;
|
||||
uint32_t rx_big_endian: 1; /*I2S Rx byte endian 1: low addr value to high addr. 0: low addr with low addr value.*/
|
||||
uint32_t rx_update: 1; /*Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done.*/
|
||||
uint32_t rx_mono_fst_vld: 1; /*1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode.*/
|
||||
uint32_t rx_pcm_conf: 2; /*I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress 1 (ltoa) : A-Law compress 2 (utol) : u-Law decompress 3 (ltou) : u-Law compress. &*/
|
||||
uint32_t rx_pcm_bypass: 1; /*Set this bit to bypass Compress/Decompress module for received data.*/
|
||||
uint32_t rx_stop_mode: 2; /*0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.*/
|
||||
uint32_t rx_left_align: 1; /*1: I2S RX left alignment mode. 0: I2S RX right alignment mode.*/
|
||||
uint32_t rx_24_fill_en: 1; /*1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.*/
|
||||
uint32_t rx_ws_idle_pol: 1; /*0: WS should be 0 when receiving left channel data and WS is 1in right channel. 1: WS should be 1 when receiving left channel data and WS is 0in right channel.*/
|
||||
uint32_t rx_bit_order: 1; /*I2S Rx bit endian. 1:small endian the LSB is received first. 0:big endian the MSB is received first.*/
|
||||
uint32_t rx_tdm_en: 1; /*1: Enable I2S TDM Rx mode . 0: Disable.*/
|
||||
uint32_t rx_pdm_en: 1; /*1: Enable I2S PDM Rx mode . 0: Disable.*/
|
||||
uint32_t reserved23: 11; /*Reserve*/
|
||||
};
|
||||
uint32_t val;
|
||||
} rx_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tx_reset: 1; /*Set this bit to reset transmitter*/
|
||||
uint32_t tx_fifo_reset: 1; /*Set this bit to reset Tx AFIFO*/
|
||||
uint32_t tx_start: 1; /*Set this bit to start transmitting data*/
|
||||
uint32_t tx_slave_mod: 1; /*Set this bit to enable slave transmitter mode*/
|
||||
uint32_t reserved4: 1; /*Reserved*/
|
||||
uint32_t tx_mono: 1; /*Set this bit to enable transmitter in mono mode*/
|
||||
uint32_t tx_chan_equal: 1; /*1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.*/
|
||||
uint32_t tx_big_endian: 1; /*I2S Tx byte endian 1: low addr value to high addr. 0: low addr with low addr value.*/
|
||||
uint32_t tx_update: 1; /*Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done.*/
|
||||
uint32_t tx_mono_fst_vld: 1; /*1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode.*/
|
||||
uint32_t tx_pcm_conf: 2; /*I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress 1 (ltoa) : A-Law compress 2 (utol) : u-Law decompress 3 (ltou) : u-Law compress. &*/
|
||||
uint32_t tx_pcm_bypass: 1; /*Set this bit to bypass Compress/Decompress module for transmitted data.*/
|
||||
uint32_t tx_stop_en: 1; /*Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy*/
|
||||
uint32_t reserved14: 1;
|
||||
uint32_t tx_left_align: 1; /*1: I2S TX left alignment mode. 0: I2S TX right alignment mode.*/
|
||||
uint32_t tx_24_fill_en: 1; /*1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode*/
|
||||
uint32_t tx_ws_idle_pol: 1; /*0: WS should be 0 when sending left channel data and WS is 1in right channel. 1: WS should be 1 when sending left channel data and WS is 0in right channel.*/
|
||||
uint32_t tx_bit_order: 1; /*I2S Tx bit endian. 1:small endian the LSB is sent first. 0:big endian the MSB is sent first.*/
|
||||
uint32_t tx_tdm_en: 1; /*1: Enable I2S TDM Tx mode . 0: Disable.*/
|
||||
uint32_t tx_pdm_en: 1; /*1: Enable I2S PDM Tx mode . 0: Disable.*/
|
||||
uint32_t reserved21: 3; /*Reserved*/
|
||||
uint32_t tx_chan_mod: 3; /*I2S transmitter channel mode configuration bits.*/
|
||||
uint32_t sig_loopback: 1; /*Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals.*/
|
||||
uint32_t reserved28: 4; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} tx_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_tdm_ws_width: 7; /*The width of rx_ws_out in TDM mode is (reg_rx_tdm_ws_width[6:0] +1) * T_bck*/
|
||||
uint32_t rx_bck_div_num: 6; /*Bit clock configuration bits in receiver mode.*/
|
||||
uint32_t rx_bits_mod: 5; /*Set the bits to configure bit length of I2S receiver channel.*/
|
||||
uint32_t rx_half_sample_bits: 6; /*I2S Rx half sample bits -1.*/
|
||||
uint32_t rx_tdm_chan_bits: 5; /*The Rx bit number for each channel minus 1in TDM mode.*/
|
||||
uint32_t rx_msb_shift: 1; /*Set this bit to enable receiver in Phillips standard mode*/
|
||||
uint32_t reserved30: 2; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} rx_conf1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tx_tdm_ws_width: 7; /*The width of tx_ws_out in TDM mode is (reg_tx_tdm_ws_width[6:0] +1) * T_bck*/
|
||||
uint32_t tx_bck_div_num: 6; /*Bit clock configuration bits in transmitter mode.*/
|
||||
uint32_t tx_bits_mod: 5; /*Set the bits to configure bit length of I2S transmitter channel.*/
|
||||
uint32_t tx_half_sample_bits: 6; /*I2S Tx half sample bits -1.*/
|
||||
uint32_t tx_tdm_chan_bits: 5; /*The Tx bit number for each channel minus 1in TDM mode.*/
|
||||
uint32_t tx_msb_shift: 1; /*Set this bit to enable transmitter in Phillips standard mode*/
|
||||
uint32_t tx_bck_no_dly: 1; /*1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode.*/
|
||||
uint32_t reserved31: 1; /* Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} tx_conf1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_clkm_div_num: 8; /*Integral I2S clock divider value*/
|
||||
uint32_t reserved8: 18; /*Reserved*/
|
||||
uint32_t rx_clk_active: 1; /*I2S Rx module clock enable signal.*/
|
||||
uint32_t rx_clk_sel: 2; /*Select I2S Rx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.*/
|
||||
uint32_t mclk_sel: 1; /*0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT.*/
|
||||
uint32_t reserved30: 2; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} rx_clkm_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tx_clkm_div_num: 8; /*Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2 z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2 z * [n-div + x * (n+1)-div] + y * (n+1)-div.*/
|
||||
uint32_t reserved8: 18; /*Reserved*/
|
||||
uint32_t tx_clk_active: 1; /*I2S Tx module clock enable signal.*/
|
||||
uint32_t tx_clk_sel: 2; /*Select I2S Tx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.*/
|
||||
uint32_t clk_en: 1; /*Set this bit to enable clk gate*/
|
||||
uint32_t reserved30: 2; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} tx_clkm_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_clkm_div_z: 9; /*For b <= a/2 the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2 the value of I2S_RX_CLKM_DIV_Z is (a-b).*/
|
||||
uint32_t rx_clkm_div_y: 9; /*For b <= a/2 the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2 the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)).*/
|
||||
uint32_t rx_clkm_div_x: 9; /*For b <= a/2 the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2 the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.*/
|
||||
uint32_t rx_clkm_div_yn1: 1; /*For b <= a/2 the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2 the value of I2S_RX_CLKM_DIV_YN1 is 1.*/
|
||||
uint32_t reserved28: 4; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} rx_clkm_div_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tx_clkm_div_z: 9; /*For b <= a/2 the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2 the value of I2S_TX_CLKM_DIV_Z is (a-b).*/
|
||||
uint32_t tx_clkm_div_y: 9; /*For b <= a/2 the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2 the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)).*/
|
||||
uint32_t tx_clkm_div_x: 9; /*For b <= a/2 the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2 the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.*/
|
||||
uint32_t tx_clkm_div_yn1: 1; /*For b <= a/2 the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2 the value of I2S_TX_CLKM_DIV_YN1 is 1.*/
|
||||
uint32_t reserved28: 4; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} tx_clkm_div_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tx_pdm_hp_bypass : 1; /*I2S TX PDM bypass hp filter or not. The option has been removed.*/
|
||||
uint32_t tx_pdm_sinc_osr2 : 4; /*I2S TX PDM OSR2 value*/
|
||||
uint32_t tx_pdm_prescale : 8; /*I2S TX PDM prescale for sigmadelta*/
|
||||
uint32_t tx_pdm_hp_in_shift : 2; /*I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4*/
|
||||
uint32_t tx_pdm_lp_in_shift : 2; /*I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4*/
|
||||
uint32_t tx_pdm_sinc_in_shift : 2; /*I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4*/
|
||||
uint32_t tx_pdm_sigmadelta_in_shift : 2; /*I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4*/
|
||||
uint32_t tx_pdm_sigmadelta_dither2 : 1; /*I2S TX PDM sigmadelta dither2 value*/
|
||||
uint32_t tx_pdm_sigmadelta_dither : 1; /*I2S TX PDM sigmadelta dither value*/
|
||||
uint32_t tx_pdm_dac_2out_en : 1; /*I2S TX PDM dac mode enable*/
|
||||
uint32_t tx_pdm_dac_mode_en : 1; /*I2S TX PDM dac 2channel enable*/
|
||||
uint32_t pcm2pdm_conv_en : 1; /*I2S TX PDM Converter enable*/
|
||||
uint32_t reserved26 : 6; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} tx_pcm2pdm_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tx_pdm_fp : 10; /*I2S TX PDM Fp*/
|
||||
uint32_t tx_pdm_fs : 10; /*I2S TX PDM Fs*/
|
||||
uint32_t tx_iir_hp_mult12_5 : 3; /*The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0])*/
|
||||
uint32_t tx_iir_hp_mult12_0 : 3; /*The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0])*/
|
||||
uint32_t reserved26 : 6; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} tx_pcm2pdm_conf1;
|
||||
uint32_t reserved_48;
|
||||
uint32_t reserved_4c;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_tdm_pdm_chan0_en : 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_pdm_chan1_en : 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_pdm_chan2_en : 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_pdm_chan3_en : 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_pdm_chan4_en : 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_pdm_chan5_en : 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_pdm_chan6_en : 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_pdm_chan7_en : 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_chan8_en : 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_chan9_en : 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_chan10_en : 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_chan11_en : 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_chan12_en : 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_chan13_en : 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_chan14_en : 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_chan15_en : 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_tot_chan_num: 4; /*The total channel number of I2S TX TDM mode.*/
|
||||
uint32_t reserved20: 12; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} rx_tdm_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tx_tdm_chan0_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_chan1_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_chan2_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_chan3_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_chan4_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_chan5_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_chan6_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_chan7_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_chan8_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_chan9_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_chan10_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_chan11_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_chan12_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_chan13_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_chan14_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_chan15_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_tot_chan_num: 4; /*The total channel number minus 1 of I2S TX TDM mode.*/
|
||||
uint32_t tx_tdm_skip_msk_en: 1; /*When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels and only the data of the enabled channels is sent then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels.*/
|
||||
uint32_t reserved21: 11; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} tx_tdm_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_sd_in_dm: 2; /*The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
uint32_t reserved2 : 14; /* Reserved*/
|
||||
uint32_t rx_ws_out_dm: 2; /*The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
uint32_t reserved18: 2;
|
||||
uint32_t rx_bck_out_dm: 2; /*The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
uint32_t reserved22: 2;
|
||||
uint32_t rx_ws_in_dm: 2; /*The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
uint32_t reserved26: 2;
|
||||
uint32_t rx_bck_in_dm: 2; /*The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
uint32_t reserved30: 2;
|
||||
};
|
||||
uint32_t val;
|
||||
} rx_timing;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tx_sd_out_dm : 2; /*The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
uint32_t reserved2 : 2; /* Reserved*/
|
||||
uint32_t tx_sd1_out_dm : 2; /*The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
uint32_t reserved6 : 10; /* Reserved*/
|
||||
uint32_t tx_ws_out_dm : 2; /*The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
uint32_t reserved18 : 2; /* Reserved*/
|
||||
uint32_t tx_bck_out_dm : 2; /*The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
uint32_t reserved22 : 2; /* Reserved*/
|
||||
uint32_t tx_ws_in_dm : 2; /*The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
uint32_t reserved26 : 2; /* Reserved*/
|
||||
uint32_t tx_bck_in_dm : 2; /*The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
uint32_t reserved30 : 2; /* Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} tx_timing;
|
||||
union {
|
||||
struct {
|
||||
uint32_t fifo_timeout: 8; /*the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value*/
|
||||
uint32_t fifo_timeout_shift: 3; /*The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift*/
|
||||
uint32_t fifo_timeout_ena: 1; /*The enable bit for FIFO timeout*/
|
||||
uint32_t reserved12: 20; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} lc_hung_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_eof_num:12; /*the length of data to be received. It will trigger i2s_in_suc_eof_int.*/
|
||||
uint32_t reserved12:20; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} rx_eof_num;
|
||||
uint32_t conf_single_data; /*the right channel or left channel put out constant value stored in this register according to tx_chan_mod and reg_tx_msb_right*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t tx_idle: 1; /*1: i2s_tx is idle state. 0: i2s_tx is working.*/
|
||||
uint32_t reserved1: 31; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} state;
|
||||
uint32_t reserved_70;
|
||||
uint32_t reserved_74;
|
||||
uint32_t reserved_78;
|
||||
uint32_t reserved_7c;
|
||||
union {
|
||||
struct {
|
||||
uint32_t date: 28; /*Version control register*/
|
||||
uint32_t reserved28: 4; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} date;
|
||||
} i2s_dev_t;
|
||||
extern i2s_dev_t I2S0;
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,856 +0,0 @@
|
||||
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_INTERRUPT_CORE0_REG_H_
|
||||
#define _SOC_INTERRUPT_CORE0_REG_H_
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#include "soc.h"
|
||||
|
||||
#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTERRUPT_BASE
|
||||
|
||||
#define INTERRUPT_CORE0_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x000)
|
||||
/* INTERRUPT_CORE0_MAC_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_MAC_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_MAC_INTR_MAP_M ((INTERRUPT_CORE0_MAC_INTR_MAP_V)<<(INTERRUPT_CORE0_MAC_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_MAC_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_MAC_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x004)
|
||||
/* INTERRUPT_CORE0_MAC_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_MAC_NMI_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_MAC_NMI_MAP_M ((INTERRUPT_CORE0_MAC_NMI_MAP_V)<<(INTERRUPT_CORE0_MAC_NMI_MAP_S))
|
||||
#define INTERRUPT_CORE0_MAC_NMI_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_MAC_NMI_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x008)
|
||||
/* INTERRUPT_CORE0_PWR_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_PWR_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_PWR_INTR_MAP_M ((INTERRUPT_CORE0_PWR_INTR_MAP_V)<<(INTERRUPT_CORE0_PWR_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_PWR_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_PWR_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_BB_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x00C)
|
||||
/* INTERRUPT_CORE0_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_BB_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_BB_INT_MAP_M ((INTERRUPT_CORE0_BB_INT_MAP_V)<<(INTERRUPT_CORE0_BB_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_BB_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_BB_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_BT_MAC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x010)
|
||||
/* INTERRUPT_CORE0_BT_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_BT_MAC_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_BT_MAC_INT_MAP_M ((INTERRUPT_CORE0_BT_MAC_INT_MAP_V)<<(INTERRUPT_CORE0_BT_MAC_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_BT_MAC_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_BT_MAC_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_BT_BB_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x014)
|
||||
/* INTERRUPT_CORE0_BT_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_BT_BB_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_BT_BB_INT_MAP_M ((INTERRUPT_CORE0_BT_BB_INT_MAP_V)<<(INTERRUPT_CORE0_BT_BB_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_BT_BB_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_BT_BB_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x018)
|
||||
/* INTERRUPT_CORE0_BT_BB_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_BT_BB_NMI_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_BT_BB_NMI_MAP_M ((INTERRUPT_CORE0_BT_BB_NMI_MAP_V)<<(INTERRUPT_CORE0_BT_BB_NMI_MAP_S))
|
||||
#define INTERRUPT_CORE0_BT_BB_NMI_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_BT_BB_NMI_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_RWBT_IRQ_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x01C)
|
||||
/* INTERRUPT_CORE0_RWBT_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_RWBT_IRQ_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_RWBT_IRQ_MAP_M ((INTERRUPT_CORE0_RWBT_IRQ_MAP_V)<<(INTERRUPT_CORE0_RWBT_IRQ_MAP_S))
|
||||
#define INTERRUPT_CORE0_RWBT_IRQ_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_RWBT_IRQ_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x020)
|
||||
/* INTERRUPT_CORE0_RWBLE_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_RWBLE_IRQ_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_M ((INTERRUPT_CORE0_RWBLE_IRQ_MAP_V)<<(INTERRUPT_CORE0_RWBLE_IRQ_MAP_S))
|
||||
#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_RWBT_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x024)
|
||||
/* INTERRUPT_CORE0_RWBT_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_RWBT_NMI_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_RWBT_NMI_MAP_M ((INTERRUPT_CORE0_RWBT_NMI_MAP_V)<<(INTERRUPT_CORE0_RWBT_NMI_MAP_S))
|
||||
#define INTERRUPT_CORE0_RWBT_NMI_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_RWBT_NMI_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_RWBLE_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x028)
|
||||
/* INTERRUPT_CORE0_RWBLE_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_RWBLE_NMI_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_RWBLE_NMI_MAP_M ((INTERRUPT_CORE0_RWBLE_NMI_MAP_V)<<(INTERRUPT_CORE0_RWBLE_NMI_MAP_S))
|
||||
#define INTERRUPT_CORE0_RWBLE_NMI_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_RWBLE_NMI_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_I2C_MST_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x02C)
|
||||
/* INTERRUPT_CORE0_I2C_MST_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_I2C_MST_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_I2C_MST_INT_MAP_M ((INTERRUPT_CORE0_I2C_MST_INT_MAP_V)<<(INTERRUPT_CORE0_I2C_MST_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_I2C_MST_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_I2C_MST_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_SLC0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x030)
|
||||
/* INTERRUPT_CORE0_SLC0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_SLC0_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_SLC0_INTR_MAP_M ((INTERRUPT_CORE0_SLC0_INTR_MAP_V)<<(INTERRUPT_CORE0_SLC0_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_SLC0_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_SLC0_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_SLC1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x034)
|
||||
/* INTERRUPT_CORE0_SLC1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_SLC1_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_SLC1_INTR_MAP_M ((INTERRUPT_CORE0_SLC1_INTR_MAP_V)<<(INTERRUPT_CORE0_SLC1_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_SLC1_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_SLC1_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x038)
|
||||
/* INTERRUPT_CORE0_APB_CTRL_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_M ((INTERRUPT_CORE0_APB_CTRL_INTR_MAP_V)<<(INTERRUPT_CORE0_APB_CTRL_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_APB_CTRL_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x03C)
|
||||
/* INTERRUPT_CORE0_UHCI0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_UHCI0_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_UHCI0_INTR_MAP_M ((INTERRUPT_CORE0_UHCI0_INTR_MAP_V)<<(INTERRUPT_CORE0_UHCI0_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_UHCI0_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_UHCI0_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x040)
|
||||
/* INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_M ((INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V)<<(INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S))
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x044)
|
||||
/* INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_M ((INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V)<<(INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S))
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_SPI_INTR_1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x048)
|
||||
/* INTERRUPT_CORE0_SPI_INTR_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_SPI_INTR_1_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_SPI_INTR_1_MAP_M ((INTERRUPT_CORE0_SPI_INTR_1_MAP_V)<<(INTERRUPT_CORE0_SPI_INTR_1_MAP_S))
|
||||
#define INTERRUPT_CORE0_SPI_INTR_1_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_SPI_INTR_1_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_SPI_INTR_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x04C)
|
||||
/* INTERRUPT_CORE0_SPI_INTR_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_SPI_INTR_2_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_SPI_INTR_2_MAP_M ((INTERRUPT_CORE0_SPI_INTR_2_MAP_V)<<(INTERRUPT_CORE0_SPI_INTR_2_MAP_S))
|
||||
#define INTERRUPT_CORE0_SPI_INTR_2_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_SPI_INTR_2_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_I2S1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x050)
|
||||
/* INTERRUPT_CORE0_I2S1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_I2S1_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_I2S1_INT_MAP_M ((INTERRUPT_CORE0_I2S1_INT_MAP_V)<<(INTERRUPT_CORE0_I2S1_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_I2S1_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_I2S1_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_UART_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x054)
|
||||
/* INTERRUPT_CORE0_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_UART_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_UART_INTR_MAP_M ((INTERRUPT_CORE0_UART_INTR_MAP_V)<<(INTERRUPT_CORE0_UART_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_UART_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_UART_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x058)
|
||||
/* INTERRUPT_CORE0_UART1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_UART1_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_UART1_INTR_MAP_M ((INTERRUPT_CORE0_UART1_INTR_MAP_V)<<(INTERRUPT_CORE0_UART1_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_UART1_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_UART1_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_LEDC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x05C)
|
||||
/* INTERRUPT_CORE0_LEDC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_LEDC_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_LEDC_INT_MAP_M ((INTERRUPT_CORE0_LEDC_INT_MAP_V)<<(INTERRUPT_CORE0_LEDC_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_LEDC_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_LEDC_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_EFUSE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x060)
|
||||
/* INTERRUPT_CORE0_EFUSE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_EFUSE_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_EFUSE_INT_MAP_M ((INTERRUPT_CORE0_EFUSE_INT_MAP_V)<<(INTERRUPT_CORE0_EFUSE_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_EFUSE_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_EFUSE_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CAN_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x064)
|
||||
/* INTERRUPT_CORE0_CAN_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CAN_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_CAN_INT_MAP_M ((INTERRUPT_CORE0_CAN_INT_MAP_V)<<(INTERRUPT_CORE0_CAN_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_CAN_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_CAN_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x068)
|
||||
/* INTERRUPT_CORE0_USB_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_USB_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_USB_INTR_MAP_M ((INTERRUPT_CORE0_USB_INTR_MAP_V)<<(INTERRUPT_CORE0_USB_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_USB_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_USB_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x06C)
|
||||
/* INTERRUPT_CORE0_RTC_CORE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_M ((INTERRUPT_CORE0_RTC_CORE_INTR_MAP_V)<<(INTERRUPT_CORE0_RTC_CORE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x070)
|
||||
/* INTERRUPT_CORE0_RMT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_RMT_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_RMT_INTR_MAP_M ((INTERRUPT_CORE0_RMT_INTR_MAP_V)<<(INTERRUPT_CORE0_RMT_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_RMT_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_RMT_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x074)
|
||||
/* INTERRUPT_CORE0_I2C_EXT0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_M ((INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V)<<(INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_TIMER_INT1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x078)
|
||||
/* INTERRUPT_CORE0_TIMER_INT1_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_TIMER_INT1_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_TIMER_INT1_MAP_M ((INTERRUPT_CORE0_TIMER_INT1_MAP_V)<<(INTERRUPT_CORE0_TIMER_INT1_MAP_S))
|
||||
#define INTERRUPT_CORE0_TIMER_INT1_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_TIMER_INT1_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_TIMER_INT2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x07C)
|
||||
/* INTERRUPT_CORE0_TIMER_INT2_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_TIMER_INT2_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_TIMER_INT2_MAP_M ((INTERRUPT_CORE0_TIMER_INT2_MAP_V)<<(INTERRUPT_CORE0_TIMER_INT2_MAP_S))
|
||||
#define INTERRUPT_CORE0_TIMER_INT2_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_TIMER_INT2_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_TG_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x080)
|
||||
/* INTERRUPT_CORE0_TG_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_TG_T0_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_TG_T0_INT_MAP_M ((INTERRUPT_CORE0_TG_T0_INT_MAP_V)<<(INTERRUPT_CORE0_TG_T0_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_TG_T0_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_TG_T0_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_TG_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x084)
|
||||
/* INTERRUPT_CORE0_TG_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_TG_WDT_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_TG_WDT_INT_MAP_M ((INTERRUPT_CORE0_TG_WDT_INT_MAP_V)<<(INTERRUPT_CORE0_TG_WDT_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_TG_WDT_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_TG_WDT_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_TG1_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x088)
|
||||
/* INTERRUPT_CORE0_TG1_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_TG1_T0_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_TG1_T0_INT_MAP_M ((INTERRUPT_CORE0_TG1_T0_INT_MAP_V)<<(INTERRUPT_CORE0_TG1_T0_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_TG1_T0_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_TG1_T0_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x08C)
|
||||
/* INTERRUPT_CORE0_TG1_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_TG1_WDT_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_M ((INTERRUPT_CORE0_TG1_WDT_INT_MAP_V)<<(INTERRUPT_CORE0_TG1_WDT_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x090)
|
||||
/* INTERRUPT_CORE0_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CACHE_IA_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_M ((INTERRUPT_CORE0_CACHE_IA_INT_MAP_V)<<(INTERRUPT_CORE0_CACHE_IA_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x094)
|
||||
/* INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_M ((INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x098)
|
||||
/* INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_M ((INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x09C)
|
||||
/* INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_M ((INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0A0)
|
||||
/* INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_M ((INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_V)<<(INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0A4)
|
||||
/* INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_M ((INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_V)<<(INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0A8)
|
||||
/* INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_M ((INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_V)<<(INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_APB_ADC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0AC)
|
||||
/* INTERRUPT_CORE0_APB_ADC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_APB_ADC_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_APB_ADC_INT_MAP_M ((INTERRUPT_CORE0_APB_ADC_INT_MAP_V)<<(INTERRUPT_CORE0_APB_ADC_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_APB_ADC_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_APB_ADC_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0B0)
|
||||
/* INTERRUPT_CORE0_DMA_CH0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_DMA_CH0_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_M ((INTERRUPT_CORE0_DMA_CH0_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_CH0_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0B4)
|
||||
/* INTERRUPT_CORE0_DMA_CH1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_DMA_CH1_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_M ((INTERRUPT_CORE0_DMA_CH1_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_CH1_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0B8)
|
||||
/* INTERRUPT_CORE0_DMA_CH2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_DMA_CH2_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_M ((INTERRUPT_CORE0_DMA_CH2_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_CH2_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_RSA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0BC)
|
||||
/* INTERRUPT_CORE0_RSA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_RSA_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_RSA_INT_MAP_M ((INTERRUPT_CORE0_RSA_INT_MAP_V)<<(INTERRUPT_CORE0_RSA_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_RSA_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_RSA_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_AES_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0C0)
|
||||
/* INTERRUPT_CORE0_AES_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_AES_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_AES_INT_MAP_M ((INTERRUPT_CORE0_AES_INT_MAP_V)<<(INTERRUPT_CORE0_AES_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_AES_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_AES_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_SHA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0C4)
|
||||
/* INTERRUPT_CORE0_SHA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_SHA_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_SHA_INT_MAP_M ((INTERRUPT_CORE0_SHA_INT_MAP_V)<<(INTERRUPT_CORE0_SHA_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_SHA_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_SHA_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0C8)
|
||||
/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S))
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0CC)
|
||||
/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S))
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0D0)
|
||||
/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S))
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0D4)
|
||||
/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S))
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0D8)
|
||||
/* INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_M ((INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V)<<(INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0DC)
|
||||
/* INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0E0)
|
||||
/* INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0E4)
|
||||
/* INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0E8)
|
||||
/* INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0EC)
|
||||
/* INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0F0)
|
||||
/* INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0F4)
|
||||
/* INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_M ((INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V)<<(INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_INTR_STATUS_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0F8)
|
||||
/* INTERRUPT_CORE0_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_INTR_STATUS_0 0xFFFFFFFF
|
||||
#define INTERRUPT_CORE0_INTR_STATUS_0_M ((INTERRUPT_CORE0_INTR_STATUS_0_V)<<(INTERRUPT_CORE0_INTR_STATUS_0_S))
|
||||
#define INTERRUPT_CORE0_INTR_STATUS_0_V 0xFFFFFFFF
|
||||
#define INTERRUPT_CORE0_INTR_STATUS_0_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_INTR_STATUS_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0FC)
|
||||
/* INTERRUPT_CORE0_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_INTR_STATUS_1 0xFFFFFFFF
|
||||
#define INTERRUPT_CORE0_INTR_STATUS_1_M ((INTERRUPT_CORE0_INTR_STATUS_1_V)<<(INTERRUPT_CORE0_INTR_STATUS_1_S))
|
||||
#define INTERRUPT_CORE0_INTR_STATUS_1_V 0xFFFFFFFF
|
||||
#define INTERRUPT_CORE0_INTR_STATUS_1_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x100)
|
||||
/* INTERRUPT_CORE0_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CLK_EN (BIT(0))
|
||||
#define INTERRUPT_CORE0_CLK_EN_M (BIT(0))
|
||||
#define INTERRUPT_CORE0_CLK_EN_V 0x1
|
||||
#define INTERRUPT_CORE0_CLK_EN_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INT_ENABLE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x104)
|
||||
/* INTERRUPT_CORE0_CPU_INT_ENABLE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_INT_ENABLE 0xFFFFFFFF
|
||||
#define INTERRUPT_CORE0_CPU_INT_ENABLE_M ((INTERRUPT_CORE0_CPU_INT_ENABLE_V)<<(INTERRUPT_CORE0_CPU_INT_ENABLE_S))
|
||||
#define INTERRUPT_CORE0_CPU_INT_ENABLE_V 0xFFFFFFFF
|
||||
#define INTERRUPT_CORE0_CPU_INT_ENABLE_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INT_TYPE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x108)
|
||||
/* INTERRUPT_CORE0_CPU_INT_TYPE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_INT_TYPE 0xFFFFFFFF
|
||||
#define INTERRUPT_CORE0_CPU_INT_TYPE_M ((INTERRUPT_CORE0_CPU_INT_TYPE_V)<<(INTERRUPT_CORE0_CPU_INT_TYPE_S))
|
||||
#define INTERRUPT_CORE0_CPU_INT_TYPE_V 0xFFFFFFFF
|
||||
#define INTERRUPT_CORE0_CPU_INT_TYPE_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INT_CLEAR_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10C)
|
||||
/* INTERRUPT_CORE0_CPU_INT_CLEAR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_INT_CLEAR 0xFFFFFFFF
|
||||
#define INTERRUPT_CORE0_CPU_INT_CLEAR_M ((INTERRUPT_CORE0_CPU_INT_CLEAR_V)<<(INTERRUPT_CORE0_CPU_INT_CLEAR_S))
|
||||
#define INTERRUPT_CORE0_CPU_INT_CLEAR_V 0xFFFFFFFF
|
||||
#define INTERRUPT_CORE0_CPU_INT_CLEAR_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x110)
|
||||
/* INTERRUPT_CORE0_CPU_INT_EIP_STATUS : RO ;bitpos:[31:0] ;default: 32'b0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS 0xFFFFFFFF
|
||||
#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_M ((INTERRUPT_CORE0_CPU_INT_EIP_STATUS_V)<<(INTERRUPT_CORE0_CPU_INT_EIP_STATUS_S))
|
||||
#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_V 0xFFFFFFFF
|
||||
#define INTERRUPT_CORE0_CPU_INT_EIP_STATUS_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INT_PRI_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x114)
|
||||
/* INTERRUPT_CORE0_CPU_PRI_0_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_PRI_0_MAP 0x0000000F
|
||||
#define INTERRUPT_CORE0_CPU_PRI_0_MAP_M ((INTERRUPT_CORE0_CPU_PRI_0_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_0_MAP_S))
|
||||
#define INTERRUPT_CORE0_CPU_PRI_0_MAP_V 0xF
|
||||
#define INTERRUPT_CORE0_CPU_PRI_0_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INT_PRI_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x118)
|
||||
/* INTERRUPT_CORE0_CPU_PRI_1_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_PRI_1_MAP 0x0000000F
|
||||
#define INTERRUPT_CORE0_CPU_PRI_1_MAP_M ((INTERRUPT_CORE0_CPU_PRI_1_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_1_MAP_S))
|
||||
#define INTERRUPT_CORE0_CPU_PRI_1_MAP_V 0xF
|
||||
#define INTERRUPT_CORE0_CPU_PRI_1_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INT_PRI_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x11C)
|
||||
/* INTERRUPT_CORE0_CPU_PRI_2_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_PRI_2_MAP 0x0000000F
|
||||
#define INTERRUPT_CORE0_CPU_PRI_2_MAP_M ((INTERRUPT_CORE0_CPU_PRI_2_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_2_MAP_S))
|
||||
#define INTERRUPT_CORE0_CPU_PRI_2_MAP_V 0xF
|
||||
#define INTERRUPT_CORE0_CPU_PRI_2_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INT_PRI_3_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x120)
|
||||
/* INTERRUPT_CORE0_CPU_PRI_3_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_PRI_3_MAP 0x0000000F
|
||||
#define INTERRUPT_CORE0_CPU_PRI_3_MAP_M ((INTERRUPT_CORE0_CPU_PRI_3_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_3_MAP_S))
|
||||
#define INTERRUPT_CORE0_CPU_PRI_3_MAP_V 0xF
|
||||
#define INTERRUPT_CORE0_CPU_PRI_3_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INT_PRI_4_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x124)
|
||||
/* INTERRUPT_CORE0_CPU_PRI_4_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_PRI_4_MAP 0x0000000F
|
||||
#define INTERRUPT_CORE0_CPU_PRI_4_MAP_M ((INTERRUPT_CORE0_CPU_PRI_4_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_4_MAP_S))
|
||||
#define INTERRUPT_CORE0_CPU_PRI_4_MAP_V 0xF
|
||||
#define INTERRUPT_CORE0_CPU_PRI_4_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INT_PRI_5_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x128)
|
||||
/* INTERRUPT_CORE0_CPU_PRI_5_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_PRI_5_MAP 0x0000000F
|
||||
#define INTERRUPT_CORE0_CPU_PRI_5_MAP_M ((INTERRUPT_CORE0_CPU_PRI_5_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_5_MAP_S))
|
||||
#define INTERRUPT_CORE0_CPU_PRI_5_MAP_V 0xF
|
||||
#define INTERRUPT_CORE0_CPU_PRI_5_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INT_PRI_6_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x12C)
|
||||
/* INTERRUPT_CORE0_CPU_PRI_6_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_PRI_6_MAP 0x0000000F
|
||||
#define INTERRUPT_CORE0_CPU_PRI_6_MAP_M ((INTERRUPT_CORE0_CPU_PRI_6_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_6_MAP_S))
|
||||
#define INTERRUPT_CORE0_CPU_PRI_6_MAP_V 0xF
|
||||
#define INTERRUPT_CORE0_CPU_PRI_6_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INT_PRI_7_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x130)
|
||||
/* INTERRUPT_CORE0_CPU_PRI_7_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_PRI_7_MAP 0x0000000F
|
||||
#define INTERRUPT_CORE0_CPU_PRI_7_MAP_M ((INTERRUPT_CORE0_CPU_PRI_7_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_7_MAP_S))
|
||||
#define INTERRUPT_CORE0_CPU_PRI_7_MAP_V 0xF
|
||||
#define INTERRUPT_CORE0_CPU_PRI_7_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INT_PRI_8_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x134)
|
||||
/* INTERRUPT_CORE0_CPU_PRI_8_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_PRI_8_MAP 0x0000000F
|
||||
#define INTERRUPT_CORE0_CPU_PRI_8_MAP_M ((INTERRUPT_CORE0_CPU_PRI_8_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_8_MAP_S))
|
||||
#define INTERRUPT_CORE0_CPU_PRI_8_MAP_V 0xF
|
||||
#define INTERRUPT_CORE0_CPU_PRI_8_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INT_PRI_9_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x138)
|
||||
/* INTERRUPT_CORE0_CPU_PRI_9_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_PRI_9_MAP 0x0000000F
|
||||
#define INTERRUPT_CORE0_CPU_PRI_9_MAP_M ((INTERRUPT_CORE0_CPU_PRI_9_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_9_MAP_S))
|
||||
#define INTERRUPT_CORE0_CPU_PRI_9_MAP_V 0xF
|
||||
#define INTERRUPT_CORE0_CPU_PRI_9_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INT_PRI_10_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x13C)
|
||||
/* INTERRUPT_CORE0_CPU_PRI_10_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_PRI_10_MAP 0x0000000F
|
||||
#define INTERRUPT_CORE0_CPU_PRI_10_MAP_M ((INTERRUPT_CORE0_CPU_PRI_10_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_10_MAP_S))
|
||||
#define INTERRUPT_CORE0_CPU_PRI_10_MAP_V 0xF
|
||||
#define INTERRUPT_CORE0_CPU_PRI_10_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INT_PRI_11_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x140)
|
||||
/* INTERRUPT_CORE0_CPU_PRI_11_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_PRI_11_MAP 0x0000000F
|
||||
#define INTERRUPT_CORE0_CPU_PRI_11_MAP_M ((INTERRUPT_CORE0_CPU_PRI_11_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_11_MAP_S))
|
||||
#define INTERRUPT_CORE0_CPU_PRI_11_MAP_V 0xF
|
||||
#define INTERRUPT_CORE0_CPU_PRI_11_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INT_PRI_12_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x144)
|
||||
/* INTERRUPT_CORE0_CPU_PRI_12_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_PRI_12_MAP 0x0000000F
|
||||
#define INTERRUPT_CORE0_CPU_PRI_12_MAP_M ((INTERRUPT_CORE0_CPU_PRI_12_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_12_MAP_S))
|
||||
#define INTERRUPT_CORE0_CPU_PRI_12_MAP_V 0xF
|
||||
#define INTERRUPT_CORE0_CPU_PRI_12_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INT_PRI_13_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x148)
|
||||
/* INTERRUPT_CORE0_CPU_PRI_13_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_PRI_13_MAP 0x0000000F
|
||||
#define INTERRUPT_CORE0_CPU_PRI_13_MAP_M ((INTERRUPT_CORE0_CPU_PRI_13_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_13_MAP_S))
|
||||
#define INTERRUPT_CORE0_CPU_PRI_13_MAP_V 0xF
|
||||
#define INTERRUPT_CORE0_CPU_PRI_13_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INT_PRI_14_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14C)
|
||||
/* INTERRUPT_CORE0_CPU_PRI_14_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_PRI_14_MAP 0x0000000F
|
||||
#define INTERRUPT_CORE0_CPU_PRI_14_MAP_M ((INTERRUPT_CORE0_CPU_PRI_14_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_14_MAP_S))
|
||||
#define INTERRUPT_CORE0_CPU_PRI_14_MAP_V 0xF
|
||||
#define INTERRUPT_CORE0_CPU_PRI_14_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INT_PRI_15_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x150)
|
||||
/* INTERRUPT_CORE0_CPU_PRI_15_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_PRI_15_MAP 0x0000000F
|
||||
#define INTERRUPT_CORE0_CPU_PRI_15_MAP_M ((INTERRUPT_CORE0_CPU_PRI_15_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_15_MAP_S))
|
||||
#define INTERRUPT_CORE0_CPU_PRI_15_MAP_V 0xF
|
||||
#define INTERRUPT_CORE0_CPU_PRI_15_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INT_PRI_16_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x154)
|
||||
/* INTERRUPT_CORE0_CPU_PRI_16_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_PRI_16_MAP 0x0000000F
|
||||
#define INTERRUPT_CORE0_CPU_PRI_16_MAP_M ((INTERRUPT_CORE0_CPU_PRI_16_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_16_MAP_S))
|
||||
#define INTERRUPT_CORE0_CPU_PRI_16_MAP_V 0xF
|
||||
#define INTERRUPT_CORE0_CPU_PRI_16_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INT_PRI_17_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x158)
|
||||
/* INTERRUPT_CORE0_CPU_PRI_17_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_PRI_17_MAP 0x0000000F
|
||||
#define INTERRUPT_CORE0_CPU_PRI_17_MAP_M ((INTERRUPT_CORE0_CPU_PRI_17_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_17_MAP_S))
|
||||
#define INTERRUPT_CORE0_CPU_PRI_17_MAP_V 0xF
|
||||
#define INTERRUPT_CORE0_CPU_PRI_17_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INT_PRI_18_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x15C)
|
||||
/* INTERRUPT_CORE0_CPU_PRI_18_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_PRI_18_MAP 0x0000000F
|
||||
#define INTERRUPT_CORE0_CPU_PRI_18_MAP_M ((INTERRUPT_CORE0_CPU_PRI_18_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_18_MAP_S))
|
||||
#define INTERRUPT_CORE0_CPU_PRI_18_MAP_V 0xF
|
||||
#define INTERRUPT_CORE0_CPU_PRI_18_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INT_PRI_19_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x160)
|
||||
/* INTERRUPT_CORE0_CPU_PRI_19_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_PRI_19_MAP 0x0000000F
|
||||
#define INTERRUPT_CORE0_CPU_PRI_19_MAP_M ((INTERRUPT_CORE0_CPU_PRI_19_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_19_MAP_S))
|
||||
#define INTERRUPT_CORE0_CPU_PRI_19_MAP_V 0xF
|
||||
#define INTERRUPT_CORE0_CPU_PRI_19_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INT_PRI_20_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x164)
|
||||
/* INTERRUPT_CORE0_CPU_PRI_20_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_PRI_20_MAP 0x0000000F
|
||||
#define INTERRUPT_CORE0_CPU_PRI_20_MAP_M ((INTERRUPT_CORE0_CPU_PRI_20_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_20_MAP_S))
|
||||
#define INTERRUPT_CORE0_CPU_PRI_20_MAP_V 0xF
|
||||
#define INTERRUPT_CORE0_CPU_PRI_20_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INT_PRI_21_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x168)
|
||||
/* INTERRUPT_CORE0_CPU_PRI_21_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_PRI_21_MAP 0x0000000F
|
||||
#define INTERRUPT_CORE0_CPU_PRI_21_MAP_M ((INTERRUPT_CORE0_CPU_PRI_21_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_21_MAP_S))
|
||||
#define INTERRUPT_CORE0_CPU_PRI_21_MAP_V 0xF
|
||||
#define INTERRUPT_CORE0_CPU_PRI_21_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INT_PRI_22_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x16C)
|
||||
/* INTERRUPT_CORE0_CPU_PRI_22_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_PRI_22_MAP 0x0000000F
|
||||
#define INTERRUPT_CORE0_CPU_PRI_22_MAP_M ((INTERRUPT_CORE0_CPU_PRI_22_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_22_MAP_S))
|
||||
#define INTERRUPT_CORE0_CPU_PRI_22_MAP_V 0xF
|
||||
#define INTERRUPT_CORE0_CPU_PRI_22_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INT_PRI_23_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x170)
|
||||
/* INTERRUPT_CORE0_CPU_PRI_23_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_PRI_23_MAP 0x0000000F
|
||||
#define INTERRUPT_CORE0_CPU_PRI_23_MAP_M ((INTERRUPT_CORE0_CPU_PRI_23_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_23_MAP_S))
|
||||
#define INTERRUPT_CORE0_CPU_PRI_23_MAP_V 0xF
|
||||
#define INTERRUPT_CORE0_CPU_PRI_23_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INT_PRI_24_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x174)
|
||||
/* INTERRUPT_CORE0_CPU_PRI_24_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_PRI_24_MAP 0x0000000F
|
||||
#define INTERRUPT_CORE0_CPU_PRI_24_MAP_M ((INTERRUPT_CORE0_CPU_PRI_24_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_24_MAP_S))
|
||||
#define INTERRUPT_CORE0_CPU_PRI_24_MAP_V 0xF
|
||||
#define INTERRUPT_CORE0_CPU_PRI_24_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INT_PRI_25_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x178)
|
||||
/* INTERRUPT_CORE0_CPU_PRI_25_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_PRI_25_MAP 0x0000000F
|
||||
#define INTERRUPT_CORE0_CPU_PRI_25_MAP_M ((INTERRUPT_CORE0_CPU_PRI_25_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_25_MAP_S))
|
||||
#define INTERRUPT_CORE0_CPU_PRI_25_MAP_V 0xF
|
||||
#define INTERRUPT_CORE0_CPU_PRI_25_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INT_PRI_26_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x17C)
|
||||
/* INTERRUPT_CORE0_CPU_PRI_26_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_PRI_26_MAP 0x0000000F
|
||||
#define INTERRUPT_CORE0_CPU_PRI_26_MAP_M ((INTERRUPT_CORE0_CPU_PRI_26_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_26_MAP_S))
|
||||
#define INTERRUPT_CORE0_CPU_PRI_26_MAP_V 0xF
|
||||
#define INTERRUPT_CORE0_CPU_PRI_26_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INT_PRI_27_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x180)
|
||||
/* INTERRUPT_CORE0_CPU_PRI_27_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_PRI_27_MAP 0x0000000F
|
||||
#define INTERRUPT_CORE0_CPU_PRI_27_MAP_M ((INTERRUPT_CORE0_CPU_PRI_27_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_27_MAP_S))
|
||||
#define INTERRUPT_CORE0_CPU_PRI_27_MAP_V 0xF
|
||||
#define INTERRUPT_CORE0_CPU_PRI_27_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INT_PRI_28_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x184)
|
||||
/* INTERRUPT_CORE0_CPU_PRI_28_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_PRI_28_MAP 0x0000000F
|
||||
#define INTERRUPT_CORE0_CPU_PRI_28_MAP_M ((INTERRUPT_CORE0_CPU_PRI_28_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_28_MAP_S))
|
||||
#define INTERRUPT_CORE0_CPU_PRI_28_MAP_V 0xF
|
||||
#define INTERRUPT_CORE0_CPU_PRI_28_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INT_PRI_29_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x188)
|
||||
/* INTERRUPT_CORE0_CPU_PRI_29_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_PRI_29_MAP 0x0000000F
|
||||
#define INTERRUPT_CORE0_CPU_PRI_29_MAP_M ((INTERRUPT_CORE0_CPU_PRI_29_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_29_MAP_S))
|
||||
#define INTERRUPT_CORE0_CPU_PRI_29_MAP_V 0xF
|
||||
#define INTERRUPT_CORE0_CPU_PRI_29_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INT_PRI_30_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x18C)
|
||||
/* INTERRUPT_CORE0_CPU_PRI_30_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_PRI_30_MAP 0x0000000F
|
||||
#define INTERRUPT_CORE0_CPU_PRI_30_MAP_M ((INTERRUPT_CORE0_CPU_PRI_30_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_30_MAP_S))
|
||||
#define INTERRUPT_CORE0_CPU_PRI_30_MAP_V 0xF
|
||||
#define INTERRUPT_CORE0_CPU_PRI_30_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INT_PRI_31_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x190)
|
||||
/* INTERRUPT_CORE0_CPU_PRI_31_MAP : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_PRI_31_MAP 0x0000000F
|
||||
#define INTERRUPT_CORE0_CPU_PRI_31_MAP_M ((INTERRUPT_CORE0_CPU_PRI_31_MAP_V)<<(INTERRUPT_CORE0_CPU_PRI_31_MAP_S))
|
||||
#define INTERRUPT_CORE0_CPU_PRI_31_MAP_V 0xF
|
||||
#define INTERRUPT_CORE0_CPU_PRI_31_MAP_S 0
|
||||
#define INTC_INT_PRIO_REG(n) (INTERRUPT_CORE0_CPU_INT_PRI_0_REG + (n)*4)
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INT_THRESH_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x194)
|
||||
/* INTERRUPT_CORE0_CPU_INT_THRESH : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_INT_THRESH 0x0000000F
|
||||
#define INTERRUPT_CORE0_CPU_INT_THRESH_M ((INTERRUPT_CORE0_CPU_INT_THRESH_V)<<(INTERRUPT_CORE0_CPU_INT_THRESH_S))
|
||||
#define INTERRUPT_CORE0_CPU_INT_THRESH_V 0xF
|
||||
#define INTERRUPT_CORE0_CPU_INT_THRESH_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_INTERRUPT_DATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7FC)
|
||||
/* INTERRUPT_CORE0_INTERRUPT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2007210 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_INTERRUPT_DATE 0x0FFFFFFF
|
||||
#define INTERRUPT_CORE0_INTERRUPT_DATE_M ((INTERRUPT_CORE0_INTERRUPT_DATE_V)<<(INTERRUPT_CORE0_INTERRUPT_DATE_S))
|
||||
#define INTERRUPT_CORE0_INTERRUPT_DATE_V 0xFFFFFFF
|
||||
#define INTERRUPT_CORE0_INTERRUPT_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /*_SOC_INTERRUPT_CORE0_REG_H_ */
|
||||
@@ -5,7 +5,7 @@
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include "interrupt_core0_reg.h"
|
||||
#include "soc/interrupt_core0_reg.h"
|
||||
|
||||
#define INTERRUPT_CURRENT_CORE_INT_THRESH_REG INTERRUPT_CORE0_CPU_INT_THRESH_REG
|
||||
#define INTERRUPT_PRIO_REG(n) (INTERRUPT_CORE0_CPU_INT_PRI_0_REG + (n)*4)
|
||||
|
||||
@@ -1,273 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#ifndef _SOC_IO_MUX_REG_H_
|
||||
#define _SOC_IO_MUX_REG_H_
|
||||
|
||||
#include "soc.h"
|
||||
|
||||
/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
|
||||
/* Output enable in sleep mode */
|
||||
#define SLP_OE (BIT(0))
|
||||
#define SLP_OE_M (BIT(0))
|
||||
#define SLP_OE_V 1
|
||||
#define SLP_OE_S 0
|
||||
/* Pin used for wakeup from sleep */
|
||||
#define SLP_SEL (BIT(1))
|
||||
#define SLP_SEL_M (BIT(1))
|
||||
#define SLP_SEL_V 1
|
||||
#define SLP_SEL_S 1
|
||||
/* Pulldown enable in sleep mode */
|
||||
#define SLP_PD (BIT(2))
|
||||
#define SLP_PD_M (BIT(2))
|
||||
#define SLP_PD_V 1
|
||||
#define SLP_PD_S 2
|
||||
/* Pullup enable in sleep mode */
|
||||
#define SLP_PU (BIT(3))
|
||||
#define SLP_PU_M (BIT(3))
|
||||
#define SLP_PU_V 1
|
||||
#define SLP_PU_S 3
|
||||
/* Input enable in sleep mode */
|
||||
#define SLP_IE (BIT(4))
|
||||
#define SLP_IE_M (BIT(4))
|
||||
#define SLP_IE_V 1
|
||||
#define SLP_IE_S 4
|
||||
/* Drive strength in sleep mode */
|
||||
#define SLP_DRV 0x3
|
||||
#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S)
|
||||
#define SLP_DRV_V 0x3
|
||||
#define SLP_DRV_S 5
|
||||
/* Pulldown enable */
|
||||
#define FUN_PD (BIT(7))
|
||||
#define FUN_PD_M (BIT(7))
|
||||
#define FUN_PD_V 1
|
||||
#define FUN_PD_S 7
|
||||
/* Pullup enable */
|
||||
#define FUN_PU (BIT(8))
|
||||
#define FUN_PU_M (BIT(8))
|
||||
#define FUN_PU_V 1
|
||||
#define FUN_PU_S 8
|
||||
/* Input enable */
|
||||
#define FUN_IE (BIT(9))
|
||||
#define FUN_IE_M (FUN_IE_V << FUN_IE_S)
|
||||
#define FUN_IE_V 1
|
||||
#define FUN_IE_S 9
|
||||
/* Drive strength */
|
||||
#define FUN_DRV 0x3
|
||||
#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)
|
||||
#define FUN_DRV_V 0x3
|
||||
#define FUN_DRV_S 10
|
||||
/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */
|
||||
#define MCU_SEL 0x7
|
||||
#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
|
||||
#define MCU_SEL_V 0x7
|
||||
#define MCU_SEL_S 12
|
||||
/* Pin filter (Pulse width shorter than 2 clock cycles will be filtered out) */
|
||||
#define FILTER_EN (BIT(15))
|
||||
#define FILTER_EN_M (FILTER_EN_V << FILTER_EN_S)
|
||||
#define FILTER_EN_V 1
|
||||
#define FILTER_EN_S 15
|
||||
|
||||
#define PIN_SLP_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_IE)
|
||||
#define PIN_SLP_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE)
|
||||
#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_OE)
|
||||
#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE)
|
||||
#define PIN_SLP_PULLUP_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PU)
|
||||
#define PIN_SLP_PULLUP_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU)
|
||||
#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PD)
|
||||
#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD)
|
||||
#define PIN_SLP_SEL_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_SEL)
|
||||
#define PIN_SLP_SEL_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL)
|
||||
|
||||
|
||||
#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
|
||||
#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
|
||||
#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
|
||||
#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU)
|
||||
#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU)
|
||||
#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD)
|
||||
#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD)
|
||||
#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
|
||||
#define PIN_FILTER_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FILTER_EN)
|
||||
#define PIN_FILTER_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FILTER_EN)
|
||||
|
||||
#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_XTAL_32K_P_U
|
||||
#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_XTAL_32K_N_U
|
||||
#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_GPIO2_U
|
||||
#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_GPIO3_U
|
||||
#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_MTMS_U
|
||||
#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_MTDI_U
|
||||
#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_MTCK_U
|
||||
#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_MTDO_U
|
||||
#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_GPIO8_U
|
||||
#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_GPIO9_U
|
||||
#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_GPIO10_U
|
||||
#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_VDD_SPI_U
|
||||
#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_SPIHD_U
|
||||
#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_SPIWP_U
|
||||
#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_SPICS0_U
|
||||
#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_SPICLK_U
|
||||
#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_SPID_U
|
||||
#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_SPIQ_U
|
||||
#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_GPIO18_U
|
||||
#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_GPIO19_U
|
||||
#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_U0RXD_U
|
||||
#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_U0TXD_U
|
||||
|
||||
/* Value to set in IO Mux to use a pin as GPIO. */
|
||||
#define PIN_FUNC_GPIO 1
|
||||
|
||||
#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
|
||||
#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
|
||||
#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
|
||||
|
||||
#define SPI_HD_GPIO_NUM 12
|
||||
#define SPI_WP_GPIO_NUM 13
|
||||
#define SPI_CS0_GPIO_NUM 14
|
||||
#define SPI_CLK_GPIO_NUM 15
|
||||
#define SPI_D_GPIO_NUM 16
|
||||
#define SPI_Q_GPIO_NUM 17
|
||||
|
||||
#define SD_CLK_GPIO_NUM 12
|
||||
#define SD_CMD_GPIO_NUM 11
|
||||
#define SD_DATA0_GPIO_NUM 13
|
||||
#define SD_DATA1_GPIO_NUM 14
|
||||
#define SD_DATA2_GPIO_NUM 9
|
||||
#define SD_DATA3_GPIO_NUM 10
|
||||
|
||||
#define USB_INT_PHY0_DM_GPIO_NUM 18
|
||||
#define USB_INT_PHY0_DP_GPIO_NUM 19
|
||||
|
||||
#define MAX_RTC_GPIO_NUM 5
|
||||
#define MAX_PAD_GPIO_NUM 21
|
||||
#define MAX_GPIO_NUM 25
|
||||
|
||||
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
|
||||
#define PIN_CTRL (REG_IO_MUX_BASE +0x00)
|
||||
#define PAD_POWER_SEL BIT(15)
|
||||
#define PAD_POWER_SEL_V 0x1
|
||||
#define PAD_POWER_SEL_M BIT(15)
|
||||
#define PAD_POWER_SEL_S 15
|
||||
|
||||
|
||||
#define PAD_POWER_SWITCH_DELAY 0x7
|
||||
#define PAD_POWER_SWITCH_DELAY_V 0x7
|
||||
#define PAD_POWER_SWITCH_DELAY_M (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S)
|
||||
#define PAD_POWER_SWITCH_DELAY_S 12
|
||||
|
||||
|
||||
#define CLK_OUT3 0xf
|
||||
#define CLK_OUT3_V CLK_OUT3
|
||||
#define CLK_OUT3_S 8
|
||||
#define CLK_OUT3_M (CLK_OUT3_V << CLK_OUT3_S)
|
||||
#define CLK_OUT2 0xf
|
||||
#define CLK_OUT2_V CLK_OUT2
|
||||
#define CLK_OUT2_S 4
|
||||
#define CLK_OUT2_M (CLK_OUT2_V << CLK_OUT2_S)
|
||||
#define CLK_OUT1 0xf
|
||||
#define CLK_OUT1_V CLK_OUT1
|
||||
#define CLK_OUT1_S 0
|
||||
#define CLK_OUT1_M (CLK_OUT1_V << CLK_OUT1_S)
|
||||
|
||||
#define PERIPHS_IO_MUX_XTAL_32K_P_U (REG_IO_MUX_BASE +0x04)
|
||||
#define FUNC_XTAL_32K_P_GPIO0 1
|
||||
#define FUNC_XTAL_32K_P_GPIO0_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_XTAL_32K_N_U (REG_IO_MUX_BASE +0x08)
|
||||
#define FUNC_XTAL_32K_N_GPIO1 1
|
||||
#define FUNC_XTAL_32K_N_GPIO1_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO2_U (REG_IO_MUX_BASE +0x0c)
|
||||
#define FUNC_GPIO2_FSPIQ 2
|
||||
#define FUNC_GPIO2_GPIO2 1
|
||||
#define FUNC_GPIO2_GPIO2_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO3_U (REG_IO_MUX_BASE +0x10)
|
||||
#define FUNC_GPIO3_GPIO3 1
|
||||
#define FUNC_GPIO3_GPIO3_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_MTMS_U (REG_IO_MUX_BASE +0x14)
|
||||
#define FUNC_MTMS_FSPIHD 2
|
||||
#define FUNC_MTMS_GPIO4 1
|
||||
#define FUNC_MTMS_MTMS 0
|
||||
|
||||
#define PERIPHS_IO_MUX_MTDI_U (REG_IO_MUX_BASE +0x18)
|
||||
#define FUNC_MTDI_FSPIWP 2
|
||||
#define FUNC_MTDI_GPIO5 1
|
||||
#define FUNC_MTDI_MTDI 0
|
||||
|
||||
#define PERIPHS_IO_MUX_MTCK_U (REG_IO_MUX_BASE +0x1c)
|
||||
#define FUNC_MTCK_FSPICLK 2
|
||||
#define FUNC_MTCK_GPIO6 1
|
||||
#define FUNC_MTCK_MTCK 0
|
||||
|
||||
#define PERIPHS_IO_MUX_MTDO_U (REG_IO_MUX_BASE +0x20)
|
||||
#define FUNC_MTDO_FSPID 2
|
||||
#define FUNC_MTDO_GPIO7 1
|
||||
#define FUNC_MTDO_MTDO 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO8_U (REG_IO_MUX_BASE +0x24)
|
||||
#define FUNC_GPIO8_GPIO8 1
|
||||
#define FUNC_GPIO8_GPIO8_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO9_U (REG_IO_MUX_BASE +0x28)
|
||||
#define FUNC_GPIO9_GPIO9 1
|
||||
#define FUNC_GPIO9_GPIO9_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO10_U (REG_IO_MUX_BASE +0x2c)
|
||||
#define FUNC_GPIO10_FSPICS0 2
|
||||
#define FUNC_GPIO10_GPIO10 1
|
||||
#define FUNC_GPIO10_GPIO10_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_VDD_SPI_U (REG_IO_MUX_BASE +0x30)
|
||||
#define FUNC_VDD_SPI_GPIO11 1
|
||||
#define FUNC_VDD_SPI_GPIO11_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_SPIHD_U (REG_IO_MUX_BASE +0x34)
|
||||
#define FUNC_SPIHD_GPIO12 1
|
||||
#define FUNC_SPIHD_SPIHD 0
|
||||
|
||||
#define PERIPHS_IO_MUX_SPIWP_U (REG_IO_MUX_BASE +0x38)
|
||||
#define FUNC_SPIWP_GPIO13 1
|
||||
#define FUNC_SPIWP_SPIWP 0
|
||||
|
||||
#define PERIPHS_IO_MUX_SPICS0_U (REG_IO_MUX_BASE +0x3c)
|
||||
#define FUNC_SPICS0_GPIO14 1
|
||||
#define FUNC_SPICS0_SPICS0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_SPICLK_U (REG_IO_MUX_BASE +0x40)
|
||||
#define FUNC_SPICLK_GPIO15 1
|
||||
#define FUNC_SPICLK_SPICLK 0
|
||||
|
||||
#define PERIPHS_IO_MUX_SPID_U (REG_IO_MUX_BASE +0x44)
|
||||
#define FUNC_SPID_GPIO16 1
|
||||
#define FUNC_SPID_SPID 0
|
||||
|
||||
#define PERIPHS_IO_MUX_SPIQ_U (REG_IO_MUX_BASE +0x48)
|
||||
#define FUNC_SPIQ_GPIO17 1
|
||||
#define FUNC_SPIQ_SPIQ 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO18_U (REG_IO_MUX_BASE +0x4c)
|
||||
#define FUNC_GPIO18_GPIO18 1
|
||||
#define FUNC_GPIO18_GPIO18_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO19_U (REG_IO_MUX_BASE +0x50)
|
||||
#define FUNC_GPIO19_GPIO19 1
|
||||
#define FUNC_GPIO19_GPIO19_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_U0RXD_U (REG_IO_MUX_BASE +0x54)
|
||||
#define FUNC_U0RXD_GPIO20 1
|
||||
#define FUNC_U0RXD_U0RXD 0
|
||||
|
||||
#define PERIPHS_IO_MUX_U0TXD_U (REG_IO_MUX_BASE +0x58)
|
||||
#define FUNC_U0TXD_GPIO21 1
|
||||
#define FUNC_U0TXD_U0TXD 0
|
||||
|
||||
#define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0xfc)
|
||||
#define IO_MUX_DATE 0xFFFFFFFF
|
||||
#define IO_MUX_DATE_S 0
|
||||
#define IO_MUX_DATE_VERSION 0x2006050
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,211 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct ledc_dev_s {
|
||||
struct {
|
||||
struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t timer_sel: 2;
|
||||
uint32_t sig_out_en: 1;
|
||||
uint32_t idle_lv: 1;
|
||||
uint32_t low_speed_update: 1;
|
||||
uint32_t ovf_num: 10;
|
||||
uint32_t ovf_cnt_en: 1;
|
||||
uint32_t ovf_cnt_rst: 1;
|
||||
uint32_t reserved17: 15;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t hpoint: 14;
|
||||
uint32_t reserved14: 18;
|
||||
};
|
||||
uint32_t val;
|
||||
} hpoint;
|
||||
union {
|
||||
struct {
|
||||
uint32_t duty: 19;
|
||||
uint32_t reserved19:13;
|
||||
};
|
||||
uint32_t val;
|
||||
} duty;
|
||||
union {
|
||||
struct {
|
||||
uint32_t duty_scale: 10;
|
||||
uint32_t duty_cycle: 10;
|
||||
uint32_t duty_num: 10;
|
||||
uint32_t duty_inc: 1;
|
||||
uint32_t duty_start: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t duty_read: 19;
|
||||
uint32_t reserved19: 13;
|
||||
};
|
||||
uint32_t val;
|
||||
} duty_rd;
|
||||
} channel[6];
|
||||
} channel_group[1];
|
||||
uint32_t reserved_78;
|
||||
uint32_t reserved_7c;
|
||||
uint32_t reserved_80;
|
||||
uint32_t reserved_84;
|
||||
uint32_t reserved_88;
|
||||
uint32_t reserved_8c;
|
||||
uint32_t reserved_90;
|
||||
uint32_t reserved_94;
|
||||
uint32_t reserved_98;
|
||||
uint32_t reserved_9c;
|
||||
struct {
|
||||
struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t duty_resolution: 4;
|
||||
uint32_t clock_divider: 18;
|
||||
uint32_t pause: 1;
|
||||
uint32_t rst: 1;
|
||||
uint32_t reserved24: 1;
|
||||
uint32_t low_speed_update: 1;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t timer_cnt: 14;
|
||||
uint32_t reserved14: 18;
|
||||
};
|
||||
uint32_t val;
|
||||
} value;
|
||||
} timer[4];
|
||||
} timer_group[1];
|
||||
union {
|
||||
struct {
|
||||
uint32_t lstimer0_ovf: 1;
|
||||
uint32_t lstimer1_ovf: 1;
|
||||
uint32_t lstimer2_ovf: 1;
|
||||
uint32_t lstimer3_ovf: 1;
|
||||
uint32_t duty_chng_end_lsch0: 1;
|
||||
uint32_t duty_chng_end_lsch1: 1;
|
||||
uint32_t duty_chng_end_lsch2: 1;
|
||||
uint32_t duty_chng_end_lsch3: 1;
|
||||
uint32_t duty_chng_end_lsch4: 1;
|
||||
uint32_t duty_chng_end_lsch5: 1;
|
||||
uint32_t ovf_cnt_lsch0: 1;
|
||||
uint32_t ovf_cnt_lsch1: 1;
|
||||
uint32_t ovf_cnt_lsch2: 1;
|
||||
uint32_t ovf_cnt_lsch3: 1;
|
||||
uint32_t ovf_cnt_lsch4: 1;
|
||||
uint32_t ovf_cnt_lsch5: 1;
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t lstimer0_ovf: 1;
|
||||
uint32_t lstimer1_ovf: 1;
|
||||
uint32_t lstimer2_ovf: 1;
|
||||
uint32_t lstimer3_ovf: 1;
|
||||
uint32_t duty_chng_end_lsch0: 1;
|
||||
uint32_t duty_chng_end_lsch1: 1;
|
||||
uint32_t duty_chng_end_lsch2: 1;
|
||||
uint32_t duty_chng_end_lsch3: 1;
|
||||
uint32_t duty_chng_end_lsch4: 1;
|
||||
uint32_t duty_chng_end_lsch5: 1;
|
||||
uint32_t ovf_cnt_lsch0: 1;
|
||||
uint32_t ovf_cnt_lsch1: 1;
|
||||
uint32_t ovf_cnt_lsch2: 1;
|
||||
uint32_t ovf_cnt_lsch3: 1;
|
||||
uint32_t ovf_cnt_lsch4: 1;
|
||||
uint32_t ovf_cnt_lsch5: 1;
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t lstimer0_ovf: 1;
|
||||
uint32_t lstimer1_ovf: 1;
|
||||
uint32_t lstimer2_ovf: 1;
|
||||
uint32_t lstimer3_ovf: 1;
|
||||
uint32_t duty_chng_end_lsch0: 1;
|
||||
uint32_t duty_chng_end_lsch1: 1;
|
||||
uint32_t duty_chng_end_lsch2: 1;
|
||||
uint32_t duty_chng_end_lsch3: 1;
|
||||
uint32_t duty_chng_end_lsch4: 1;
|
||||
uint32_t duty_chng_end_lsch5: 1;
|
||||
uint32_t ovf_cnt_lsch0: 1;
|
||||
uint32_t ovf_cnt_lsch1: 1;
|
||||
uint32_t ovf_cnt_lsch2: 1;
|
||||
uint32_t ovf_cnt_lsch3: 1;
|
||||
uint32_t ovf_cnt_lsch4: 1;
|
||||
uint32_t ovf_cnt_lsch5: 1;
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t lstimer0_ovf: 1;
|
||||
uint32_t lstimer1_ovf: 1;
|
||||
uint32_t lstimer2_ovf: 1;
|
||||
uint32_t lstimer3_ovf: 1;
|
||||
uint32_t duty_chng_end_lsch0: 1;
|
||||
uint32_t duty_chng_end_lsch1: 1;
|
||||
uint32_t duty_chng_end_lsch2: 1;
|
||||
uint32_t duty_chng_end_lsch3: 1;
|
||||
uint32_t duty_chng_end_lsch4: 1;
|
||||
uint32_t duty_chng_end_lsch5: 1;
|
||||
uint32_t ovf_cnt_lsch0: 1;
|
||||
uint32_t ovf_cnt_lsch1: 1;
|
||||
uint32_t ovf_cnt_lsch2: 1;
|
||||
uint32_t ovf_cnt_lsch3: 1;
|
||||
uint32_t ovf_cnt_lsch4: 1;
|
||||
uint32_t ovf_cnt_lsch5: 1;
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t apb_clk_sel: 2;
|
||||
uint32_t reserved2: 29;
|
||||
uint32_t clk_en: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf;
|
||||
uint32_t reserved_d4;
|
||||
uint32_t reserved_d8;
|
||||
uint32_t reserved_dc;
|
||||
uint32_t reserved_e0;
|
||||
uint32_t reserved_e4;
|
||||
uint32_t reserved_e8;
|
||||
uint32_t reserved_ec;
|
||||
uint32_t reserved_f0;
|
||||
uint32_t reserved_f4;
|
||||
uint32_t reserved_f8;
|
||||
union {
|
||||
struct {
|
||||
uint32_t date: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} date;
|
||||
} ledc_dev_t;
|
||||
extern ledc_dev_t LEDC;
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,55 +0,0 @@
|
||||
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "soc/soc.h"
|
||||
|
||||
/* Some of the WiFi RX control registers.
|
||||
* PU/PD fields defined here are used in sleep related functions.
|
||||
*/
|
||||
|
||||
#define NRXPD_CTRL (DR_REG_NRX_BASE + 0x00d4)
|
||||
#define NRX_CHAN_EST_FORCE_PU (BIT(7))
|
||||
#define NRX_CHAN_EST_FORCE_PU_M (BIT(7))
|
||||
#define NRX_CHAN_EST_FORCE_PU_V 1
|
||||
#define NRX_CHAN_EST_FORCE_PU_S 7
|
||||
#define NRX_CHAN_EST_FORCE_PD (BIT(6))
|
||||
#define NRX_CHAN_EST_FORCE_PD_M (BIT(6))
|
||||
#define NRX_CHAN_EST_FORCE_PD_V 1
|
||||
#define NRX_CHAN_EST_FORCE_PD_S 6
|
||||
#define NRX_RX_ROT_FORCE_PU (BIT(5))
|
||||
#define NRX_RX_ROT_FORCE_PU_M (BIT(5))
|
||||
#define NRX_RX_ROT_FORCE_PU_V 1
|
||||
#define NRX_RX_ROT_FORCE_PU_S 5
|
||||
#define NRX_RX_ROT_FORCE_PD (BIT(4))
|
||||
#define NRX_RX_ROT_FORCE_PD_M (BIT(4))
|
||||
#define NRX_RX_ROT_FORCE_PD_V 1
|
||||
#define NRX_RX_ROT_FORCE_PD_S 4
|
||||
#define NRX_VIT_FORCE_PU (BIT(3))
|
||||
#define NRX_VIT_FORCE_PU_M (BIT(3))
|
||||
#define NRX_VIT_FORCE_PU_V 1
|
||||
#define NRX_VIT_FORCE_PU_S 3
|
||||
#define NRX_VIT_FORCE_PD (BIT(2))
|
||||
#define NRX_VIT_FORCE_PD_M (BIT(2))
|
||||
#define NRX_VIT_FORCE_PD_V 1
|
||||
#define NRX_VIT_FORCE_PD_S 2
|
||||
#define NRX_DEMAP_FORCE_PU (BIT(1))
|
||||
#define NRX_DEMAP_FORCE_PU_M (BIT(1))
|
||||
#define NRX_DEMAP_FORCE_PU_V 1
|
||||
#define NRX_DEMAP_FORCE_PU_S 1
|
||||
#define NRX_DEMAP_FORCE_PD (BIT(0))
|
||||
#define NRX_DEMAP_FORCE_PD_M (BIT(0))
|
||||
#define NRX_DEMAP_FORCE_PD_V 1
|
||||
#define NRX_DEMAP_FORCE_PD_S 0
|
||||
@@ -1,50 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#define DR_REG_SYSTEM_BASE 0x600c0000
|
||||
#define DR_REG_SENSITIVE_BASE 0x600c1000
|
||||
#define DR_REG_INTERRUPT_BASE 0x600c2000
|
||||
#define DR_REG_EXTMEM_BASE 0x600c4000
|
||||
#define DR_REG_MMU_TABLE 0x600c5000
|
||||
#define DR_REG_AES_BASE 0x6003a000
|
||||
#define DR_REG_SHA_BASE 0x6003b000
|
||||
#define DR_REG_RSA_BASE 0x6003c000
|
||||
#define DR_REG_HMAC_BASE 0x6003e000
|
||||
#define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003d000
|
||||
#define DR_REG_GDMA_BASE 0x6003f000
|
||||
#define DR_REG_ASSIST_DEBUG_BASE 0x600ce000
|
||||
#define DR_REG_DEDICATED_GPIO_BASE 0x600cf000
|
||||
#define DR_REG_WORLD_CNTL_BASE 0x600d0000
|
||||
#define DR_REG_UART_BASE 0x60000000
|
||||
#define DR_REG_SPI1_BASE 0x60002000
|
||||
#define DR_REG_SPI0_BASE 0x60003000
|
||||
#define DR_REG_GPIO_BASE 0x60004000
|
||||
#define DR_REG_FE2_BASE 0x60005000
|
||||
#define DR_REG_FE_BASE 0x60006000
|
||||
#define DR_REG_RTCCNTL_BASE 0x60008000
|
||||
#define DR_REG_IO_MUX_BASE 0x60009000
|
||||
#define DR_REG_RTC_I2C_BASE 0x6000e000
|
||||
#define DR_REG_UART1_BASE 0x60010000
|
||||
#define DR_REG_I2C_EXT_BASE 0x60013000
|
||||
#define DR_REG_UHCI0_BASE 0x60014000
|
||||
#define DR_REG_RMT_BASE 0x60016000
|
||||
#define DR_REG_LEDC_BASE 0x60019000
|
||||
#define DR_REG_EFUSE_BASE 0x60008800
|
||||
#define DR_REG_NRX_BASE 0x6001CC00
|
||||
#define DR_REG_BB_BASE 0x6001D000
|
||||
#define DR_REG_TIMERGROUP0_BASE 0x6001F000
|
||||
#define DR_REG_TIMERGROUP1_BASE 0x60020000
|
||||
#define DR_REG_SYSTIMER_BASE 0x60023000
|
||||
#define DR_REG_SPI2_BASE 0x60024000
|
||||
#define DR_REG_SYSCON_BASE 0x60026000
|
||||
#define DR_REG_APB_CTRL_BASE 0x60026000 /* Old name for SYSCON, to be removed */
|
||||
#define DR_REG_TWAI_BASE 0x6002B000
|
||||
#define DR_REG_I2S_BASE 0x6002D000
|
||||
#define DR_REG_APB_SARADC_BASE 0x60040000
|
||||
#define DR_REG_USB_SERIAL_JTAG_BASE 0x60043000
|
||||
#define DR_REG_XTS_AES_BASE 0x600CC000
|
||||
|
||||
/* For backward compatability with the older register names */
|
||||
#define DR_REG_AES_XTS_BASE DR_REG_XTS_AES_BASE
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,274 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef struct rmt_dev_t {
|
||||
volatile uint32_t data_ch[4];
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t tx_start: 1;
|
||||
uint32_t mem_rd_rst: 1;
|
||||
uint32_t mem_rst: 1;
|
||||
uint32_t tx_conti_mode: 1;
|
||||
uint32_t mem_tx_wrap_en: 1;
|
||||
uint32_t idle_out_lv: 1;
|
||||
uint32_t idle_out_en: 1;
|
||||
uint32_t tx_stop: 1;
|
||||
uint32_t div_cnt: 8;
|
||||
uint32_t mem_size: 3;
|
||||
uint32_t reserved19: 1;
|
||||
uint32_t carrier_eff_en: 1;
|
||||
uint32_t carrier_en: 1;
|
||||
uint32_t carrier_out_lv: 1;
|
||||
uint32_t afifo_rst: 1;
|
||||
uint32_t conf_update: 1;
|
||||
uint32_t reserved25: 7;
|
||||
};
|
||||
uint32_t val;
|
||||
} tx_conf[2];
|
||||
volatile struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t div_cnt: 8;
|
||||
uint32_t idle_thres: 15;
|
||||
uint32_t mem_size: 3;
|
||||
uint32_t reserved26: 2;
|
||||
uint32_t carrier_en: 1;
|
||||
uint32_t carrier_out_lv: 1;
|
||||
uint32_t reserved30: 2;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_en: 1;
|
||||
uint32_t mem_wr_rst: 1;
|
||||
uint32_t mem_rst: 1;
|
||||
uint32_t mem_owner: 1;
|
||||
uint32_t rx_filter_en: 1;
|
||||
uint32_t rx_filter_thres: 8;
|
||||
uint32_t mem_rx_wrap_en: 1;
|
||||
uint32_t afifo_rst: 1;
|
||||
uint32_t conf_update: 1;
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf1;
|
||||
} rx_conf[2];
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t mem_raddr_ex: 9;
|
||||
uint32_t state: 3;
|
||||
uint32_t waddr: 9;
|
||||
uint32_t mem_rd_err: 1;
|
||||
uint32_t mem_empty: 1;
|
||||
uint32_t mem_wr_err: 1;
|
||||
uint32_t raddr: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} tx_status[2];
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t mem_waddr_ex: 9;
|
||||
uint32_t reserved9: 3;
|
||||
uint32_t mem_raddr: 9;
|
||||
uint32_t reserved21: 1;
|
||||
uint32_t state: 3;
|
||||
uint32_t mem_owner_err: 1;
|
||||
uint32_t mem_full: 1;
|
||||
uint32_t mem_rd_err: 1;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} rx_status[2];
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t ch0_tx_end: 1;
|
||||
uint32_t ch1_tx_end: 1;
|
||||
uint32_t ch2_rx_end: 1;
|
||||
uint32_t ch3_rx_end: 1;
|
||||
uint32_t ch0_err: 1;
|
||||
uint32_t ch1_err: 1;
|
||||
uint32_t ch2_err: 1;
|
||||
uint32_t ch3_err: 1;
|
||||
uint32_t ch0_tx_thr_event: 1;
|
||||
uint32_t ch1_tx_thr_event: 1;
|
||||
uint32_t ch2_rx_thr_event: 1;
|
||||
uint32_t ch3_rx_thr_event: 1;
|
||||
uint32_t ch0_tx_loop: 1;
|
||||
uint32_t ch1_tx_loop: 1;
|
||||
uint32_t reserved14: 18;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_raw;
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t ch0_tx_end: 1;
|
||||
uint32_t ch1_tx_end: 1;
|
||||
uint32_t ch2_rx_end: 1;
|
||||
uint32_t ch3_rx_end: 1;
|
||||
uint32_t ch0_err: 1;
|
||||
uint32_t ch1_err: 1;
|
||||
uint32_t ch2_err: 1;
|
||||
uint32_t ch3_err: 1;
|
||||
uint32_t ch0_tx_thr_event: 1;
|
||||
uint32_t ch1_tx_thr_event: 1;
|
||||
uint32_t ch2_rx_thr_event: 1;
|
||||
uint32_t ch3_rx_thr_event: 1;
|
||||
uint32_t ch0_tx_loop: 1;
|
||||
uint32_t ch1_tx_loop: 1;
|
||||
uint32_t reserved14: 18;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_st;
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t ch0_tx_end: 1;
|
||||
uint32_t ch1_tx_end: 1;
|
||||
uint32_t ch2_rx_end: 1;
|
||||
uint32_t ch3_rx_end: 1;
|
||||
uint32_t ch0_err: 1;
|
||||
uint32_t ch1_err: 1;
|
||||
uint32_t ch2_err: 1;
|
||||
uint32_t ch3_err: 1;
|
||||
uint32_t ch0_tx_thr_event: 1;
|
||||
uint32_t ch1_tx_thr_event: 1;
|
||||
uint32_t ch2_rx_thr_event: 1;
|
||||
uint32_t ch3_rx_thr_event: 1;
|
||||
uint32_t ch0_tx_loop: 1;
|
||||
uint32_t ch1_tx_loop: 1;
|
||||
uint32_t reserved14: 18;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_ena;
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t ch0_tx_end: 1;
|
||||
uint32_t ch1_tx_end: 1;
|
||||
uint32_t ch2_rx_end: 1;
|
||||
uint32_t ch3_rx_end: 1;
|
||||
uint32_t ch0_err: 1;
|
||||
uint32_t ch1_err: 1;
|
||||
uint32_t ch2_err: 1;
|
||||
uint32_t ch3_err: 1;
|
||||
uint32_t ch0_tx_thr_event: 1;
|
||||
uint32_t ch1_tx_thr_event: 1;
|
||||
uint32_t ch2_rx_thr_event: 1;
|
||||
uint32_t ch3_rx_thr_event: 1;
|
||||
uint32_t ch0_tx_loop: 1;
|
||||
uint32_t ch1_tx_loop: 1;
|
||||
uint32_t reserved14: 18;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_clr;
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t low: 16;
|
||||
uint32_t high: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} tx_carrier[2];
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t low_thres: 16;
|
||||
uint32_t high_thres: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} rx_carrier[2];
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t limit: 9;
|
||||
uint32_t tx_loop_num: 10;
|
||||
uint32_t tx_loop_cnt_en: 1;
|
||||
uint32_t loop_count_reset: 1;
|
||||
uint32_t reserved21: 11;
|
||||
};
|
||||
uint32_t val;
|
||||
} tx_lim[2];
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t rx_lim: 9;
|
||||
uint32_t reserved9: 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} rx_lim[2];
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t fifo_mask: 1;
|
||||
uint32_t mem_clk_force_on: 1;
|
||||
uint32_t mem_force_pd: 1;
|
||||
uint32_t mem_force_pu: 1;
|
||||
uint32_t sclk_div_num: 8;
|
||||
uint32_t sclk_div_a: 6;
|
||||
uint32_t sclk_div_b: 6;
|
||||
uint32_t sclk_sel: 2;
|
||||
uint32_t sclk_active: 1;
|
||||
uint32_t reserved27: 4;
|
||||
uint32_t clk_en: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} sys_conf;
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t ch0: 1;
|
||||
uint32_t ch1: 1;
|
||||
uint32_t en: 1;
|
||||
uint32_t reserved3: 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} tx_sim;
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t ch0: 1;
|
||||
uint32_t ch1: 1;
|
||||
uint32_t ch2: 1;
|
||||
uint32_t ch3: 1;
|
||||
uint32_t reserved4: 28;
|
||||
};
|
||||
uint32_t val;
|
||||
} ref_cnt_rst;
|
||||
uint32_t reserved_74;
|
||||
uint32_t reserved_78;
|
||||
uint32_t reserved_7c;
|
||||
uint32_t reserved_80;
|
||||
uint32_t reserved_84;
|
||||
uint32_t reserved_88;
|
||||
uint32_t reserved_8c;
|
||||
uint32_t reserved_90;
|
||||
uint32_t reserved_94;
|
||||
uint32_t reserved_98;
|
||||
uint32_t reserved_9c;
|
||||
uint32_t reserved_a0;
|
||||
uint32_t reserved_a4;
|
||||
uint32_t reserved_a8;
|
||||
uint32_t reserved_ac;
|
||||
uint32_t reserved_b0;
|
||||
uint32_t reserved_b4;
|
||||
uint32_t reserved_b8;
|
||||
uint32_t reserved_bc;
|
||||
uint32_t reserved_c0;
|
||||
uint32_t reserved_c4;
|
||||
uint32_t reserved_c8;
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t date: 28;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} date;
|
||||
} rmt_dev_t;
|
||||
|
||||
extern rmt_dev_t RMT;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,834 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct rtc_cntl_dev_s {
|
||||
union {
|
||||
struct {
|
||||
uint32_t sw_stall_appcpu_c0: 2; /*{reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/
|
||||
uint32_t sw_stall_procpu_c0: 2; /*{reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU*/
|
||||
uint32_t sw_appcpu_rst: 1; /*APP CPU SW reset*/
|
||||
uint32_t sw_procpu_rst: 1; /*PRO CPU SW reset*/
|
||||
uint32_t bb_i2c_force_pd: 1; /*BB_I2C force power down*/
|
||||
uint32_t bb_i2c_force_pu: 1; /*BB_I2C force power up*/
|
||||
uint32_t bbpll_i2c_force_pd: 1; /*BB_PLL _I2C force power down*/
|
||||
uint32_t bbpll_i2c_force_pu: 1; /*BB_PLL_I2C force power up*/
|
||||
uint32_t bbpll_force_pd: 1; /*BB_PLL force power down*/
|
||||
uint32_t bbpll_force_pu: 1; /*BB_PLL force power up*/
|
||||
uint32_t xtl_force_pd: 1; /*crystall force power down*/
|
||||
uint32_t xtl_force_pu: 1; /*crystall force power up*/
|
||||
uint32_t xtl_en_wait: 4; /*wait bias_sleep and current source wakeup*/
|
||||
uint32_t reserved18: 2;
|
||||
uint32_t ctr_sel: 3;
|
||||
uint32_t xtl_force_iso: 1;
|
||||
uint32_t pll_force_iso: 1;
|
||||
uint32_t analog_force_iso: 1;
|
||||
uint32_t xtl_force_noiso: 1;
|
||||
uint32_t pll_force_noiso: 1;
|
||||
uint32_t analog_force_noiso: 1;
|
||||
uint32_t dg_wrap_force_rst: 1; /*digital wrap force reset in deep sleep*/
|
||||
uint32_t dg_wrap_force_norst: 1; /*digital core force no reset in deep sleep*/
|
||||
uint32_t sw_sys_rst: 1; /*SW system reset*/
|
||||
};
|
||||
uint32_t val;
|
||||
} options0;
|
||||
uint32_t slp_timer0; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t slp_val_hi: 16; /*RTC sleep timer high 16 bits*/
|
||||
uint32_t main_timer_alarm_en: 1; /*timer alarm enable bit*/
|
||||
uint32_t reserved17: 15;
|
||||
};
|
||||
uint32_t val;
|
||||
} slp_timer1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 27;
|
||||
uint32_t timer_sys_stall: 1; /*Enable to record system stall time*/
|
||||
uint32_t timer_xtl_off: 1; /*Enable to record 40M XTAL OFF time*/
|
||||
uint32_t timer_sys_rst: 1; /*enable to record system reset time*/
|
||||
uint32_t reserved30: 1;
|
||||
uint32_t update: 1; /*Set 1: to update register with RTC timer*/
|
||||
};
|
||||
uint32_t val;
|
||||
} time_update;
|
||||
uint32_t time_low0; /*RTC timer low 32 bits*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t rtc_timer_value0_high:16; /*RTC timer high 16 bits*/
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} time_high0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rtc_sw_cpu_int: 1; /*rtc software interrupt to main cpu*/
|
||||
uint32_t rtc_slp_reject_cause_clr: 1; /*clear rtc sleep reject cause*/
|
||||
uint32_t reserved2: 20;
|
||||
uint32_t apb2rtc_bridge_sel: 1; /*1: APB to RTC using bridge*/
|
||||
uint32_t reserved23: 5;
|
||||
uint32_t sdio_active_ind: 1; /*SDIO active indication*/
|
||||
uint32_t slp_wakeup: 1; /*leep wakeup bit*/
|
||||
uint32_t slp_reject: 1; /*leep reject bit*/
|
||||
uint32_t sleep_en: 1; /*sleep enable bit*/
|
||||
};
|
||||
uint32_t val;
|
||||
} state0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cpu_stall_en: 1; /*CPU stall enable bit*/
|
||||
uint32_t cpu_stall_wait: 5; /*CPU stall wait cycles in fast_clk_rtc*/
|
||||
uint32_t ck8m_wait: 8; /*CK8M wait cycles in slow_clk_rtc*/
|
||||
uint32_t xtl_buf_wait: 10; /*XTAL wait cycles in slow_clk_rtc*/
|
||||
uint32_t pll_buf_wait: 8; /*PLL wait cycles in slow_clk_rtc*/
|
||||
};
|
||||
uint32_t val;
|
||||
} timer1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 24;
|
||||
uint32_t min_time_ck8m_off: 8; /*minimal cycles in slow_clk_rtc for CK8M in power down state*/
|
||||
};
|
||||
uint32_t val;
|
||||
} timer2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t wifi_wait_timer: 9;
|
||||
uint32_t wifi_powerup_timer: 7;
|
||||
uint32_t bt_wait_timer: 9;
|
||||
uint32_t bt_powerup_timer: 7;
|
||||
};
|
||||
uint32_t val;
|
||||
} timer3;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cpu_top_wait_timer: 9;
|
||||
uint32_t cpu_top_powerup_timer: 7;
|
||||
uint32_t dg_wrap_wait_timer: 9;
|
||||
uint32_t dg_wrap_powerup_timer: 7;
|
||||
};
|
||||
uint32_t val;
|
||||
} timer4;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 8;
|
||||
uint32_t min_slp_val: 8; /*minimal sleep cycles in slow_clk_rtc*/
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} timer5;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 16;
|
||||
uint32_t dg_peri_wait_timer: 9;
|
||||
uint32_t dg_peri_powerup_timer: 7;
|
||||
};
|
||||
uint32_t val;
|
||||
} timer6;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 18;
|
||||
uint32_t i2c_reset_por_force_pd: 1;
|
||||
uint32_t i2c_reset_por_force_pu: 1;
|
||||
uint32_t glitch_rst_en: 1;
|
||||
uint32_t reserved21: 1; /*PLLA force power down*/
|
||||
uint32_t sar_i2c_pu: 1; /*PLLA force power up*/
|
||||
uint32_t plla_force_pd: 1; /*PLLA force power down*/
|
||||
uint32_t plla_force_pu: 1; /*PLLA force power up*/
|
||||
uint32_t bbpll_cal_slp_start: 1; /*start BBPLL calibration during sleep*/
|
||||
uint32_t pvtmon_pu: 1; /*1: PVTMON power up*/
|
||||
uint32_t txrf_i2c_pu: 1; /*1: TXRF_I2C power up*/
|
||||
uint32_t rfrx_pbus_pu: 1; /*1: RFRX_PBUS power up*/
|
||||
uint32_t reserved29: 1;
|
||||
uint32_t ckgen_i2c_pu: 1; /*1: CKGEN_I2C power up*/
|
||||
uint32_t pll_i2c_pu: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} ana_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reset_cause_procpu: 6; /*reset cause of PRO CPU*/
|
||||
uint32_t reset_cause_appcpu: 6; /*reset cause of APP CPU*/
|
||||
uint32_t stat_vector_sel_appcpu: 1; /*APP CPU state vector sel*/
|
||||
uint32_t stat_vector_sel_procpu: 1; /*PRO CPU state vector sel*/
|
||||
uint32_t all_reset_flag_procpu: 1; /*PRO CPU reset_flag*/
|
||||
uint32_t all_reset_flag_appcpu: 1; /*APP CPU reset flag*/
|
||||
uint32_t all_reset_flag_clr_procpu: 1; /*clear PRO CPU reset_flag*/
|
||||
uint32_t all_reset_flag_clr_appcpu: 1; /*clear APP CPU reset flag*/
|
||||
uint32_t ocd_halt_on_reset_appcpu: 1; /*APPCPU OcdHaltOnReset*/
|
||||
uint32_t ocd_halt_on_reset_procpu: 1; /*PROCPU OcdHaltOnReset*/
|
||||
uint32_t jtag_reset_flag_procpu: 1;
|
||||
uint32_t jtag_reset_flag_appcpu: 1;
|
||||
uint32_t jtag_reset_flag_clr_procpu: 1;
|
||||
uint32_t jtag_reset_flag_clr_appcpu: 1;
|
||||
uint32_t rtc_dreset_mask_appcpu: 1;
|
||||
uint32_t rtc_dreset_mask_procpu: 1;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} reset_state;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 15;
|
||||
uint32_t rtc_wakeup_ena:17; /*wakeup enable bitmap*/
|
||||
};
|
||||
uint32_t val;
|
||||
} wakeup_state;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slp_wakeup: 1; /*enable sleep wakeup interrupt*/
|
||||
uint32_t slp_reject: 1; /*enable sleep reject interrupt*/
|
||||
uint32_t reserved2: 1; /*enable SDIO idle interrupt*/
|
||||
uint32_t rtc_wdt: 1; /*enable RTC WDT interrupt*/
|
||||
uint32_t reserved4: 5;
|
||||
uint32_t rtc_brown_out: 1; /*enable brown out interrupt*/
|
||||
uint32_t rtc_main_timer: 1; /*enable RTC main timer interrupt*/
|
||||
uint32_t reserved11: 4; /*enable saradc2 interrupt*/
|
||||
uint32_t rtc_swd: 1; /*enable super watch dog interrupt*/
|
||||
uint32_t rtc_xtal32k_dead: 1; /*enable xtal32k_dead interrupt*/
|
||||
uint32_t reserved17: 2; /*enable touch timeout interrupt*/
|
||||
uint32_t rtc_glitch_det: 1; /*enbale gitch det interrupt*/
|
||||
uint32_t rtc_bbpll_cal: 1;
|
||||
uint32_t reserved21: 11;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slp_wakeup: 1; /*sleep wakeup interrupt raw*/
|
||||
uint32_t slp_reject: 1; /*sleep reject interrupt raw*/
|
||||
uint32_t reserved2: 1; /*SDIO idle interrupt raw*/
|
||||
uint32_t rtc_wdt: 1; /*RTC WDT interrupt raw*/
|
||||
uint32_t reserved4: 5; /*touch inactive interrupt raw*/
|
||||
uint32_t rtc_brown_out: 1; /*brown out interrupt raw*/
|
||||
uint32_t rtc_main_timer: 1; /*RTC main timer interrupt raw*/
|
||||
uint32_t reserved11: 4; /*saradc2 interrupt raw*/
|
||||
uint32_t rtc_swd: 1; /*super watch dog interrupt raw*/
|
||||
uint32_t rtc_xtal32k_dead: 1; /*xtal32k dead detection interrupt raw*/
|
||||
uint32_t reserved17: 2; /*touch timeout interrupt raw*/
|
||||
uint32_t rtc_glitch_det: 1; /*glitch_det_interrupt_raw*/
|
||||
uint32_t rtc_bbpll_cal: 1;
|
||||
uint32_t reserved21: 11;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slp_wakeup: 1; /*sleep wakeup interrupt state*/
|
||||
uint32_t slp_reject: 1; /*sleep reject interrupt state*/
|
||||
uint32_t reserved2: 1;
|
||||
uint32_t rtc_wdt: 1; /*RTC WDT interrupt state*/
|
||||
uint32_t reserved4: 5;
|
||||
uint32_t rtc_brown_out: 1; /*brown out interrupt state*/
|
||||
uint32_t rtc_main_timer: 1; /*RTC main timer interrupt state*/
|
||||
uint32_t reserved11: 4;
|
||||
uint32_t rtc_swd: 1; /*super watch dog interrupt state*/
|
||||
uint32_t rtc_xtal32k_dead: 1; /*xtal32k dead detection interrupt state*/
|
||||
uint32_t reserved17: 2;
|
||||
uint32_t rtc_glitch_det: 1; /*glitch_det_interrupt state*/
|
||||
uint32_t rtc_bbpll_cal: 1;
|
||||
uint32_t reserved21: 11;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slp_wakeup: 1; /*Clear sleep wakeup interrupt state*/
|
||||
uint32_t slp_reject: 1; /*Clear sleep reject interrupt state*/
|
||||
uint32_t reserved2: 1;
|
||||
uint32_t rtc_wdt: 1; /*Clear RTC WDT interrupt state*/
|
||||
uint32_t reserved4: 5;
|
||||
uint32_t rtc_brown_out: 1; /*Clear brown out interrupt state*/
|
||||
uint32_t rtc_main_timer: 1; /*Clear RTC main timer interrupt state*/
|
||||
uint32_t reserved11: 4;
|
||||
uint32_t rtc_swd: 1; /*Clear super watch dog interrupt state*/
|
||||
uint32_t rtc_xtal32k_dead: 1; /*Clear RTC WDT interrupt state*/
|
||||
uint32_t reserved17: 2;
|
||||
uint32_t rtc_glitch_det: 1; /*Clear glitch det interrupt state*/
|
||||
uint32_t rtc_bbpll_cal: 1;
|
||||
uint32_t reserved21: 11;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_clr;
|
||||
uint32_t store[4]; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t xtal32k_wdt_en: 1; /*xtal 32k watch dog enable*/
|
||||
uint32_t xtal32k_wdt_clk_fo: 1; /*xtal 32k watch dog clock force on*/
|
||||
uint32_t xtal32k_wdt_reset: 1; /*xtal 32k watch dog sw reset*/
|
||||
uint32_t xtal32k_ext_clk_fo: 1; /*xtal 32k external xtal clock force on*/
|
||||
uint32_t xtal32k_auto_backup: 1; /*xtal 32k switch to back up clock when xtal is dead*/
|
||||
uint32_t xtal32k_auto_restart: 1; /*xtal 32k restart xtal when xtal is dead*/
|
||||
uint32_t xtal32k_auto_return: 1; /*xtal 32k switch back xtal when xtal is restarted*/
|
||||
uint32_t xtal32k_xpd_force: 1; /*Xtal 32k xpd control by sw or fsm*/
|
||||
uint32_t enckinit_xtal_32k: 1; /*apply an internal clock to help xtal 32k to start*/
|
||||
uint32_t dbuf_xtal_32k: 1; /*0: single-end buffer 1: differential buffer*/
|
||||
uint32_t dgm_xtal_32k: 3; /*xtal_32k gm control*/
|
||||
uint32_t dres_xtal_32k: 3; /*DRES_XTAL_32K*/
|
||||
uint32_t xpd_xtal_32k: 1; /*XPD_XTAL_32K*/
|
||||
uint32_t dac_xtal_32k: 3; /*DAC_XTAL_32K*/
|
||||
uint32_t rtc_wdt_state: 3; /*state of 32k_wdt*/
|
||||
uint32_t rtc_xtal32k_gpio_sel: 1; /*XTAL_32K sel. 0: external XTAL_32K*/
|
||||
uint32_t reserved24: 6;
|
||||
uint32_t ctr_lv: 1; /*0: power down XTAL at high level*/
|
||||
uint32_t ctr_en: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} ext_xtl_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 31;
|
||||
uint32_t gpio_wakeup_filter: 1; /*enable filter for gpio wakeup event*/
|
||||
};
|
||||
uint32_t val;
|
||||
} ext_wakeup_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 12;
|
||||
uint32_t rtc_sleep_reject_ena:18; /*sleep reject enable*/
|
||||
uint32_t light_slp_reject_en: 1; /*enable reject for light sleep*/
|
||||
uint32_t deep_slp_reject_en: 1; /*enable reject for deep sleep*/
|
||||
};
|
||||
uint32_t val;
|
||||
} slp_reject_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 29;
|
||||
uint32_t cpusel_conf: 1; /*CPU sel option*/
|
||||
uint32_t cpuperiod_sel: 2;
|
||||
};
|
||||
uint32_t val;
|
||||
} cpu_period_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 1;
|
||||
uint32_t efuse_clk_force_gating: 1;
|
||||
uint32_t efuse_clk_force_nogating: 1;
|
||||
uint32_t ck8m_div_sel_vld: 1; /*used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel*/
|
||||
uint32_t ck8m_div: 2; /*CK8M_D256_OUT divider. 00: div128*/
|
||||
uint32_t enb_ck8m: 1; /*disable CK8M and CK8M_D256_OUT*/
|
||||
uint32_t enb_ck8m_div: 1; /*1: CK8M_D256_OUT is actually CK8M*/
|
||||
uint32_t dig_xtal32k_en: 1; /*enable CK_XTAL_32K for digital core (no relationship with RTC core)*/
|
||||
uint32_t dig_clk8m_d256_en: 1; /*enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/
|
||||
uint32_t dig_clk8m_en: 1; /*enable CK8M for digital core (no relationship with RTC core)*/
|
||||
uint32_t reserved11: 1;
|
||||
uint32_t ck8m_div_sel: 3; /*divider = reg_ck8m_div_sel + 1*/
|
||||
uint32_t xtal_force_nogating: 1; /*XTAL force no gating during sleep*/
|
||||
uint32_t ck8m_force_nogating: 1; /*CK8M force no gating during sleep*/
|
||||
uint32_t ck8m_dfreq: 8; /*CK8M_DFREQ*/
|
||||
uint32_t ck8m_force_pd: 1; /*CK8M force power down*/
|
||||
uint32_t ck8m_force_pu: 1; /*CK8M force power up*/
|
||||
uint32_t xtal_global_force_gating: 1;
|
||||
uint32_t xtal_global_force_nogating: 1;
|
||||
uint32_t fast_clk_rtc_sel: 1; /*fast_clk_rtc sel. 0: XTAL div 2*/
|
||||
uint32_t ana_clk_rtc_sel: 2;
|
||||
};
|
||||
uint32_t val;
|
||||
} clk_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 22;
|
||||
uint32_t rtc_ana_clk_div_vld: 1; /*used to sync div bus. clear vld before set reg_rtc_ana_clk_div*/
|
||||
uint32_t rtc_ana_clk_div: 8;
|
||||
uint32_t slow_clk_next_edge: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} slow_clk_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sdio_timer_target: 8; /*timer count to apply reg_sdio_dcap after sdio power on*/
|
||||
uint32_t reserved8: 1;
|
||||
uint32_t sdio_dthdrv: 2; /*Tieh = 1 mode drive ability. Initially set to 0 to limit charge current*/
|
||||
uint32_t sdio_dcap: 2; /*ability to prevent LDO from overshoot*/
|
||||
uint32_t sdio_initi: 2; /*add resistor from ldo output to ground. 0: no res*/
|
||||
uint32_t sdio_en_initi: 1; /*0 to set init[1:0]=0*/
|
||||
uint32_t sdio_dcurlim: 3; /*tune current limit threshold when tieh = 0. About 800mA/(8+d)*/
|
||||
uint32_t sdio_modecurlim: 1; /*select current limit mode*/
|
||||
uint32_t sdio_encurlim: 1; /*enable current limit*/
|
||||
uint32_t sdio_pd_en: 1; /*power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/
|
||||
uint32_t sdio_force: 1; /*1: use SW option to control SDIO_REG*/
|
||||
uint32_t sdio_tieh: 1; /*SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/
|
||||
uint32_t reg1p8_ready: 1; /*read only register for REG1P8_READY*/
|
||||
uint32_t drefl_sdio: 2; /*SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/
|
||||
uint32_t drefm_sdio: 2; /*SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/
|
||||
uint32_t drefh_sdio: 2; /*SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/
|
||||
uint32_t xpd_sdio: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} sdio_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dg_vdd_drv_b_slp: 8;
|
||||
uint32_t dg_vdd_drv_b_slp_en: 1;
|
||||
uint32_t reserved9: 1;
|
||||
uint32_t bias_buf_idle: 1;
|
||||
uint32_t bias_buf_wake: 1;
|
||||
uint32_t bias_buf_deep_slp: 1;
|
||||
uint32_t bias_buf_monitor: 1;
|
||||
uint32_t pd_cur_deep_slp: 1; /*xpd cur when rtc in sleep_state*/
|
||||
uint32_t pd_cur_monitor: 1; /*xpd cur when rtc in monitor state*/
|
||||
uint32_t bias_sleep_deep_slp: 1; /*bias_sleep when rtc in sleep_state*/
|
||||
uint32_t bias_sleep_monitor: 1; /*bias_sleep when rtc in monitor state*/
|
||||
uint32_t dbg_atten_deep_slp: 4; /*DBG_ATTEN when rtc in sleep state*/
|
||||
uint32_t dbg_atten_monitor: 4; /*DBG_ATTEN when rtc in monitor state*/
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} bias_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 7;
|
||||
uint32_t dig_cal_en: 1;
|
||||
uint32_t reserved8: 6;
|
||||
uint32_t sck_dcap: 8; /*SCK_DCAP*/
|
||||
uint32_t reserved22: 6;
|
||||
uint32_t rtc_dboost_force_pd: 1; /*RTC_DBOOST force power down*/
|
||||
uint32_t rtc_dboost_force_pu: 1; /*RTC_DBOOST force power up*/
|
||||
uint32_t rtculator_force_pd: 1; /*RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )*/
|
||||
uint32_t rtculator_force_pu: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 21;
|
||||
uint32_t rtc_pad_force_hold: 1; /*rtc pad force hold*/
|
||||
uint32_t reserved22: 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_pwc;
|
||||
union {
|
||||
struct {
|
||||
uint32_t vdd_spi_pwr_drv: 2;
|
||||
uint32_t vdd_spi_pwr_force: 1;
|
||||
uint32_t lslp_mem_force_pd: 1; /*memories in digital core force PD in sleep*/
|
||||
uint32_t lslp_mem_force_pu: 1; /*memories in digital core force no PD in sleep*/
|
||||
uint32_t reserved5: 6;
|
||||
uint32_t bt_force_pd: 1;
|
||||
uint32_t bt_force_pu: 1;
|
||||
uint32_t dg_peri_force_pd: 1;
|
||||
uint32_t dg_peri_force_pu: 1;
|
||||
uint32_t fastmem_force_lpd: 1;
|
||||
uint32_t fastmem_force_lpu: 1;
|
||||
uint32_t wifi_force_pd: 1; /*wifi force power down*/
|
||||
uint32_t wifi_force_pu: 1; /*wifi force power up*/
|
||||
uint32_t dg_wrap_force_pd: 1; /*digital core force power down*/
|
||||
uint32_t dg_wrap_force_pu: 1; /*digital core force power up*/
|
||||
uint32_t cpu_top_force_pd: 1;
|
||||
uint32_t cpu_top_force_pu: 1;
|
||||
uint32_t reserved23: 4;
|
||||
uint32_t bt_pd_en: 1;
|
||||
uint32_t dg_peri_pd_en: 1;
|
||||
uint32_t cpu_top_pd_en: 1;
|
||||
uint32_t wifi_pd_en: 1; /*enable power down wifi in sleep*/
|
||||
uint32_t dg_wrap_pd_en: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} dig_pwc;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 7;
|
||||
uint32_t dig_iso_force_off: 1;
|
||||
uint32_t dig_iso_force_on: 1;
|
||||
uint32_t dg_pad_autohold: 1; /*read only register to indicate digital pad auto-hold status*/
|
||||
uint32_t clr_dg_pad_autohold: 1; /*wtite only register to clear digital pad auto-hold*/
|
||||
uint32_t dg_pad_autohold_en: 1; /*digital pad enable auto-hold*/
|
||||
uint32_t dg_pad_force_noiso: 1; /*digital pad force no ISO*/
|
||||
uint32_t dg_pad_force_iso: 1; /*digital pad force ISO*/
|
||||
uint32_t dg_pad_force_unhold: 1; /*digital pad force un-hold*/
|
||||
uint32_t dg_pad_force_hold: 1; /*digital pad force hold*/
|
||||
uint32_t reserved16: 6;
|
||||
uint32_t bt_force_iso: 1;
|
||||
uint32_t bt_force_noiso: 1;
|
||||
uint32_t dg_peri_force_iso: 1;
|
||||
uint32_t dg_peri_force_noiso: 1;
|
||||
uint32_t cpu_top_force_iso: 1; /*cpu force ISO*/
|
||||
uint32_t cpu_top_force_noiso: 1; /*cpu force no ISO*/
|
||||
uint32_t wifi_force_iso: 1; /*wifi force ISO*/
|
||||
uint32_t wifi_force_noiso: 1; /*wifi force no ISO*/
|
||||
uint32_t dg_wrap_force_iso: 1; /*digital core force ISO*/
|
||||
uint32_t dg_wrap_force_noiso: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} dig_iso;
|
||||
union {
|
||||
struct {
|
||||
uint32_t chip_reset_width: 8; /*chip reset siginal pulse width*/
|
||||
uint32_t chip_reset_en: 1; /*wdt reset whole chip enable*/
|
||||
uint32_t pause_in_slp: 1; /*pause WDT in sleep*/
|
||||
uint32_t appcpu_reset_en: 1; /*enable WDT reset APP CPU*/
|
||||
uint32_t procpu_reset_en: 1; /*enable WDT reset PRO CPU*/
|
||||
uint32_t flashboot_mod_en: 1; /*enable WDT in flash boot*/
|
||||
uint32_t sys_reset_length: 3; /*system reset counter length*/
|
||||
uint32_t cpu_reset_length: 3; /*CPU reset counter length*/
|
||||
uint32_t stg3: 3; /*1: interrupt stage en*/
|
||||
uint32_t stg2: 3; /*1: interrupt stage en*/
|
||||
uint32_t stg1: 3; /*1: interrupt stage en*/
|
||||
uint32_t stg0: 3; /*1: interrupt stage en*/
|
||||
uint32_t en: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} wdt_config0;
|
||||
uint32_t wdt_config1; /**/
|
||||
uint32_t wdt_config2; /**/
|
||||
uint32_t wdt_config3; /**/
|
||||
uint32_t wdt_config4; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 31;
|
||||
uint32_t feed: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} wdt_feed;
|
||||
uint32_t wdt_wprotect; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t swd_reset_flag: 1; /*swd reset flag*/
|
||||
uint32_t swd_feed_int: 1; /*swd interrupt for feeding*/
|
||||
uint32_t reserved2: 15;
|
||||
uint32_t swd_bypass_rst: 1;
|
||||
uint32_t swd_signal_width:10; /*adjust signal width send to swd*/
|
||||
uint32_t swd_rst_flag_clr: 1; /*reset swd reset flag*/
|
||||
uint32_t swd_feed: 1; /*Sw feed swd*/
|
||||
uint32_t swd_disable: 1; /*disabel SWD*/
|
||||
uint32_t swd_auto_feed_en: 1; /*automatically feed swd when int comes*/
|
||||
};
|
||||
uint32_t val;
|
||||
} swd_conf;
|
||||
uint32_t swd_wprotect; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 20;
|
||||
uint32_t appcpu_c1: 6; /*{reg_sw_stall_appcpu_c1[5:0]*/
|
||||
uint32_t procpu_c1: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} sw_cpu_stall;
|
||||
uint32_t store4; /**/
|
||||
uint32_t store5; /**/
|
||||
uint32_t store6; /**/
|
||||
uint32_t store7; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t xpd_rom0: 1; /*rom0 power down*/
|
||||
uint32_t reserved1: 1;
|
||||
uint32_t xpd_dig_dcdc: 1; /*External DCDC power down*/
|
||||
uint32_t rtc_peri_iso: 1; /*rtc peripheral iso*/
|
||||
uint32_t xpd_rtc_peri: 1; /*rtc peripheral power down*/
|
||||
uint32_t wifi_iso: 1; /*wifi iso*/
|
||||
uint32_t xpd_wifi: 1; /*wifi wrap power down*/
|
||||
uint32_t dig_iso: 1; /*digital wrap iso*/
|
||||
uint32_t xpd_dig: 1; /*digital wrap power down*/
|
||||
uint32_t rtc_touch_state_start: 1; /*touch should start to work*/
|
||||
uint32_t rtc_touch_state_switch: 1; /*touch is about to working. Switch rtc main state*/
|
||||
uint32_t rtc_touch_state_slp: 1; /*touch is in sleep state*/
|
||||
uint32_t rtc_touch_state_done: 1; /*touch is done*/
|
||||
uint32_t rtc_cocpu_state_start: 1; /*ulp/cocpu should start to work*/
|
||||
uint32_t rtc_cocpu_state_switch: 1; /*ulp/cocpu is about to working. Switch rtc main state*/
|
||||
uint32_t rtc_cocpu_state_slp: 1; /*ulp/cocpu is in sleep state*/
|
||||
uint32_t rtc_cocpu_state_done: 1; /*ulp/cocpu is done*/
|
||||
uint32_t rtc_main_state_xtal_iso: 1; /*no use any more*/
|
||||
uint32_t rtc_main_state_pll_on: 1; /*rtc main state machine is in states that pll should be running*/
|
||||
uint32_t rtc_rdy_for_wakeup: 1; /*rtc is ready to receive wake up trigger from wake up source*/
|
||||
uint32_t rtc_main_state_wait_end: 1; /*rtc main state machine has been waited for some cycles*/
|
||||
uint32_t rtc_in_wakeup_state: 1; /*rtc main state machine is in the states of wakeup process*/
|
||||
uint32_t rtc_in_low_power_state: 1; /*rtc main state machine is in the states of low power*/
|
||||
uint32_t rtc_main_state_in_wait_8m: 1; /*rtc main state machine is in wait 8m state*/
|
||||
uint32_t rtc_main_state_in_wait_pll: 1; /*rtc main state machine is in wait pll state*/
|
||||
uint32_t rtc_main_state_in_wait_xtl: 1; /*rtc main state machine is in wait xtal state*/
|
||||
uint32_t rtc_main_state_in_slp: 1; /*rtc main state machine is in sleep state*/
|
||||
uint32_t rtc_main_state_in_idle: 1; /*rtc main state machine is in idle state*/
|
||||
uint32_t rtc_main_state: 4; /*rtc main state machine status*/
|
||||
};
|
||||
uint32_t val;
|
||||
} low_power_st;
|
||||
uint32_t diag0; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t rtc_gpio_pin0_hold: 1;
|
||||
uint32_t rtc_gpio_pin1_hold: 1;
|
||||
uint32_t rtc_gpio_pin2_hold: 1;
|
||||
uint32_t rtc_gpio_pin3_hold: 1;
|
||||
uint32_t rtc_gpio_pin4_hold: 1;
|
||||
uint32_t rtc_gpio_pin5_hold: 1;
|
||||
uint32_t reserved6: 26;
|
||||
};
|
||||
uint32_t val;
|
||||
} pad_hold;
|
||||
uint32_t dig_pad_hold; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 4;
|
||||
uint32_t int_wait: 10; /*brown out interrupt wait cycles*/
|
||||
uint32_t close_flash_ena: 1; /*enable close flash when brown out happens*/
|
||||
uint32_t pd_rf_ena: 1; /*enable power down RF when brown out happens*/
|
||||
uint32_t rst_wait: 10; /*brown out reset wait cycles*/
|
||||
uint32_t rst_ena: 1; /*enable brown out reset*/
|
||||
uint32_t rst_sel: 1; /*1: 4-pos reset*/
|
||||
uint32_t ana_rst_en: 1;
|
||||
uint32_t cnt_clr: 1; /*clear brown out counter*/
|
||||
uint32_t ena: 1; /*enable brown out*/
|
||||
uint32_t det: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} brown_out;
|
||||
uint32_t time_low1; /*RTC timer low 32 bits*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t rtc_timer_value1_high:16; /*RTC timer high 16 bits*/
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} time_high1;
|
||||
uint32_t xtal32k_clk_factor; /*xtal 32k watch dog backup clock factor*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t xtal32k_return_wait: 4; /*cycles to wait to return noral xtal 32k*/
|
||||
uint32_t xtal32k_restart_wait:16; /*cycles to wait to repower on xtal 32k*/
|
||||
uint32_t xtal32k_wdt_timeout: 8; /*If no clock detected for this amount of time*/
|
||||
uint32_t xtal32k_stable_thres: 4; /*if restarted xtal32k period is smaller than this*/
|
||||
};
|
||||
uint32_t val;
|
||||
} xtal32k_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 18;
|
||||
uint32_t io_mux_reset_disable: 1;
|
||||
uint32_t reserved19: 13;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reject_cause:18; /*sleep reject cause*/
|
||||
uint32_t reserved18: 14;
|
||||
};
|
||||
uint32_t val;
|
||||
} slp_reject_cause;
|
||||
union {
|
||||
struct {
|
||||
uint32_t force_download_boot: 1;
|
||||
uint32_t reserved1: 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} option1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t wakeup_cause:17; /*sleep wakeup cause*/
|
||||
uint32_t reserved17: 15;
|
||||
};
|
||||
uint32_t val;
|
||||
} slp_wakeup_cause;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 8;
|
||||
uint32_t ulp_cp_timer_slp_cycle:24; /*sleep cycles for ULP-coprocessor timer*/
|
||||
};
|
||||
uint32_t val;
|
||||
} ulp_cp_timer_1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slp_wakeup_w1ts: 1; /*enable sleep wakeup interrupt*/
|
||||
uint32_t slp_reject_w1ts: 1; /*enable sleep reject interrupt*/
|
||||
uint32_t reserved2: 1;
|
||||
uint32_t rtc_wdt_w1ts: 1; /*enable RTC WDT interrupt*/
|
||||
uint32_t reserved4: 5;
|
||||
uint32_t w1ts: 1; /*enable brown out interrupt*/
|
||||
uint32_t rtc_main_timer_w1ts: 1; /*enable RTC main timer interrupt*/
|
||||
uint32_t reserved11: 4;
|
||||
uint32_t rtc_swd_w1ts: 1; /*enable super watch dog interrupt*/
|
||||
uint32_t rtc_xtal32k_dead_w1ts: 1; /*enable xtal32k_dead interrupt*/
|
||||
uint32_t reserved17: 2;
|
||||
uint32_t rtc_glitch_det_w1ts: 1; /*enbale gitch det interrupt*/
|
||||
uint32_t rtc_bbpll_cal_w1ts: 1;
|
||||
uint32_t reserved21: 11;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_ena_w1ts;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slp_wakeup_w1tc: 1; /*enable sleep wakeup interrupt*/
|
||||
uint32_t slp_reject_w1tc: 1; /*enable sleep reject interrupt*/
|
||||
uint32_t reserved2: 1;
|
||||
uint32_t rtc_wdt_w1tc: 1; /*enable RTC WDT interrupt*/
|
||||
uint32_t reserved4: 5;
|
||||
uint32_t w1tc: 1; /*enable brown out interrupt*/
|
||||
uint32_t rtc_main_timer_w1tc: 1; /*enable RTC main timer interrupt*/
|
||||
uint32_t reserved11: 4;
|
||||
uint32_t rtc_swd_w1tc: 1; /*enable super watch dog interrupt*/
|
||||
uint32_t rtc_xtal32k_dead_w1tc: 1; /*enable xtal32k_dead interrupt*/
|
||||
uint32_t reserved17: 2;
|
||||
uint32_t rtc_glitch_det_w1tc: 1; /*enbale gitch det interrupt*/
|
||||
uint32_t rtc_bbpll_cal_w1tc: 1;
|
||||
uint32_t reserved21: 11;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_ena_w1tc;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 18;
|
||||
uint32_t retention_clk_sel: 1;
|
||||
uint32_t retention_done_wait: 3;
|
||||
uint32_t retention_clkoff_wait: 4;
|
||||
uint32_t retention_en: 1;
|
||||
uint32_t retention_wait: 5; /*wait cycles for rention operation*/
|
||||
};
|
||||
uint32_t val;
|
||||
} retention_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rtc_fib_sel: 3; /*select use analog fib signal*/
|
||||
uint32_t reserved3: 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} fib_sel;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rtc_gpio_wakeup_status: 6;
|
||||
uint32_t rtc_gpio_wakeup_status_clr: 1;
|
||||
uint32_t rtc_gpio_pin_clk_gate: 1;
|
||||
uint32_t rtc_gpio_pin5_int_type: 3;
|
||||
uint32_t rtc_gpio_pin4_int_type: 3;
|
||||
uint32_t rtc_gpio_pin3_int_type: 3;
|
||||
uint32_t rtc_gpio_pin2_int_type: 3;
|
||||
uint32_t rtc_gpio_pin1_int_type: 3;
|
||||
uint32_t rtc_gpio_pin0_int_type: 3;
|
||||
uint32_t rtc_gpio_pin5_wakeup_enable: 1;
|
||||
uint32_t rtc_gpio_pin4_wakeup_enable: 1;
|
||||
uint32_t rtc_gpio_pin3_wakeup_enable: 1;
|
||||
uint32_t rtc_gpio_pin2_wakeup_enable: 1;
|
||||
uint32_t rtc_gpio_pin1_wakeup_enable: 1;
|
||||
uint32_t rtc_gpio_pin0_wakeup_enable: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} gpio_wakeup;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 1;
|
||||
uint32_t rtc_debug_12m_no_gating: 1;
|
||||
uint32_t rtc_debug_bit_sel: 5;
|
||||
uint32_t rtc_debug_sel0: 5;
|
||||
uint32_t rtc_debug_sel1: 5;
|
||||
uint32_t rtc_debug_sel2: 5;
|
||||
uint32_t rtc_debug_sel3: 5;
|
||||
uint32_t rtc_debug_sel4: 5;
|
||||
};
|
||||
uint32_t val;
|
||||
} dbg_sel;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 2;
|
||||
uint32_t rtc_gpio_pin5_mux_sel: 1;
|
||||
uint32_t rtc_gpio_pin4_mux_sel: 1;
|
||||
uint32_t rtc_gpio_pin3_mux_sel: 1;
|
||||
uint32_t rtc_gpio_pin2_mux_sel: 1;
|
||||
uint32_t rtc_gpio_pin1_mux_sel: 1;
|
||||
uint32_t rtc_gpio_pin0_mux_sel: 1;
|
||||
uint32_t rtc_gpio_pin5_fun_sel: 4;
|
||||
uint32_t rtc_gpio_pin4_fun_sel: 4;
|
||||
uint32_t rtc_gpio_pin3_fun_sel: 4;
|
||||
uint32_t rtc_gpio_pin2_fun_sel: 4;
|
||||
uint32_t rtc_gpio_pin1_fun_sel: 4;
|
||||
uint32_t rtc_gpio_pin0_fun_sel: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} dbg_map;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 27;
|
||||
uint32_t sar2_pwdet_cct: 3;
|
||||
uint32_t force_xpd_sar: 2;
|
||||
};
|
||||
uint32_t val;
|
||||
} sensor_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 27;
|
||||
uint32_t sar_debug_sel: 5;
|
||||
};
|
||||
uint32_t val;
|
||||
} dbg_sar_sel;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 26;
|
||||
uint32_t power_glitch_dsense: 2;
|
||||
uint32_t power_glitch_force_pd: 1;
|
||||
uint32_t power_glitch_force_pu: 1;
|
||||
uint32_t power_glitch_efuse_sel: 1;
|
||||
uint32_t power_glitch_en: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} pg_ctrl;
|
||||
uint32_t reserved_128;
|
||||
uint32_t reserved_12c;
|
||||
uint32_t reserved_130;
|
||||
uint32_t reserved_134;
|
||||
uint32_t reserved_138;
|
||||
uint32_t reserved_13c;
|
||||
uint32_t reserved_140;
|
||||
uint32_t reserved_144;
|
||||
uint32_t reserved_148;
|
||||
uint32_t reserved_14c;
|
||||
uint32_t reserved_150;
|
||||
uint32_t reserved_154;
|
||||
uint32_t reserved_158;
|
||||
uint32_t reserved_15c;
|
||||
uint32_t reserved_160;
|
||||
uint32_t reserved_164;
|
||||
uint32_t reserved_168;
|
||||
uint32_t reserved_16c;
|
||||
uint32_t reserved_170;
|
||||
uint32_t reserved_174;
|
||||
uint32_t reserved_178;
|
||||
uint32_t reserved_17c;
|
||||
uint32_t reserved_180;
|
||||
uint32_t reserved_184;
|
||||
uint32_t reserved_188;
|
||||
uint32_t reserved_18c;
|
||||
uint32_t reserved_190;
|
||||
uint32_t reserved_194;
|
||||
uint32_t reserved_198;
|
||||
uint32_t reserved_19c;
|
||||
uint32_t reserved_1a0;
|
||||
uint32_t reserved_1a4;
|
||||
uint32_t reserved_1a8;
|
||||
uint32_t reserved_1ac;
|
||||
uint32_t reserved_1b0;
|
||||
uint32_t reserved_1b4;
|
||||
uint32_t reserved_1b8;
|
||||
uint32_t reserved_1bc;
|
||||
uint32_t reserved_1c0;
|
||||
uint32_t reserved_1c4;
|
||||
uint32_t reserved_1c8;
|
||||
uint32_t reserved_1cc;
|
||||
uint32_t reserved_1d0;
|
||||
uint32_t reserved_1d4;
|
||||
uint32_t reserved_1d8;
|
||||
uint32_t reserved_1dc;
|
||||
uint32_t reserved_1e0;
|
||||
uint32_t reserved_1e4;
|
||||
uint32_t reserved_1e8;
|
||||
uint32_t reserved_1ec;
|
||||
uint32_t reserved_1f0;
|
||||
uint32_t reserved_1f4;
|
||||
uint32_t reserved_1f8;
|
||||
union {
|
||||
struct {
|
||||
uint32_t date: 28;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} date;
|
||||
} rtc_cntl_dev_t;
|
||||
extern rtc_cntl_dev_t RTCCNTL;
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,684 +0,0 @@
|
||||
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_RTC_I2C_REG_H_
|
||||
#define _SOC_RTC_I2C_REG_H_
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#include "soc.h"
|
||||
#define RTC_I2C_SCL_LOW_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x0000)
|
||||
/* RTC_I2C_SCL_LOW_PERIOD : R/W ;bitpos:[19:0] ;default: 20'h100 ; */
|
||||
/*description: time period that scl = 0*/
|
||||
#define RTC_I2C_SCL_LOW_PERIOD 0x000FFFFF
|
||||
#define RTC_I2C_SCL_LOW_PERIOD_M ((RTC_I2C_SCL_LOW_PERIOD_V)<<(RTC_I2C_SCL_LOW_PERIOD_S))
|
||||
#define RTC_I2C_SCL_LOW_PERIOD_V 0xFFFFF
|
||||
#define RTC_I2C_SCL_LOW_PERIOD_S 0
|
||||
|
||||
#define RTC_I2C_CTRL_REG (DR_REG_RTC_I2C_BASE + 0x0004)
|
||||
/* RTC_I2C_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: rtc i2c reg clk gating*/
|
||||
#define RTC_I2C_CLK_EN (BIT(31))
|
||||
#define RTC_I2C_CLK_EN_M (BIT(31))
|
||||
#define RTC_I2C_CLK_EN_V 0x1
|
||||
#define RTC_I2C_CLK_EN_S 31
|
||||
/* RTC_I2C_RESET : R/W ;bitpos:[30] ;default: 1'b0 ; */
|
||||
/*description: rtc i2c sw reset*/
|
||||
#define RTC_I2C_RESET (BIT(30))
|
||||
#define RTC_I2C_RESET_M (BIT(30))
|
||||
#define RTC_I2C_RESET_V 0x1
|
||||
#define RTC_I2C_RESET_S 30
|
||||
/* RTC_I2C_CTRL_CLK_GATE_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define RTC_I2C_CTRL_CLK_GATE_EN (BIT(29))
|
||||
#define RTC_I2C_CTRL_CLK_GATE_EN_M (BIT(29))
|
||||
#define RTC_I2C_CTRL_CLK_GATE_EN_V 0x1
|
||||
#define RTC_I2C_CTRL_CLK_GATE_EN_S 29
|
||||
/* RTC_I2C_RX_LSB_FIRST : R/W ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: receive lsb first*/
|
||||
#define RTC_I2C_RX_LSB_FIRST (BIT(5))
|
||||
#define RTC_I2C_RX_LSB_FIRST_M (BIT(5))
|
||||
#define RTC_I2C_RX_LSB_FIRST_V 0x1
|
||||
#define RTC_I2C_RX_LSB_FIRST_S 5
|
||||
/* RTC_I2C_TX_LSB_FIRST : R/W ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: transit lsb first*/
|
||||
#define RTC_I2C_TX_LSB_FIRST (BIT(4))
|
||||
#define RTC_I2C_TX_LSB_FIRST_M (BIT(4))
|
||||
#define RTC_I2C_TX_LSB_FIRST_V 0x1
|
||||
#define RTC_I2C_TX_LSB_FIRST_S 4
|
||||
/* RTC_I2C_TRANS_START : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: force start*/
|
||||
#define RTC_I2C_TRANS_START (BIT(3))
|
||||
#define RTC_I2C_TRANS_START_M (BIT(3))
|
||||
#define RTC_I2C_TRANS_START_V 0x1
|
||||
#define RTC_I2C_TRANS_START_S 3
|
||||
/* RTC_I2C_MS_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: 1=master 0=slave*/
|
||||
#define RTC_I2C_MS_MODE (BIT(2))
|
||||
#define RTC_I2C_MS_MODE_M (BIT(2))
|
||||
#define RTC_I2C_MS_MODE_V 0x1
|
||||
#define RTC_I2C_MS_MODE_S 2
|
||||
/* RTC_I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: 1=push pull 0=open drain*/
|
||||
#define RTC_I2C_SCL_FORCE_OUT (BIT(1))
|
||||
#define RTC_I2C_SCL_FORCE_OUT_M (BIT(1))
|
||||
#define RTC_I2C_SCL_FORCE_OUT_V 0x1
|
||||
#define RTC_I2C_SCL_FORCE_OUT_S 1
|
||||
/* RTC_I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: 1=push pull 0=open drain*/
|
||||
#define RTC_I2C_SDA_FORCE_OUT (BIT(0))
|
||||
#define RTC_I2C_SDA_FORCE_OUT_M (BIT(0))
|
||||
#define RTC_I2C_SDA_FORCE_OUT_V 0x1
|
||||
#define RTC_I2C_SDA_FORCE_OUT_S 0
|
||||
|
||||
#define RTC_I2C_STATUS_REG (DR_REG_RTC_I2C_BASE + 0x0008)
|
||||
/* RTC_I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */
|
||||
/*description: scl last status*/
|
||||
#define RTC_I2C_SCL_STATE_LAST 0x00000007
|
||||
#define RTC_I2C_SCL_STATE_LAST_M ((RTC_I2C_SCL_STATE_LAST_V)<<(RTC_I2C_SCL_STATE_LAST_S))
|
||||
#define RTC_I2C_SCL_STATE_LAST_V 0x7
|
||||
#define RTC_I2C_SCL_STATE_LAST_S 28
|
||||
/* RTC_I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */
|
||||
/*description: i2c last main status*/
|
||||
#define RTC_I2C_SCL_MAIN_STATE_LAST 0x00000007
|
||||
#define RTC_I2C_SCL_MAIN_STATE_LAST_M ((RTC_I2C_SCL_MAIN_STATE_LAST_V)<<(RTC_I2C_SCL_MAIN_STATE_LAST_S))
|
||||
#define RTC_I2C_SCL_MAIN_STATE_LAST_V 0x7
|
||||
#define RTC_I2C_SCL_MAIN_STATE_LAST_S 24
|
||||
/* RTC_I2C_SHIFT : RO ;bitpos:[23:16] ;default: 8'b0 ; */
|
||||
/*description: shifter content*/
|
||||
#define RTC_I2C_SHIFT 0x000000FF
|
||||
#define RTC_I2C_SHIFT_M ((RTC_I2C_SHIFT_V)<<(RTC_I2C_SHIFT_S))
|
||||
#define RTC_I2C_SHIFT_V 0xFF
|
||||
#define RTC_I2C_SHIFT_S 16
|
||||
/* RTC_I2C_OP_CNT : RO ;bitpos:[7:6] ;default: 2'b0 ; */
|
||||
/*description: which operation is working*/
|
||||
#define RTC_I2C_OP_CNT 0x00000003
|
||||
#define RTC_I2C_OP_CNT_M ((RTC_I2C_OP_CNT_V)<<(RTC_I2C_OP_CNT_S))
|
||||
#define RTC_I2C_OP_CNT_V 0x3
|
||||
#define RTC_I2C_OP_CNT_S 6
|
||||
/* RTC_I2C_BYTE_TRANS : RO ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: One byte transit done*/
|
||||
#define RTC_I2C_BYTE_TRANS (BIT(5))
|
||||
#define RTC_I2C_BYTE_TRANS_M (BIT(5))
|
||||
#define RTC_I2C_BYTE_TRANS_V 0x1
|
||||
#define RTC_I2C_BYTE_TRANS_S 5
|
||||
/* RTC_I2C_SLAVE_ADDRESSED : RO ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: slave reg sub address*/
|
||||
#define RTC_I2C_SLAVE_ADDRESSED (BIT(4))
|
||||
#define RTC_I2C_SLAVE_ADDRESSED_M (BIT(4))
|
||||
#define RTC_I2C_SLAVE_ADDRESSED_V 0x1
|
||||
#define RTC_I2C_SLAVE_ADDRESSED_S 4
|
||||
/* RTC_I2C_BUS_BUSY : RO ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: bus is busy*/
|
||||
#define RTC_I2C_BUS_BUSY (BIT(3))
|
||||
#define RTC_I2C_BUS_BUSY_M (BIT(3))
|
||||
#define RTC_I2C_BUS_BUSY_V 0x1
|
||||
#define RTC_I2C_BUS_BUSY_S 3
|
||||
/* RTC_I2C_ARB_LOST : RO ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: arbitration is lost*/
|
||||
#define RTC_I2C_ARB_LOST (BIT(2))
|
||||
#define RTC_I2C_ARB_LOST_M (BIT(2))
|
||||
#define RTC_I2C_ARB_LOST_V 0x1
|
||||
#define RTC_I2C_ARB_LOST_S 2
|
||||
/* RTC_I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: slave read or write*/
|
||||
#define RTC_I2C_SLAVE_RW (BIT(1))
|
||||
#define RTC_I2C_SLAVE_RW_M (BIT(1))
|
||||
#define RTC_I2C_SLAVE_RW_V 0x1
|
||||
#define RTC_I2C_SLAVE_RW_S 1
|
||||
/* RTC_I2C_ACK_REC : RO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: ack response*/
|
||||
#define RTC_I2C_ACK_REC (BIT(0))
|
||||
#define RTC_I2C_ACK_REC_M (BIT(0))
|
||||
#define RTC_I2C_ACK_REC_V 0x1
|
||||
#define RTC_I2C_ACK_REC_S 0
|
||||
|
||||
#define RTC_I2C_TIMEOUT_REG (DR_REG_RTC_I2C_BASE + 0x000c)
|
||||
/* RTC_I2C_TIMEOUT : R/W ;bitpos:[19:0] ;default: 20'h10000 ; */
|
||||
/*description: time out threshold*/
|
||||
#define RTC_I2C_TIMEOUT 0x000FFFFF
|
||||
#define RTC_I2C_TIMEOUT_M ((RTC_I2C_TIMEOUT_V)<<(RTC_I2C_TIMEOUT_S))
|
||||
#define RTC_I2C_TIMEOUT_V 0xFFFFF
|
||||
#define RTC_I2C_TIMEOUT_S 0
|
||||
|
||||
#define RTC_I2C_SLAVE_ADDR_REG (DR_REG_RTC_I2C_BASE + 0x0010)
|
||||
/* RTC_I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: i2c 10bit mode enable*/
|
||||
#define RTC_I2C_ADDR_10BIT_EN (BIT(31))
|
||||
#define RTC_I2C_ADDR_10BIT_EN_M (BIT(31))
|
||||
#define RTC_I2C_ADDR_10BIT_EN_V 0x1
|
||||
#define RTC_I2C_ADDR_10BIT_EN_S 31
|
||||
/* RTC_I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */
|
||||
/*description: slave address*/
|
||||
#define RTC_I2C_SLAVE_ADDR 0x00007FFF
|
||||
#define RTC_I2C_SLAVE_ADDR_M ((RTC_I2C_SLAVE_ADDR_V)<<(RTC_I2C_SLAVE_ADDR_S))
|
||||
#define RTC_I2C_SLAVE_ADDR_V 0x7FFF
|
||||
#define RTC_I2C_SLAVE_ADDR_S 0
|
||||
|
||||
#define RTC_I2C_SCL_HIGH_REG (DR_REG_RTC_I2C_BASE + 0x0014)
|
||||
/* RTC_I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[19:0] ;default: 20'h100 ; */
|
||||
/*description: time period that scl = 1*/
|
||||
#define RTC_I2C_SCL_HIGH_PERIOD 0x000FFFFF
|
||||
#define RTC_I2C_SCL_HIGH_PERIOD_M ((RTC_I2C_SCL_HIGH_PERIOD_V)<<(RTC_I2C_SCL_HIGH_PERIOD_S))
|
||||
#define RTC_I2C_SCL_HIGH_PERIOD_V 0xFFFFF
|
||||
#define RTC_I2C_SCL_HIGH_PERIOD_S 0
|
||||
|
||||
#define RTC_I2C_SDA_DUTY_REG (DR_REG_RTC_I2C_BASE + 0x0018)
|
||||
/* RTC_I2C_SDA_DUTY_NUM : R/W ;bitpos:[19:0] ;default: 20'h10 ; */
|
||||
/*description: time period for SDA to toggle after SCL goes low*/
|
||||
#define RTC_I2C_SDA_DUTY_NUM 0x000FFFFF
|
||||
#define RTC_I2C_SDA_DUTY_NUM_M ((RTC_I2C_SDA_DUTY_NUM_V)<<(RTC_I2C_SDA_DUTY_NUM_S))
|
||||
#define RTC_I2C_SDA_DUTY_NUM_V 0xFFFFF
|
||||
#define RTC_I2C_SDA_DUTY_NUM_S 0
|
||||
|
||||
#define RTC_I2C_SCL_START_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x001c)
|
||||
/* RTC_I2C_SCL_START_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b1000 ; */
|
||||
/*description: time period for SCL to toggle after I2C start is triggered*/
|
||||
#define RTC_I2C_SCL_START_PERIOD 0x000FFFFF
|
||||
#define RTC_I2C_SCL_START_PERIOD_M ((RTC_I2C_SCL_START_PERIOD_V)<<(RTC_I2C_SCL_START_PERIOD_S))
|
||||
#define RTC_I2C_SCL_START_PERIOD_V 0xFFFFF
|
||||
#define RTC_I2C_SCL_START_PERIOD_S 0
|
||||
|
||||
#define RTC_I2C_SCL_STOP_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x0020)
|
||||
/* RTC_I2C_SCL_STOP_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b1000 ; */
|
||||
/*description: time period for SCL to stop after I2C end is triggered*/
|
||||
#define RTC_I2C_SCL_STOP_PERIOD 0x000FFFFF
|
||||
#define RTC_I2C_SCL_STOP_PERIOD_M ((RTC_I2C_SCL_STOP_PERIOD_V)<<(RTC_I2C_SCL_STOP_PERIOD_S))
|
||||
#define RTC_I2C_SCL_STOP_PERIOD_V 0xFFFFF
|
||||
#define RTC_I2C_SCL_STOP_PERIOD_S 0
|
||||
|
||||
#define RTC_I2C_INT_CLR_REG (DR_REG_RTC_I2C_BASE + 0x0024)
|
||||
/* RTC_I2C_DETECT_START_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: clear detect start interrupt*/
|
||||
#define RTC_I2C_DETECT_START_INT_CLR (BIT(8))
|
||||
#define RTC_I2C_DETECT_START_INT_CLR_M (BIT(8))
|
||||
#define RTC_I2C_DETECT_START_INT_CLR_V 0x1
|
||||
#define RTC_I2C_DETECT_START_INT_CLR_S 8
|
||||
/* RTC_I2C_TX_DATA_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: clear transit load data complete interrupt*/
|
||||
#define RTC_I2C_TX_DATA_INT_CLR (BIT(7))
|
||||
#define RTC_I2C_TX_DATA_INT_CLR_M (BIT(7))
|
||||
#define RTC_I2C_TX_DATA_INT_CLR_V 0x1
|
||||
#define RTC_I2C_TX_DATA_INT_CLR_S 7
|
||||
/* RTC_I2C_RX_DATA_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: clear receive data interrupt*/
|
||||
#define RTC_I2C_RX_DATA_INT_CLR (BIT(6))
|
||||
#define RTC_I2C_RX_DATA_INT_CLR_M (BIT(6))
|
||||
#define RTC_I2C_RX_DATA_INT_CLR_V 0x1
|
||||
#define RTC_I2C_RX_DATA_INT_CLR_S 6
|
||||
/* RTC_I2C_ACK_ERR_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: clear ack error interrupt*/
|
||||
#define RTC_I2C_ACK_ERR_INT_CLR (BIT(5))
|
||||
#define RTC_I2C_ACK_ERR_INT_CLR_M (BIT(5))
|
||||
#define RTC_I2C_ACK_ERR_INT_CLR_V 0x1
|
||||
#define RTC_I2C_ACK_ERR_INT_CLR_S 5
|
||||
/* RTC_I2C_TIMEOUT_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: clear time out interrupt*/
|
||||
#define RTC_I2C_TIMEOUT_INT_CLR (BIT(4))
|
||||
#define RTC_I2C_TIMEOUT_INT_CLR_M (BIT(4))
|
||||
#define RTC_I2C_TIMEOUT_INT_CLR_V 0x1
|
||||
#define RTC_I2C_TIMEOUT_INT_CLR_S 4
|
||||
/* RTC_I2C_TRANS_COMPLETE_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: clear transit complete interrupt*/
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_CLR (BIT(3))
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_CLR_M (BIT(3))
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_CLR_V 0x1
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_CLR_S 3
|
||||
/* RTC_I2C_MASTER_TRAN_COMP_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: clear master transit complete interrupt*/
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR (BIT(2))
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_M (BIT(2))
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_V 0x1
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_S 2
|
||||
/* RTC_I2C_ARBITRATION_LOST_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: clear arbitration lost interrupt*/
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_CLR (BIT(1))
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_CLR_M (BIT(1))
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_CLR_V 0x1
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_CLR_S 1
|
||||
/* RTC_I2C_SLAVE_TRAN_COMP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: clear slave transit complete interrupt*/
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR (BIT(0))
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_M (BIT(0))
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_V 0x1
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_S 0
|
||||
|
||||
#define RTC_I2C_INT_RAW_REG (DR_REG_RTC_I2C_BASE + 0x0028)
|
||||
/* RTC_I2C_DETECT_START_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: detect start interrupt raw*/
|
||||
#define RTC_I2C_DETECT_START_INT_RAW (BIT(8))
|
||||
#define RTC_I2C_DETECT_START_INT_RAW_M (BIT(8))
|
||||
#define RTC_I2C_DETECT_START_INT_RAW_V 0x1
|
||||
#define RTC_I2C_DETECT_START_INT_RAW_S 8
|
||||
/* RTC_I2C_TX_DATA_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: transit data interrupt raw*/
|
||||
#define RTC_I2C_TX_DATA_INT_RAW (BIT(7))
|
||||
#define RTC_I2C_TX_DATA_INT_RAW_M (BIT(7))
|
||||
#define RTC_I2C_TX_DATA_INT_RAW_V 0x1
|
||||
#define RTC_I2C_TX_DATA_INT_RAW_S 7
|
||||
/* RTC_I2C_RX_DATA_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: receive data interrupt raw*/
|
||||
#define RTC_I2C_RX_DATA_INT_RAW (BIT(6))
|
||||
#define RTC_I2C_RX_DATA_INT_RAW_M (BIT(6))
|
||||
#define RTC_I2C_RX_DATA_INT_RAW_V 0x1
|
||||
#define RTC_I2C_RX_DATA_INT_RAW_S 6
|
||||
/* RTC_I2C_ACK_ERR_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: ack error interrupt raw*/
|
||||
#define RTC_I2C_ACK_ERR_INT_RAW (BIT(5))
|
||||
#define RTC_I2C_ACK_ERR_INT_RAW_M (BIT(5))
|
||||
#define RTC_I2C_ACK_ERR_INT_RAW_V 0x1
|
||||
#define RTC_I2C_ACK_ERR_INT_RAW_S 5
|
||||
/* RTC_I2C_TIMEOUT_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: time out interrupt raw*/
|
||||
#define RTC_I2C_TIMEOUT_INT_RAW (BIT(4))
|
||||
#define RTC_I2C_TIMEOUT_INT_RAW_M (BIT(4))
|
||||
#define RTC_I2C_TIMEOUT_INT_RAW_V 0x1
|
||||
#define RTC_I2C_TIMEOUT_INT_RAW_S 4
|
||||
/* RTC_I2C_TRANS_COMPLETE_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: transit complete interrupt raw*/
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_RAW (BIT(3))
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_RAW_M (BIT(3))
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_RAW_V 0x1
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_RAW_S 3
|
||||
/* RTC_I2C_MASTER_TRAN_COMP_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: master transit complete interrupt raw*/
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW (BIT(2))
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_M (BIT(2))
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_V 0x1
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_S 2
|
||||
/* RTC_I2C_ARBITRATION_LOST_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: arbitration lost interrupt raw*/
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_RAW (BIT(1))
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_RAW_M (BIT(1))
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_RAW_V 0x1
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_RAW_S 1
|
||||
/* RTC_I2C_SLAVE_TRAN_COMP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: slave transit complete interrupt raw*/
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW (BIT(0))
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_M (BIT(0))
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_V 0x1
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_S 0
|
||||
|
||||
#define RTC_I2C_INT_ST_REG (DR_REG_RTC_I2C_BASE + 0x002c)
|
||||
/* RTC_I2C_DETECT_START_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: detect start interrupt state*/
|
||||
#define RTC_I2C_DETECT_START_INT_ST (BIT(8))
|
||||
#define RTC_I2C_DETECT_START_INT_ST_M (BIT(8))
|
||||
#define RTC_I2C_DETECT_START_INT_ST_V 0x1
|
||||
#define RTC_I2C_DETECT_START_INT_ST_S 8
|
||||
/* RTC_I2C_TX_DATA_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: transit data interrupt state*/
|
||||
#define RTC_I2C_TX_DATA_INT_ST (BIT(7))
|
||||
#define RTC_I2C_TX_DATA_INT_ST_M (BIT(7))
|
||||
#define RTC_I2C_TX_DATA_INT_ST_V 0x1
|
||||
#define RTC_I2C_TX_DATA_INT_ST_S 7
|
||||
/* RTC_I2C_RX_DATA_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: receive data interrupt state*/
|
||||
#define RTC_I2C_RX_DATA_INT_ST (BIT(6))
|
||||
#define RTC_I2C_RX_DATA_INT_ST_M (BIT(6))
|
||||
#define RTC_I2C_RX_DATA_INT_ST_V 0x1
|
||||
#define RTC_I2C_RX_DATA_INT_ST_S 6
|
||||
/* RTC_I2C_ACK_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: ack error interrupt state*/
|
||||
#define RTC_I2C_ACK_ERR_INT_ST (BIT(5))
|
||||
#define RTC_I2C_ACK_ERR_INT_ST_M (BIT(5))
|
||||
#define RTC_I2C_ACK_ERR_INT_ST_V 0x1
|
||||
#define RTC_I2C_ACK_ERR_INT_ST_S 5
|
||||
/* RTC_I2C_TIMEOUT_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: time out interrupt state*/
|
||||
#define RTC_I2C_TIMEOUT_INT_ST (BIT(4))
|
||||
#define RTC_I2C_TIMEOUT_INT_ST_M (BIT(4))
|
||||
#define RTC_I2C_TIMEOUT_INT_ST_V 0x1
|
||||
#define RTC_I2C_TIMEOUT_INT_ST_S 4
|
||||
/* RTC_I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: transit complete interrupt state*/
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_ST (BIT(3))
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_ST_M (BIT(3))
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_ST_V 0x1
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_ST_S 3
|
||||
/* RTC_I2C_MASTER_TRAN_COMP_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: master transit complete interrupt state*/
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_ST (BIT(2))
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_M (BIT(2))
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_V 0x1
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_S 2
|
||||
/* RTC_I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: arbitration lost interrupt state*/
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_ST (BIT(1))
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_ST_M (BIT(1))
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_ST_V 0x1
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_ST_S 1
|
||||
/* RTC_I2C_SLAVE_TRAN_COMP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: slave transit complete interrupt state*/
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST (BIT(0))
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_M (BIT(0))
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_V 0x1
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_S 0
|
||||
|
||||
#define RTC_I2C_INT_ENA_REG (DR_REG_RTC_I2C_BASE + 0x0030)
|
||||
/* RTC_I2C_DETECT_START_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: enable detect start interrupt*/
|
||||
#define RTC_I2C_DETECT_START_INT_ENA (BIT(8))
|
||||
#define RTC_I2C_DETECT_START_INT_ENA_M (BIT(8))
|
||||
#define RTC_I2C_DETECT_START_INT_ENA_V 0x1
|
||||
#define RTC_I2C_DETECT_START_INT_ENA_S 8
|
||||
/* RTC_I2C_TX_DATA_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: enable transit data interrupt*/
|
||||
#define RTC_I2C_TX_DATA_INT_ENA (BIT(7))
|
||||
#define RTC_I2C_TX_DATA_INT_ENA_M (BIT(7))
|
||||
#define RTC_I2C_TX_DATA_INT_ENA_V 0x1
|
||||
#define RTC_I2C_TX_DATA_INT_ENA_S 7
|
||||
/* RTC_I2C_RX_DATA_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: enable receive data interrupt*/
|
||||
#define RTC_I2C_RX_DATA_INT_ENA (BIT(6))
|
||||
#define RTC_I2C_RX_DATA_INT_ENA_M (BIT(6))
|
||||
#define RTC_I2C_RX_DATA_INT_ENA_V 0x1
|
||||
#define RTC_I2C_RX_DATA_INT_ENA_S 6
|
||||
/* RTC_I2C_ACK_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: enable eack error interrupt*/
|
||||
#define RTC_I2C_ACK_ERR_INT_ENA (BIT(5))
|
||||
#define RTC_I2C_ACK_ERR_INT_ENA_M (BIT(5))
|
||||
#define RTC_I2C_ACK_ERR_INT_ENA_V 0x1
|
||||
#define RTC_I2C_ACK_ERR_INT_ENA_S 5
|
||||
/* RTC_I2C_TIMEOUT_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: enable time out interrupt*/
|
||||
#define RTC_I2C_TIMEOUT_INT_ENA (BIT(4))
|
||||
#define RTC_I2C_TIMEOUT_INT_ENA_M (BIT(4))
|
||||
#define RTC_I2C_TIMEOUT_INT_ENA_V 0x1
|
||||
#define RTC_I2C_TIMEOUT_INT_ENA_S 4
|
||||
/* RTC_I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: enable transit complete interrupt*/
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_ENA (BIT(3))
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_ENA_M (BIT(3))
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_ENA_V 0x1
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_ENA_S 3
|
||||
/* RTC_I2C_MASTER_TRAN_COMP_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: enable master transit complete interrupt*/
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA (BIT(2))
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_M (BIT(2))
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_V 0x1
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_S 2
|
||||
/* RTC_I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: enable arbitration lost interrupt*/
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_ENA (BIT(1))
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_ENA_M (BIT(1))
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_ENA_V 0x1
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_ENA_S 1
|
||||
/* RTC_I2C_SLAVE_TRAN_COMP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: enable slave transit complete interrupt*/
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA (BIT(0))
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_M (BIT(0))
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_V 0x1
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_S 0
|
||||
|
||||
#define RTC_I2C_DATA_REG (DR_REG_RTC_I2C_BASE + 0x0034)
|
||||
/* RTC_I2C_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: i2c done*/
|
||||
#define RTC_I2C_DONE (BIT(31))
|
||||
#define RTC_I2C_DONE_M (BIT(31))
|
||||
#define RTC_I2C_DONE_V 0x1
|
||||
#define RTC_I2C_DONE_S 31
|
||||
/* RTC_I2C_SLAVE_TX_DATA : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
|
||||
/*description: data sent by slave*/
|
||||
#define RTC_I2C_SLAVE_TX_DATA 0x000000FF
|
||||
#define RTC_I2C_SLAVE_TX_DATA_M ((RTC_I2C_SLAVE_TX_DATA_V)<<(RTC_I2C_SLAVE_TX_DATA_S))
|
||||
#define RTC_I2C_SLAVE_TX_DATA_V 0xFF
|
||||
#define RTC_I2C_SLAVE_TX_DATA_S 8
|
||||
/* RTC_I2C_RDATA : RO ;bitpos:[7:0] ;default: 8'h0 ; */
|
||||
/*description: data received*/
|
||||
#define RTC_I2C_RDATA 0x000000FF
|
||||
#define RTC_I2C_RDATA_M ((RTC_I2C_RDATA_V)<<(RTC_I2C_RDATA_S))
|
||||
#define RTC_I2C_RDATA_V 0xFF
|
||||
#define RTC_I2C_RDATA_S 0
|
||||
|
||||
#define RTC_I2C_CMD0_REG (DR_REG_RTC_I2C_BASE + 0x0038)
|
||||
/* RTC_I2C_COMMAND0_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command0_done*/
|
||||
#define RTC_I2C_COMMAND0_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND0_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND0_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND0_DONE_S 31
|
||||
/* RTC_I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'h0903 ; */
|
||||
/*description: command0*/
|
||||
#define RTC_I2C_COMMAND0 0x00003FFF
|
||||
#define RTC_I2C_COMMAND0_M ((RTC_I2C_COMMAND0_V)<<(RTC_I2C_COMMAND0_S))
|
||||
#define RTC_I2C_COMMAND0_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND0_S 0
|
||||
|
||||
#define RTC_I2C_CMD1_REG (DR_REG_RTC_I2C_BASE + 0x003c)
|
||||
/* RTC_I2C_COMMAND1_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command1_done*/
|
||||
#define RTC_I2C_COMMAND1_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND1_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND1_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND1_DONE_S 31
|
||||
/* RTC_I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */
|
||||
/*description: command1*/
|
||||
#define RTC_I2C_COMMAND1 0x00003FFF
|
||||
#define RTC_I2C_COMMAND1_M ((RTC_I2C_COMMAND1_V)<<(RTC_I2C_COMMAND1_S))
|
||||
#define RTC_I2C_COMMAND1_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND1_S 0
|
||||
|
||||
#define RTC_I2C_CMD2_REG (DR_REG_RTC_I2C_BASE + 0x0040)
|
||||
/* RTC_I2C_COMMAND2_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command2_done*/
|
||||
#define RTC_I2C_COMMAND2_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND2_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND2_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND2_DONE_S 31
|
||||
/* RTC_I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'h0902 ; */
|
||||
/*description: command2*/
|
||||
#define RTC_I2C_COMMAND2 0x00003FFF
|
||||
#define RTC_I2C_COMMAND2_M ((RTC_I2C_COMMAND2_V)<<(RTC_I2C_COMMAND2_S))
|
||||
#define RTC_I2C_COMMAND2_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND2_S 0
|
||||
|
||||
#define RTC_I2C_CMD3_REG (DR_REG_RTC_I2C_BASE + 0x0044)
|
||||
/* RTC_I2C_COMMAND3_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command3_done*/
|
||||
#define RTC_I2C_COMMAND3_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND3_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND3_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND3_DONE_S 31
|
||||
/* RTC_I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'h0101 ; */
|
||||
/*description: command3*/
|
||||
#define RTC_I2C_COMMAND3 0x00003FFF
|
||||
#define RTC_I2C_COMMAND3_M ((RTC_I2C_COMMAND3_V)<<(RTC_I2C_COMMAND3_S))
|
||||
#define RTC_I2C_COMMAND3_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND3_S 0
|
||||
|
||||
#define RTC_I2C_CMD4_REG (DR_REG_RTC_I2C_BASE + 0x0048)
|
||||
/* RTC_I2C_COMMAND4_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command4_done*/
|
||||
#define RTC_I2C_COMMAND4_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND4_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND4_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND4_DONE_S 31
|
||||
/* RTC_I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'h0901 ; */
|
||||
/*description: command4*/
|
||||
#define RTC_I2C_COMMAND4 0x00003FFF
|
||||
#define RTC_I2C_COMMAND4_M ((RTC_I2C_COMMAND4_V)<<(RTC_I2C_COMMAND4_S))
|
||||
#define RTC_I2C_COMMAND4_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND4_S 0
|
||||
|
||||
#define RTC_I2C_CMD5_REG (DR_REG_RTC_I2C_BASE + 0x004c)
|
||||
/* RTC_I2C_COMMAND5_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command5_done*/
|
||||
#define RTC_I2C_COMMAND5_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND5_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND5_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND5_DONE_S 31
|
||||
/* RTC_I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'h1701 ; */
|
||||
/*description: command5*/
|
||||
#define RTC_I2C_COMMAND5 0x00003FFF
|
||||
#define RTC_I2C_COMMAND5_M ((RTC_I2C_COMMAND5_V)<<(RTC_I2C_COMMAND5_S))
|
||||
#define RTC_I2C_COMMAND5_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND5_S 0
|
||||
|
||||
#define RTC_I2C_CMD6_REG (DR_REG_RTC_I2C_BASE + 0x0050)
|
||||
/* RTC_I2C_COMMAND6_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command6_done*/
|
||||
#define RTC_I2C_COMMAND6_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND6_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND6_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND6_DONE_S 31
|
||||
/* RTC_I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */
|
||||
/*description: command6*/
|
||||
#define RTC_I2C_COMMAND6 0x00003FFF
|
||||
#define RTC_I2C_COMMAND6_M ((RTC_I2C_COMMAND6_V)<<(RTC_I2C_COMMAND6_S))
|
||||
#define RTC_I2C_COMMAND6_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND6_S 0
|
||||
|
||||
#define RTC_I2C_CMD7_REG (DR_REG_RTC_I2C_BASE + 0x0054)
|
||||
/* RTC_I2C_COMMAND7_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command7_done*/
|
||||
#define RTC_I2C_COMMAND7_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND7_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND7_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND7_DONE_S 31
|
||||
/* RTC_I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'h0904 ; */
|
||||
/*description: command7*/
|
||||
#define RTC_I2C_COMMAND7 0x00003FFF
|
||||
#define RTC_I2C_COMMAND7_M ((RTC_I2C_COMMAND7_V)<<(RTC_I2C_COMMAND7_S))
|
||||
#define RTC_I2C_COMMAND7_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND7_S 0
|
||||
|
||||
#define RTC_I2C_CMD8_REG (DR_REG_RTC_I2C_BASE + 0x0058)
|
||||
/* RTC_I2C_COMMAND8_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command8_done*/
|
||||
#define RTC_I2C_COMMAND8_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND8_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND8_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND8_DONE_S 31
|
||||
/* RTC_I2C_COMMAND8 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */
|
||||
/*description: command8*/
|
||||
#define RTC_I2C_COMMAND8 0x00003FFF
|
||||
#define RTC_I2C_COMMAND8_M ((RTC_I2C_COMMAND8_V)<<(RTC_I2C_COMMAND8_S))
|
||||
#define RTC_I2C_COMMAND8_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND8_S 0
|
||||
|
||||
#define RTC_I2C_CMD9_REG (DR_REG_RTC_I2C_BASE + 0x005c)
|
||||
/* RTC_I2C_COMMAND9_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command9_done*/
|
||||
#define RTC_I2C_COMMAND9_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND9_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND9_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND9_DONE_S 31
|
||||
/* RTC_I2C_COMMAND9 : R/W ;bitpos:[13:0] ;default: 14'h0903 ; */
|
||||
/*description: command9*/
|
||||
#define RTC_I2C_COMMAND9 0x00003FFF
|
||||
#define RTC_I2C_COMMAND9_M ((RTC_I2C_COMMAND9_V)<<(RTC_I2C_COMMAND9_S))
|
||||
#define RTC_I2C_COMMAND9_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND9_S 0
|
||||
|
||||
#define RTC_I2C_CMD10_REG (DR_REG_RTC_I2C_BASE + 0x0060)
|
||||
/* RTC_I2C_COMMAND10_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command10_done*/
|
||||
#define RTC_I2C_COMMAND10_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND10_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND10_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND10_DONE_S 31
|
||||
/* RTC_I2C_COMMAND10 : R/W ;bitpos:[13:0] ;default: 14'h0101 ; */
|
||||
/*description: command10*/
|
||||
#define RTC_I2C_COMMAND10 0x00003FFF
|
||||
#define RTC_I2C_COMMAND10_M ((RTC_I2C_COMMAND10_V)<<(RTC_I2C_COMMAND10_S))
|
||||
#define RTC_I2C_COMMAND10_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND10_S 0
|
||||
|
||||
#define RTC_I2C_CMD11_REG (DR_REG_RTC_I2C_BASE + 0x0064)
|
||||
/* RTC_I2C_COMMAND11_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command11_done*/
|
||||
#define RTC_I2C_COMMAND11_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND11_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND11_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND11_DONE_S 31
|
||||
/* RTC_I2C_COMMAND11 : R/W ;bitpos:[13:0] ;default: 14'h0901 ; */
|
||||
/*description: command11*/
|
||||
#define RTC_I2C_COMMAND11 0x00003FFF
|
||||
#define RTC_I2C_COMMAND11_M ((RTC_I2C_COMMAND11_V)<<(RTC_I2C_COMMAND11_S))
|
||||
#define RTC_I2C_COMMAND11_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND11_S 0
|
||||
|
||||
#define RTC_I2C_CMD12_REG (DR_REG_RTC_I2C_BASE + 0x0068)
|
||||
/* RTC_I2C_COMMAND12_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command12_done*/
|
||||
#define RTC_I2C_COMMAND12_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND12_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND12_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND12_DONE_S 31
|
||||
/* RTC_I2C_COMMAND12 : R/W ;bitpos:[13:0] ;default: 14'h1701 ; */
|
||||
/*description: command12*/
|
||||
#define RTC_I2C_COMMAND12 0x00003FFF
|
||||
#define RTC_I2C_COMMAND12_M ((RTC_I2C_COMMAND12_V)<<(RTC_I2C_COMMAND12_S))
|
||||
#define RTC_I2C_COMMAND12_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND12_S 0
|
||||
|
||||
#define RTC_I2C_CMD13_REG (DR_REG_RTC_I2C_BASE + 0x006c)
|
||||
/* RTC_I2C_COMMAND13_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command13_done*/
|
||||
#define RTC_I2C_COMMAND13_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND13_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND13_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND13_DONE_S 31
|
||||
/* RTC_I2C_COMMAND13 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */
|
||||
/*description: command13*/
|
||||
#define RTC_I2C_COMMAND13 0x00003FFF
|
||||
#define RTC_I2C_COMMAND13_M ((RTC_I2C_COMMAND13_V)<<(RTC_I2C_COMMAND13_S))
|
||||
#define RTC_I2C_COMMAND13_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND13_S 0
|
||||
|
||||
#define RTC_I2C_CMD14_REG (DR_REG_RTC_I2C_BASE + 0x0070)
|
||||
/* RTC_I2C_COMMAND14_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command14_done*/
|
||||
#define RTC_I2C_COMMAND14_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND14_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND14_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND14_DONE_S 31
|
||||
/* RTC_I2C_COMMAND14 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
|
||||
/*description: command14*/
|
||||
#define RTC_I2C_COMMAND14 0x00003FFF
|
||||
#define RTC_I2C_COMMAND14_M ((RTC_I2C_COMMAND14_V)<<(RTC_I2C_COMMAND14_S))
|
||||
#define RTC_I2C_COMMAND14_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND14_S 0
|
||||
|
||||
#define RTC_I2C_CMD15_REG (DR_REG_RTC_I2C_BASE + 0x0074)
|
||||
/* RTC_I2C_COMMAND15_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command15_done*/
|
||||
#define RTC_I2C_COMMAND15_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND15_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND15_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND15_DONE_S 31
|
||||
/* RTC_I2C_COMMAND15 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
|
||||
/*description: command15*/
|
||||
#define RTC_I2C_COMMAND15 0x00003FFF
|
||||
#define RTC_I2C_COMMAND15_M ((RTC_I2C_COMMAND15_V)<<(RTC_I2C_COMMAND15_S))
|
||||
#define RTC_I2C_COMMAND15_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND15_S 0
|
||||
|
||||
#define RTC_I2C_DATE_REG (DR_REG_RTC_I2C_BASE + 0x00FC)
|
||||
/* RTC_I2C_DATE : R/W ;bitpos:[27:0] ;default: 28'h1905310 ; */
|
||||
/*description: */
|
||||
#define RTC_I2C_DATE 0x0FFFFFFF
|
||||
#define RTC_I2C_DATE_M ((RTC_I2C_DATE_V)<<(RTC_I2C_DATE_S))
|
||||
#define RTC_I2C_DATE_V 0xFFFFFFF
|
||||
#define RTC_I2C_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /*_SOC_RTC_I2C_REG_H_ */
|
||||
@@ -1,222 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct rtc_i2c_dev_s {
|
||||
union {
|
||||
struct {
|
||||
uint32_t period: 20; /*time period that scl = 0*/
|
||||
uint32_t reserved20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} scl_low;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sda_force_out: 1; /*1=push pull 0=open drain*/
|
||||
uint32_t scl_force_out: 1; /*1=push pull 0=open drain*/
|
||||
uint32_t ms_mode: 1; /*1=master 0=slave*/
|
||||
uint32_t trans_start: 1; /*force start*/
|
||||
uint32_t tx_lsb_first: 1; /*transit lsb first*/
|
||||
uint32_t rx_lsb_first: 1; /*receive lsb first*/
|
||||
uint32_t reserved6: 23;
|
||||
uint32_t i2c_ctrl_clk_gate_en: 1;
|
||||
uint32_t i2c_reset: 1; /*rtc i2c sw reset*/
|
||||
uint32_t i2cclk_en: 1; /*rtc i2c reg clk gating*/
|
||||
};
|
||||
uint32_t val;
|
||||
} ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t ack_rec: 1; /*ack response*/
|
||||
uint32_t slave_rw: 1; /*slave read or write*/
|
||||
uint32_t arb_lost: 1; /*arbitration is lost*/
|
||||
uint32_t bus_busy: 1; /*bus is busy*/
|
||||
uint32_t slave_addressed: 1; /*slave reg sub address*/
|
||||
uint32_t byte_trans: 1; /*One byte transit done*/
|
||||
uint32_t op_cnt: 2; /*which operation is working*/
|
||||
uint32_t reserved8: 8;
|
||||
uint32_t shift: 8; /*shifter content*/
|
||||
uint32_t scl_main_state_last: 3; /*i2c last main status*/
|
||||
uint32_t reserved27: 1;
|
||||
uint32_t scl_state_last: 3; /*scl last status*/
|
||||
uint32_t reserved31: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} status;
|
||||
union {
|
||||
struct {
|
||||
uint32_t time_out: 20; /*time out threshold*/
|
||||
uint32_t reserved20:12;
|
||||
};
|
||||
uint32_t val;
|
||||
} timeout;
|
||||
union {
|
||||
struct {
|
||||
uint32_t addr: 15; /*slave address*/
|
||||
uint32_t reserved15: 16;
|
||||
uint32_t en_10bit: 1; /*i2c 10bit mode enable*/
|
||||
};
|
||||
uint32_t val;
|
||||
} slave_addr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t period: 20; /*time period that scl = 1*/
|
||||
uint32_t reserved20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} scl_high;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sda_duty_num:20; /*time period for SDA to toggle after SCL goes low*/
|
||||
uint32_t reserved20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} sda_duty;
|
||||
union {
|
||||
struct {
|
||||
uint32_t scl_start_period:20; /*time period for SCL to toggle after I2C start is triggered*/
|
||||
uint32_t reserved20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} scl_start_period;
|
||||
union {
|
||||
struct {
|
||||
uint32_t scl_stop_period:20; /*time period for SCL to stop after I2C end is triggered*/
|
||||
uint32_t reserved20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} scl_stop_period;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slave_tran_comp: 1; /*clear slave transit complete interrupt*/
|
||||
uint32_t arbitration_lost: 1; /*clear arbitration lost interrupt*/
|
||||
uint32_t master_tran_comp: 1; /*clear master transit complete interrupt*/
|
||||
uint32_t trans_complete: 1; /*clear transit complete interrupt*/
|
||||
uint32_t time_out: 1; /*clear time out interrupt*/
|
||||
uint32_t ack_err: 1; /*clear ack error interrupt*/
|
||||
uint32_t rx_data: 1; /*clear receive data interrupt*/
|
||||
uint32_t tx_data: 1; /*clear transit load data complete interrupt*/
|
||||
uint32_t detect_start: 1; /*clear detect start interrupt*/
|
||||
uint32_t reserved9: 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slave_tran_comp: 1; /*slave transit complete interrupt raw*/
|
||||
uint32_t arbitration_lost: 1; /*arbitration lost interrupt raw*/
|
||||
uint32_t master_tran_comp: 1; /*master transit complete interrupt raw*/
|
||||
uint32_t trans_complete: 1; /*transit complete interrupt raw*/
|
||||
uint32_t time_out: 1; /*time out interrupt raw*/
|
||||
uint32_t ack_err: 1; /*ack error interrupt raw*/
|
||||
uint32_t rx_data: 1; /*receive data interrupt raw*/
|
||||
uint32_t tx_data: 1; /*transit data interrupt raw*/
|
||||
uint32_t detect_start: 1; /*detect start interrupt raw*/
|
||||
uint32_t reserved9: 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slave_tran_comp: 1; /*slave transit complete interrupt state*/
|
||||
uint32_t arbitration_lost: 1; /*arbitration lost interrupt state*/
|
||||
uint32_t master_tran_comp: 1; /*master transit complete interrupt state*/
|
||||
uint32_t trans_complete: 1; /*transit complete interrupt state*/
|
||||
uint32_t time_out: 1; /*time out interrupt state*/
|
||||
uint32_t ack_err: 1; /*ack error interrupt state*/
|
||||
uint32_t rx_data: 1; /*receive data interrupt state*/
|
||||
uint32_t tx_data: 1; /*transit data interrupt state*/
|
||||
uint32_t detect_start: 1; /*detect start interrupt state*/
|
||||
uint32_t reserved9: 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slave_tran_comp: 1; /*enable slave transit complete interrupt*/
|
||||
uint32_t arbitration_lost: 1; /*enable arbitration lost interrupt*/
|
||||
uint32_t master_tran_comp: 1; /*enable master transit complete interrupt*/
|
||||
uint32_t trans_complete: 1; /*enable transit complete interrupt*/
|
||||
uint32_t time_out: 1; /*enable time out interrupt*/
|
||||
uint32_t ack_err: 1; /*enable eack error interrupt*/
|
||||
uint32_t rx_data: 1; /*enable receive data interrupt*/
|
||||
uint32_t tx_data: 1; /*enable transit data interrupt*/
|
||||
uint32_t detect_start: 1; /*enable detect start interrupt*/
|
||||
uint32_t reserved9: 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t i2c_rdata: 8; /*data received*/
|
||||
uint32_t slave_tx_data: 8; /*data sent by slave*/
|
||||
uint32_t reserved16: 15;
|
||||
uint32_t i2c_done: 1; /*i2c done*/
|
||||
};
|
||||
uint32_t val;
|
||||
} fifo_data;
|
||||
union {
|
||||
struct {
|
||||
uint32_t byte_num: 8;
|
||||
uint32_t ack_en: 1;
|
||||
uint32_t ack_exp: 1;
|
||||
uint32_t ack_val: 1;
|
||||
uint32_t op_code: 3;
|
||||
uint32_t reserved14: 17;
|
||||
uint32_t done: 1; /*command0_done*/
|
||||
};
|
||||
uint32_t val;
|
||||
} command[16];
|
||||
uint32_t reserved_78;
|
||||
uint32_t reserved_7c;
|
||||
uint32_t reserved_80;
|
||||
uint32_t reserved_84;
|
||||
uint32_t reserved_88;
|
||||
uint32_t reserved_8c;
|
||||
uint32_t reserved_90;
|
||||
uint32_t reserved_94;
|
||||
uint32_t reserved_98;
|
||||
uint32_t reserved_9c;
|
||||
uint32_t reserved_a0;
|
||||
uint32_t reserved_a4;
|
||||
uint32_t reserved_a8;
|
||||
uint32_t reserved_ac;
|
||||
uint32_t reserved_b0;
|
||||
uint32_t reserved_b4;
|
||||
uint32_t reserved_b8;
|
||||
uint32_t reserved_bc;
|
||||
uint32_t reserved_c0;
|
||||
uint32_t reserved_c4;
|
||||
uint32_t reserved_c8;
|
||||
uint32_t reserved_cc;
|
||||
uint32_t reserved_d0;
|
||||
uint32_t reserved_d4;
|
||||
uint32_t reserved_d8;
|
||||
uint32_t reserved_dc;
|
||||
uint32_t reserved_e0;
|
||||
uint32_t reserved_e4;
|
||||
uint32_t reserved_e8;
|
||||
uint32_t reserved_ec;
|
||||
uint32_t reserved_f0;
|
||||
uint32_t reserved_f4;
|
||||
uint32_t reserved_f8;
|
||||
union {
|
||||
struct {
|
||||
uint32_t i2c_date: 28;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} date;
|
||||
} rtc_i2c_dev_t;
|
||||
extern rtc_i2c_dev_t RTC_I2C;
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -12,7 +12,7 @@
|
||||
#endif
|
||||
|
||||
#include "esp_bit_defs.h"
|
||||
#include "reg_base.h"
|
||||
#include "soc/reg_base.h"
|
||||
|
||||
#define PRO_CPU_NUM (0)
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,569 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct spi_mem_dev_s {
|
||||
union {
|
||||
struct {
|
||||
uint32_t mst_st: 4; /*The current status of SPI1 master FSM.*/
|
||||
uint32_t st: 4; /*The current status of SPI1 slave FSM: mspi_st. 0: idle state 1: preparation state 2: send command state 3: send address state 4: wait state 5: read data state 6:write data state 7: done state 8: read data end state.*/
|
||||
uint32_t reserved8: 9; /*reserved*/
|
||||
uint32_t flash_pe: 1; /*In user mode it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable.*/
|
||||
uint32_t usr: 1; /*User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
|
||||
uint32_t flash_hpm: 1; /*Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable.*/
|
||||
uint32_t flash_res: 1; /*This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.*/
|
||||
uint32_t flash_dp: 1; /*Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
|
||||
uint32_t flash_ce: 1; /*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
|
||||
uint32_t flash_be: 1; /*Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
|
||||
uint32_t flash_se: 1; /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
|
||||
uint32_t flash_pp: 1; /*Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/
|
||||
uint32_t flash_wrsr: 1; /*Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
|
||||
uint32_t flash_rdsr: 1; /*Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
|
||||
uint32_t flash_rdid: 1; /*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
|
||||
uint32_t flash_wrdi: 1; /*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
|
||||
uint32_t flash_wren: 1; /*Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
|
||||
uint32_t flash_read: 1; /*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} cmd;
|
||||
uint32_t addr; /*SPI1 address register*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 3; /*reserved*/
|
||||
uint32_t fdummy_out: 1; /*In the dummy phase the signal level of spi is output by the spi controller.*/
|
||||
uint32_t reserved4: 3; /*reserved*/
|
||||
uint32_t fcmd_dual: 1; /*Apply 2 signals during command phase 1:enable 0: disable*/
|
||||
uint32_t fcmd_quad: 1; /*Apply 4 signals during command phase 1:enable 0: disable*/
|
||||
uint32_t reserved9: 1; /*reserved*/
|
||||
uint32_t fcs_crc_en: 1; /*For SPI1 initialize crc32 module before writing encrypted data to flash. Active low.*/
|
||||
uint32_t tx_crc_en: 1; /*For SPI1 enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/
|
||||
uint32_t reserved12: 1; /*reserved*/
|
||||
uint32_t fastrd_mode: 1; /*This bit enable the bits: spi_mem_fread_qio spi_mem_fread_dio spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.*/
|
||||
uint32_t fread_dual: 1; /*In the read operations read-data phase apply 2 signals. 1: enable 0: disable.*/
|
||||
uint32_t resandres: 1; /*The Device ID is read out to SPI_MEM_RD_STATUS register this bit combine with spi_mem_flash_res bit. 1: enable 0: disable.*/
|
||||
uint32_t reserved16: 2; /*reserved*/
|
||||
uint32_t q_pol: 1; /*The bit is used to set MISO line polarity 1: high 0 low*/
|
||||
uint32_t d_pol: 1; /*The bit is used to set MOSI line polarity 1: high 0 low*/
|
||||
uint32_t fread_quad: 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/
|
||||
uint32_t wp: 1; /*Write protect signal output when SPI is idle. 1: output high 0: output low.*/
|
||||
uint32_t wrsr_2b: 1; /*two bytes data will be written to status register when it is set. 1: enable 0: disable.*/
|
||||
uint32_t fread_dio: 1; /*In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.*/
|
||||
uint32_t fread_qio: 1; /*In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.*/
|
||||
uint32_t reserved25: 7; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_mode: 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/
|
||||
uint32_t cs_hold_dly_res: 10; /*After RES/DP/HPM command is sent SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.*/
|
||||
uint32_t reserved2: 18; /*reserved*/
|
||||
uint32_t rxfifo_rst: 1; /*SPI0 RX FIFO reset signal.*/
|
||||
uint32_t rxfifo_wfull_err: 1; /*1: SPI0 RX FIFO write full error Cache/EDMA do not read all the data out. 0: Not error.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} ctrl1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cs_setup_time: 5; /*(cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.*/
|
||||
uint32_t cs_hold_time: 5; /*Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.*/
|
||||
uint32_t reserved10: 15; /*reserved*/
|
||||
uint32_t cs_hold_delay: 6; /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/
|
||||
uint32_t sync_reset: 1; /*The FSM will be reset.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} ctrl2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clkcnt_l: 8; /*In the master mode it must be equal to spi_mem_clkcnt_N.*/
|
||||
uint32_t clkcnt_h: 8; /*In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).*/
|
||||
uint32_t clkcnt_n: 8; /*In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
|
||||
uint32_t reserved24: 7; /*reserved*/
|
||||
uint32_t clk_equ_sysclk: 1; /*Set this bit in 1-division mode.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} clock;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 6; /*reserved*/
|
||||
uint32_t cs_hold: 1; /*spi cs keep low when spi is in done phase. 1: enable 0: disable.*/
|
||||
uint32_t cs_setup: 1; /*spi cs is enable when spi is in prepare phase. 1: enable 0: disable.*/
|
||||
uint32_t reserved8: 1; /*reserved*/
|
||||
uint32_t ck_out_edge: 1; /*the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.*/
|
||||
uint32_t reserved10: 2; /*reserved*/
|
||||
uint32_t fwrite_dual: 1; /*In the write operations read-data phase apply 2 signals*/
|
||||
uint32_t fwrite_quad: 1; /*In the write operations read-data phase apply 4 signals*/
|
||||
uint32_t fwrite_dio: 1; /*In the write operations address phase and read-data phase apply 2 signals.*/
|
||||
uint32_t fwrite_qio: 1; /*In the write operations address phase and read-data phase apply 4 signals.*/
|
||||
uint32_t reserved16: 8; /*reserved*/
|
||||
uint32_t usr_miso_highpart: 1; /*read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.*/
|
||||
uint32_t usr_mosi_highpart: 1; /*write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.*/
|
||||
uint32_t usr_dummy_idle: 1; /*SPI clock is disable in dummy phase when the bit is enable.*/
|
||||
uint32_t usr_mosi: 1; /*This bit enable the write-data phase of an operation.*/
|
||||
uint32_t usr_miso: 1; /*This bit enable the read-data phase of an operation.*/
|
||||
uint32_t usr_dummy: 1; /*This bit enable the dummy phase of an operation.*/
|
||||
uint32_t usr_addr: 1; /*This bit enable the address phase of an operation.*/
|
||||
uint32_t usr_command: 1; /*This bit enable the command phase of an operation.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} user;
|
||||
union {
|
||||
struct {
|
||||
uint32_t usr_dummy_cyclelen: 6; /*The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/
|
||||
uint32_t reserved6: 20; /*reserved*/
|
||||
uint32_t usr_addr_bitlen: 6; /*The length in bits of address phase. The register value shall be (bit_num-1).*/
|
||||
};
|
||||
uint32_t val;
|
||||
} user1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t usr_command_value: 16; /*The value of command.*/
|
||||
uint32_t reserved16: 12; /*reserved*/
|
||||
uint32_t usr_command_bitlen: 4; /*The length in bits of command phase. The register value shall be (bit_num-1)*/
|
||||
};
|
||||
uint32_t val;
|
||||
} user2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t usr_mosi_bit_len: 10; /*The length in bits of write-data. The register value shall be (bit_num-1).*/
|
||||
uint32_t reserved10: 22; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} mosi_dlen;
|
||||
union {
|
||||
struct {
|
||||
uint32_t usr_miso_bit_len: 10; /*The length in bits of read-data. The register value shall be (bit_num-1).*/
|
||||
uint32_t reserved10: 22; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} miso_dlen;
|
||||
union {
|
||||
struct {
|
||||
uint32_t status: 16; /*The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.*/
|
||||
uint32_t wb_mode: 8; /*Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit.*/
|
||||
uint32_t reserved24: 8; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} rd_status;
|
||||
uint32_t reserved_30;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cs0_dis: 1; /*SPI_CS0 pin enable 1: disable SPI_CS0 0: SPI_CS0 pin is active to select SPI device such as flash external RAM and so on.*/
|
||||
uint32_t cs1_dis: 1; /*SPI_CS1 pin enable 1: disable SPI_CS1 0: SPI_CS1 pin is active to select SPI device such as flash external RAM and so on.*/
|
||||
uint32_t reserved2: 1; /*reserved*/
|
||||
uint32_t mst_st_trans_end: 1; /*The bit is used to indicate the spi0_mst_st controlled transmitting is done.*/
|
||||
uint32_t mst_st_trans_end_en: 1; /*The bit is used to enable the interrupt of spi0_mst_st controlled transmitting is done.*/
|
||||
uint32_t st_trans_end: 1; /*The bit is used to indicate the spi0_slv_st controlled transmitting is done.*/
|
||||
uint32_t st_trans_end_en: 1; /*The bit is used to enable the interrupt of spi0_slv_st controlled transmitting is done.*/
|
||||
uint32_t reserved7: 2; /*reserved*/
|
||||
uint32_t ck_idle_edge: 1; /*1: spi clk line is high when idle 0: spi clk line is low when idle*/
|
||||
uint32_t cs_keep_active: 1; /*spi cs line keep low when the bit is set.*/
|
||||
uint32_t reserved11: 21; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} misc;
|
||||
uint32_t tx_crc; /*SPI1 TX CRC data register.*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t req_en: 1; /*For SPI0 Cache access enable 1: enable 0:disable.*/
|
||||
uint32_t usr_addr_4byte: 1; /*For SPI1 cache read flash with 4 bytes address 1: enable 0:disable.*/
|
||||
uint32_t flash_usr_cmd: 1; /*For SPI0 cache read flash for user define command 1: enable 0:disable.*/
|
||||
uint32_t fdin_dual: 1; /*For SPI1 din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
|
||||
uint32_t fdout_dual: 1; /*For SPI1 dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
|
||||
uint32_t faddr_dual: 1; /*For SPI1 address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
|
||||
uint32_t fdin_quad: 1; /*For SPI1 din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/
|
||||
uint32_t fdout_quad: 1; /*For SPI1 dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/
|
||||
uint32_t faddr_quad: 1; /*For SPI1 address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/
|
||||
uint32_t reserved9: 23; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} cache_fctrl;
|
||||
uint32_t reserved_40;
|
||||
uint32_t reserved_44;
|
||||
uint32_t reserved_48;
|
||||
uint32_t reserved_4c;
|
||||
uint32_t reserved_50;
|
||||
union {
|
||||
struct {
|
||||
uint32_t spi0_st: 4; /*The current status of SPI0 slave FSM: spi0_slv_st. 0: idle state 1: preparation state 2: send command state 3: send address state 4: wait state 5: read data state 6:write data state 7: done state 8: read data end state.*/
|
||||
uint32_t spi0_mst_st: 3; /*The current status of SPI0 master FSM: spi0_mst_st. 0: idle state 1:EM_CACHE_GRANT 2: program/erase suspend state 3: SPI0 read data state 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO 5: SPI0 write data state.*/
|
||||
uint32_t cspi_lock_delay_time: 5; /*The lock delay time of SPI0/1 arbiter by spi0_slv_st after PER is sent by SPI1.*/
|
||||
uint32_t reserved12: 20; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} fsm;
|
||||
uint32_t data_buf[16];
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 1; /*reserved*/
|
||||
uint32_t waiti_dummy: 1; /*The dummy phase enable when wait flash idle (RDSR)*/
|
||||
uint32_t waiti_cmd: 8; /*The command to wait flash idle(RDSR).*/
|
||||
uint32_t waiti_dummy_cyclelen: 6; /*The dummy cycle length when wait flash idle(RDSR).*/
|
||||
uint32_t reserved16: 16; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_waiti_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_per: 1; /*program erase resume bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
|
||||
uint32_t flash_pes: 1; /*program erase suspend bit program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
|
||||
uint32_t flash_per_wait_en: 1; /*Set this bit to enable SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after program erase suspend.*/
|
||||
uint32_t flash_pes_wait_en: 1; /*Set this bit to enable SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after program erase suspend.*/
|
||||
uint32_t pes_per_en: 1; /*Set this bit to enable PES end triggers PER transfer option. If this bit is 0 application should send PER after PES is done.*/
|
||||
uint32_t flash_pes_en: 1; /*Set this bit to enable Auto-suspending function.*/
|
||||
uint32_t pesr_end_msk: 16; /*The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out status_in[15:0] is valid when two bytes of data are read out) SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].*/
|
||||
uint32_t frd_sus_2b: 1; /*1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when check flash SUS/SUS1/SUS2 status bit*/
|
||||
uint32_t per_end_en: 1; /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0.*/
|
||||
uint32_t pes_end_en: 1; /*1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0.*/
|
||||
uint32_t sus_timeout_cnt: 7; /*When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times it will be treated as check pass.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_sus_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_per_command: 8; /*Program/Erase resume command.*/
|
||||
uint32_t flash_pes_command: 8; /*Program/Erase suspend command.*/
|
||||
uint32_t wait_pesr_command: 16; /*Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_sus_cmd;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_sus: 1; /*The status of flash suspend only used in SPI1.*/
|
||||
uint32_t wait_pesr_cmd_2b:1;
|
||||
uint32_t hpm_dly_128: 1;
|
||||
uint32_t res_dly_128: 1;
|
||||
uint32_t dp_dly_128: 1;
|
||||
uint32_t per_dly_128: 1;
|
||||
uint32_t pes_dly_128: 1;
|
||||
uint32_t spi0_lock_en: 1;
|
||||
uint32_t reserved1: 24; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} sus_status;
|
||||
union {
|
||||
struct {
|
||||
uint32_t timing_clk_ena: 1; /*The bit is used to enable timing adjust clock for all reading operations.*/
|
||||
uint32_t timing_cali: 1; /*The bit is used to enable timing auto-calibration for all reading operations.*/
|
||||
uint32_t extra_dummy_cyclelen: 3; /*add extra dummy spi clock cycle length for spi clock calibration.*/
|
||||
uint32_t reserved5: 27; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} timing_cali;
|
||||
union {
|
||||
struct {
|
||||
uint32_t din0_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
|
||||
uint32_t din1_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
|
||||
uint32_t din2_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
|
||||
uint32_t din3_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
|
||||
uint32_t reserved8: 24; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} din_mode;
|
||||
union {
|
||||
struct {
|
||||
uint32_t din0_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
|
||||
uint32_t din1_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
|
||||
uint32_t din2_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
|
||||
uint32_t din3_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
|
||||
uint32_t reserved8: 24; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} din_num;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dout0_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
|
||||
uint32_t dout1_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
|
||||
uint32_t dout2_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
|
||||
uint32_t dout3_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
|
||||
uint32_t reserved4: 28; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} dout_mode;
|
||||
uint32_t reserved_b8;
|
||||
uint32_t reserved_bc;
|
||||
union {
|
||||
struct {
|
||||
uint32_t per_end_int_ena: 1; /*The enable bit for SPI_MEM_PER_END_INT interrupt.*/
|
||||
uint32_t pes_end_int_ena: 1; /*The enable bit for SPI_MEM_PES_END_INT interrupt.*/
|
||||
uint32_t wpe_end_int_ena: 1; /*The enable bit for SPI_MEM_WPE_END_INT interrupt.*/
|
||||
uint32_t st_end_int_ena: 1; /*The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
|
||||
uint32_t mst_st_end_int_ena: 1; /*The enable bit for SPI_MEM_MST_ST_END_INT interrupt.*/
|
||||
uint32_t reserved5: 27; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t per_end: 1; /*The clear bit for SPI_MEM_PER_END_INT interrupt.*/
|
||||
uint32_t pes_end: 1; /*The clear bit for SPI_MEM_PES_END_INT interrupt.*/
|
||||
uint32_t wpe_end: 1; /*The clear bit for SPI_MEM_WPE_END_INT interrupt.*/
|
||||
uint32_t st_end: 1; /*The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
|
||||
uint32_t mst_st_end: 1; /*The clear bit for SPI_MEM_MST_ST_END_INT interrupt.*/
|
||||
uint32_t reserved5: 27; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t per_end: 1; /*The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed. 0: Others.*/
|
||||
uint32_t pes_end: 1; /*The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended. 0: Others.*/
|
||||
uint32_t wpe_end: 1; /*The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.*/
|
||||
uint32_t st_end: 1; /*The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others*/
|
||||
uint32_t mst_st_end: 1; /*The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others.*/
|
||||
uint32_t reserved5: 27; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t per_end: 1; /*The status bit for SPI_MEM_PER_END_INT interrupt.*/
|
||||
uint32_t pes_end: 1; /*The status bit for SPI_MEM_PES_END_INT interrupt.*/
|
||||
uint32_t wpe_end: 1; /*The status bit for SPI_MEM_WPE_END_INT interrupt.*/
|
||||
uint32_t st_end: 1; /*The status bit for SPI_MEM_SLV_ST_END_INT interrupt.*/
|
||||
uint32_t mst_st_end: 1; /*The status bit for SPI_MEM_MST_ST_END_INT interrupt.*/
|
||||
uint32_t reserved5: 27; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_st;
|
||||
uint32_t reserved_d0;
|
||||
uint32_t reserved_d4;
|
||||
uint32_t reserved_d8;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_en: 1; /*Register clock gate enable signal. 1: Enable. 0: Disable.*/
|
||||
uint32_t reserved1: 31; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} clock_gate;
|
||||
union {
|
||||
struct {
|
||||
uint32_t spi01_clk_sel: 2; /*When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used.*/
|
||||
uint32_t reserved2: 30; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} core_clk_sel;
|
||||
uint32_t reserved_e4;
|
||||
uint32_t reserved_e8;
|
||||
uint32_t reserved_ec;
|
||||
uint32_t reserved_f0;
|
||||
uint32_t reserved_f4;
|
||||
uint32_t reserved_f8;
|
||||
uint32_t reserved_fc;
|
||||
uint32_t reserved_100;
|
||||
uint32_t reserved_104;
|
||||
uint32_t reserved_108;
|
||||
uint32_t reserved_10c;
|
||||
uint32_t reserved_110;
|
||||
uint32_t reserved_114;
|
||||
uint32_t reserved_118;
|
||||
uint32_t reserved_11c;
|
||||
uint32_t reserved_120;
|
||||
uint32_t reserved_124;
|
||||
uint32_t reserved_128;
|
||||
uint32_t reserved_12c;
|
||||
uint32_t reserved_130;
|
||||
uint32_t reserved_134;
|
||||
uint32_t reserved_138;
|
||||
uint32_t reserved_13c;
|
||||
uint32_t reserved_140;
|
||||
uint32_t reserved_144;
|
||||
uint32_t reserved_148;
|
||||
uint32_t reserved_14c;
|
||||
uint32_t reserved_150;
|
||||
uint32_t reserved_154;
|
||||
uint32_t reserved_158;
|
||||
uint32_t reserved_15c;
|
||||
uint32_t reserved_160;
|
||||
uint32_t reserved_164;
|
||||
uint32_t reserved_168;
|
||||
uint32_t reserved_16c;
|
||||
uint32_t reserved_170;
|
||||
uint32_t reserved_174;
|
||||
uint32_t reserved_178;
|
||||
uint32_t reserved_17c;
|
||||
uint32_t reserved_180;
|
||||
uint32_t reserved_184;
|
||||
uint32_t reserved_188;
|
||||
uint32_t reserved_18c;
|
||||
uint32_t reserved_190;
|
||||
uint32_t reserved_194;
|
||||
uint32_t reserved_198;
|
||||
uint32_t reserved_19c;
|
||||
uint32_t reserved_1a0;
|
||||
uint32_t reserved_1a4;
|
||||
uint32_t reserved_1a8;
|
||||
uint32_t reserved_1ac;
|
||||
uint32_t reserved_1b0;
|
||||
uint32_t reserved_1b4;
|
||||
uint32_t reserved_1b8;
|
||||
uint32_t reserved_1bc;
|
||||
uint32_t reserved_1c0;
|
||||
uint32_t reserved_1c4;
|
||||
uint32_t reserved_1c8;
|
||||
uint32_t reserved_1cc;
|
||||
uint32_t reserved_1d0;
|
||||
uint32_t reserved_1d4;
|
||||
uint32_t reserved_1d8;
|
||||
uint32_t reserved_1dc;
|
||||
uint32_t reserved_1e0;
|
||||
uint32_t reserved_1e4;
|
||||
uint32_t reserved_1e8;
|
||||
uint32_t reserved_1ec;
|
||||
uint32_t reserved_1f0;
|
||||
uint32_t reserved_1f4;
|
||||
uint32_t reserved_1f8;
|
||||
uint32_t reserved_1fc;
|
||||
uint32_t reserved_200;
|
||||
uint32_t reserved_204;
|
||||
uint32_t reserved_208;
|
||||
uint32_t reserved_20c;
|
||||
uint32_t reserved_210;
|
||||
uint32_t reserved_214;
|
||||
uint32_t reserved_218;
|
||||
uint32_t reserved_21c;
|
||||
uint32_t reserved_220;
|
||||
uint32_t reserved_224;
|
||||
uint32_t reserved_228;
|
||||
uint32_t reserved_22c;
|
||||
uint32_t reserved_230;
|
||||
uint32_t reserved_234;
|
||||
uint32_t reserved_238;
|
||||
uint32_t reserved_23c;
|
||||
uint32_t reserved_240;
|
||||
uint32_t reserved_244;
|
||||
uint32_t reserved_248;
|
||||
uint32_t reserved_24c;
|
||||
uint32_t reserved_250;
|
||||
uint32_t reserved_254;
|
||||
uint32_t reserved_258;
|
||||
uint32_t reserved_25c;
|
||||
uint32_t reserved_260;
|
||||
uint32_t reserved_264;
|
||||
uint32_t reserved_268;
|
||||
uint32_t reserved_26c;
|
||||
uint32_t reserved_270;
|
||||
uint32_t reserved_274;
|
||||
uint32_t reserved_278;
|
||||
uint32_t reserved_27c;
|
||||
uint32_t reserved_280;
|
||||
uint32_t reserved_284;
|
||||
uint32_t reserved_288;
|
||||
uint32_t reserved_28c;
|
||||
uint32_t reserved_290;
|
||||
uint32_t reserved_294;
|
||||
uint32_t reserved_298;
|
||||
uint32_t reserved_29c;
|
||||
uint32_t reserved_2a0;
|
||||
uint32_t reserved_2a4;
|
||||
uint32_t reserved_2a8;
|
||||
uint32_t reserved_2ac;
|
||||
uint32_t reserved_2b0;
|
||||
uint32_t reserved_2b4;
|
||||
uint32_t reserved_2b8;
|
||||
uint32_t reserved_2bc;
|
||||
uint32_t reserved_2c0;
|
||||
uint32_t reserved_2c4;
|
||||
uint32_t reserved_2c8;
|
||||
uint32_t reserved_2cc;
|
||||
uint32_t reserved_2d0;
|
||||
uint32_t reserved_2d4;
|
||||
uint32_t reserved_2d8;
|
||||
uint32_t reserved_2dc;
|
||||
uint32_t reserved_2e0;
|
||||
uint32_t reserved_2e4;
|
||||
uint32_t reserved_2e8;
|
||||
uint32_t reserved_2ec;
|
||||
uint32_t reserved_2f0;
|
||||
uint32_t reserved_2f4;
|
||||
uint32_t reserved_2f8;
|
||||
uint32_t reserved_2fc;
|
||||
uint32_t reserved_300;
|
||||
uint32_t reserved_304;
|
||||
uint32_t reserved_308;
|
||||
uint32_t reserved_30c;
|
||||
uint32_t reserved_310;
|
||||
uint32_t reserved_314;
|
||||
uint32_t reserved_318;
|
||||
uint32_t reserved_31c;
|
||||
uint32_t reserved_320;
|
||||
uint32_t reserved_324;
|
||||
uint32_t reserved_328;
|
||||
uint32_t reserved_32c;
|
||||
uint32_t reserved_330;
|
||||
uint32_t reserved_334;
|
||||
uint32_t reserved_338;
|
||||
uint32_t reserved_33c;
|
||||
uint32_t reserved_340;
|
||||
uint32_t reserved_344;
|
||||
uint32_t reserved_348;
|
||||
uint32_t reserved_34c;
|
||||
uint32_t reserved_350;
|
||||
uint32_t reserved_354;
|
||||
uint32_t reserved_358;
|
||||
uint32_t reserved_35c;
|
||||
uint32_t reserved_360;
|
||||
uint32_t reserved_364;
|
||||
uint32_t reserved_368;
|
||||
uint32_t reserved_36c;
|
||||
uint32_t reserved_370;
|
||||
uint32_t reserved_374;
|
||||
uint32_t reserved_378;
|
||||
uint32_t reserved_37c;
|
||||
uint32_t reserved_380;
|
||||
uint32_t reserved_384;
|
||||
uint32_t reserved_388;
|
||||
uint32_t reserved_38c;
|
||||
uint32_t reserved_390;
|
||||
uint32_t reserved_394;
|
||||
uint32_t reserved_398;
|
||||
uint32_t reserved_39c;
|
||||
uint32_t reserved_3a0;
|
||||
uint32_t reserved_3a4;
|
||||
uint32_t reserved_3a8;
|
||||
uint32_t reserved_3ac;
|
||||
uint32_t reserved_3b0;
|
||||
uint32_t reserved_3b4;
|
||||
uint32_t reserved_3b8;
|
||||
uint32_t reserved_3bc;
|
||||
uint32_t reserved_3c0;
|
||||
uint32_t reserved_3c4;
|
||||
uint32_t reserved_3c8;
|
||||
uint32_t reserved_3cc;
|
||||
uint32_t reserved_3d0;
|
||||
uint32_t reserved_3d4;
|
||||
uint32_t reserved_3d8;
|
||||
uint32_t reserved_3dc;
|
||||
uint32_t reserved_3e0;
|
||||
uint32_t reserved_3e4;
|
||||
uint32_t reserved_3e8;
|
||||
uint32_t reserved_3ec;
|
||||
uint32_t reserved_3f0;
|
||||
uint32_t reserved_3f4;
|
||||
uint32_t reserved_3f8;
|
||||
union {
|
||||
struct {
|
||||
uint32_t date: 28; /*Version control register*/
|
||||
uint32_t reserved28: 4; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} date;
|
||||
} spi_mem_dev_t;
|
||||
extern spi_mem_dev_t SPIMEM0;
|
||||
extern spi_mem_dev_t SPIMEM1;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(spi_mem_dev_t) == 0x400, "spi_mem_dev_t size error!");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,368 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct spi_dev_s {
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf_bitlen : 18; /*Define the APB cycles of SPI_CONF state. Can be configured in CONF state.*/
|
||||
uint32_t reserved18 : 5; /*reserved*/
|
||||
uint32_t update : 1; /*Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode.*/
|
||||
uint32_t usr : 1; /*User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf.*/
|
||||
uint32_t reserved25 : 7; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} cmd;
|
||||
uint32_t addr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 3; /*reserved*/
|
||||
uint32_t dummy_out : 1; /*In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state.*/
|
||||
uint32_t reserved4 : 1; /*reserved*/
|
||||
uint32_t faddr_dual : 1; /*Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/
|
||||
uint32_t faddr_quad : 1; /*Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/
|
||||
uint32_t reserved7 : 1; /*reserved*/
|
||||
uint32_t fcmd_dual : 1; /*Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/
|
||||
uint32_t fcmd_quad : 1; /*Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/
|
||||
uint32_t reserved10 : 4; /*reserved*/
|
||||
uint32_t fread_dual : 1; /*In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.*/
|
||||
uint32_t fread_quad : 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state.*/
|
||||
uint32_t reserved16 : 1; /*reserved*/
|
||||
uint32_t reserved17 : 1; /*reserved*/
|
||||
uint32_t q_pol : 1; /*The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state.*/
|
||||
uint32_t d_pol : 1; /*The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.*/
|
||||
uint32_t hold_pol : 1; /*SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.*/
|
||||
uint32_t wp_pol : 1; /*Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.*/
|
||||
uint32_t reserved22 : 3; /*reserved*/
|
||||
uint32_t rd_bit_order : 1; /*In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.*/
|
||||
uint32_t wr_bit_order : 1; /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.*/
|
||||
uint32_t reserved27 : 5; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clkcnt_l : 6; /*In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state.*/
|
||||
uint32_t clkcnt_h : 6; /*In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state.*/
|
||||
uint32_t clkcnt_n : 6; /*In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.*/
|
||||
uint32_t clkdiv_pre : 4; /*In the master mode it is pre-divider of spi_clk. Can be configured in CONF state.*/
|
||||
uint32_t reserved22 : 9; /*reserved*/
|
||||
uint32_t clk_equ_sysclk : 1; /*In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} clock;
|
||||
union {
|
||||
struct {
|
||||
uint32_t doutdin : 1; /*Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state.*/
|
||||
uint32_t reserved1 : 2; /*reserved*/
|
||||
uint32_t qpi_mode : 1; /*Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.*/
|
||||
uint32_t reserved4 : 1; /*reserved*/
|
||||
uint32_t tsck_i_edge : 1; /*In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.*/
|
||||
uint32_t cs_hold : 1; /*spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state.*/
|
||||
uint32_t cs_setup : 1; /*spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state.*/
|
||||
uint32_t rsck_i_edge : 1; /*In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.*/
|
||||
uint32_t ck_out_edge : 1; /*the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state.*/
|
||||
uint32_t reserved10 : 2; /*reserved*/
|
||||
uint32_t fwrite_dual : 1; /*In the write operations read-data phase apply 2 signals. Can be configured in CONF state.*/
|
||||
uint32_t fwrite_quad : 1; /*In the write operations read-data phase apply 4 signals. Can be configured in CONF state.*/
|
||||
uint32_t reserved14 : 1; /*reserved*/
|
||||
uint32_t usr_conf_nxt : 1; /*1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.*/
|
||||
uint32_t reserved16 : 1; /*reserved*/
|
||||
uint32_t sio : 1; /*Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.*/
|
||||
uint32_t reserved18 : 6; /*reserved*/
|
||||
uint32_t usr_miso_highpart : 1; /*read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.*/
|
||||
uint32_t usr_mosi_highpart : 1; /*write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.*/
|
||||
uint32_t usr_dummy_idle : 1; /*spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state.*/
|
||||
uint32_t usr_mosi : 1; /*This bit enable the write-data phase of an operation. Can be configured in CONF state.*/
|
||||
uint32_t usr_miso : 1; /*This bit enable the read-data phase of an operation. Can be configured in CONF state.*/
|
||||
uint32_t usr_dummy : 1; /*This bit enable the dummy phase of an operation. Can be configured in CONF state.*/
|
||||
uint32_t usr_addr : 1; /*This bit enable the address phase of an operation. Can be configured in CONF state.*/
|
||||
uint32_t usr_command : 1; /*This bit enable the command phase of an operation. Can be configured in CONF state.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} user;
|
||||
union {
|
||||
struct {
|
||||
uint32_t usr_dummy_cyclelen : 8; /*The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state.*/
|
||||
uint32_t reserved8 : 8; /*reserved*/
|
||||
uint32_t mst_wfull_err_end_en : 1; /*1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode.*/
|
||||
uint32_t cs_setup_time : 5; /*(cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state.*/
|
||||
uint32_t cs_hold_time : 5; /*delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state.*/
|
||||
uint32_t usr_addr_bitlen : 5; /*The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} user1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t usr_command_value : 16; /*The value of command. Can be configured in CONF state.*/
|
||||
uint32_t reserved16 : 11; /*reserved*/
|
||||
uint32_t mst_rempty_err_end_en : 1; /*1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode.*/
|
||||
uint32_t usr_command_bitlen : 4; /*The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} user2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t ms_data_bitlen : 18; /*The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state.*/
|
||||
uint32_t reserved18 : 14; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} ms_dlen;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cs0_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
|
||||
uint32_t cs1_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
|
||||
uint32_t cs2_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
|
||||
uint32_t cs3_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
|
||||
uint32_t cs4_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
|
||||
uint32_t cs5_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
|
||||
uint32_t ck_dis : 1; /*1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state.*/
|
||||
uint32_t master_cs_pol : 6; /*In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.*/
|
||||
uint32_t reserved13 : 10; /*reserved*/
|
||||
uint32_t slave_cs_pol : 1; /*spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state.*/
|
||||
uint32_t reserved24 : 5; /*reserved*/
|
||||
uint32_t ck_idle_edge : 1; /*1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state.*/
|
||||
uint32_t cs_keep_active : 1; /*spi cs line keep low when the bit is set. Can be configured in CONF state.*/
|
||||
uint32_t quad_din_pin_swap : 1; /*1: spi quad input swap enable 0: spi quad input swap disable. Can be configured in CONF state.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} misc;
|
||||
union {
|
||||
struct {
|
||||
uint32_t din0_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
|
||||
uint32_t din1_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
|
||||
uint32_t din2_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
|
||||
uint32_t din3_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
|
||||
uint32_t reserved8 : 8; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
|
||||
uint32_t timing_hclk_active : 1; /*1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state.*/
|
||||
uint32_t reserved17 : 15; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} din_mode;
|
||||
union {
|
||||
struct {
|
||||
uint32_t din0_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/
|
||||
uint32_t din1_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/
|
||||
uint32_t din2_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/
|
||||
uint32_t din3_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/
|
||||
uint32_t reserved8 : 24; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} din_num;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dout0_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
|
||||
uint32_t dout1_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
|
||||
uint32_t dout2_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
|
||||
uint32_t dout3_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
|
||||
uint32_t reserved4 : 28; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} dout_mode;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 18; /*reserved*/
|
||||
uint32_t dma_seg_trans_en : 1; /*Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.*/
|
||||
uint32_t rx_seg_trans_clr_en : 1; /*1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.*/
|
||||
uint32_t tx_seg_trans_clr_en : 1; /*1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.*/
|
||||
uint32_t rx_eof_en : 1; /*1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.*/
|
||||
uint32_t reserved22 : 5; /*reserved*/
|
||||
uint32_t dma_rx_ena : 1; /*Set this bit to enable SPI DMA controlled receive data mode.*/
|
||||
uint32_t dma_tx_ena : 1; /*Set this bit to enable SPI DMA controlled send data mode.*/
|
||||
uint32_t rx_afifo_rst : 1; /*Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer.*/
|
||||
uint32_t buf_afifo_rst : 1; /*Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer.*/
|
||||
uint32_t dma_afifo_rst : 1; /*Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} dma_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t infifo_full_err : 1; /*The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/
|
||||
uint32_t outfifo_empty_err : 1; /*The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/
|
||||
uint32_t ex_qpi : 1; /*The enable bit for SPI slave Ex_QPI interrupt.*/
|
||||
uint32_t en_qpi : 1; /*The enable bit for SPI slave En_QPI interrupt.*/
|
||||
uint32_t cmd7 : 1; /*The enable bit for SPI slave CMD7 interrupt.*/
|
||||
uint32_t cmd8 : 1; /*The enable bit for SPI slave CMD8 interrupt.*/
|
||||
uint32_t cmd9 : 1; /*The enable bit for SPI slave CMD9 interrupt.*/
|
||||
uint32_t cmda : 1; /*The enable bit for SPI slave CMDA interrupt.*/
|
||||
uint32_t rd_dma_done : 1; /*The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/
|
||||
uint32_t wr_dma_done : 1; /*The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/
|
||||
uint32_t rd_buf_done : 1; /*The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/
|
||||
uint32_t wr_buf_done : 1; /*The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
|
||||
uint32_t trans_done : 1; /*The enable bit for SPI_TRANS_DONE_INT interrupt.*/
|
||||
uint32_t dma_seg_trans_done : 1; /*The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/
|
||||
uint32_t seg_magic_err : 1; /*The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
|
||||
uint32_t buf_addr_err : 1; /*The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
|
||||
uint32_t cmd_err : 1; /*The enable bit for SPI_SLV_CMD_ERR_INT interrupt.*/
|
||||
uint32_t mst_rx_afifo_wfull_err : 1; /*The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
|
||||
uint32_t mst_tx_afifo_rempty_err : 1; /*The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
|
||||
uint32_t app2 : 1; /*The enable bit for SPI_APP2_INT interrupt.*/
|
||||
uint32_t app1 : 1; /*The enable bit for SPI_APP1_INT interrupt.*/
|
||||
uint32_t reserved21 : 11; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} dma_int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t infifo_full_err : 1; /*The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/
|
||||
uint32_t outfifo_empty_err : 1; /*The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/
|
||||
uint32_t ex_qpi : 1; /*The clear bit for SPI slave Ex_QPI interrupt.*/
|
||||
uint32_t en_qpi : 1; /*The clear bit for SPI slave En_QPI interrupt.*/
|
||||
uint32_t cmd7 : 1; /*The clear bit for SPI slave CMD7 interrupt.*/
|
||||
uint32_t cmd8 : 1; /*The clear bit for SPI slave CMD8 interrupt.*/
|
||||
uint32_t cmd9 : 1; /*The clear bit for SPI slave CMD9 interrupt.*/
|
||||
uint32_t cmda : 1; /*The clear bit for SPI slave CMDA interrupt.*/
|
||||
uint32_t rd_dma_done : 1; /*The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/
|
||||
uint32_t wr_dma_done : 1; /*The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/
|
||||
uint32_t rd_buf_done : 1; /*The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/
|
||||
uint32_t wr_buf_done : 1; /*The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
|
||||
uint32_t trans_done : 1; /*The clear bit for SPI_TRANS_DONE_INT interrupt.*/
|
||||
uint32_t dma_seg_trans_done : 1; /*The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/
|
||||
uint32_t seg_magic_err : 1; /*The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
|
||||
uint32_t buf_addr_err : 1; /*The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
|
||||
uint32_t cmd_err : 1; /*The clear bit for SPI_SLV_CMD_ERR_INT interrupt.*/
|
||||
uint32_t mst_rx_afifo_wfull_err : 1; /*The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
|
||||
uint32_t mst_tx_afifo_rempty_err : 1; /*The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
|
||||
uint32_t app2 : 1; /*The clear bit for SPI_APP2_INT interrupt.*/
|
||||
uint32_t app1 : 1; /*The clear bit for SPI_APP1_INT interrupt.*/
|
||||
uint32_t reserved21 : 11; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} dma_int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t infifo_full_err : 1; /*1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others. */
|
||||
uint32_t outfifo_empty_err : 1; /*1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others. */
|
||||
uint32_t ex_qpi : 1; /*The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others.*/
|
||||
uint32_t en_qpi : 1; /*The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others.*/
|
||||
uint32_t cmd7 : 1; /*The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others.*/
|
||||
uint32_t cmd8 : 1; /*The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others.*/
|
||||
uint32_t cmd9 : 1; /*The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others.*/
|
||||
uint32_t cmda : 1; /*The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others.*/
|
||||
uint32_t rd_dma_done : 1; /*The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others.*/
|
||||
uint32_t wr_dma_done : 1; /*The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others.*/
|
||||
uint32_t rd_buf_done : 1; /*The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others.*/
|
||||
uint32_t wr_buf_done : 1; /*The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others.*/
|
||||
uint32_t trans_done : 1; /*The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others.*/
|
||||
uint32_t dma_seg_trans_done : 1; /*The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred. */
|
||||
uint32_t seg_magic_err : 1; /*The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others.*/
|
||||
uint32_t buf_addr_err : 1; /*The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others.*/
|
||||
uint32_t cmd_err : 1; /*The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others.*/
|
||||
uint32_t mst_rx_afifo_wfull_err : 1; /*The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others.*/
|
||||
uint32_t mst_tx_afifo_rempty_err : 1; /*The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others.*/
|
||||
uint32_t app2 : 1; /*The raw bit for SPI_APP2_INT interrupt. The value is only controlled by application.*/
|
||||
uint32_t app1 : 1; /*The raw bit for SPI_APP1_INT interrupt. The value is only controlled by application.*/
|
||||
uint32_t reserved21 : 11; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} dma_int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t infifo_full_err : 1; /*The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/
|
||||
uint32_t outfifo_empty_err : 1; /*The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/
|
||||
uint32_t ex_qpi : 1; /*The status bit for SPI slave Ex_QPI interrupt.*/
|
||||
uint32_t en_qpi : 1; /*The status bit for SPI slave En_QPI interrupt.*/
|
||||
uint32_t cmd7 : 1; /*The status bit for SPI slave CMD7 interrupt.*/
|
||||
uint32_t cmd8 : 1; /*The status bit for SPI slave CMD8 interrupt.*/
|
||||
uint32_t cmd9 : 1; /*The status bit for SPI slave CMD9 interrupt.*/
|
||||
uint32_t cmda : 1; /*The status bit for SPI slave CMDA interrupt.*/
|
||||
uint32_t rd_dma_done : 1; /*The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/
|
||||
uint32_t wr_dma_done : 1; /*The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/
|
||||
uint32_t rd_buf_done : 1; /*The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/
|
||||
uint32_t wr_buf_done : 1; /*The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
|
||||
uint32_t trans_done : 1; /*The status bit for SPI_TRANS_DONE_INT interrupt.*/
|
||||
uint32_t dma_seg_trans_done : 1; /*The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/
|
||||
uint32_t seg_magic_err : 1; /*The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
|
||||
uint32_t buf_addr_err : 1; /*The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
|
||||
uint32_t cmd_err : 1; /*The status bit for SPI_SLV_CMD_ERR_INT interrupt.*/
|
||||
uint32_t mst_rx_afifo_wfull_err : 1; /*The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
|
||||
uint32_t mst_tx_afifo_rempty_err : 1; /*The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
|
||||
uint32_t app2 : 1; /*The status bit for SPI_APP2_INT interrupt.*/
|
||||
uint32_t app1 : 1; /*The status bit for SPI_APP1_INT interrupt.*/
|
||||
uint32_t reserved21 : 11; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} dma_int_st;
|
||||
uint32_t reserved_44;
|
||||
uint32_t reserved_48;
|
||||
uint32_t reserved_4c;
|
||||
uint32_t reserved_50;
|
||||
uint32_t reserved_54;
|
||||
uint32_t reserved_58;
|
||||
uint32_t reserved_5c;
|
||||
uint32_t reserved_60;
|
||||
uint32_t reserved_64;
|
||||
uint32_t reserved_68;
|
||||
uint32_t reserved_6c;
|
||||
uint32_t reserved_70;
|
||||
uint32_t reserved_74;
|
||||
uint32_t reserved_78;
|
||||
uint32_t reserved_7c;
|
||||
uint32_t reserved_80;
|
||||
uint32_t reserved_84;
|
||||
uint32_t reserved_88;
|
||||
uint32_t reserved_8c;
|
||||
uint32_t reserved_90;
|
||||
uint32_t reserved_94;
|
||||
uint32_t data_buf[16];
|
||||
uint32_t reserved_d8;
|
||||
uint32_t reserved_dc;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.*/
|
||||
uint32_t clk_mode_13 : 1; /*{CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].*/
|
||||
uint32_t rsck_data_out : 1; /*It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge */
|
||||
uint32_t reserved4 : 4; /*reserved*/
|
||||
uint32_t rddma_bitlen_en : 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others*/
|
||||
uint32_t wrdma_bitlen_en : 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others*/
|
||||
uint32_t rdbuf_bitlen_en : 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others*/
|
||||
uint32_t wrbuf_bitlen_en : 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others*/
|
||||
uint32_t reserved12 : 10; /*reserved*/
|
||||
uint32_t dma_seg_magic_value : 4; /*The magic value of BM table in master DMA seg-trans.*/
|
||||
uint32_t slave_mode : 1; /*Set SPI work mode. 1: slave mode 0: master mode.*/
|
||||
uint32_t soft_reset : 1; /*Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state.*/
|
||||
uint32_t usr_conf : 1; /*1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode.*/
|
||||
uint32_t reserved29 : 3; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} slave;
|
||||
union {
|
||||
struct {
|
||||
uint32_t data_bitlen : 18; /*The transferred data bit length in SPI slave FD and HD mode. */
|
||||
uint32_t last_command : 8; /*In the slave mode it is the value of command.*/
|
||||
uint32_t last_addr : 6; /*In the slave mode it is the value of address.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} slave1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_en : 1; /*Set this bit to enable clk gate*/
|
||||
uint32_t mst_clk_active : 1; /*Set this bit to power on the SPI module clock.*/
|
||||
uint32_t mst_clk_sel : 1; /*This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK.*/
|
||||
uint32_t reserved3 : 29; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} clk_gate;
|
||||
uint32_t reserved_ec;
|
||||
union {
|
||||
struct {
|
||||
uint32_t date : 28; /*SPI register version.*/
|
||||
uint32_t reserved28 : 4; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} date;
|
||||
} spi_dev_t;
|
||||
|
||||
extern spi_dev_t GPSPI2;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,630 +0,0 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#ifndef _SOC_SYSCON_REG_H_
|
||||
#define _SOC_SYSCON_REG_H_
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#include "soc.h"
|
||||
#define SYSCON_SYSCLK_CONF_REG (DR_REG_SYSCON_BASE + 0x000)
|
||||
/* SYSCON_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define SYSCON_RST_TICK_CNT (BIT(12))
|
||||
#define SYSCON_RST_TICK_CNT_M (BIT(12))
|
||||
#define SYSCON_RST_TICK_CNT_V 0x1
|
||||
#define SYSCON_RST_TICK_CNT_S 12
|
||||
/* SYSCON_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define SYSCON_CLK_EN (BIT(11))
|
||||
#define SYSCON_CLK_EN_M (BIT(11))
|
||||
#define SYSCON_CLK_EN_V 0x1
|
||||
#define SYSCON_CLK_EN_S 11
|
||||
/* SYSCON_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define SYSCON_CLK_320M_EN (BIT(10))
|
||||
#define SYSCON_CLK_320M_EN_M (BIT(10))
|
||||
#define SYSCON_CLK_320M_EN_V 0x1
|
||||
#define SYSCON_CLK_320M_EN_S 10
|
||||
/* SYSCON_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */
|
||||
/*description: */
|
||||
#define SYSCON_PRE_DIV_CNT 0x000003FF
|
||||
#define SYSCON_PRE_DIV_CNT_M ((SYSCON_PRE_DIV_CNT_V)<<(SYSCON_PRE_DIV_CNT_S))
|
||||
#define SYSCON_PRE_DIV_CNT_V 0x3FF
|
||||
#define SYSCON_PRE_DIV_CNT_S 0
|
||||
|
||||
#define SYSCON_TICK_CONF_REG (DR_REG_SYSCON_BASE + 0x004)
|
||||
/* SYSCON_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */
|
||||
/*description: */
|
||||
#define SYSCON_TICK_ENABLE (BIT(16))
|
||||
#define SYSCON_TICK_ENABLE_M (BIT(16))
|
||||
#define SYSCON_TICK_ENABLE_V 0x1
|
||||
#define SYSCON_TICK_ENABLE_S 16
|
||||
/* SYSCON_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */
|
||||
/*description: */
|
||||
#define SYSCON_CK8M_TICK_NUM 0x000000FF
|
||||
#define SYSCON_CK8M_TICK_NUM_M ((SYSCON_CK8M_TICK_NUM_V)<<(SYSCON_CK8M_TICK_NUM_S))
|
||||
#define SYSCON_CK8M_TICK_NUM_V 0xFF
|
||||
#define SYSCON_CK8M_TICK_NUM_S 8
|
||||
/* SYSCON_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */
|
||||
/*description: */
|
||||
#define SYSCON_XTAL_TICK_NUM 0x000000FF
|
||||
#define SYSCON_XTAL_TICK_NUM_M ((SYSCON_XTAL_TICK_NUM_V)<<(SYSCON_XTAL_TICK_NUM_S))
|
||||
#define SYSCON_XTAL_TICK_NUM_V 0xFF
|
||||
#define SYSCON_XTAL_TICK_NUM_S 0
|
||||
|
||||
#define SYSCON_CLK_OUT_EN_REG (DR_REG_SYSCON_BASE + 0x008)
|
||||
/* SYSCON_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define SYSCON_CLK_XTAL_OEN (BIT(10))
|
||||
#define SYSCON_CLK_XTAL_OEN_M (BIT(10))
|
||||
#define SYSCON_CLK_XTAL_OEN_V 0x1
|
||||
#define SYSCON_CLK_XTAL_OEN_S 10
|
||||
/* SYSCON_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define SYSCON_CLK40X_BB_OEN (BIT(9))
|
||||
#define SYSCON_CLK40X_BB_OEN_M (BIT(9))
|
||||
#define SYSCON_CLK40X_BB_OEN_V 0x1
|
||||
#define SYSCON_CLK40X_BB_OEN_S 9
|
||||
/* SYSCON_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define SYSCON_CLK_DAC_CPU_OEN (BIT(8))
|
||||
#define SYSCON_CLK_DAC_CPU_OEN_M (BIT(8))
|
||||
#define SYSCON_CLK_DAC_CPU_OEN_V 0x1
|
||||
#define SYSCON_CLK_DAC_CPU_OEN_S 8
|
||||
/* SYSCON_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define SYSCON_CLK_ADC_INF_OEN (BIT(7))
|
||||
#define SYSCON_CLK_ADC_INF_OEN_M (BIT(7))
|
||||
#define SYSCON_CLK_ADC_INF_OEN_V 0x1
|
||||
#define SYSCON_CLK_ADC_INF_OEN_S 7
|
||||
/* SYSCON_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define SYSCON_CLK_320M_OEN (BIT(6))
|
||||
#define SYSCON_CLK_320M_OEN_M (BIT(6))
|
||||
#define SYSCON_CLK_320M_OEN_V 0x1
|
||||
#define SYSCON_CLK_320M_OEN_S 6
|
||||
/* SYSCON_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define SYSCON_CLK160_OEN (BIT(5))
|
||||
#define SYSCON_CLK160_OEN_M (BIT(5))
|
||||
#define SYSCON_CLK160_OEN_V 0x1
|
||||
#define SYSCON_CLK160_OEN_S 5
|
||||
/* SYSCON_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define SYSCON_CLK80_OEN (BIT(4))
|
||||
#define SYSCON_CLK80_OEN_M (BIT(4))
|
||||
#define SYSCON_CLK80_OEN_V 0x1
|
||||
#define SYSCON_CLK80_OEN_S 4
|
||||
/* SYSCON_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define SYSCON_CLK_BB_OEN (BIT(3))
|
||||
#define SYSCON_CLK_BB_OEN_M (BIT(3))
|
||||
#define SYSCON_CLK_BB_OEN_V 0x1
|
||||
#define SYSCON_CLK_BB_OEN_S 3
|
||||
/* SYSCON_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define SYSCON_CLK44_OEN (BIT(2))
|
||||
#define SYSCON_CLK44_OEN_M (BIT(2))
|
||||
#define SYSCON_CLK44_OEN_V 0x1
|
||||
#define SYSCON_CLK44_OEN_S 2
|
||||
/* SYSCON_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define SYSCON_CLK22_OEN (BIT(1))
|
||||
#define SYSCON_CLK22_OEN_M (BIT(1))
|
||||
#define SYSCON_CLK22_OEN_V 0x1
|
||||
#define SYSCON_CLK22_OEN_S 1
|
||||
/* SYSCON_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define SYSCON_CLK20_OEN (BIT(0))
|
||||
#define SYSCON_CLK20_OEN_M (BIT(0))
|
||||
#define SYSCON_CLK20_OEN_V 0x1
|
||||
#define SYSCON_CLK20_OEN_S 0
|
||||
|
||||
#define SYSCON_WIFI_BB_CFG_REG (DR_REG_SYSCON_BASE + 0x00C)
|
||||
/* SYSCON_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: */
|
||||
#define SYSCON_WIFI_BB_CFG 0xFFFFFFFF
|
||||
#define SYSCON_WIFI_BB_CFG_M ((SYSCON_WIFI_BB_CFG_V)<<(SYSCON_WIFI_BB_CFG_S))
|
||||
#define SYSCON_WIFI_BB_CFG_V 0xFFFFFFFF
|
||||
#define SYSCON_WIFI_BB_CFG_S 0
|
||||
|
||||
#define SYSCON_WIFI_BB_CFG_2_REG (DR_REG_SYSCON_BASE + 0x010)
|
||||
/* SYSCON_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: */
|
||||
#define SYSCON_WIFI_BB_CFG_2 0xFFFFFFFF
|
||||
#define SYSCON_WIFI_BB_CFG_2_M ((SYSCON_WIFI_BB_CFG_2_V)<<(SYSCON_WIFI_BB_CFG_2_S))
|
||||
#define SYSCON_WIFI_BB_CFG_2_V 0xFFFFFFFF
|
||||
#define SYSCON_WIFI_BB_CFG_2_S 0
|
||||
|
||||
#define SYSCON_WIFI_CLK_EN_REG (DR_REG_SYSCON_BASE + 0x014)
|
||||
/* SYSCON_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
|
||||
/*description: */
|
||||
#define SYSCON_WIFI_CLK_EN 0xFFFFFFFF
|
||||
#define SYSCON_WIFI_CLK_EN_M ((SYSCON_WIFI_CLK_EN_V)<<(SYSCON_WIFI_CLK_EN_S))
|
||||
#define SYSCON_WIFI_CLK_EN_V 0xFFFFFFFF
|
||||
#define SYSCON_WIFI_CLK_EN_S 0
|
||||
|
||||
#define SYSCON_WIFI_RST_EN_REG (DR_REG_SYSCON_BASE + 0x018)
|
||||
/* SYSCON_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: */
|
||||
#define SYSCON_WIFI_RST 0xFFFFFFFF
|
||||
#define SYSCON_WIFI_RST_M ((SYSCON_WIFI_RST_V)<<(SYSCON_WIFI_RST_S))
|
||||
#define SYSCON_WIFI_RST_V 0xFFFFFFFF
|
||||
#define SYSCON_WIFI_RST_S 0
|
||||
|
||||
#define SYSTEM_WIFI_CLK_EN_REG SYSCON_WIFI_CLK_EN_REG
|
||||
/* SYSTEM_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
|
||||
/*description: */
|
||||
#define SYSTEM_WIFI_CLK_EN 0x00FB9FCF
|
||||
#define SYSTEM_WIFI_CLK_EN_M ((SYSTEM_WIFI_CLK_EN_V)<<(SYSTEM_WIFI_CLK_EN_S))
|
||||
#define SYSTEM_WIFI_CLK_EN_V 0x00FB9FCF
|
||||
#define SYSTEM_WIFI_CLK_EN_S 0
|
||||
|
||||
/* Mask for all Wifi clock bits, 6 */
|
||||
#define SYSTEM_WIFI_CLK_WIFI_EN 0x0
|
||||
#define SYSTEM_WIFI_CLK_WIFI_EN_M ((SYSTEM_WIFI_CLK_WIFI_EN_V)<<(SYSTEM_WIFI_CLK_WIFI_EN_S))
|
||||
#define SYSTEM_WIFI_CLK_WIFI_EN_V 0x0
|
||||
#define SYSTEM_WIFI_CLK_WIFI_EN_S 0
|
||||
/* Mask for all Bluetooth clock bits, 11, 16, 17 */
|
||||
#define SYSTEM_WIFI_CLK_BT_EN 0x0
|
||||
#define SYSTEM_WIFI_CLK_BT_EN_M ((SYSTEM_WIFI_CLK_BT_EN_V)<<(SYSTEM_WIFI_CLK_BT_EN_S))
|
||||
#define SYSTEM_WIFI_CLK_BT_EN_V 0x0
|
||||
#define SYSTEM_WIFI_CLK_BT_EN_S 0
|
||||
/* Mask for clock bits used by both WIFI and Bluetooth, 0, 1, 2, 3, 7, 8, 9, 10, 19, 20, 21, 22, 23 */
|
||||
#define SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M 0x78078F
|
||||
|
||||
/* Digital team to check */
|
||||
//bluetooth baseband bit11
|
||||
#define SYSTEM_BT_BASEBAND_EN BIT(11)
|
||||
//bluetooth LC bit16 and bit17
|
||||
#define SYSTEM_BT_LC_EN (BIT(16)|BIT(17))
|
||||
|
||||
/* Remaining single bit clock masks */
|
||||
#define SYSTEM_WIFI_CLK_SDIOSLAVE_EN BIT(4)
|
||||
#define SYSTEM_WIFI_CLK_I2C_CLK_EN BIT(5)
|
||||
#define SYSTEM_WIFI_CLK_UNUSED_BIT12 BIT(12)
|
||||
#define SYSTEM_WIFI_CLK_EMAC_EN BIT(14)
|
||||
#define SYSTEM_WIFI_CLK_RNG_EN BIT(15)
|
||||
|
||||
#define SYSTEM_CORE_RST_EN_REG SYSTEM_WIFI_RST_EN_REG
|
||||
#define SYSTEM_WIFI_RST_EN_REG SYSCON_WIFI_RST_EN_REG
|
||||
|
||||
/* SYSTEM_WIFI_RST_EN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: */
|
||||
#define SYSTEM_WIFIBB_RST BIT(0)
|
||||
#define SYSTEM_FE_RST BIT(1)
|
||||
#define SYSTEM_WIFIMAC_RST BIT(2)
|
||||
#define SYSTEM_BTBB_RST BIT(3) /* Bluetooth Baseband */
|
||||
#define SYSTEM_BTMAC_RST BIT(4) /* deprecated */
|
||||
#define SYSTEM_SDIO_RST BIT(5)
|
||||
#define SYSTEM_EMAC_RST BIT(7)
|
||||
#define SYSTEM_MACPWR_RST BIT(8)
|
||||
#define SYSTEM_RW_BTMAC_RST BIT(9) /* Bluetooth MAC */
|
||||
#define SYSTEM_RW_BTLP_RST BIT(10) /* Bluetooth Low Power Module */
|
||||
#define SYSTEM_RW_BTMAC_REG_RST BIT(11) /* Bluetooth MAC Regsiters */
|
||||
#define SYSTEM_RW_BTLP_REG_RST BIT(12) /* Bluetooth Low Power Registers */
|
||||
#define SYSTEM_BTBB_REG_RST BIT(13) /* Bluetooth Baseband Registers */
|
||||
|
||||
#define MODEM_RESET_FIELD_WHEN_PU (SYSTEM_WIFIBB_RST | \
|
||||
SYSTEM_FE_RST | \
|
||||
SYSTEM_WIFIMAC_RST | \
|
||||
SYSTEM_BTBB_RST | \
|
||||
SYSTEM_BTMAC_RST | \
|
||||
SYSTEM_RW_BTMAC_RST | \
|
||||
SYSTEM_RW_BTMAC_REG_RST | \
|
||||
SYSTEM_BTBB_REG_RST)
|
||||
|
||||
#define SYSCON_HOST_INF_SEL_REG (DR_REG_SYSCON_BASE + 0x01C)
|
||||
/* SYSCON_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
|
||||
/*description: */
|
||||
#define SYSCON_PERI_IO_SWAP 0x000000FF
|
||||
#define SYSCON_PERI_IO_SWAP_M ((SYSCON_PERI_IO_SWAP_V)<<(SYSCON_PERI_IO_SWAP_S))
|
||||
#define SYSCON_PERI_IO_SWAP_V 0xFF
|
||||
#define SYSCON_PERI_IO_SWAP_S 0
|
||||
|
||||
#define SYSCON_EXT_MEM_PMS_LOCK_REG (DR_REG_SYSCON_BASE + 0x020)
|
||||
/* SYSCON_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define SYSCON_EXT_MEM_PMS_LOCK (BIT(0))
|
||||
#define SYSCON_EXT_MEM_PMS_LOCK_M (BIT(0))
|
||||
#define SYSCON_EXT_MEM_PMS_LOCK_V 0x1
|
||||
#define SYSCON_EXT_MEM_PMS_LOCK_S 0
|
||||
|
||||
#define SYSCON_FLASH_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x028)
|
||||
/* SYSCON_FLASH_ACE0_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
|
||||
/*description: */
|
||||
#define SYSCON_FLASH_ACE0_ATTR 0x00000003
|
||||
#define SYSCON_FLASH_ACE0_ATTR_M ((SYSCON_FLASH_ACE0_ATTR_V)<<(SYSCON_FLASH_ACE0_ATTR_S))
|
||||
#define SYSCON_FLASH_ACE0_ATTR_V 0x3
|
||||
#define SYSCON_FLASH_ACE0_ATTR_S 0
|
||||
|
||||
#define SYSCON_FLASH_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x02C)
|
||||
/* SYSCON_FLASH_ACE1_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
|
||||
/*description: */
|
||||
#define SYSCON_FLASH_ACE1_ATTR 0x00000003
|
||||
#define SYSCON_FLASH_ACE1_ATTR_M ((SYSCON_FLASH_ACE1_ATTR_V)<<(SYSCON_FLASH_ACE1_ATTR_S))
|
||||
#define SYSCON_FLASH_ACE1_ATTR_V 0x3
|
||||
#define SYSCON_FLASH_ACE1_ATTR_S 0
|
||||
|
||||
#define SYSCON_FLASH_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x030)
|
||||
/* SYSCON_FLASH_ACE2_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
|
||||
/*description: */
|
||||
#define SYSCON_FLASH_ACE2_ATTR 0x00000003
|
||||
#define SYSCON_FLASH_ACE2_ATTR_M ((SYSCON_FLASH_ACE2_ATTR_V)<<(SYSCON_FLASH_ACE2_ATTR_S))
|
||||
#define SYSCON_FLASH_ACE2_ATTR_V 0x3
|
||||
#define SYSCON_FLASH_ACE2_ATTR_S 0
|
||||
|
||||
#define SYSCON_FLASH_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x034)
|
||||
/* SYSCON_FLASH_ACE3_ATTR : R/W ;bitpos:[1:0] ;default: 2'h3 ; */
|
||||
/*description: */
|
||||
#define SYSCON_FLASH_ACE3_ATTR 0x00000003
|
||||
#define SYSCON_FLASH_ACE3_ATTR_M ((SYSCON_FLASH_ACE3_ATTR_V)<<(SYSCON_FLASH_ACE3_ATTR_S))
|
||||
#define SYSCON_FLASH_ACE3_ATTR_V 0x3
|
||||
#define SYSCON_FLASH_ACE3_ATTR_S 0
|
||||
|
||||
#define SYSCON_FLASH_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x038)
|
||||
/* SYSCON_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: */
|
||||
#define SYSCON_FLASH_ACE0_ADDR_S 0xFFFFFFFF
|
||||
#define SYSCON_FLASH_ACE0_ADDR_S_M ((SYSCON_FLASH_ACE0_ADDR_S_V)<<(SYSCON_FLASH_ACE0_ADDR_S_S))
|
||||
#define SYSCON_FLASH_ACE0_ADDR_S_V 0xFFFFFFFF
|
||||
#define SYSCON_FLASH_ACE0_ADDR_S_S 0
|
||||
|
||||
#define SYSCON_FLASH_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x03C)
|
||||
/* SYSCON_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h400000 ; */
|
||||
/*description: */
|
||||
#define SYSCON_FLASH_ACE1_ADDR_S 0xFFFFFFFF
|
||||
#define SYSCON_FLASH_ACE1_ADDR_S_M ((SYSCON_FLASH_ACE1_ADDR_S_V)<<(SYSCON_FLASH_ACE1_ADDR_S_S))
|
||||
#define SYSCON_FLASH_ACE1_ADDR_S_V 0xFFFFFFFF
|
||||
#define SYSCON_FLASH_ACE1_ADDR_S_S 0
|
||||
|
||||
#define SYSCON_FLASH_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x040)
|
||||
/* SYSCON_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h800000 ; */
|
||||
/*description: */
|
||||
#define SYSCON_FLASH_ACE2_ADDR_S 0xFFFFFFFF
|
||||
#define SYSCON_FLASH_ACE2_ADDR_S_M ((SYSCON_FLASH_ACE2_ADDR_S_V)<<(SYSCON_FLASH_ACE2_ADDR_S_S))
|
||||
#define SYSCON_FLASH_ACE2_ADDR_S_V 0xFFFFFFFF
|
||||
#define SYSCON_FLASH_ACE2_ADDR_S_S 0
|
||||
|
||||
#define SYSCON_FLASH_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x044)
|
||||
/* SYSCON_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'hC00000 ; */
|
||||
/*description: */
|
||||
#define SYSCON_FLASH_ACE3_ADDR_S 0xFFFFFFFF
|
||||
#define SYSCON_FLASH_ACE3_ADDR_S_M ((SYSCON_FLASH_ACE3_ADDR_S_V)<<(SYSCON_FLASH_ACE3_ADDR_S_S))
|
||||
#define SYSCON_FLASH_ACE3_ADDR_S_V 0xFFFFFFFF
|
||||
#define SYSCON_FLASH_ACE3_ADDR_S_S 0
|
||||
|
||||
#define SYSCON_FLASH_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x048)
|
||||
/* SYSCON_FLASH_ACE0_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
|
||||
/*description: */
|
||||
#define SYSCON_FLASH_ACE0_SIZE 0x00001FFF
|
||||
#define SYSCON_FLASH_ACE0_SIZE_M ((SYSCON_FLASH_ACE0_SIZE_V)<<(SYSCON_FLASH_ACE0_SIZE_S))
|
||||
#define SYSCON_FLASH_ACE0_SIZE_V 0x1FFF
|
||||
#define SYSCON_FLASH_ACE0_SIZE_S 0
|
||||
|
||||
#define SYSCON_FLASH_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x04C)
|
||||
/* SYSCON_FLASH_ACE1_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
|
||||
/*description: */
|
||||
#define SYSCON_FLASH_ACE1_SIZE 0x00001FFF
|
||||
#define SYSCON_FLASH_ACE1_SIZE_M ((SYSCON_FLASH_ACE1_SIZE_V)<<(SYSCON_FLASH_ACE1_SIZE_S))
|
||||
#define SYSCON_FLASH_ACE1_SIZE_V 0x1FFF
|
||||
#define SYSCON_FLASH_ACE1_SIZE_S 0
|
||||
|
||||
#define SYSCON_FLASH_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x050)
|
||||
/* SYSCON_FLASH_ACE2_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
|
||||
/*description: */
|
||||
#define SYSCON_FLASH_ACE2_SIZE 0x00001FFF
|
||||
#define SYSCON_FLASH_ACE2_SIZE_M ((SYSCON_FLASH_ACE2_SIZE_V)<<(SYSCON_FLASH_ACE2_SIZE_S))
|
||||
#define SYSCON_FLASH_ACE2_SIZE_V 0x1FFF
|
||||
#define SYSCON_FLASH_ACE2_SIZE_S 0
|
||||
|
||||
#define SYSCON_FLASH_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x054)
|
||||
/* SYSCON_FLASH_ACE3_SIZE : R/W ;bitpos:[12:0] ;default: 13'h400 ; */
|
||||
/*description: */
|
||||
#define SYSCON_FLASH_ACE3_SIZE 0x00001FFF
|
||||
#define SYSCON_FLASH_ACE3_SIZE_M ((SYSCON_FLASH_ACE3_SIZE_V)<<(SYSCON_FLASH_ACE3_SIZE_S))
|
||||
#define SYSCON_FLASH_ACE3_SIZE_V 0x1FFF
|
||||
#define SYSCON_FLASH_ACE3_SIZE_S 0
|
||||
|
||||
#define SYSCON_SPI_MEM_PMS_CTRL_REG (DR_REG_SYSCON_BASE + 0x088)
|
||||
/* SYSCON_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */
|
||||
/*description: */
|
||||
#define SYSCON_SPI_MEM_REJECT_CDE 0x0000001F
|
||||
#define SYSCON_SPI_MEM_REJECT_CDE_M ((SYSCON_SPI_MEM_REJECT_CDE_V)<<(SYSCON_SPI_MEM_REJECT_CDE_S))
|
||||
#define SYSCON_SPI_MEM_REJECT_CDE_V 0x1F
|
||||
#define SYSCON_SPI_MEM_REJECT_CDE_S 2
|
||||
/* SYSCON_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define SYSCON_SPI_MEM_REJECT_CLR (BIT(1))
|
||||
#define SYSCON_SPI_MEM_REJECT_CLR_M (BIT(1))
|
||||
#define SYSCON_SPI_MEM_REJECT_CLR_V 0x1
|
||||
#define SYSCON_SPI_MEM_REJECT_CLR_S 1
|
||||
/* SYSCON_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define SYSCON_SPI_MEM_REJECT_INT (BIT(0))
|
||||
#define SYSCON_SPI_MEM_REJECT_INT_M (BIT(0))
|
||||
#define SYSCON_SPI_MEM_REJECT_INT_V 0x1
|
||||
#define SYSCON_SPI_MEM_REJECT_INT_S 0
|
||||
|
||||
#define SYSCON_SPI_MEM_REJECT_ADDR_REG (DR_REG_SYSCON_BASE + 0x08C)
|
||||
/* SYSCON_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: */
|
||||
#define SYSCON_SPI_MEM_REJECT_ADDR 0xFFFFFFFF
|
||||
#define SYSCON_SPI_MEM_REJECT_ADDR_M ((SYSCON_SPI_MEM_REJECT_ADDR_V)<<(SYSCON_SPI_MEM_REJECT_ADDR_S))
|
||||
#define SYSCON_SPI_MEM_REJECT_ADDR_V 0xFFFFFFFF
|
||||
#define SYSCON_SPI_MEM_REJECT_ADDR_S 0
|
||||
|
||||
#define SYSCON_SDIO_CTRL_REG (DR_REG_SYSCON_BASE + 0x090)
|
||||
/* SYSCON_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
|
||||
/*description: */
|
||||
#define SYSCON_SDIO_WIN_ACCESS_EN (BIT(0))
|
||||
#define SYSCON_SDIO_WIN_ACCESS_EN_M (BIT(0))
|
||||
#define SYSCON_SDIO_WIN_ACCESS_EN_V 0x1
|
||||
#define SYSCON_SDIO_WIN_ACCESS_EN_S 0
|
||||
|
||||
#define SYSCON_REDCY_SIG0_REG (DR_REG_SYSCON_BASE + 0x094)
|
||||
/* SYSCON_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
|
||||
/*description: */
|
||||
#define SYSCON_REDCY_ANDOR (BIT(31))
|
||||
#define SYSCON_REDCY_ANDOR_M (BIT(31))
|
||||
#define SYSCON_REDCY_ANDOR_V 0x1
|
||||
#define SYSCON_REDCY_ANDOR_S 31
|
||||
/* SYSCON_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
|
||||
/*description: */
|
||||
#define SYSCON_REDCY_SIG0 0x7FFFFFFF
|
||||
#define SYSCON_REDCY_SIG0_M ((SYSCON_REDCY_SIG0_V)<<(SYSCON_REDCY_SIG0_S))
|
||||
#define SYSCON_REDCY_SIG0_V 0x7FFFFFFF
|
||||
#define SYSCON_REDCY_SIG0_S 0
|
||||
|
||||
#define SYSCON_REDCY_SIG1_REG (DR_REG_SYSCON_BASE + 0x098)
|
||||
/* SYSCON_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
|
||||
/*description: */
|
||||
#define SYSCON_REDCY_NANDOR (BIT(31))
|
||||
#define SYSCON_REDCY_NANDOR_M (BIT(31))
|
||||
#define SYSCON_REDCY_NANDOR_V 0x1
|
||||
#define SYSCON_REDCY_NANDOR_S 31
|
||||
/* SYSCON_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
|
||||
/*description: */
|
||||
#define SYSCON_REDCY_SIG1 0x7FFFFFFF
|
||||
#define SYSCON_REDCY_SIG1_M ((SYSCON_REDCY_SIG1_V)<<(SYSCON_REDCY_SIG1_S))
|
||||
#define SYSCON_REDCY_SIG1_V 0x7FFFFFFF
|
||||
#define SYSCON_REDCY_SIG1_S 0
|
||||
|
||||
#define SYSCON_FRONT_END_MEM_PD_REG (DR_REG_SYSCON_BASE + 0x09C)
|
||||
/* SYSCON_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define SYSCON_DC_MEM_FORCE_PD (BIT(5))
|
||||
#define SYSCON_DC_MEM_FORCE_PD_M (BIT(5))
|
||||
#define SYSCON_DC_MEM_FORCE_PD_V 0x1
|
||||
#define SYSCON_DC_MEM_FORCE_PD_S 5
|
||||
/* SYSCON_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define SYSCON_DC_MEM_FORCE_PU (BIT(4))
|
||||
#define SYSCON_DC_MEM_FORCE_PU_M (BIT(4))
|
||||
#define SYSCON_DC_MEM_FORCE_PU_V 0x1
|
||||
#define SYSCON_DC_MEM_FORCE_PU_S 4
|
||||
/* SYSCON_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define SYSCON_PBUS_MEM_FORCE_PD (BIT(3))
|
||||
#define SYSCON_PBUS_MEM_FORCE_PD_M (BIT(3))
|
||||
#define SYSCON_PBUS_MEM_FORCE_PD_V 0x1
|
||||
#define SYSCON_PBUS_MEM_FORCE_PD_S 3
|
||||
/* SYSCON_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define SYSCON_PBUS_MEM_FORCE_PU (BIT(2))
|
||||
#define SYSCON_PBUS_MEM_FORCE_PU_M (BIT(2))
|
||||
#define SYSCON_PBUS_MEM_FORCE_PU_V 0x1
|
||||
#define SYSCON_PBUS_MEM_FORCE_PU_S 2
|
||||
/* SYSCON_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define SYSCON_AGC_MEM_FORCE_PD (BIT(1))
|
||||
#define SYSCON_AGC_MEM_FORCE_PD_M (BIT(1))
|
||||
#define SYSCON_AGC_MEM_FORCE_PD_V 0x1
|
||||
#define SYSCON_AGC_MEM_FORCE_PD_S 1
|
||||
/* SYSCON_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define SYSCON_AGC_MEM_FORCE_PU (BIT(0))
|
||||
#define SYSCON_AGC_MEM_FORCE_PU_M (BIT(0))
|
||||
#define SYSCON_AGC_MEM_FORCE_PU_V 0x1
|
||||
#define SYSCON_AGC_MEM_FORCE_PU_S 0
|
||||
|
||||
#define SYSCON_RETENTION_CTRL_REG (DR_REG_SYSCON_BASE + 0x0A0)
|
||||
/* SYSCON_NOBYPASS_CPU_ISO_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define SYSCON_NOBYPASS_CPU_ISO_RST (BIT(27))
|
||||
#define SYSCON_NOBYPASS_CPU_ISO_RST_M (BIT(27))
|
||||
#define SYSCON_NOBYPASS_CPU_ISO_RST_V 0x1
|
||||
#define SYSCON_NOBYPASS_CPU_ISO_RST_S 27
|
||||
/* SYSCON_RETENTION_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */
|
||||
/*description: */
|
||||
#define SYSCON_RETENTION_LINK_ADDR 0x07FFFFFF
|
||||
#define SYSCON_RETENTION_LINK_ADDR_M ((SYSCON_RETENTION_LINK_ADDR_V)<<(SYSCON_RETENTION_LINK_ADDR_S))
|
||||
#define SYSCON_RETENTION_LINK_ADDR_V 0x7FFFFFF
|
||||
#define SYSCON_RETENTION_LINK_ADDR_S 0
|
||||
|
||||
#define SYSCON_CLKGATE_FORCE_ON_REG (DR_REG_SYSCON_BASE + 0x0A4)
|
||||
/* SYSCON_SRAM_CLKGATE_FORCE_ON : R/W ;bitpos:[5:2] ;default: ~4'b0 ; */
|
||||
/*description: */
|
||||
#define SYSCON_SRAM_CLKGATE_FORCE_ON 0x0000000F
|
||||
#define SYSCON_SRAM_CLKGATE_FORCE_ON_M ((SYSCON_SRAM_CLKGATE_FORCE_ON_V)<<(SYSCON_SRAM_CLKGATE_FORCE_ON_S))
|
||||
#define SYSCON_SRAM_CLKGATE_FORCE_ON_V 0xF
|
||||
#define SYSCON_SRAM_CLKGATE_FORCE_ON_S 2
|
||||
/* SYSCON_ROM_CLKGATE_FORCE_ON : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
|
||||
/*description: */
|
||||
#define SYSCON_ROM_CLKGATE_FORCE_ON 0x00000003
|
||||
#define SYSCON_ROM_CLKGATE_FORCE_ON_M ((SYSCON_ROM_CLKGATE_FORCE_ON_V)<<(SYSCON_ROM_CLKGATE_FORCE_ON_S))
|
||||
#define SYSCON_ROM_CLKGATE_FORCE_ON_V 0x3
|
||||
#define SYSCON_ROM_CLKGATE_FORCE_ON_S 0
|
||||
|
||||
#define SYSCON_MEM_POWER_DOWN_REG (DR_REG_SYSCON_BASE + 0x0A8)
|
||||
/* SYSCON_SRAM_POWER_DOWN : R/W ;bitpos:[5:2] ;default: 4'b0 ; */
|
||||
/*description: */
|
||||
#define SYSCON_SRAM_POWER_DOWN 0x0000000F
|
||||
#define SYSCON_SRAM_POWER_DOWN_M ((SYSCON_SRAM_POWER_DOWN_V)<<(SYSCON_SRAM_POWER_DOWN_S))
|
||||
#define SYSCON_SRAM_POWER_DOWN_V 0xF
|
||||
#define SYSCON_SRAM_POWER_DOWN_S 2
|
||||
/* SYSCON_ROM_POWER_DOWN : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
|
||||
/*description: */
|
||||
#define SYSCON_ROM_POWER_DOWN 0x00000003
|
||||
#define SYSCON_ROM_POWER_DOWN_M ((SYSCON_ROM_POWER_DOWN_V)<<(SYSCON_ROM_POWER_DOWN_S))
|
||||
#define SYSCON_ROM_POWER_DOWN_V 0x3
|
||||
#define SYSCON_ROM_POWER_DOWN_S 0
|
||||
|
||||
#define SYSCON_MEM_POWER_UP_REG (DR_REG_SYSCON_BASE + 0x0AC)
|
||||
/* SYSCON_SRAM_POWER_UP : R/W ;bitpos:[5:2] ;default: ~4'b0 ; */
|
||||
/*description: */
|
||||
#define SYSCON_SRAM_POWER_UP 0x0000000F
|
||||
#define SYSCON_SRAM_POWER_UP_M ((SYSCON_SRAM_POWER_UP_V)<<(SYSCON_SRAM_POWER_UP_S))
|
||||
#define SYSCON_SRAM_POWER_UP_V 0xF
|
||||
#define SYSCON_SRAM_POWER_UP_S 2
|
||||
/* SYSCON_ROM_POWER_UP : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
|
||||
/*description: */
|
||||
#define SYSCON_ROM_POWER_UP 0x00000003
|
||||
#define SYSCON_ROM_POWER_UP_M ((SYSCON_ROM_POWER_UP_V)<<(SYSCON_ROM_POWER_UP_S))
|
||||
#define SYSCON_ROM_POWER_UP_V 0x3
|
||||
#define SYSCON_ROM_POWER_UP_S 0
|
||||
|
||||
#define SYSCON_RND_DATA_REG (DR_REG_SYSCON_BASE + 0x0B0)
|
||||
/* SYSCON_RND_DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
|
||||
/*description: */
|
||||
#define SYSCON_RND_DATA 0xFFFFFFFF
|
||||
#define SYSCON_RND_DATA_M ((SYSCON_RND_DATA_V)<<(SYSCON_RND_DATA_S))
|
||||
#define SYSCON_RND_DATA_V 0xFFFFFFFF
|
||||
#define SYSCON_RND_DATA_S 0
|
||||
|
||||
#define SYSCON_PERI_BACKUP_CONFIG_REG (DR_REG_SYSCON_BASE + 0x0B4)
|
||||
/* SYSCON_PERI_BACKUP_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define SYSCON_PERI_BACKUP_ENA (BIT(31))
|
||||
#define SYSCON_PERI_BACKUP_ENA_M (BIT(31))
|
||||
#define SYSCON_PERI_BACKUP_ENA_V 0x1
|
||||
#define SYSCON_PERI_BACKUP_ENA_S 31
|
||||
/* SYSCON_PERI_BACKUP_TO_MEM : R/W ;bitpos:[30] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define SYSCON_PERI_BACKUP_TO_MEM (BIT(30))
|
||||
#define SYSCON_PERI_BACKUP_TO_MEM_M (BIT(30))
|
||||
#define SYSCON_PERI_BACKUP_TO_MEM_V 0x1
|
||||
#define SYSCON_PERI_BACKUP_TO_MEM_S 30
|
||||
/* SYSCON_PERI_BACKUP_START : WO ;bitpos:[29] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define SYSCON_PERI_BACKUP_START (BIT(29))
|
||||
#define SYSCON_PERI_BACKUP_START_M (BIT(29))
|
||||
#define SYSCON_PERI_BACKUP_START_V 0x1
|
||||
#define SYSCON_PERI_BACKUP_START_S 29
|
||||
/* SYSCON_PERI_BACKUP_SIZE : R/W ;bitpos:[28:19] ;default: 10'd0 ; */
|
||||
/*description: */
|
||||
#define SYSCON_PERI_BACKUP_SIZE 0x000003FF
|
||||
#define SYSCON_PERI_BACKUP_SIZE_M ((SYSCON_PERI_BACKUP_SIZE_V)<<(SYSCON_PERI_BACKUP_SIZE_S))
|
||||
#define SYSCON_PERI_BACKUP_SIZE_V 0x3FF
|
||||
#define SYSCON_PERI_BACKUP_SIZE_S 19
|
||||
/* SYSCON_PERI_BACKUP_TOUT_THRES : R/W ;bitpos:[18:9] ;default: 10'd50 ; */
|
||||
/*description: */
|
||||
#define SYSCON_PERI_BACKUP_TOUT_THRES 0x000003FF
|
||||
#define SYSCON_PERI_BACKUP_TOUT_THRES_M ((SYSCON_PERI_BACKUP_TOUT_THRES_V)<<(SYSCON_PERI_BACKUP_TOUT_THRES_S))
|
||||
#define SYSCON_PERI_BACKUP_TOUT_THRES_V 0x3FF
|
||||
#define SYSCON_PERI_BACKUP_TOUT_THRES_S 9
|
||||
/* SYSCON_PERI_BACKUP_BURST_LIMIT : R/W ;bitpos:[8:4] ;default: 5'd8 ; */
|
||||
/*description: */
|
||||
#define SYSCON_PERI_BACKUP_BURST_LIMIT 0x0000001F
|
||||
#define SYSCON_PERI_BACKUP_BURST_LIMIT_M ((SYSCON_PERI_BACKUP_BURST_LIMIT_V)<<(SYSCON_PERI_BACKUP_BURST_LIMIT_S))
|
||||
#define SYSCON_PERI_BACKUP_BURST_LIMIT_V 0x1F
|
||||
#define SYSCON_PERI_BACKUP_BURST_LIMIT_S 4
|
||||
/* SYSCON_PERI_BACKUP_FLOW_ERR : RO ;bitpos:[2:1] ;default: 2'd0 ; */
|
||||
/*description: */
|
||||
#define SYSCON_PERI_BACKUP_FLOW_ERR 0x00000003
|
||||
#define SYSCON_PERI_BACKUP_FLOW_ERR_M ((SYSCON_PERI_BACKUP_FLOW_ERR_V)<<(SYSCON_PERI_BACKUP_FLOW_ERR_S))
|
||||
#define SYSCON_PERI_BACKUP_FLOW_ERR_V 0x3
|
||||
#define SYSCON_PERI_BACKUP_FLOW_ERR_S 1
|
||||
|
||||
#define SYSCON_PERI_BACKUP_APB_ADDR_REG (DR_REG_SYSCON_BASE + 0x0B8)
|
||||
/* SYSCON_BACKUP_APB_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
|
||||
/*description: */
|
||||
#define SYSCON_BACKUP_APB_START_ADDR 0xFFFFFFFF
|
||||
#define SYSCON_BACKUP_APB_START_ADDR_M ((SYSCON_BACKUP_APB_START_ADDR_V)<<(SYSCON_BACKUP_APB_START_ADDR_S))
|
||||
#define SYSCON_BACKUP_APB_START_ADDR_V 0xFFFFFFFF
|
||||
#define SYSCON_BACKUP_APB_START_ADDR_S 0
|
||||
|
||||
#define SYSCON_PERI_BACKUP_MEM_ADDR_REG (DR_REG_SYSCON_BASE + 0x0BC)
|
||||
/* SYSCON_BACKUP_MEM_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
|
||||
/*description: */
|
||||
#define SYSCON_BACKUP_MEM_START_ADDR 0xFFFFFFFF
|
||||
#define SYSCON_BACKUP_MEM_START_ADDR_M ((SYSCON_BACKUP_MEM_START_ADDR_V)<<(SYSCON_BACKUP_MEM_START_ADDR_S))
|
||||
#define SYSCON_BACKUP_MEM_START_ADDR_V 0xFFFFFFFF
|
||||
#define SYSCON_BACKUP_MEM_START_ADDR_S 0
|
||||
|
||||
#define SYSCON_PERI_BACKUP_INT_RAW_REG (DR_REG_SYSCON_BASE + 0x0C0)
|
||||
/* SYSCON_PERI_BACKUP_ERR_INT_RAW : RO ;bitpos:[1] ;default: 1'd0 ; */
|
||||
/*description: */
|
||||
#define SYSCON_PERI_BACKUP_ERR_INT_RAW (BIT(1))
|
||||
#define SYSCON_PERI_BACKUP_ERR_INT_RAW_M (BIT(1))
|
||||
#define SYSCON_PERI_BACKUP_ERR_INT_RAW_V 0x1
|
||||
#define SYSCON_PERI_BACKUP_ERR_INT_RAW_S 1
|
||||
/* SYSCON_PERI_BACKUP_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'd0 ; */
|
||||
/*description: */
|
||||
#define SYSCON_PERI_BACKUP_DONE_INT_RAW (BIT(0))
|
||||
#define SYSCON_PERI_BACKUP_DONE_INT_RAW_M (BIT(0))
|
||||
#define SYSCON_PERI_BACKUP_DONE_INT_RAW_V 0x1
|
||||
#define SYSCON_PERI_BACKUP_DONE_INT_RAW_S 0
|
||||
|
||||
#define SYSCON_PERI_BACKUP_INT_ST_REG (DR_REG_SYSCON_BASE + 0x0C4)
|
||||
/* SYSCON_PERI_BACKUP_ERR_INT_ST : RO ;bitpos:[1] ;default: 1'd0 ; */
|
||||
/*description: */
|
||||
#define SYSCON_PERI_BACKUP_ERR_INT_ST (BIT(1))
|
||||
#define SYSCON_PERI_BACKUP_ERR_INT_ST_M (BIT(1))
|
||||
#define SYSCON_PERI_BACKUP_ERR_INT_ST_V 0x1
|
||||
#define SYSCON_PERI_BACKUP_ERR_INT_ST_S 1
|
||||
/* SYSCON_PERI_BACKUP_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'd0 ; */
|
||||
/*description: */
|
||||
#define SYSCON_PERI_BACKUP_DONE_INT_ST (BIT(0))
|
||||
#define SYSCON_PERI_BACKUP_DONE_INT_ST_M (BIT(0))
|
||||
#define SYSCON_PERI_BACKUP_DONE_INT_ST_V 0x1
|
||||
#define SYSCON_PERI_BACKUP_DONE_INT_ST_S 0
|
||||
|
||||
#define SYSCON_PERI_BACKUP_INT_ENA_REG (DR_REG_SYSCON_BASE + 0x0C8)
|
||||
/* SYSCON_PERI_BACKUP_ERR_INT_ENA : R/W ;bitpos:[1] ;default: 1'd0 ; */
|
||||
/*description: */
|
||||
#define SYSCON_PERI_BACKUP_ERR_INT_ENA (BIT(1))
|
||||
#define SYSCON_PERI_BACKUP_ERR_INT_ENA_M (BIT(1))
|
||||
#define SYSCON_PERI_BACKUP_ERR_INT_ENA_V 0x1
|
||||
#define SYSCON_PERI_BACKUP_ERR_INT_ENA_S 1
|
||||
/* SYSCON_PERI_BACKUP_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'd0 ; */
|
||||
/*description: */
|
||||
#define SYSCON_PERI_BACKUP_DONE_INT_ENA (BIT(0))
|
||||
#define SYSCON_PERI_BACKUP_DONE_INT_ENA_M (BIT(0))
|
||||
#define SYSCON_PERI_BACKUP_DONE_INT_ENA_V 0x1
|
||||
#define SYSCON_PERI_BACKUP_DONE_INT_ENA_S 0
|
||||
|
||||
#define SYSCON_PERI_BACKUP_INT_CLR_REG (DR_REG_SYSCON_BASE + 0x0D0)
|
||||
/* SYSCON_PERI_BACKUP_ERR_INT_CLR : WO ;bitpos:[1] ;default: 1'd0 ; */
|
||||
/*description: */
|
||||
#define SYSCON_PERI_BACKUP_ERR_INT_CLR (BIT(1))
|
||||
#define SYSCON_PERI_BACKUP_ERR_INT_CLR_M (BIT(1))
|
||||
#define SYSCON_PERI_BACKUP_ERR_INT_CLR_V 0x1
|
||||
#define SYSCON_PERI_BACKUP_ERR_INT_CLR_S 1
|
||||
/* SYSCON_PERI_BACKUP_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'd0 ; */
|
||||
/*description: */
|
||||
#define SYSCON_PERI_BACKUP_DONE_INT_CLR (BIT(0))
|
||||
#define SYSCON_PERI_BACKUP_DONE_INT_CLR_M (BIT(0))
|
||||
#define SYSCON_PERI_BACKUP_DONE_INT_CLR_V 0x1
|
||||
#define SYSCON_PERI_BACKUP_DONE_INT_CLR_S 0
|
||||
|
||||
#define SYSCON_DATE_REG (DR_REG_SYSCON_BASE + 0x3FC)
|
||||
/* SYSCON_DATE : R/W ;bitpos:[31:0] ;default: 32'h2007210 ; */
|
||||
/*description: Version control*/
|
||||
#define SYSCON_DATE 0xFFFFFFFF
|
||||
#define SYSCON_DATE_M ((SYSCON_DATE_V)<<(SYSCON_DATE_S))
|
||||
#define SYSCON_DATE_V 0xFFFFFFFF
|
||||
#define SYSCON_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /*_SOC_SYSCON_REG_H_ */
|
||||
@@ -1,473 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct syscon_dev_s {
|
||||
union {
|
||||
struct {
|
||||
uint32_t pre_div_cnt: 10;
|
||||
uint32_t clk_320m_en: 1;
|
||||
uint32_t clk_en: 1;
|
||||
uint32_t rst_tick_cnt: 1;
|
||||
uint32_t reserved13: 19;
|
||||
};
|
||||
uint32_t val;
|
||||
} sysclk_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t xtal_tick_num: 8;
|
||||
uint32_t ck8m_tick_num: 8;
|
||||
uint32_t tick_enable: 1;
|
||||
uint32_t reserved17: 15;
|
||||
};
|
||||
uint32_t val;
|
||||
} tick_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk20_oen: 1;
|
||||
uint32_t clk22_oen: 1;
|
||||
uint32_t clk44_oen: 1;
|
||||
uint32_t clk_bb_oen: 1;
|
||||
uint32_t clk80_oen: 1;
|
||||
uint32_t clk160_oen: 1;
|
||||
uint32_t clk_320m_oen: 1;
|
||||
uint32_t clk_adc_inf_oen: 1;
|
||||
uint32_t clk_dac_cpu_oen: 1;
|
||||
uint32_t clk40x_bb_oen: 1;
|
||||
uint32_t clk_xtal_oen: 1;
|
||||
uint32_t reserved11: 21;
|
||||
};
|
||||
uint32_t val;
|
||||
} clk_out_en;
|
||||
uint32_t wifi_bb_cfg; /**/
|
||||
uint32_t wifi_bb_cfg_2; /**/
|
||||
uint32_t wifi_clk_en; /**/
|
||||
uint32_t wifi_rst_en; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t peri_io_swap: 8;
|
||||
uint32_t reserved8: 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} host_inf_sel;
|
||||
union {
|
||||
struct {
|
||||
uint32_t ext_mem_pms_lock: 1;
|
||||
uint32_t reserved1: 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} ext_mem_pms_lock;
|
||||
uint32_t reserved_24;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace0_attr: 2;
|
||||
uint32_t reserved2: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace0_attr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace1_attr: 2;
|
||||
uint32_t reserved2: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace1_attr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace2_attr: 2;
|
||||
uint32_t reserved2: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace2_attr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace3_attr: 2;
|
||||
uint32_t reserved2: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace3_attr;
|
||||
uint32_t flash_ace0_addr; /**/
|
||||
uint32_t flash_ace1_addr; /**/
|
||||
uint32_t flash_ace2_addr; /**/
|
||||
uint32_t flash_ace3_addr; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace0_size:13;
|
||||
uint32_t reserved13: 19;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace0_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace1_size:13;
|
||||
uint32_t reserved13: 19;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace1_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace2_size:13;
|
||||
uint32_t reserved13: 19;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace2_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace3_size:13;
|
||||
uint32_t reserved13: 19;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace3_size;
|
||||
uint32_t reserved_58;
|
||||
uint32_t reserved_5c;
|
||||
uint32_t reserved_60;
|
||||
uint32_t reserved_64;
|
||||
uint32_t reserved_68;
|
||||
uint32_t reserved_6c;
|
||||
uint32_t reserved_70;
|
||||
uint32_t reserved_74;
|
||||
uint32_t reserved_78;
|
||||
uint32_t reserved_7c;
|
||||
uint32_t reserved_80;
|
||||
uint32_t reserved_84;
|
||||
union {
|
||||
struct {
|
||||
uint32_t spi_mem_reject_int: 1;
|
||||
uint32_t spi_mem_reject_clr: 1;
|
||||
uint32_t spi_mem_reject_cde: 5;
|
||||
uint32_t reserved7: 25;
|
||||
};
|
||||
uint32_t val;
|
||||
} spi_mem_pms_ctrl;
|
||||
uint32_t spi_mem_reject_addr; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t sdio_win_access_en: 1;
|
||||
uint32_t reserved1: 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} sdio_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t redcy_sig0: 31;
|
||||
uint32_t redcy_andor: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} redcy_sig0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t redcy_sig1: 31;
|
||||
uint32_t redcy_nandor: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} redcy_sig1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t agc_mem_force_pu: 1;
|
||||
uint32_t agc_mem_force_pd: 1;
|
||||
uint32_t pbus_mem_force_pu: 1;
|
||||
uint32_t pbus_mem_force_pd: 1;
|
||||
uint32_t dc_mem_force_pu: 1;
|
||||
uint32_t dc_mem_force_pd: 1;
|
||||
uint32_t reserved6: 26;
|
||||
};
|
||||
uint32_t val;
|
||||
} front_end_mem_pd;
|
||||
union {
|
||||
struct {
|
||||
uint32_t retention_link_addr: 27;
|
||||
uint32_t nobypass_cpu_iso_rst: 1;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} retention_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rom_clkgate_force_on: 2;
|
||||
uint32_t sram_clkgate_force_on: 4;
|
||||
uint32_t reserved6: 26;
|
||||
};
|
||||
uint32_t val;
|
||||
} clkgate_force_on;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rom_power_down: 2;
|
||||
uint32_t sram_power_down: 4;
|
||||
uint32_t reserved6: 26;
|
||||
};
|
||||
uint32_t val;
|
||||
} mem_power_down;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rom_power_up: 2;
|
||||
uint32_t sram_power_up: 4;
|
||||
uint32_t reserved6: 26;
|
||||
};
|
||||
uint32_t val;
|
||||
} mem_power_up;
|
||||
uint32_t rnd_data; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 1;
|
||||
uint32_t peri_backup_flow_err: 2;
|
||||
uint32_t reserved3: 1;
|
||||
uint32_t peri_backup_burst_limit: 5;
|
||||
uint32_t peri_backup_tout_thres: 10;
|
||||
uint32_t peri_backup_size: 10;
|
||||
uint32_t peri_backup_start: 1;
|
||||
uint32_t peri_backup_to_mem: 1;
|
||||
uint32_t peri_backup_ena: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} peri_backup_config;
|
||||
uint32_t peri_backup_apb_addr; /**/
|
||||
uint32_t peri_backup_mem_addr; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t peri_backup_done: 1;
|
||||
uint32_t peri_backup_err: 1;
|
||||
uint32_t reserved2: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} peri_backup_int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t peri_backup_done: 1;
|
||||
uint32_t peri_backup_err: 1;
|
||||
uint32_t reserved2: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} peri_backup_int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t peri_backup_done: 1;
|
||||
uint32_t peri_backup_err: 1;
|
||||
uint32_t reserved2: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} peri_backup_int_ena;
|
||||
uint32_t reserved_cc;
|
||||
union {
|
||||
struct {
|
||||
uint32_t peri_backup_done: 1;
|
||||
uint32_t peri_backup_err: 1;
|
||||
uint32_t reserved2: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} peri_backup_int_clr;
|
||||
uint32_t reserved_d4;
|
||||
uint32_t reserved_d8;
|
||||
uint32_t reserved_dc;
|
||||
uint32_t reserved_e0;
|
||||
uint32_t reserved_e4;
|
||||
uint32_t reserved_e8;
|
||||
uint32_t reserved_ec;
|
||||
uint32_t reserved_f0;
|
||||
uint32_t reserved_f4;
|
||||
uint32_t reserved_f8;
|
||||
uint32_t reserved_fc;
|
||||
uint32_t reserved_100;
|
||||
uint32_t reserved_104;
|
||||
uint32_t reserved_108;
|
||||
uint32_t reserved_10c;
|
||||
uint32_t reserved_110;
|
||||
uint32_t reserved_114;
|
||||
uint32_t reserved_118;
|
||||
uint32_t reserved_11c;
|
||||
uint32_t reserved_120;
|
||||
uint32_t reserved_124;
|
||||
uint32_t reserved_128;
|
||||
uint32_t reserved_12c;
|
||||
uint32_t reserved_130;
|
||||
uint32_t reserved_134;
|
||||
uint32_t reserved_138;
|
||||
uint32_t reserved_13c;
|
||||
uint32_t reserved_140;
|
||||
uint32_t reserved_144;
|
||||
uint32_t reserved_148;
|
||||
uint32_t reserved_14c;
|
||||
uint32_t reserved_150;
|
||||
uint32_t reserved_154;
|
||||
uint32_t reserved_158;
|
||||
uint32_t reserved_15c;
|
||||
uint32_t reserved_160;
|
||||
uint32_t reserved_164;
|
||||
uint32_t reserved_168;
|
||||
uint32_t reserved_16c;
|
||||
uint32_t reserved_170;
|
||||
uint32_t reserved_174;
|
||||
uint32_t reserved_178;
|
||||
uint32_t reserved_17c;
|
||||
uint32_t reserved_180;
|
||||
uint32_t reserved_184;
|
||||
uint32_t reserved_188;
|
||||
uint32_t reserved_18c;
|
||||
uint32_t reserved_190;
|
||||
uint32_t reserved_194;
|
||||
uint32_t reserved_198;
|
||||
uint32_t reserved_19c;
|
||||
uint32_t reserved_1a0;
|
||||
uint32_t reserved_1a4;
|
||||
uint32_t reserved_1a8;
|
||||
uint32_t reserved_1ac;
|
||||
uint32_t reserved_1b0;
|
||||
uint32_t reserved_1b4;
|
||||
uint32_t reserved_1b8;
|
||||
uint32_t reserved_1bc;
|
||||
uint32_t reserved_1c0;
|
||||
uint32_t reserved_1c4;
|
||||
uint32_t reserved_1c8;
|
||||
uint32_t reserved_1cc;
|
||||
uint32_t reserved_1d0;
|
||||
uint32_t reserved_1d4;
|
||||
uint32_t reserved_1d8;
|
||||
uint32_t reserved_1dc;
|
||||
uint32_t reserved_1e0;
|
||||
uint32_t reserved_1e4;
|
||||
uint32_t reserved_1e8;
|
||||
uint32_t reserved_1ec;
|
||||
uint32_t reserved_1f0;
|
||||
uint32_t reserved_1f4;
|
||||
uint32_t reserved_1f8;
|
||||
uint32_t reserved_1fc;
|
||||
uint32_t reserved_200;
|
||||
uint32_t reserved_204;
|
||||
uint32_t reserved_208;
|
||||
uint32_t reserved_20c;
|
||||
uint32_t reserved_210;
|
||||
uint32_t reserved_214;
|
||||
uint32_t reserved_218;
|
||||
uint32_t reserved_21c;
|
||||
uint32_t reserved_220;
|
||||
uint32_t reserved_224;
|
||||
uint32_t reserved_228;
|
||||
uint32_t reserved_22c;
|
||||
uint32_t reserved_230;
|
||||
uint32_t reserved_234;
|
||||
uint32_t reserved_238;
|
||||
uint32_t reserved_23c;
|
||||
uint32_t reserved_240;
|
||||
uint32_t reserved_244;
|
||||
uint32_t reserved_248;
|
||||
uint32_t reserved_24c;
|
||||
uint32_t reserved_250;
|
||||
uint32_t reserved_254;
|
||||
uint32_t reserved_258;
|
||||
uint32_t reserved_25c;
|
||||
uint32_t reserved_260;
|
||||
uint32_t reserved_264;
|
||||
uint32_t reserved_268;
|
||||
uint32_t reserved_26c;
|
||||
uint32_t reserved_270;
|
||||
uint32_t reserved_274;
|
||||
uint32_t reserved_278;
|
||||
uint32_t reserved_27c;
|
||||
uint32_t reserved_280;
|
||||
uint32_t reserved_284;
|
||||
uint32_t reserved_288;
|
||||
uint32_t reserved_28c;
|
||||
uint32_t reserved_290;
|
||||
uint32_t reserved_294;
|
||||
uint32_t reserved_298;
|
||||
uint32_t reserved_29c;
|
||||
uint32_t reserved_2a0;
|
||||
uint32_t reserved_2a4;
|
||||
uint32_t reserved_2a8;
|
||||
uint32_t reserved_2ac;
|
||||
uint32_t reserved_2b0;
|
||||
uint32_t reserved_2b4;
|
||||
uint32_t reserved_2b8;
|
||||
uint32_t reserved_2bc;
|
||||
uint32_t reserved_2c0;
|
||||
uint32_t reserved_2c4;
|
||||
uint32_t reserved_2c8;
|
||||
uint32_t reserved_2cc;
|
||||
uint32_t reserved_2d0;
|
||||
uint32_t reserved_2d4;
|
||||
uint32_t reserved_2d8;
|
||||
uint32_t reserved_2dc;
|
||||
uint32_t reserved_2e0;
|
||||
uint32_t reserved_2e4;
|
||||
uint32_t reserved_2e8;
|
||||
uint32_t reserved_2ec;
|
||||
uint32_t reserved_2f0;
|
||||
uint32_t reserved_2f4;
|
||||
uint32_t reserved_2f8;
|
||||
uint32_t reserved_2fc;
|
||||
uint32_t reserved_300;
|
||||
uint32_t reserved_304;
|
||||
uint32_t reserved_308;
|
||||
uint32_t reserved_30c;
|
||||
uint32_t reserved_310;
|
||||
uint32_t reserved_314;
|
||||
uint32_t reserved_318;
|
||||
uint32_t reserved_31c;
|
||||
uint32_t reserved_320;
|
||||
uint32_t reserved_324;
|
||||
uint32_t reserved_328;
|
||||
uint32_t reserved_32c;
|
||||
uint32_t reserved_330;
|
||||
uint32_t reserved_334;
|
||||
uint32_t reserved_338;
|
||||
uint32_t reserved_33c;
|
||||
uint32_t reserved_340;
|
||||
uint32_t reserved_344;
|
||||
uint32_t reserved_348;
|
||||
uint32_t reserved_34c;
|
||||
uint32_t reserved_350;
|
||||
uint32_t reserved_354;
|
||||
uint32_t reserved_358;
|
||||
uint32_t reserved_35c;
|
||||
uint32_t reserved_360;
|
||||
uint32_t reserved_364;
|
||||
uint32_t reserved_368;
|
||||
uint32_t reserved_36c;
|
||||
uint32_t reserved_370;
|
||||
uint32_t reserved_374;
|
||||
uint32_t reserved_378;
|
||||
uint32_t reserved_37c;
|
||||
uint32_t reserved_380;
|
||||
uint32_t reserved_384;
|
||||
uint32_t reserved_388;
|
||||
uint32_t reserved_38c;
|
||||
uint32_t reserved_390;
|
||||
uint32_t reserved_394;
|
||||
uint32_t reserved_398;
|
||||
uint32_t reserved_39c;
|
||||
uint32_t reserved_3a0;
|
||||
uint32_t reserved_3a4;
|
||||
uint32_t reserved_3a8;
|
||||
uint32_t reserved_3ac;
|
||||
uint32_t reserved_3b0;
|
||||
uint32_t reserved_3b4;
|
||||
uint32_t reserved_3b8;
|
||||
uint32_t reserved_3bc;
|
||||
uint32_t reserved_3c0;
|
||||
uint32_t reserved_3c4;
|
||||
uint32_t reserved_3c8;
|
||||
uint32_t reserved_3cc;
|
||||
uint32_t reserved_3d0;
|
||||
uint32_t reserved_3d4;
|
||||
uint32_t reserved_3d8;
|
||||
uint32_t reserved_3dc;
|
||||
uint32_t reserved_3e0;
|
||||
uint32_t reserved_3e4;
|
||||
uint32_t reserved_3e8;
|
||||
uint32_t reserved_3ec;
|
||||
uint32_t reserved_3f0;
|
||||
uint32_t reserved_3f4;
|
||||
uint32_t reserved_3f8;
|
||||
uint32_t date; /*Version control*/
|
||||
} syscon_dev_t;
|
||||
extern syscon_dev_t SYSCON;
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,567 +0,0 @@
|
||||
/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** SYSTIMER_CONF_REG register
|
||||
* SYSTIMER_CONF.
|
||||
*/
|
||||
#define SYSTIMER_CONF_REG (DR_REG_SYSTIMER_BASE + 0x0)
|
||||
/** SYSTIMER_SYSTIMER_CLK_FO : R/W; bitpos: [0]; default: 0;
|
||||
* systimer clock force on
|
||||
*/
|
||||
#define SYSTIMER_SYSTIMER_CLK_FO (BIT(0))
|
||||
#define SYSTIMER_SYSTIMER_CLK_FO_M (SYSTIMER_SYSTIMER_CLK_FO_V << SYSTIMER_SYSTIMER_CLK_FO_S)
|
||||
#define SYSTIMER_SYSTIMER_CLK_FO_V 0x00000001
|
||||
#define SYSTIMER_SYSTIMER_CLK_FO_S 0
|
||||
/** SYSTIMER_TARGET2_WORK_EN : R/W; bitpos: [22]; default: 0;
|
||||
* target2 work enable
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_WORK_EN (BIT(22))
|
||||
#define SYSTIMER_TARGET2_WORK_EN_M (SYSTIMER_TARGET2_WORK_EN_V << SYSTIMER_TARGET2_WORK_EN_S)
|
||||
#define SYSTIMER_TARGET2_WORK_EN_V 0x00000001
|
||||
#define SYSTIMER_TARGET2_WORK_EN_S 22
|
||||
/** SYSTIMER_TARGET1_WORK_EN : R/W; bitpos: [23]; default: 0;
|
||||
* target1 work enable
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_WORK_EN (BIT(23))
|
||||
#define SYSTIMER_TARGET1_WORK_EN_M (SYSTIMER_TARGET1_WORK_EN_V << SYSTIMER_TARGET1_WORK_EN_S)
|
||||
#define SYSTIMER_TARGET1_WORK_EN_V 0x00000001
|
||||
#define SYSTIMER_TARGET1_WORK_EN_S 23
|
||||
/** SYSTIMER_TARGET0_WORK_EN : R/W; bitpos: [24]; default: 0;
|
||||
* target0 work enable
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_WORK_EN (BIT(24))
|
||||
#define SYSTIMER_TARGET0_WORK_EN_M (SYSTIMER_TARGET0_WORK_EN_V << SYSTIMER_TARGET0_WORK_EN_S)
|
||||
#define SYSTIMER_TARGET0_WORK_EN_V 0x00000001
|
||||
#define SYSTIMER_TARGET0_WORK_EN_S 24
|
||||
/** SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W; bitpos: [25]; default: 1;
|
||||
* If timer unit1 is stalled when core1 stalled
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN (BIT(25))
|
||||
#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V 0x00000001
|
||||
#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S 25
|
||||
/** SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W; bitpos: [26]; default: 1;
|
||||
* If timer unit1 is stalled when core0 stalled
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN (BIT(26))
|
||||
#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V 0x00000001
|
||||
#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S 26
|
||||
/** SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W; bitpos: [27]; default: 0;
|
||||
* If timer unit0 is stalled when core1 stalled
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN (BIT(27))
|
||||
#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V 0x00000001
|
||||
#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S 27
|
||||
/** SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W; bitpos: [28]; default: 0;
|
||||
* If timer unit0 is stalled when core0 stalled
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN (BIT(28))
|
||||
#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V 0x00000001
|
||||
#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S 28
|
||||
/** SYSTIMER_TIMER_UNIT1_WORK_EN : R/W; bitpos: [29]; default: 0;
|
||||
* timer unit1 work enable
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_WORK_EN (BIT(29))
|
||||
#define SYSTIMER_TIMER_UNIT1_WORK_EN_M (SYSTIMER_TIMER_UNIT1_WORK_EN_V << SYSTIMER_TIMER_UNIT1_WORK_EN_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_WORK_EN_V 0x00000001
|
||||
#define SYSTIMER_TIMER_UNIT1_WORK_EN_S 29
|
||||
/** SYSTIMER_TIMER_UNIT0_WORK_EN : R/W; bitpos: [30]; default: 1;
|
||||
* timer unit0 work enable
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_WORK_EN (BIT(30))
|
||||
#define SYSTIMER_TIMER_UNIT0_WORK_EN_M (SYSTIMER_TIMER_UNIT0_WORK_EN_V << SYSTIMER_TIMER_UNIT0_WORK_EN_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_WORK_EN_V 0x00000001
|
||||
#define SYSTIMER_TIMER_UNIT0_WORK_EN_S 30
|
||||
/** SYSTIMER_CLK_EN : R/W; bitpos: [31]; default: 0;
|
||||
* register file clk gating
|
||||
*/
|
||||
#define SYSTIMER_CLK_EN (BIT(31))
|
||||
#define SYSTIMER_CLK_EN_M (SYSTIMER_CLK_EN_V << SYSTIMER_CLK_EN_S)
|
||||
#define SYSTIMER_CLK_EN_V 0x00000001
|
||||
#define SYSTIMER_CLK_EN_S 31
|
||||
|
||||
/** SYSTIMER_UNIT0_OP_REG register
|
||||
* SYSTIMER_UNIT0_OP.
|
||||
*/
|
||||
#define SYSTIMER_UNIT0_OP_REG (DR_REG_SYSTIMER_BASE + 0x4)
|
||||
/** SYSTIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0;
|
||||
* reg_timer_unit0_value_valid
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_VALID (BIT(29))
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_M (SYSTIMER_TIMER_UNIT0_VALUE_VALID_V << SYSTIMER_TIMER_UNIT0_VALUE_VALID_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_V 0x00000001
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_S 29
|
||||
/** SYSTIMER_TIMER_UNIT0_UPDATE : WT; bitpos: [30]; default: 0;
|
||||
* update timer_unit0
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_UPDATE (BIT(30))
|
||||
#define SYSTIMER_TIMER_UNIT0_UPDATE_M (SYSTIMER_TIMER_UNIT0_UPDATE_V << SYSTIMER_TIMER_UNIT0_UPDATE_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_UPDATE_V 0x00000001
|
||||
#define SYSTIMER_TIMER_UNIT0_UPDATE_S 30
|
||||
|
||||
/** SYSTIMER_UNIT1_OP_REG register
|
||||
* SYSTIMER_UNIT1_OP.
|
||||
*/
|
||||
#define SYSTIMER_UNIT1_OP_REG (DR_REG_SYSTIMER_BASE + 0x8)
|
||||
/** SYSTIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0;
|
||||
* timer value is sync and valid
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_VALID (BIT(29))
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_M (SYSTIMER_TIMER_UNIT1_VALUE_VALID_V << SYSTIMER_TIMER_UNIT1_VALUE_VALID_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_V 0x00000001
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_S 29
|
||||
/** SYSTIMER_TIMER_UNIT1_UPDATE : WT; bitpos: [30]; default: 0;
|
||||
* update timer unit1
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_UPDATE (BIT(30))
|
||||
#define SYSTIMER_TIMER_UNIT1_UPDATE_M (SYSTIMER_TIMER_UNIT1_UPDATE_V << SYSTIMER_TIMER_UNIT1_UPDATE_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_UPDATE_V 0x00000001
|
||||
#define SYSTIMER_TIMER_UNIT1_UPDATE_S 30
|
||||
|
||||
/** SYSTIMER_UNIT0_LOAD_HI_REG register
|
||||
* SYSTIMER_UNIT0_LOAD_HI.
|
||||
*/
|
||||
#define SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0xc)
|
||||
/** SYSTIMER_TIMER_UNIT0_LOAD_HI : R/W; bitpos: [19:0]; default: 0;
|
||||
* timer unit0 load high 32 bit
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_HI 0x000FFFFF
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_HI_M (SYSTIMER_TIMER_UNIT0_LOAD_HI_V << SYSTIMER_TIMER_UNIT0_LOAD_HI_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_HI_V 0x000FFFFF
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_HI_S 0
|
||||
|
||||
/** SYSTIMER_UNIT0_LOAD_LO_REG register
|
||||
* SYSTIMER_UNIT0_LOAD_LO.
|
||||
*/
|
||||
#define SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x10)
|
||||
/** SYSTIMER_TIMER_UNIT0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
|
||||
* timer unit0 load low 32 bit
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_LO 0xFFFFFFFF
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_LO_M (SYSTIMER_TIMER_UNIT0_LOAD_LO_V << SYSTIMER_TIMER_UNIT0_LOAD_LO_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_LO_V 0xFFFFFFFF
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_LO_S 0
|
||||
|
||||
/** SYSTIMER_UNIT1_LOAD_HI_REG register
|
||||
* SYSTIMER_UNIT1_LOAD_HI.
|
||||
*/
|
||||
#define SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0x14)
|
||||
/** SYSTIMER_TIMER_UNIT1_LOAD_HI : R/W; bitpos: [19:0]; default: 0;
|
||||
* timer unit1 load high 32 bit
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_HI 0x000FFFFF
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_HI_M (SYSTIMER_TIMER_UNIT1_LOAD_HI_V << SYSTIMER_TIMER_UNIT1_LOAD_HI_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_HI_V 0x000FFFFF
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_HI_S 0
|
||||
|
||||
/** SYSTIMER_UNIT1_LOAD_LO_REG register
|
||||
* SYSTIMER_UNIT1_LOAD_LO.
|
||||
*/
|
||||
#define SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x18)
|
||||
/** SYSTIMER_TIMER_UNIT1_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
|
||||
* timer unit1 load low 32 bit
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_LO 0xFFFFFFFF
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_LO_M (SYSTIMER_TIMER_UNIT1_LOAD_LO_V << SYSTIMER_TIMER_UNIT1_LOAD_LO_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_LO_V 0xFFFFFFFF
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_LO_S 0
|
||||
|
||||
/** SYSTIMER_TARGET0_HI_REG register
|
||||
* SYSTIMER_TARGET0_HI.
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x1c)
|
||||
/** SYSTIMER_TIMER_TARGET0_HI : R/W; bitpos: [19:0]; default: 0;
|
||||
* timer taget0 high 32 bit
|
||||
*/
|
||||
#define SYSTIMER_TIMER_TARGET0_HI 0x000FFFFF
|
||||
#define SYSTIMER_TIMER_TARGET0_HI_M (SYSTIMER_TIMER_TARGET0_HI_V << SYSTIMER_TIMER_TARGET0_HI_S)
|
||||
#define SYSTIMER_TIMER_TARGET0_HI_V 0x000FFFFF
|
||||
#define SYSTIMER_TIMER_TARGET0_HI_S 0
|
||||
|
||||
/** SYSTIMER_TARGET0_LO_REG register
|
||||
* SYSTIMER_TARGET0_LO.
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x20)
|
||||
/** SYSTIMER_TIMER_TARGET0_LO : R/W; bitpos: [31:0]; default: 0;
|
||||
* timer taget0 low 32 bit
|
||||
*/
|
||||
#define SYSTIMER_TIMER_TARGET0_LO 0xFFFFFFFF
|
||||
#define SYSTIMER_TIMER_TARGET0_LO_M (SYSTIMER_TIMER_TARGET0_LO_V << SYSTIMER_TIMER_TARGET0_LO_S)
|
||||
#define SYSTIMER_TIMER_TARGET0_LO_V 0xFFFFFFFF
|
||||
#define SYSTIMER_TIMER_TARGET0_LO_S 0
|
||||
|
||||
/** SYSTIMER_TARGET1_HI_REG register
|
||||
* SYSTIMER_TARGET1_HI.
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x24)
|
||||
/** SYSTIMER_TIMER_TARGET1_HI : R/W; bitpos: [19:0]; default: 0;
|
||||
* timer taget1 high 32 bit
|
||||
*/
|
||||
#define SYSTIMER_TIMER_TARGET1_HI 0x000FFFFF
|
||||
#define SYSTIMER_TIMER_TARGET1_HI_M (SYSTIMER_TIMER_TARGET1_HI_V << SYSTIMER_TIMER_TARGET1_HI_S)
|
||||
#define SYSTIMER_TIMER_TARGET1_HI_V 0x000FFFFF
|
||||
#define SYSTIMER_TIMER_TARGET1_HI_S 0
|
||||
|
||||
/** SYSTIMER_TARGET1_LO_REG register
|
||||
* SYSTIMER_TARGET1_LO.
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x28)
|
||||
/** SYSTIMER_TIMER_TARGET1_LO : R/W; bitpos: [31:0]; default: 0;
|
||||
* timer taget1 low 32 bit
|
||||
*/
|
||||
#define SYSTIMER_TIMER_TARGET1_LO 0xFFFFFFFF
|
||||
#define SYSTIMER_TIMER_TARGET1_LO_M (SYSTIMER_TIMER_TARGET1_LO_V << SYSTIMER_TIMER_TARGET1_LO_S)
|
||||
#define SYSTIMER_TIMER_TARGET1_LO_V 0xFFFFFFFF
|
||||
#define SYSTIMER_TIMER_TARGET1_LO_S 0
|
||||
|
||||
/** SYSTIMER_TARGET2_HI_REG register
|
||||
* SYSTIMER_TARGET2_HI.
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x2c)
|
||||
/** SYSTIMER_TIMER_TARGET2_HI : R/W; bitpos: [19:0]; default: 0;
|
||||
* timer taget2 high 32 bit
|
||||
*/
|
||||
#define SYSTIMER_TIMER_TARGET2_HI 0x000FFFFF
|
||||
#define SYSTIMER_TIMER_TARGET2_HI_M (SYSTIMER_TIMER_TARGET2_HI_V << SYSTIMER_TIMER_TARGET2_HI_S)
|
||||
#define SYSTIMER_TIMER_TARGET2_HI_V 0x000FFFFF
|
||||
#define SYSTIMER_TIMER_TARGET2_HI_S 0
|
||||
|
||||
/** SYSTIMER_TARGET2_LO_REG register
|
||||
* SYSTIMER_TARGET2_LO.
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x30)
|
||||
/** SYSTIMER_TIMER_TARGET2_LO : R/W; bitpos: [31:0]; default: 0;
|
||||
* timer taget2 low 32 bit
|
||||
*/
|
||||
#define SYSTIMER_TIMER_TARGET2_LO 0xFFFFFFFF
|
||||
#define SYSTIMER_TIMER_TARGET2_LO_M (SYSTIMER_TIMER_TARGET2_LO_V << SYSTIMER_TIMER_TARGET2_LO_S)
|
||||
#define SYSTIMER_TIMER_TARGET2_LO_V 0xFFFFFFFF
|
||||
#define SYSTIMER_TIMER_TARGET2_LO_S 0
|
||||
|
||||
/** SYSTIMER_TARGET0_CONF_REG register
|
||||
* SYSTIMER_TARGET0_CONF.
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_CONF_REG (DR_REG_SYSTIMER_BASE + 0x34)
|
||||
/** SYSTIMER_TARGET0_PERIOD : R/W; bitpos: [25:0]; default: 0;
|
||||
* target0 period
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_PERIOD 0x03FFFFFF
|
||||
#define SYSTIMER_TARGET0_PERIOD_M (SYSTIMER_TARGET0_PERIOD_V << SYSTIMER_TARGET0_PERIOD_S)
|
||||
#define SYSTIMER_TARGET0_PERIOD_V 0x03FFFFFF
|
||||
#define SYSTIMER_TARGET0_PERIOD_S 0
|
||||
/** SYSTIMER_TARGET0_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
|
||||
* Set target0 to period mode
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_PERIOD_MODE (BIT(30))
|
||||
#define SYSTIMER_TARGET0_PERIOD_MODE_M (SYSTIMER_TARGET0_PERIOD_MODE_V << SYSTIMER_TARGET0_PERIOD_MODE_S)
|
||||
#define SYSTIMER_TARGET0_PERIOD_MODE_V 0x00000001
|
||||
#define SYSTIMER_TARGET0_PERIOD_MODE_S 30
|
||||
/** SYSTIMER_TARGET0_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
|
||||
* select which unit to compare
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL (BIT(31))
|
||||
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_M (SYSTIMER_TARGET0_TIMER_UNIT_SEL_V << SYSTIMER_TARGET0_TIMER_UNIT_SEL_S)
|
||||
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_V 0x00000001
|
||||
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_S 31
|
||||
|
||||
/** SYSTIMER_TARGET1_CONF_REG register
|
||||
* SYSTIMER_TARGET1_CONF.
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_CONF_REG (DR_REG_SYSTIMER_BASE + 0x38)
|
||||
/** SYSTIMER_TARGET1_PERIOD : R/W; bitpos: [25:0]; default: 0;
|
||||
* target1 period
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_PERIOD 0x03FFFFFF
|
||||
#define SYSTIMER_TARGET1_PERIOD_M (SYSTIMER_TARGET1_PERIOD_V << SYSTIMER_TARGET1_PERIOD_S)
|
||||
#define SYSTIMER_TARGET1_PERIOD_V 0x03FFFFFF
|
||||
#define SYSTIMER_TARGET1_PERIOD_S 0
|
||||
/** SYSTIMER_TARGET1_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
|
||||
* Set target1 to period mode
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_PERIOD_MODE (BIT(30))
|
||||
#define SYSTIMER_TARGET1_PERIOD_MODE_M (SYSTIMER_TARGET1_PERIOD_MODE_V << SYSTIMER_TARGET1_PERIOD_MODE_S)
|
||||
#define SYSTIMER_TARGET1_PERIOD_MODE_V 0x00000001
|
||||
#define SYSTIMER_TARGET1_PERIOD_MODE_S 30
|
||||
/** SYSTIMER_TARGET1_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
|
||||
* select which unit to compare
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL (BIT(31))
|
||||
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_M (SYSTIMER_TARGET1_TIMER_UNIT_SEL_V << SYSTIMER_TARGET1_TIMER_UNIT_SEL_S)
|
||||
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_V 0x00000001
|
||||
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_S 31
|
||||
|
||||
/** SYSTIMER_TARGET2_CONF_REG register
|
||||
* SYSTIMER_TARGET2_CONF.
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_CONF_REG (DR_REG_SYSTIMER_BASE + 0x3c)
|
||||
/** SYSTIMER_TARGET2_PERIOD : R/W; bitpos: [25:0]; default: 0;
|
||||
* target2 period
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_PERIOD 0x03FFFFFF
|
||||
#define SYSTIMER_TARGET2_PERIOD_M (SYSTIMER_TARGET2_PERIOD_V << SYSTIMER_TARGET2_PERIOD_S)
|
||||
#define SYSTIMER_TARGET2_PERIOD_V 0x03FFFFFF
|
||||
#define SYSTIMER_TARGET2_PERIOD_S 0
|
||||
/** SYSTIMER_TARGET2_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
|
||||
* Set target2 to period mode
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_PERIOD_MODE (BIT(30))
|
||||
#define SYSTIMER_TARGET2_PERIOD_MODE_M (SYSTIMER_TARGET2_PERIOD_MODE_V << SYSTIMER_TARGET2_PERIOD_MODE_S)
|
||||
#define SYSTIMER_TARGET2_PERIOD_MODE_V 0x00000001
|
||||
#define SYSTIMER_TARGET2_PERIOD_MODE_S 30
|
||||
/** SYSTIMER_TARGET2_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
|
||||
* select which unit to compare
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL (BIT(31))
|
||||
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_M (SYSTIMER_TARGET2_TIMER_UNIT_SEL_V << SYSTIMER_TARGET2_TIMER_UNIT_SEL_S)
|
||||
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_V 0x00000001
|
||||
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_S 31
|
||||
|
||||
/** SYSTIMER_UNIT0_VALUE_HI_REG register
|
||||
* SYSTIMER_UNIT0_VALUE_HI.
|
||||
*/
|
||||
#define SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x40)
|
||||
/** SYSTIMER_TIMER_UNIT0_VALUE_HI : RO; bitpos: [19:0]; default: 0;
|
||||
* timer read value high 32bit
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_HI 0x000FFFFF
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_HI_M (SYSTIMER_TIMER_UNIT0_VALUE_HI_V << SYSTIMER_TIMER_UNIT0_VALUE_HI_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_HI_V 0x000FFFFF
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_HI_S 0
|
||||
|
||||
/** SYSTIMER_UNIT0_VALUE_LO_REG register
|
||||
* SYSTIMER_UNIT0_VALUE_LO.
|
||||
*/
|
||||
#define SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x44)
|
||||
/** SYSTIMER_TIMER_UNIT0_VALUE_LO : RO; bitpos: [31:0]; default: 0;
|
||||
* timer read value low 32bit
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_LO 0xFFFFFFFF
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_LO_M (SYSTIMER_TIMER_UNIT0_VALUE_LO_V << SYSTIMER_TIMER_UNIT0_VALUE_LO_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_LO_V 0xFFFFFFFF
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_LO_S 0
|
||||
|
||||
/** SYSTIMER_UNIT1_VALUE_HI_REG register
|
||||
* SYSTIMER_UNIT1_VALUE_HI.
|
||||
*/
|
||||
#define SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x48)
|
||||
/** SYSTIMER_TIMER_UNIT1_VALUE_HI : RO; bitpos: [19:0]; default: 0;
|
||||
* timer read value high 32bit
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_HI 0x000FFFFF
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_HI_M (SYSTIMER_TIMER_UNIT1_VALUE_HI_V << SYSTIMER_TIMER_UNIT1_VALUE_HI_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_HI_V 0x000FFFFF
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_HI_S 0
|
||||
|
||||
/** SYSTIMER_UNIT1_VALUE_LO_REG register
|
||||
* SYSTIMER_UNIT1_VALUE_LO.
|
||||
*/
|
||||
#define SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x4c)
|
||||
/** SYSTIMER_TIMER_UNIT1_VALUE_LO : RO; bitpos: [31:0]; default: 0;
|
||||
* timer read value low 32bit
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_LO 0xFFFFFFFF
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_LO_M (SYSTIMER_TIMER_UNIT1_VALUE_LO_V << SYSTIMER_TIMER_UNIT1_VALUE_LO_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_LO_V 0xFFFFFFFF
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_LO_S 0
|
||||
|
||||
/** SYSTIMER_COMP0_LOAD_REG register
|
||||
* SYSTIMER_COMP0_LOAD.
|
||||
*/
|
||||
#define SYSTIMER_COMP0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x50)
|
||||
/** SYSTIMER_TIMER_COMP0_LOAD : WT; bitpos: [0]; default: 0;
|
||||
* timer comp0 load value
|
||||
*/
|
||||
#define SYSTIMER_TIMER_COMP0_LOAD (BIT(0))
|
||||
#define SYSTIMER_TIMER_COMP0_LOAD_M (SYSTIMER_TIMER_COMP0_LOAD_V << SYSTIMER_TIMER_COMP0_LOAD_S)
|
||||
#define SYSTIMER_TIMER_COMP0_LOAD_V 0x00000001
|
||||
#define SYSTIMER_TIMER_COMP0_LOAD_S 0
|
||||
|
||||
/** SYSTIMER_COMP1_LOAD_REG register
|
||||
* SYSTIMER_COMP1_LOAD.
|
||||
*/
|
||||
#define SYSTIMER_COMP1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x54)
|
||||
/** SYSTIMER_TIMER_COMP1_LOAD : WT; bitpos: [0]; default: 0;
|
||||
* timer comp1 load value
|
||||
*/
|
||||
#define SYSTIMER_TIMER_COMP1_LOAD (BIT(0))
|
||||
#define SYSTIMER_TIMER_COMP1_LOAD_M (SYSTIMER_TIMER_COMP1_LOAD_V << SYSTIMER_TIMER_COMP1_LOAD_S)
|
||||
#define SYSTIMER_TIMER_COMP1_LOAD_V 0x00000001
|
||||
#define SYSTIMER_TIMER_COMP1_LOAD_S 0
|
||||
|
||||
/** SYSTIMER_COMP2_LOAD_REG register
|
||||
* SYSTIMER_COMP2_LOAD.
|
||||
*/
|
||||
#define SYSTIMER_COMP2_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x58)
|
||||
/** SYSTIMER_TIMER_COMP2_LOAD : WT; bitpos: [0]; default: 0;
|
||||
* timer comp2 load value
|
||||
*/
|
||||
#define SYSTIMER_TIMER_COMP2_LOAD (BIT(0))
|
||||
#define SYSTIMER_TIMER_COMP2_LOAD_M (SYSTIMER_TIMER_COMP2_LOAD_V << SYSTIMER_TIMER_COMP2_LOAD_S)
|
||||
#define SYSTIMER_TIMER_COMP2_LOAD_V 0x00000001
|
||||
#define SYSTIMER_TIMER_COMP2_LOAD_S 0
|
||||
|
||||
/** SYSTIMER_UNIT0_LOAD_REG register
|
||||
* SYSTIMER_UNIT0_LOAD.
|
||||
*/
|
||||
#define SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x5c)
|
||||
/** SYSTIMER_TIMER_UNIT0_LOAD : WT; bitpos: [0]; default: 0;
|
||||
* timer unit0 load value
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD (BIT(0))
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_M (SYSTIMER_TIMER_UNIT0_LOAD_V << SYSTIMER_TIMER_UNIT0_LOAD_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_V 0x00000001
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_S 0
|
||||
|
||||
/** SYSTIMER_UNIT1_LOAD_REG register
|
||||
* SYSTIMER_UNIT1_LOAD.
|
||||
*/
|
||||
#define SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x60)
|
||||
/** SYSTIMER_TIMER_UNIT1_LOAD : WT; bitpos: [0]; default: 0;
|
||||
* timer unit1 load value
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD (BIT(0))
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_M (SYSTIMER_TIMER_UNIT1_LOAD_V << SYSTIMER_TIMER_UNIT1_LOAD_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_V 0x00000001
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_S 0
|
||||
|
||||
/** SYSTIMER_INT_ENA_REG register
|
||||
* SYSTIMER_INT_ENA.
|
||||
*/
|
||||
#define SYSTIMER_INT_ENA_REG (DR_REG_SYSTIMER_BASE + 0x64)
|
||||
/** SYSTIMER_TARGET0_INT_ENA : R/W; bitpos: [0]; default: 0;
|
||||
* interupt0 enable
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_INT_ENA (BIT(0))
|
||||
#define SYSTIMER_TARGET0_INT_ENA_M (SYSTIMER_TARGET0_INT_ENA_V << SYSTIMER_TARGET0_INT_ENA_S)
|
||||
#define SYSTIMER_TARGET0_INT_ENA_V 0x00000001
|
||||
#define SYSTIMER_TARGET0_INT_ENA_S 0
|
||||
/** SYSTIMER_TARGET1_INT_ENA : R/W; bitpos: [1]; default: 0;
|
||||
* interupt1 enable
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_INT_ENA (BIT(1))
|
||||
#define SYSTIMER_TARGET1_INT_ENA_M (SYSTIMER_TARGET1_INT_ENA_V << SYSTIMER_TARGET1_INT_ENA_S)
|
||||
#define SYSTIMER_TARGET1_INT_ENA_V 0x00000001
|
||||
#define SYSTIMER_TARGET1_INT_ENA_S 1
|
||||
/** SYSTIMER_TARGET2_INT_ENA : R/W; bitpos: [2]; default: 0;
|
||||
* interupt2 enable
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_INT_ENA (BIT(2))
|
||||
#define SYSTIMER_TARGET2_INT_ENA_M (SYSTIMER_TARGET2_INT_ENA_V << SYSTIMER_TARGET2_INT_ENA_S)
|
||||
#define SYSTIMER_TARGET2_INT_ENA_V 0x00000001
|
||||
#define SYSTIMER_TARGET2_INT_ENA_S 2
|
||||
|
||||
/** SYSTIMER_INT_RAW_REG register
|
||||
* SYSTIMER_INT_RAW.
|
||||
*/
|
||||
#define SYSTIMER_INT_RAW_REG (DR_REG_SYSTIMER_BASE + 0x68)
|
||||
/** SYSTIMER_TARGET0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
|
||||
* interupt0 raw
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_INT_RAW (BIT(0))
|
||||
#define SYSTIMER_TARGET0_INT_RAW_M (SYSTIMER_TARGET0_INT_RAW_V << SYSTIMER_TARGET0_INT_RAW_S)
|
||||
#define SYSTIMER_TARGET0_INT_RAW_V 0x00000001
|
||||
#define SYSTIMER_TARGET0_INT_RAW_S 0
|
||||
/** SYSTIMER_TARGET1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
|
||||
* interupt1 raw
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_INT_RAW (BIT(1))
|
||||
#define SYSTIMER_TARGET1_INT_RAW_M (SYSTIMER_TARGET1_INT_RAW_V << SYSTIMER_TARGET1_INT_RAW_S)
|
||||
#define SYSTIMER_TARGET1_INT_RAW_V 0x00000001
|
||||
#define SYSTIMER_TARGET1_INT_RAW_S 1
|
||||
/** SYSTIMER_TARGET2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
|
||||
* interupt2 raw
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_INT_RAW (BIT(2))
|
||||
#define SYSTIMER_TARGET2_INT_RAW_M (SYSTIMER_TARGET2_INT_RAW_V << SYSTIMER_TARGET2_INT_RAW_S)
|
||||
#define SYSTIMER_TARGET2_INT_RAW_V 0x00000001
|
||||
#define SYSTIMER_TARGET2_INT_RAW_S 2
|
||||
|
||||
/** SYSTIMER_INT_CLR_REG register
|
||||
* SYSTIMER_INT_CLR.
|
||||
*/
|
||||
#define SYSTIMER_INT_CLR_REG (DR_REG_SYSTIMER_BASE + 0x6c)
|
||||
/** SYSTIMER_TARGET0_INT_CLR : WT; bitpos: [0]; default: 0;
|
||||
* interupt0 clear
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_INT_CLR (BIT(0))
|
||||
#define SYSTIMER_TARGET0_INT_CLR_M (SYSTIMER_TARGET0_INT_CLR_V << SYSTIMER_TARGET0_INT_CLR_S)
|
||||
#define SYSTIMER_TARGET0_INT_CLR_V 0x00000001
|
||||
#define SYSTIMER_TARGET0_INT_CLR_S 0
|
||||
/** SYSTIMER_TARGET1_INT_CLR : WT; bitpos: [1]; default: 0;
|
||||
* interupt1 clear
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_INT_CLR (BIT(1))
|
||||
#define SYSTIMER_TARGET1_INT_CLR_M (SYSTIMER_TARGET1_INT_CLR_V << SYSTIMER_TARGET1_INT_CLR_S)
|
||||
#define SYSTIMER_TARGET1_INT_CLR_V 0x00000001
|
||||
#define SYSTIMER_TARGET1_INT_CLR_S 1
|
||||
/** SYSTIMER_TARGET2_INT_CLR : WT; bitpos: [2]; default: 0;
|
||||
* interupt2 clear
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_INT_CLR (BIT(2))
|
||||
#define SYSTIMER_TARGET2_INT_CLR_M (SYSTIMER_TARGET2_INT_CLR_V << SYSTIMER_TARGET2_INT_CLR_S)
|
||||
#define SYSTIMER_TARGET2_INT_CLR_V 0x00000001
|
||||
#define SYSTIMER_TARGET2_INT_CLR_S 2
|
||||
|
||||
/** SYSTIMER_INT_ST_REG register
|
||||
* SYSTIMER_INT_ST.
|
||||
*/
|
||||
#define SYSTIMER_INT_ST_REG (DR_REG_SYSTIMER_BASE + 0x70)
|
||||
/** SYSTIMER_TARGET0_INT_ST : RO; bitpos: [0]; default: 0;
|
||||
* reg_target0_int_st
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_INT_ST (BIT(0))
|
||||
#define SYSTIMER_TARGET0_INT_ST_M (SYSTIMER_TARGET0_INT_ST_V << SYSTIMER_TARGET0_INT_ST_S)
|
||||
#define SYSTIMER_TARGET0_INT_ST_V 0x00000001
|
||||
#define SYSTIMER_TARGET0_INT_ST_S 0
|
||||
/** SYSTIMER_TARGET1_INT_ST : RO; bitpos: [1]; default: 0;
|
||||
* reg_target1_int_st
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_INT_ST (BIT(1))
|
||||
#define SYSTIMER_TARGET1_INT_ST_M (SYSTIMER_TARGET1_INT_ST_V << SYSTIMER_TARGET1_INT_ST_S)
|
||||
#define SYSTIMER_TARGET1_INT_ST_V 0x00000001
|
||||
#define SYSTIMER_TARGET1_INT_ST_S 1
|
||||
/** SYSTIMER_TARGET2_INT_ST : RO; bitpos: [2]; default: 0;
|
||||
* reg_target2_int_st
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_INT_ST (BIT(2))
|
||||
#define SYSTIMER_TARGET2_INT_ST_M (SYSTIMER_TARGET2_INT_ST_V << SYSTIMER_TARGET2_INT_ST_S)
|
||||
#define SYSTIMER_TARGET2_INT_ST_V 0x00000001
|
||||
#define SYSTIMER_TARGET2_INT_ST_S 2
|
||||
|
||||
/** SYSTIMER_DATE_REG register
|
||||
* SYSTIMER_DATE.
|
||||
*/
|
||||
#define SYSTIMER_DATE_REG (DR_REG_SYSTIMER_BASE + 0xfc)
|
||||
/** SYSTIMER_DATE : R/W; bitpos: [31:0]; default: 33579377;
|
||||
* reg_date
|
||||
*/
|
||||
#define SYSTIMER_DATE 0xFFFFFFFF
|
||||
#define SYSTIMER_DATE_M (SYSTIMER_DATE_V << SYSTIMER_DATE_S)
|
||||
#define SYSTIMER_DATE_V 0xFFFFFFFF
|
||||
#define SYSTIMER_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,380 +0,0 @@
|
||||
/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Configuration Register */
|
||||
/** Type of conf register
|
||||
* SYSTIMER_CONF.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** systimer_clk_fo : R/W; bitpos: [0]; default: 0;
|
||||
* systimer clock force on
|
||||
*/
|
||||
uint32_t systimer_clk_fo: 1;
|
||||
uint32_t reserved_1: 21;
|
||||
/** target2_work_en : R/W; bitpos: [22]; default: 0;
|
||||
* target2 work enable
|
||||
*/
|
||||
uint32_t target2_work_en: 1;
|
||||
/** target1_work_en : R/W; bitpos: [23]; default: 0;
|
||||
* target1 work enable
|
||||
*/
|
||||
uint32_t target1_work_en: 1;
|
||||
/** target0_work_en : R/W; bitpos: [24]; default: 0;
|
||||
* target0 work enable
|
||||
*/
|
||||
uint32_t target0_work_en: 1;
|
||||
/** timer_unit1_core1_stall_en : R/W; bitpos: [25]; default: 1;
|
||||
* If timer unit1 is stalled when core1 stalled
|
||||
*/
|
||||
uint32_t timer_unit1_core1_stall_en: 1;
|
||||
/** timer_unit1_core0_stall_en : R/W; bitpos: [26]; default: 1;
|
||||
* If timer unit1 is stalled when core0 stalled
|
||||
*/
|
||||
uint32_t timer_unit1_core0_stall_en: 1;
|
||||
/** timer_unit0_core1_stall_en : R/W; bitpos: [27]; default: 0;
|
||||
* If timer unit0 is stalled when core1 stalled
|
||||
*/
|
||||
uint32_t timer_unit0_core1_stall_en: 1;
|
||||
/** timer_unit0_core0_stall_en : R/W; bitpos: [28]; default: 0;
|
||||
* If timer unit0 is stalled when core0 stalled
|
||||
*/
|
||||
uint32_t timer_unit0_core0_stall_en: 1;
|
||||
/** timer_unit1_work_en : R/W; bitpos: [29]; default: 0;
|
||||
* timer unit1 work enable
|
||||
*/
|
||||
uint32_t timer_unit1_work_en: 1;
|
||||
/** timer_unit0_work_en : R/W; bitpos: [30]; default: 1;
|
||||
* timer unit0 work enable
|
||||
*/
|
||||
uint32_t timer_unit0_work_en: 1;
|
||||
/** clk_en : R/W; bitpos: [31]; default: 0;
|
||||
* register file clk gating
|
||||
*/
|
||||
uint32_t clk_en: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_conf_reg_t;
|
||||
|
||||
/** Type of unit_op register
|
||||
* SYSTIMER_UNIT_OP.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0: 29;
|
||||
/** timer_unit_value_valid : R/SS/WTC; bitpos: [29]; default: 0;
|
||||
* reg_timer_unit0_value_valid
|
||||
*/
|
||||
uint32_t timer_unit_value_valid: 1;
|
||||
/** timer_unit_update : WT; bitpos: [30]; default: 0;
|
||||
* update timer_unit0
|
||||
*/
|
||||
uint32_t timer_unit_update: 1;
|
||||
uint32_t reserved31: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_unit_op_reg_t;
|
||||
|
||||
/** Type of unit_load register
|
||||
* SYSTIMER_UNIT_LOAD
|
||||
*/
|
||||
typedef struct {
|
||||
union {
|
||||
struct {
|
||||
/** timer_unit_load_hi : R/W; bitpos: [19:0]; default: 0;
|
||||
* timer unit load high 32 bit
|
||||
*/
|
||||
uint32_t timer_unit_load_hi: 20;
|
||||
uint32_t reserved20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} hi;
|
||||
union {
|
||||
struct {
|
||||
/** timer_unit_load_lo : R/W; bitpos: [31:0]; default: 0;
|
||||
* timer unit load low 32 bit
|
||||
*/
|
||||
uint32_t timer_unit_load_lo: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} lo;
|
||||
} systimer_unit_load_val_reg_t;
|
||||
|
||||
/** Type of target register
|
||||
* SYSTIMER_TARGET.
|
||||
*/
|
||||
typedef struct {
|
||||
union {
|
||||
struct {
|
||||
/** timer_target_hi : R/W; bitpos: [19:0]; default: 0;
|
||||
* timer target high 32 bit
|
||||
*/
|
||||
uint32_t timer_target_hi: 20;
|
||||
uint32_t reserved20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} hi;
|
||||
union {
|
||||
struct {
|
||||
/** timer_target_lo : R/W; bitpos: [31:0]; default: 0;
|
||||
* timer target low 32 bit
|
||||
*/
|
||||
uint32_t timer_target_lo: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} lo;
|
||||
} systimer_target_val_reg_t;
|
||||
|
||||
/** Type of target_conf register
|
||||
* SYSTIMER_TARGET_CONF.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** target_period : R/W; bitpos: [25:0]; default: 0;
|
||||
* target period
|
||||
*/
|
||||
uint32_t target_period: 26;
|
||||
uint32_t reserved_26: 4;
|
||||
/** target_period_mode : R/W; bitpos: [30]; default: 0;
|
||||
* Set target to period mode
|
||||
*/
|
||||
uint32_t target_period_mode: 1;
|
||||
/** target_timer_unit_sel : R/W; bitpos: [31]; default: 0;
|
||||
* select which unit to compare
|
||||
*/
|
||||
uint32_t target_timer_unit_sel: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_target_conf_reg_t;
|
||||
|
||||
/** Type of unit_value_hi register
|
||||
* SYSTIMER_UNIT_VALUE_HI.
|
||||
*/
|
||||
typedef struct {
|
||||
union {
|
||||
struct {
|
||||
/** timer_unit_value_hi : RO; bitpos: [19:0]; default: 0;
|
||||
* timer read value high 20bit
|
||||
*/
|
||||
uint32_t timer_unit_value_hi: 20;
|
||||
uint32_t reserved20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} hi;
|
||||
union {
|
||||
struct {
|
||||
/** timer_unit_value_lo : RO; bitpos: [31:0]; default: 0;
|
||||
* timer read value low 32bit
|
||||
*/
|
||||
uint32_t timer_unit_value_lo: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} lo;
|
||||
} systimer_unit_value_reg_t;
|
||||
|
||||
/** Type of comp_load register
|
||||
* SYSTIMER_COMP_LOAD.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_comp_load : WT; bitpos: [0]; default: 0;
|
||||
* timer comp load value
|
||||
*/
|
||||
uint32_t timer_comp_load: 1;
|
||||
uint32_t reserved1: 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_comp_load_reg_t;
|
||||
|
||||
/** Type of unit_load register
|
||||
* SYSTIMER_UNIT_LOAD.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_unit_load : WT; bitpos: [0]; default: 0;
|
||||
* timer unit load value
|
||||
*/
|
||||
uint32_t timer_unit_load: 1;
|
||||
uint32_t reserved1: 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_unit_load_reg_t;
|
||||
|
||||
/** Interrupt Register */
|
||||
/** Type of int_ena register
|
||||
* SYSTIMER_INT_ENA.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** target0_int_ena : R/W; bitpos: [0]; default: 0;
|
||||
* interupt0 enable
|
||||
*/
|
||||
uint32_t target0_int_ena: 1;
|
||||
/** target1_int_ena : R/W; bitpos: [1]; default: 0;
|
||||
* interupt1 enable
|
||||
*/
|
||||
uint32_t target1_int_ena: 1;
|
||||
/** target2_int_ena : R/W; bitpos: [2]; default: 0;
|
||||
* interupt2 enable
|
||||
*/
|
||||
uint32_t target2_int_ena: 1;
|
||||
uint32_t reserved3: 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_int_ena_reg_t;
|
||||
|
||||
/** Type of int_raw register
|
||||
* SYSTIMER_INT_RAW.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** target0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
|
||||
* interupt0 raw
|
||||
*/
|
||||
uint32_t target0_int_raw: 1;
|
||||
/** target1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
|
||||
* interupt1 raw
|
||||
*/
|
||||
uint32_t target1_int_raw: 1;
|
||||
/** target2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
|
||||
* interupt2 raw
|
||||
*/
|
||||
uint32_t target2_int_raw: 1;
|
||||
uint32_t reserved3: 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_int_raw_reg_t;
|
||||
|
||||
/** Type of int_clr register
|
||||
* SYSTIMER_INT_CLR.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** target0_int_clr : WT; bitpos: [0]; default: 0;
|
||||
* interupt0 clear
|
||||
*/
|
||||
uint32_t target0_int_clr: 1;
|
||||
/** target1_int_clr : WT; bitpos: [1]; default: 0;
|
||||
* interupt1 clear
|
||||
*/
|
||||
uint32_t target1_int_clr: 1;
|
||||
/** target2_int_clr : WT; bitpos: [2]; default: 0;
|
||||
* interupt2 clear
|
||||
*/
|
||||
uint32_t target2_int_clr: 1;
|
||||
uint32_t reserved3: 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_int_clr_reg_t;
|
||||
|
||||
/** Type of int_st register
|
||||
* SYSTIMER_INT_ST.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** target0_int_st : RO; bitpos: [0]; default: 0;
|
||||
* reg_target0_int_st
|
||||
*/
|
||||
uint32_t target0_int_st: 1;
|
||||
/** target1_int_st : RO; bitpos: [1]; default: 0;
|
||||
* reg_target1_int_st
|
||||
*/
|
||||
uint32_t target1_int_st: 1;
|
||||
/** target2_int_st : RO; bitpos: [2]; default: 0;
|
||||
* reg_target2_int_st
|
||||
*/
|
||||
uint32_t target2_int_st: 1;
|
||||
uint32_t reserved3: 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_int_st_reg_t;
|
||||
|
||||
|
||||
/** Version Register */
|
||||
/** Type of date register
|
||||
* SYSTIMER_DATE.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** date : R/W; bitpos: [31:0]; default: 33579377;
|
||||
* reg_date
|
||||
*/
|
||||
uint32_t date: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_date_reg_t;
|
||||
|
||||
|
||||
typedef struct systimer_dev_t {
|
||||
volatile systimer_conf_reg_t conf;
|
||||
volatile systimer_unit_op_reg_t unit_op[2];
|
||||
volatile systimer_unit_load_val_reg_t unit_load_val[2];
|
||||
volatile systimer_target_val_reg_t target_val[3];
|
||||
volatile systimer_target_conf_reg_t target_conf[3];
|
||||
volatile systimer_unit_value_reg_t unit_val[2];
|
||||
volatile systimer_comp_load_reg_t comp_load[3];
|
||||
volatile systimer_unit_load_reg_t unit_load[2];
|
||||
volatile systimer_int_ena_reg_t int_ena;
|
||||
volatile systimer_int_raw_reg_t int_raw;
|
||||
volatile systimer_int_clr_reg_t int_clr;
|
||||
volatile systimer_int_st_reg_t int_st;
|
||||
uint32_t reserved_074;
|
||||
uint32_t reserved_078;
|
||||
uint32_t reserved_07c;
|
||||
uint32_t reserved_080;
|
||||
uint32_t reserved_084;
|
||||
uint32_t reserved_088;
|
||||
uint32_t reserved_08c;
|
||||
uint32_t reserved_090;
|
||||
uint32_t reserved_094;
|
||||
uint32_t reserved_098;
|
||||
uint32_t reserved_09c;
|
||||
uint32_t reserved_0a0;
|
||||
uint32_t reserved_0a4;
|
||||
uint32_t reserved_0a8;
|
||||
uint32_t reserved_0ac;
|
||||
uint32_t reserved_0b0;
|
||||
uint32_t reserved_0b4;
|
||||
uint32_t reserved_0b8;
|
||||
uint32_t reserved_0bc;
|
||||
uint32_t reserved_0c0;
|
||||
uint32_t reserved_0c4;
|
||||
uint32_t reserved_0c8;
|
||||
uint32_t reserved_0cc;
|
||||
uint32_t reserved_0d0;
|
||||
uint32_t reserved_0d4;
|
||||
uint32_t reserved_0d8;
|
||||
uint32_t reserved_0dc;
|
||||
uint32_t reserved_0e0;
|
||||
uint32_t reserved_0e4;
|
||||
uint32_t reserved_0e8;
|
||||
uint32_t reserved_0ec;
|
||||
uint32_t reserved_0f0;
|
||||
uint32_t reserved_0f4;
|
||||
uint32_t reserved_0f8;
|
||||
volatile systimer_date_reg_t date;
|
||||
} systimer_dev_t;
|
||||
|
||||
extern systimer_dev_t SYSTIMER;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,561 +0,0 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define DR_REG_TIMG_BASE(i) REG_TIMG_BASE(i)
|
||||
|
||||
/** TIMG_T0CONFIG_REG register
|
||||
* Timer 0 configuration register
|
||||
*/
|
||||
#define TIMG_T0CONFIG_REG(i) (DR_REG_TIMG_BASE(i) + 0x0)
|
||||
/** TIMG_T0_USE_XTAL : R/W; bitpos: [9]; default: 0;
|
||||
* 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source
|
||||
* clock of timer group.
|
||||
*/
|
||||
#define TIMG_T0_USE_XTAL (BIT(9))
|
||||
#define TIMG_T0_USE_XTAL_M (TIMG_T0_USE_XTAL_V << TIMG_T0_USE_XTAL_S)
|
||||
#define TIMG_T0_USE_XTAL_V 0x00000001U
|
||||
#define TIMG_T0_USE_XTAL_S 9
|
||||
/** TIMG_T0_ALARM_EN : R/W/SC; bitpos: [10]; default: 0;
|
||||
* When set, the alarm is enabled. This bit is automatically cleared once an
|
||||
* alarm occurs.
|
||||
*/
|
||||
#define TIMG_T0_ALARM_EN (BIT(10))
|
||||
#define TIMG_T0_ALARM_EN_M (TIMG_T0_ALARM_EN_V << TIMG_T0_ALARM_EN_S)
|
||||
#define TIMG_T0_ALARM_EN_V 0x00000001U
|
||||
#define TIMG_T0_ALARM_EN_S 10
|
||||
/** TIMG_T0_DIVCNT_RST : WT; bitpos: [12]; default: 0;
|
||||
* When set, Timer 0 's clock divider counter will be reset.
|
||||
*/
|
||||
#define TIMG_T0_DIVCNT_RST (BIT(12))
|
||||
#define TIMG_T0_DIVCNT_RST_M (TIMG_T0_DIVCNT_RST_V << TIMG_T0_DIVCNT_RST_S)
|
||||
#define TIMG_T0_DIVCNT_RST_V 0x00000001U
|
||||
#define TIMG_T0_DIVCNT_RST_S 12
|
||||
/** TIMG_T0_DIVIDER : R/W; bitpos: [28:13]; default: 1;
|
||||
* Timer 0 clock (T0_clk) prescaler value.
|
||||
*/
|
||||
#define TIMG_T0_DIVIDER 0x0000FFFFU
|
||||
#define TIMG_T0_DIVIDER_M (TIMG_T0_DIVIDER_V << TIMG_T0_DIVIDER_S)
|
||||
#define TIMG_T0_DIVIDER_V 0x0000FFFFU
|
||||
#define TIMG_T0_DIVIDER_S 13
|
||||
/** TIMG_T0_AUTORELOAD : R/W; bitpos: [29]; default: 1;
|
||||
* When set, timer 0 auto-reload at alarm is enabled.
|
||||
*/
|
||||
#define TIMG_T0_AUTORELOAD (BIT(29))
|
||||
#define TIMG_T0_AUTORELOAD_M (TIMG_T0_AUTORELOAD_V << TIMG_T0_AUTORELOAD_S)
|
||||
#define TIMG_T0_AUTORELOAD_V 0x00000001U
|
||||
#define TIMG_T0_AUTORELOAD_S 29
|
||||
/** TIMG_T0_INCREASE : R/W; bitpos: [30]; default: 1;
|
||||
* When set, the timer 0 time-base counter will increment every clock tick. When
|
||||
* cleared, the timer 0 time-base counter will decrement.
|
||||
*/
|
||||
#define TIMG_T0_INCREASE (BIT(30))
|
||||
#define TIMG_T0_INCREASE_M (TIMG_T0_INCREASE_V << TIMG_T0_INCREASE_S)
|
||||
#define TIMG_T0_INCREASE_V 0x00000001U
|
||||
#define TIMG_T0_INCREASE_S 30
|
||||
/** TIMG_T0_EN : R/W; bitpos: [31]; default: 0;
|
||||
* When set, the timer 0 time-base counter is enabled.
|
||||
*/
|
||||
#define TIMG_T0_EN (BIT(31))
|
||||
#define TIMG_T0_EN_M (TIMG_T0_EN_V << TIMG_T0_EN_S)
|
||||
#define TIMG_T0_EN_V 0x00000001U
|
||||
#define TIMG_T0_EN_S 31
|
||||
|
||||
/** TIMG_T0LO_REG register
|
||||
* Timer 0 current value, low 32 bits
|
||||
*/
|
||||
#define TIMG_T0LO_REG(i) (DR_REG_TIMG_BASE(i) + 0x4)
|
||||
/** TIMG_T0_LO : RO; bitpos: [31:0]; default: 0;
|
||||
* After writing to TIMG_T0UPDATE_REG, the low 32 bits of the time-base counter
|
||||
* of timer 0 can be read here.
|
||||
*/
|
||||
#define TIMG_T0_LO 0xFFFFFFFFU
|
||||
#define TIMG_T0_LO_M (TIMG_T0_LO_V << TIMG_T0_LO_S)
|
||||
#define TIMG_T0_LO_V 0xFFFFFFFFU
|
||||
#define TIMG_T0_LO_S 0
|
||||
|
||||
/** TIMG_T0HI_REG register
|
||||
* Timer $x current value, high 22 bits
|
||||
*/
|
||||
#define TIMG_T0HI_REG(i) (DR_REG_TIMG_BASE(i) + 0x8)
|
||||
/** TIMG_T0_HI : RO; bitpos: [21:0]; default: 0;
|
||||
* After writing to TIMG_T$xUPDATE_REG, the high 22 bits of the time-base counter
|
||||
* of timer $x can be read here.
|
||||
*/
|
||||
#define TIMG_T0_HI 0x003FFFFFU
|
||||
#define TIMG_T0_HI_M (TIMG_T0_HI_V << TIMG_T0_HI_S)
|
||||
#define TIMG_T0_HI_V 0x003FFFFFU
|
||||
#define TIMG_T0_HI_S 0
|
||||
|
||||
/** TIMG_T0UPDATE_REG register
|
||||
* Write to copy current timer value to TIMGn_T$x_(LO/HI)_REG
|
||||
*/
|
||||
#define TIMG_T0UPDATE_REG(i) (DR_REG_TIMG_BASE(i) + 0xc)
|
||||
/** TIMG_T0_UPDATE : R/W/SC; bitpos: [31]; default: 0;
|
||||
* After writing 0 or 1 to TIMG_T$xUPDATE_REG, the counter value is latched.
|
||||
*/
|
||||
#define TIMG_T0_UPDATE (BIT(31))
|
||||
#define TIMG_T0_UPDATE_M (TIMG_T0_UPDATE_V << TIMG_T0_UPDATE_S)
|
||||
#define TIMG_T0_UPDATE_V 0x00000001U
|
||||
#define TIMG_T0_UPDATE_S 31
|
||||
|
||||
/** TIMG_T0ALARMLO_REG register
|
||||
* Timer $x alarm value, low 32 bits
|
||||
*/
|
||||
#define TIMG_T0ALARMLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x10)
|
||||
/** TIMG_T0_ALARM_LO : R/W; bitpos: [31:0]; default: 0;
|
||||
* Timer $x alarm trigger time-base counter value, low 32 bits.
|
||||
*/
|
||||
#define TIMG_T0_ALARM_LO 0xFFFFFFFFU
|
||||
#define TIMG_T0_ALARM_LO_M (TIMG_T0_ALARM_LO_V << TIMG_T0_ALARM_LO_S)
|
||||
#define TIMG_T0_ALARM_LO_V 0xFFFFFFFFU
|
||||
#define TIMG_T0_ALARM_LO_S 0
|
||||
|
||||
/** TIMG_T0ALARMHI_REG register
|
||||
* Timer $x alarm value, high bits
|
||||
*/
|
||||
#define TIMG_T0ALARMHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x14)
|
||||
/** TIMG_T0_ALARM_HI : R/W; bitpos: [21:0]; default: 0;
|
||||
* Timer $x alarm trigger time-base counter value, high 22 bits.
|
||||
*/
|
||||
#define TIMG_T0_ALARM_HI 0x003FFFFFU
|
||||
#define TIMG_T0_ALARM_HI_M (TIMG_T0_ALARM_HI_V << TIMG_T0_ALARM_HI_S)
|
||||
#define TIMG_T0_ALARM_HI_V 0x003FFFFFU
|
||||
#define TIMG_T0_ALARM_HI_S 0
|
||||
|
||||
/** TIMG_T0LOADLO_REG register
|
||||
* Timer $x reload value, low 32 bits
|
||||
*/
|
||||
#define TIMG_T0LOADLO_REG(i) (DR_REG_TIMG_BASE(i) + 0x18)
|
||||
/** TIMG_T0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
|
||||
* Low 32 bits of the value that a reload will load onto timer $x time-base
|
||||
* Counter.
|
||||
*/
|
||||
#define TIMG_T0_LOAD_LO 0xFFFFFFFFU
|
||||
#define TIMG_T0_LOAD_LO_M (TIMG_T0_LOAD_LO_V << TIMG_T0_LOAD_LO_S)
|
||||
#define TIMG_T0_LOAD_LO_V 0xFFFFFFFFU
|
||||
#define TIMG_T0_LOAD_LO_S 0
|
||||
|
||||
/** TIMG_T0LOADHI_REG register
|
||||
* Timer $x reload value, high 22 bits
|
||||
*/
|
||||
#define TIMG_T0LOADHI_REG(i) (DR_REG_TIMG_BASE(i) + 0x1c)
|
||||
/** TIMG_T0_LOAD_HI : R/W; bitpos: [21:0]; default: 0;
|
||||
* High 22 bits of the value that a reload will load onto timer $x time-base
|
||||
* counter.
|
||||
*/
|
||||
#define TIMG_T0_LOAD_HI 0x003FFFFFU
|
||||
#define TIMG_T0_LOAD_HI_M (TIMG_T0_LOAD_HI_V << TIMG_T0_LOAD_HI_S)
|
||||
#define TIMG_T0_LOAD_HI_V 0x003FFFFFU
|
||||
#define TIMG_T0_LOAD_HI_S 0
|
||||
|
||||
/** TIMG_T0LOAD_REG register
|
||||
* Write to reload timer from TIMG_T$x_(LOADLOLOADHI)_REG
|
||||
*/
|
||||
#define TIMG_T0LOAD_REG(i) (DR_REG_TIMG_BASE(i) + 0x20)
|
||||
/** TIMG_T0_LOAD : WT; bitpos: [31:0]; default: 0;
|
||||
*
|
||||
* Write any value to trigger a timer $x time-base counter reload.
|
||||
*/
|
||||
#define TIMG_T0_LOAD 0xFFFFFFFFU
|
||||
#define TIMG_T0_LOAD_M (TIMG_T0_LOAD_V << TIMG_T0_LOAD_S)
|
||||
#define TIMG_T0_LOAD_V 0xFFFFFFFFU
|
||||
#define TIMG_T0_LOAD_S 0
|
||||
|
||||
/** TIMG_WDTCONFIG0_REG register
|
||||
* Watchdog timer configuration register
|
||||
*/
|
||||
#define TIMG_WDTCONFIG0_REG(i) (DR_REG_TIMG_BASE(i) + 0x48)
|
||||
/** TIMG_WDT_APPCPU_RESET_EN : R/W; bitpos: [12]; default: 0;
|
||||
* WDT reset CPU enable.
|
||||
*/
|
||||
#define TIMG_WDT_APPCPU_RESET_EN (BIT(12))
|
||||
#define TIMG_WDT_APPCPU_RESET_EN_M (TIMG_WDT_APPCPU_RESET_EN_V << TIMG_WDT_APPCPU_RESET_EN_S)
|
||||
#define TIMG_WDT_APPCPU_RESET_EN_V 0x00000001U
|
||||
#define TIMG_WDT_APPCPU_RESET_EN_S 12
|
||||
/** TIMG_WDT_PROCPU_RESET_EN : R/W; bitpos: [13]; default: 0;
|
||||
* WDT reset CPU enable.
|
||||
*/
|
||||
#define TIMG_WDT_PROCPU_RESET_EN (BIT(13))
|
||||
#define TIMG_WDT_PROCPU_RESET_EN_M (TIMG_WDT_PROCPU_RESET_EN_V << TIMG_WDT_PROCPU_RESET_EN_S)
|
||||
#define TIMG_WDT_PROCPU_RESET_EN_V 0x00000001U
|
||||
#define TIMG_WDT_PROCPU_RESET_EN_S 13
|
||||
/** TIMG_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [14]; default: 1;
|
||||
* When set, Flash boot protection is enabled.
|
||||
*/
|
||||
#define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14))
|
||||
#define TIMG_WDT_FLASHBOOT_MOD_EN_M (TIMG_WDT_FLASHBOOT_MOD_EN_V << TIMG_WDT_FLASHBOOT_MOD_EN_S)
|
||||
#define TIMG_WDT_FLASHBOOT_MOD_EN_V 0x00000001U
|
||||
#define TIMG_WDT_FLASHBOOT_MOD_EN_S 14
|
||||
/** TIMG_WDT_SYS_RESET_LENGTH : R/W; bitpos: [17:15]; default: 1;
|
||||
* System reset signal length selection. 0: 100 ns, 1: 200 ns,
|
||||
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
|
||||
*/
|
||||
#define TIMG_WDT_SYS_RESET_LENGTH 0x00000007U
|
||||
#define TIMG_WDT_SYS_RESET_LENGTH_M (TIMG_WDT_SYS_RESET_LENGTH_V << TIMG_WDT_SYS_RESET_LENGTH_S)
|
||||
#define TIMG_WDT_SYS_RESET_LENGTH_V 0x00000007U
|
||||
#define TIMG_WDT_SYS_RESET_LENGTH_S 15
|
||||
/** TIMG_WDT_CPU_RESET_LENGTH : R/W; bitpos: [20:18]; default: 1;
|
||||
* CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
|
||||
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
|
||||
*/
|
||||
#define TIMG_WDT_CPU_RESET_LENGTH 0x00000007U
|
||||
#define TIMG_WDT_CPU_RESET_LENGTH_M (TIMG_WDT_CPU_RESET_LENGTH_V << TIMG_WDT_CPU_RESET_LENGTH_S)
|
||||
#define TIMG_WDT_CPU_RESET_LENGTH_V 0x00000007U
|
||||
#define TIMG_WDT_CPU_RESET_LENGTH_S 18
|
||||
/** TIMG_WDT_USE_XTAL : R/W; bitpos: [21]; default: 0;
|
||||
* choose WDT clock:0-apb_clk; 1-xtal_clk.
|
||||
*/
|
||||
#define TIMG_WDT_USE_XTAL (BIT(21))
|
||||
#define TIMG_WDT_USE_XTAL_M (TIMG_WDT_USE_XTAL_V << TIMG_WDT_USE_XTAL_S)
|
||||
#define TIMG_WDT_USE_XTAL_V 0x00000001U
|
||||
#define TIMG_WDT_USE_XTAL_S 21
|
||||
/** TIMG_WDT_CONF_UPDATE_EN : WT; bitpos: [22]; default: 0;
|
||||
* update the WDT configuration registers
|
||||
*/
|
||||
#define TIMG_WDT_CONF_UPDATE_EN (BIT(22))
|
||||
#define TIMG_WDT_CONF_UPDATE_EN_M (TIMG_WDT_CONF_UPDATE_EN_V << TIMG_WDT_CONF_UPDATE_EN_S)
|
||||
#define TIMG_WDT_CONF_UPDATE_EN_V 0x00000001U
|
||||
#define TIMG_WDT_CONF_UPDATE_EN_S 22
|
||||
/** TIMG_WDT_STG3 : R/W; bitpos: [24:23]; default: 0;
|
||||
* Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
|
||||
*/
|
||||
#define TIMG_WDT_STG3 0x00000003U
|
||||
#define TIMG_WDT_STG3_M (TIMG_WDT_STG3_V << TIMG_WDT_STG3_S)
|
||||
#define TIMG_WDT_STG3_V 0x00000003U
|
||||
#define TIMG_WDT_STG3_S 23
|
||||
/** TIMG_WDT_STG2 : R/W; bitpos: [26:25]; default: 0;
|
||||
* Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
|
||||
*/
|
||||
#define TIMG_WDT_STG2 0x00000003U
|
||||
#define TIMG_WDT_STG2_M (TIMG_WDT_STG2_V << TIMG_WDT_STG2_S)
|
||||
#define TIMG_WDT_STG2_V 0x00000003U
|
||||
#define TIMG_WDT_STG2_S 25
|
||||
/** TIMG_WDT_STG1 : R/W; bitpos: [28:27]; default: 0;
|
||||
* Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
|
||||
*/
|
||||
#define TIMG_WDT_STG1 0x00000003U
|
||||
#define TIMG_WDT_STG1_M (TIMG_WDT_STG1_V << TIMG_WDT_STG1_S)
|
||||
#define TIMG_WDT_STG1_V 0x00000003U
|
||||
#define TIMG_WDT_STG1_S 27
|
||||
/** TIMG_WDT_STG0 : R/W; bitpos: [30:29]; default: 0;
|
||||
* Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
|
||||
*/
|
||||
#define TIMG_WDT_STG0 0x00000003U
|
||||
#define TIMG_WDT_STG0_M (TIMG_WDT_STG0_V << TIMG_WDT_STG0_S)
|
||||
#define TIMG_WDT_STG0_V 0x00000003U
|
||||
#define TIMG_WDT_STG0_S 29
|
||||
/** TIMG_WDT_EN : R/W; bitpos: [31]; default: 0;
|
||||
* When set, MWDT is enabled.
|
||||
*/
|
||||
#define TIMG_WDT_EN (BIT(31))
|
||||
#define TIMG_WDT_EN_M (TIMG_WDT_EN_V << TIMG_WDT_EN_S)
|
||||
#define TIMG_WDT_EN_V 0x00000001U
|
||||
#define TIMG_WDT_EN_S 31
|
||||
|
||||
/** TIMG_WDTCONFIG1_REG register
|
||||
* Watchdog timer prescaler register
|
||||
*/
|
||||
#define TIMG_WDTCONFIG1_REG(i) (DR_REG_TIMG_BASE(i) + 0x4c)
|
||||
/** TIMG_WDT_DIVCNT_RST : WT; bitpos: [0]; default: 0;
|
||||
* When set, WDT 's clock divider counter will be reset.
|
||||
*/
|
||||
#define TIMG_WDT_DIVCNT_RST (BIT(0))
|
||||
#define TIMG_WDT_DIVCNT_RST_M (TIMG_WDT_DIVCNT_RST_V << TIMG_WDT_DIVCNT_RST_S)
|
||||
#define TIMG_WDT_DIVCNT_RST_V 0x00000001U
|
||||
#define TIMG_WDT_DIVCNT_RST_S 0
|
||||
/** TIMG_WDT_CLK_PRESCALE : R/W; bitpos: [31:16]; default: 1;
|
||||
* MWDT clock prescaler value. MWDT clock period = 12.5 ns *
|
||||
* TIMG_WDT_CLK_PRESCALE.
|
||||
*/
|
||||
#define TIMG_WDT_CLK_PRESCALE 0x0000FFFFU
|
||||
#define TIMG_WDT_CLK_PRESCALE_M (TIMG_WDT_CLK_PRESCALE_V << TIMG_WDT_CLK_PRESCALE_S)
|
||||
#define TIMG_WDT_CLK_PRESCALE_V 0x0000FFFFU
|
||||
#define TIMG_WDT_CLK_PRESCALE_S 16
|
||||
|
||||
/** TIMG_WDTCONFIG2_REG register
|
||||
* Watchdog timer stage 0 timeout value
|
||||
*/
|
||||
#define TIMG_WDTCONFIG2_REG(i) (DR_REG_TIMG_BASE(i) + 0x50)
|
||||
/** TIMG_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 26000000;
|
||||
* Stage 0 timeout value, in MWDT clock cycles.
|
||||
*/
|
||||
#define TIMG_WDT_STG0_HOLD 0xFFFFFFFFU
|
||||
#define TIMG_WDT_STG0_HOLD_M (TIMG_WDT_STG0_HOLD_V << TIMG_WDT_STG0_HOLD_S)
|
||||
#define TIMG_WDT_STG0_HOLD_V 0xFFFFFFFFU
|
||||
#define TIMG_WDT_STG0_HOLD_S 0
|
||||
|
||||
/** TIMG_WDTCONFIG3_REG register
|
||||
* Watchdog timer stage 1 timeout value
|
||||
*/
|
||||
#define TIMG_WDTCONFIG3_REG(i) (DR_REG_TIMG_BASE(i) + 0x54)
|
||||
/** TIMG_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 134217727;
|
||||
* Stage 1 timeout value, in MWDT clock cycles.
|
||||
*/
|
||||
#define TIMG_WDT_STG1_HOLD 0xFFFFFFFFU
|
||||
#define TIMG_WDT_STG1_HOLD_M (TIMG_WDT_STG1_HOLD_V << TIMG_WDT_STG1_HOLD_S)
|
||||
#define TIMG_WDT_STG1_HOLD_V 0xFFFFFFFFU
|
||||
#define TIMG_WDT_STG1_HOLD_S 0
|
||||
|
||||
/** TIMG_WDTCONFIG4_REG register
|
||||
* Watchdog timer stage 2 timeout value
|
||||
*/
|
||||
#define TIMG_WDTCONFIG4_REG(i) (DR_REG_TIMG_BASE(i) + 0x58)
|
||||
/** TIMG_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 1048575;
|
||||
* Stage 2 timeout value, in MWDT clock cycles.
|
||||
*/
|
||||
#define TIMG_WDT_STG2_HOLD 0xFFFFFFFFU
|
||||
#define TIMG_WDT_STG2_HOLD_M (TIMG_WDT_STG2_HOLD_V << TIMG_WDT_STG2_HOLD_S)
|
||||
#define TIMG_WDT_STG2_HOLD_V 0xFFFFFFFFU
|
||||
#define TIMG_WDT_STG2_HOLD_S 0
|
||||
|
||||
/** TIMG_WDTCONFIG5_REG register
|
||||
* Watchdog timer stage 3 timeout value
|
||||
*/
|
||||
#define TIMG_WDTCONFIG5_REG(i) (DR_REG_TIMG_BASE(i) + 0x5c)
|
||||
/** TIMG_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 1048575;
|
||||
* Stage 3 timeout value, in MWDT clock cycles.
|
||||
*/
|
||||
#define TIMG_WDT_STG3_HOLD 0xFFFFFFFFU
|
||||
#define TIMG_WDT_STG3_HOLD_M (TIMG_WDT_STG3_HOLD_V << TIMG_WDT_STG3_HOLD_S)
|
||||
#define TIMG_WDT_STG3_HOLD_V 0xFFFFFFFFU
|
||||
#define TIMG_WDT_STG3_HOLD_S 0
|
||||
|
||||
/** TIMG_WDTFEED_REG register
|
||||
* Write to feed the watchdog timer
|
||||
*/
|
||||
#define TIMG_WDTFEED_REG(i) (DR_REG_TIMG_BASE(i) + 0x60)
|
||||
/** TIMG_WDT_FEED : WT; bitpos: [31:0]; default: 0;
|
||||
* Write any value to feed the MWDT. (WO)
|
||||
*/
|
||||
#define TIMG_WDT_FEED 0xFFFFFFFFU
|
||||
#define TIMG_WDT_FEED_M (TIMG_WDT_FEED_V << TIMG_WDT_FEED_S)
|
||||
#define TIMG_WDT_FEED_V 0xFFFFFFFFU
|
||||
#define TIMG_WDT_FEED_S 0
|
||||
|
||||
/** TIMG_WDTWPROTECT_REG register
|
||||
* Watchdog write protect register
|
||||
*/
|
||||
#define TIMG_WDTWPROTECT_REG(i) (DR_REG_TIMG_BASE(i) + 0x64)
|
||||
/** TIMG_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065;
|
||||
* If the register contains a different value than its reset value, write
|
||||
* protection is enabled.
|
||||
*/
|
||||
#define TIMG_WDT_WKEY 0xFFFFFFFFU
|
||||
#define TIMG_WDT_WKEY_M (TIMG_WDT_WKEY_V << TIMG_WDT_WKEY_S)
|
||||
#define TIMG_WDT_WKEY_V 0xFFFFFFFFU
|
||||
#define TIMG_WDT_WKEY_S 0
|
||||
|
||||
/** TIMG_RTCCALICFG_REG register
|
||||
* RTC calibration configure register
|
||||
*/
|
||||
#define TIMG_RTCCALICFG_REG(i) (DR_REG_TIMG_BASE(i) + 0x68)
|
||||
/** TIMG_RTC_CALI_START_CYCLING : R/W; bitpos: [12]; default: 1;
|
||||
* Reserved
|
||||
*/
|
||||
#define TIMG_RTC_CALI_START_CYCLING (BIT(12))
|
||||
#define TIMG_RTC_CALI_START_CYCLING_M (TIMG_RTC_CALI_START_CYCLING_V << TIMG_RTC_CALI_START_CYCLING_S)
|
||||
#define TIMG_RTC_CALI_START_CYCLING_V 0x00000001U
|
||||
#define TIMG_RTC_CALI_START_CYCLING_S 12
|
||||
/** TIMG_RTC_CALI_CLK_SEL : R/W; bitpos: [14:13]; default: 1;
|
||||
* 0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
|
||||
*/
|
||||
#define TIMG_RTC_CALI_CLK_SEL 0x00000003U
|
||||
#define TIMG_RTC_CALI_CLK_SEL_M (TIMG_RTC_CALI_CLK_SEL_V << TIMG_RTC_CALI_CLK_SEL_S)
|
||||
#define TIMG_RTC_CALI_CLK_SEL_V 0x00000003U
|
||||
#define TIMG_RTC_CALI_CLK_SEL_S 13
|
||||
/** TIMG_RTC_CALI_RDY : RO; bitpos: [15]; default: 0;
|
||||
* Reserved
|
||||
*/
|
||||
#define TIMG_RTC_CALI_RDY (BIT(15))
|
||||
#define TIMG_RTC_CALI_RDY_M (TIMG_RTC_CALI_RDY_V << TIMG_RTC_CALI_RDY_S)
|
||||
#define TIMG_RTC_CALI_RDY_V 0x00000001U
|
||||
#define TIMG_RTC_CALI_RDY_S 15
|
||||
/** TIMG_RTC_CALI_MAX : R/W; bitpos: [30:16]; default: 1;
|
||||
* Reserved
|
||||
*/
|
||||
#define TIMG_RTC_CALI_MAX 0x00007FFFU
|
||||
#define TIMG_RTC_CALI_MAX_M (TIMG_RTC_CALI_MAX_V << TIMG_RTC_CALI_MAX_S)
|
||||
#define TIMG_RTC_CALI_MAX_V 0x00007FFFU
|
||||
#define TIMG_RTC_CALI_MAX_S 16
|
||||
/** TIMG_RTC_CALI_START : R/W; bitpos: [31]; default: 0;
|
||||
* Reserved
|
||||
*/
|
||||
#define TIMG_RTC_CALI_START (BIT(31))
|
||||
#define TIMG_RTC_CALI_START_M (TIMG_RTC_CALI_START_V << TIMG_RTC_CALI_START_S)
|
||||
#define TIMG_RTC_CALI_START_V 0x00000001U
|
||||
#define TIMG_RTC_CALI_START_S 31
|
||||
|
||||
/** TIMG_RTCCALICFG1_REG register
|
||||
* RTC calibration configure1 register
|
||||
*/
|
||||
#define TIMG_RTCCALICFG1_REG(i) (DR_REG_TIMG_BASE(i) + 0x6c)
|
||||
/** TIMG_RTC_CALI_CYCLING_DATA_VLD : RO; bitpos: [0]; default: 0;
|
||||
* Reserved
|
||||
*/
|
||||
#define TIMG_RTC_CALI_CYCLING_DATA_VLD (BIT(0))
|
||||
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M (TIMG_RTC_CALI_CYCLING_DATA_VLD_V << TIMG_RTC_CALI_CYCLING_DATA_VLD_S)
|
||||
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_V 0x00000001U
|
||||
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_S 0
|
||||
/** TIMG_RTC_CALI_VALUE : RO; bitpos: [31:7]; default: 0;
|
||||
* Reserved
|
||||
*/
|
||||
#define TIMG_RTC_CALI_VALUE 0x01FFFFFFU
|
||||
#define TIMG_RTC_CALI_VALUE_M (TIMG_RTC_CALI_VALUE_V << TIMG_RTC_CALI_VALUE_S)
|
||||
#define TIMG_RTC_CALI_VALUE_V 0x01FFFFFFU
|
||||
#define TIMG_RTC_CALI_VALUE_S 7
|
||||
|
||||
/** TIMG_INT_ENA_TIMERS_REG register
|
||||
* Interrupt enable bits
|
||||
*/
|
||||
#define TIMG_INT_ENA_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x70)
|
||||
/** TIMG_T0_INT_ENA : R/W; bitpos: [0]; default: 0;
|
||||
* The interrupt enable bit for the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
#define TIMG_T0_INT_ENA (BIT(0))
|
||||
#define TIMG_T0_INT_ENA_M (TIMG_T0_INT_ENA_V << TIMG_T0_INT_ENA_S)
|
||||
#define TIMG_T0_INT_ENA_V 0x00000001U
|
||||
#define TIMG_T0_INT_ENA_S 0
|
||||
/** TIMG_WDT_INT_ENA : R/W; bitpos: [1]; default: 0;
|
||||
* The interrupt enable bit for the TIMG_WDT_INT interrupt.
|
||||
*/
|
||||
#define TIMG_WDT_INT_ENA (BIT(1))
|
||||
#define TIMG_WDT_INT_ENA_M (TIMG_WDT_INT_ENA_V << TIMG_WDT_INT_ENA_S)
|
||||
#define TIMG_WDT_INT_ENA_V 0x00000001U
|
||||
#define TIMG_WDT_INT_ENA_S 1
|
||||
|
||||
/** TIMG_INT_RAW_TIMERS_REG register
|
||||
* Raw interrupt status
|
||||
*/
|
||||
#define TIMG_INT_RAW_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x74)
|
||||
/** TIMG_T0_INT_RAW : R/SS/WTC; bitpos: [0]; default: 0;
|
||||
* The raw interrupt status bit for the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
#define TIMG_T0_INT_RAW (BIT(0))
|
||||
#define TIMG_T0_INT_RAW_M (TIMG_T0_INT_RAW_V << TIMG_T0_INT_RAW_S)
|
||||
#define TIMG_T0_INT_RAW_V 0x00000001U
|
||||
#define TIMG_T0_INT_RAW_S 0
|
||||
/** TIMG_WDT_INT_RAW : R/SS/WTC; bitpos: [1]; default: 0;
|
||||
* The raw interrupt status bit for the TIMG_WDT_INT interrupt.
|
||||
*/
|
||||
#define TIMG_WDT_INT_RAW (BIT(1))
|
||||
#define TIMG_WDT_INT_RAW_M (TIMG_WDT_INT_RAW_V << TIMG_WDT_INT_RAW_S)
|
||||
#define TIMG_WDT_INT_RAW_V 0x00000001U
|
||||
#define TIMG_WDT_INT_RAW_S 1
|
||||
|
||||
/** TIMG_INT_ST_TIMERS_REG register
|
||||
* Masked interrupt status
|
||||
*/
|
||||
#define TIMG_INT_ST_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x78)
|
||||
/** TIMG_T0_INT_ST : RO; bitpos: [0]; default: 0;
|
||||
* The masked interrupt status bit for the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
#define TIMG_T0_INT_ST (BIT(0))
|
||||
#define TIMG_T0_INT_ST_M (TIMG_T0_INT_ST_V << TIMG_T0_INT_ST_S)
|
||||
#define TIMG_T0_INT_ST_V 0x00000001U
|
||||
#define TIMG_T0_INT_ST_S 0
|
||||
/** TIMG_WDT_INT_ST : RO; bitpos: [1]; default: 0;
|
||||
* The masked interrupt status bit for the TIMG_WDT_INT interrupt.
|
||||
*/
|
||||
#define TIMG_WDT_INT_ST (BIT(1))
|
||||
#define TIMG_WDT_INT_ST_M (TIMG_WDT_INT_ST_V << TIMG_WDT_INT_ST_S)
|
||||
#define TIMG_WDT_INT_ST_V 0x00000001U
|
||||
#define TIMG_WDT_INT_ST_S 1
|
||||
|
||||
/** TIMG_INT_CLR_TIMERS_REG register
|
||||
* Interrupt clear bits
|
||||
*/
|
||||
#define TIMG_INT_CLR_TIMERS_REG(i) (DR_REG_TIMG_BASE(i) + 0x7c)
|
||||
/** TIMG_T0_INT_CLR : WT; bitpos: [0]; default: 0;
|
||||
* Set this bit to clear the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
#define TIMG_T0_INT_CLR (BIT(0))
|
||||
#define TIMG_T0_INT_CLR_M (TIMG_T0_INT_CLR_V << TIMG_T0_INT_CLR_S)
|
||||
#define TIMG_T0_INT_CLR_V 0x00000001U
|
||||
#define TIMG_T0_INT_CLR_S 0
|
||||
/** TIMG_WDT_INT_CLR : WT; bitpos: [1]; default: 0;
|
||||
* Set this bit to clear the TIMG_WDT_INT interrupt.
|
||||
*/
|
||||
#define TIMG_WDT_INT_CLR (BIT(1))
|
||||
#define TIMG_WDT_INT_CLR_M (TIMG_WDT_INT_CLR_V << TIMG_WDT_INT_CLR_S)
|
||||
#define TIMG_WDT_INT_CLR_V 0x00000001U
|
||||
#define TIMG_WDT_INT_CLR_S 1
|
||||
|
||||
/** TIMG_RTCCALICFG2_REG register
|
||||
* Timer group calibration register
|
||||
*/
|
||||
#define TIMG_RTCCALICFG2_REG(i) (DR_REG_TIMG_BASE(i) + 0x80)
|
||||
/** TIMG_RTC_CALI_TIMEOUT : RO; bitpos: [0]; default: 0;
|
||||
* RTC calibration timeout indicator
|
||||
*/
|
||||
#define TIMG_RTC_CALI_TIMEOUT (BIT(0))
|
||||
#define TIMG_RTC_CALI_TIMEOUT_M (TIMG_RTC_CALI_TIMEOUT_V << TIMG_RTC_CALI_TIMEOUT_S)
|
||||
#define TIMG_RTC_CALI_TIMEOUT_V 0x00000001U
|
||||
#define TIMG_RTC_CALI_TIMEOUT_S 0
|
||||
/** TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W; bitpos: [6:3]; default: 3;
|
||||
* Cycles that release calibration timeout reset
|
||||
*/
|
||||
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT 0x0000000FU
|
||||
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M (TIMG_RTC_CALI_TIMEOUT_RST_CNT_V << TIMG_RTC_CALI_TIMEOUT_RST_CNT_S)
|
||||
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V 0x0000000FU
|
||||
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S 3
|
||||
/** TIMG_RTC_CALI_TIMEOUT_THRES : R/W; bitpos: [31:7]; default: 33554431;
|
||||
* Threshold value for the RTC calibration timer. If the calibration timer's value
|
||||
* exceeds this threshold, a timeout is triggered.
|
||||
*/
|
||||
#define TIMG_RTC_CALI_TIMEOUT_THRES 0x01FFFFFFU
|
||||
#define TIMG_RTC_CALI_TIMEOUT_THRES_M (TIMG_RTC_CALI_TIMEOUT_THRES_V << TIMG_RTC_CALI_TIMEOUT_THRES_S)
|
||||
#define TIMG_RTC_CALI_TIMEOUT_THRES_V 0x01FFFFFFU
|
||||
#define TIMG_RTC_CALI_TIMEOUT_THRES_S 7
|
||||
|
||||
/** TIMG_NTIMERS_DATE_REG register
|
||||
* Timer version control register
|
||||
*/
|
||||
#define TIMG_NTIMERS_DATE_REG(i) (DR_REG_TIMG_BASE(i) + 0xf8)
|
||||
/** TIMG_NTIMGS_DATE : R/W; bitpos: [27:0]; default: 33579409;
|
||||
* Timer version control register
|
||||
*/
|
||||
#define TIMG_NTIMGS_DATE 0x0FFFFFFFU
|
||||
#define TIMG_NTIMGS_DATE_M (TIMG_NTIMGS_DATE_V << TIMG_NTIMGS_DATE_S)
|
||||
#define TIMG_NTIMGS_DATE_V 0x0FFFFFFFU
|
||||
#define TIMG_NTIMGS_DATE_S 0
|
||||
|
||||
/** TIMG_REGCLK_REG register
|
||||
* Timer group clock gate register
|
||||
*/
|
||||
#define TIMG_REGCLK_REG(i) (DR_REG_TIMG_BASE(i) + 0xfc)
|
||||
/** TIMG_WDT_CLK_IS_ACTIVE : R/W; bitpos: [29]; default: 1;
|
||||
* enable WDT's clock
|
||||
*/
|
||||
#define TIMG_WDT_CLK_IS_ACTIVE (BIT(29))
|
||||
#define TIMG_WDT_CLK_IS_ACTIVE_M (TIMG_WDT_CLK_IS_ACTIVE_V << TIMG_WDT_CLK_IS_ACTIVE_S)
|
||||
#define TIMG_WDT_CLK_IS_ACTIVE_V 0x00000001U
|
||||
#define TIMG_WDT_CLK_IS_ACTIVE_S 29
|
||||
/** TIMG_TIMER_CLK_IS_ACTIVE : R/W; bitpos: [30]; default: 1;
|
||||
* enable Timer $x's clock
|
||||
*/
|
||||
#define TIMG_TIMER_CLK_IS_ACTIVE (BIT(30))
|
||||
#define TIMG_TIMER_CLK_IS_ACTIVE_M (TIMG_TIMER_CLK_IS_ACTIVE_V << TIMG_TIMER_CLK_IS_ACTIVE_S)
|
||||
#define TIMG_TIMER_CLK_IS_ACTIVE_V 0x00000001U
|
||||
#define TIMG_TIMER_CLK_IS_ACTIVE_S 30
|
||||
/** TIMG_CLK_EN : R/W; bitpos: [31]; default: 0;
|
||||
* Register clock gate signal. 1: Registers can be read and written to by software. 0:
|
||||
* Registers can not be read or written to by software.
|
||||
*/
|
||||
#define TIMG_CLK_EN (BIT(31))
|
||||
#define TIMG_CLK_EN_M (TIMG_CLK_EN_V << TIMG_CLK_EN_S)
|
||||
#define TIMG_CLK_EN_V 0x00000001U
|
||||
#define TIMG_CLK_EN_S 31
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,561 +0,0 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Group: T0 Control and configuration registers */
|
||||
/** Type of txconfig register
|
||||
* Timer x configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0: 9;
|
||||
/** tx_use_xtal : R/W; bitpos: [9]; default: 0;
|
||||
* 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source
|
||||
* clock of timer group.
|
||||
*/
|
||||
uint32_t tx_use_xtal: 1;
|
||||
/** tx_alarm_en : R/W/SC; bitpos: [10]; default: 0;
|
||||
* When set, the alarm is enabled. This bit is automatically cleared once an
|
||||
* alarm occurs.
|
||||
*/
|
||||
uint32_t tx_alarm_en: 1;
|
||||
uint32_t reserved_11: 1;
|
||||
/** tx_divcnt_rst : WT; bitpos: [12]; default: 0;
|
||||
* When set, Timer x 's clock divider counter will be reset.
|
||||
*/
|
||||
uint32_t tx_divcnt_rst: 1;
|
||||
/** tx_divider : R/W; bitpos: [28:13]; default: 1;
|
||||
* Timer x clock (Tx_clk) prescaler value.
|
||||
*/
|
||||
uint32_t tx_divider: 16;
|
||||
/** tx_autoreload : R/W; bitpos: [29]; default: 1;
|
||||
* When set, timer x auto-reload at alarm is enabled.
|
||||
*/
|
||||
uint32_t tx_autoreload: 1;
|
||||
/** tx_increase : R/W; bitpos: [30]; default: 1;
|
||||
* When set, the timer x time-base counter will increment every clock tick. When
|
||||
* cleared, the timer x time-base counter will decrement.
|
||||
*/
|
||||
uint32_t tx_increase: 1;
|
||||
/** tx_en : R/W; bitpos: [31]; default: 0;
|
||||
* When set, the timer x time-base counter is enabled.
|
||||
*/
|
||||
uint32_t tx_en: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txconfig_reg_t;
|
||||
|
||||
/** Type of txlo register
|
||||
* Timer x current value, low 32 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_lo : RO; bitpos: [31:0]; default: 0;
|
||||
* After writing to TIMG_TxUPDATE_REG, the low 32 bits of the time-base counter
|
||||
* of timer x can be read here.
|
||||
*/
|
||||
uint32_t tx_lo: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txlo_reg_t;
|
||||
|
||||
/** Type of txhi register
|
||||
* Timer $x current value, high 22 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_hi : RO; bitpos: [21:0]; default: 0;
|
||||
* After writing to TIMG_T$xUPDATE_REG, the high 22 bits of the time-base counter
|
||||
* of timer $x can be read here.
|
||||
*/
|
||||
uint32_t tx_hi: 22;
|
||||
uint32_t reserved_22: 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txhi_reg_t;
|
||||
|
||||
/** Type of txupdate register
|
||||
* Write to copy current timer value to TIMGn_T$x_(LO/HI)_REG
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0: 31;
|
||||
/** tx_update : R/W/SC; bitpos: [31]; default: 0;
|
||||
* After writing 0 or 1 to TIMG_T$xUPDATE_REG, the counter value is latched.
|
||||
*/
|
||||
uint32_t tx_update: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txupdate_reg_t;
|
||||
|
||||
/** Type of txalarmlo register
|
||||
* Timer $x alarm value, low 32 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_alarm_lo : R/W; bitpos: [31:0]; default: 0;
|
||||
* Timer $x alarm trigger time-base counter value, low 32 bits.
|
||||
*/
|
||||
uint32_t tx_alarm_lo: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txalarmlo_reg_t;
|
||||
|
||||
/** Type of txalarmhi register
|
||||
* Timer $x alarm value, high bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_alarm_hi : R/W; bitpos: [21:0]; default: 0;
|
||||
* Timer $x alarm trigger time-base counter value, high 22 bits.
|
||||
*/
|
||||
uint32_t tx_alarm_hi: 22;
|
||||
uint32_t reserved_22: 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txalarmhi_reg_t;
|
||||
|
||||
/** Type of txloadlo register
|
||||
* Timer $x reload value, low 32 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_load_lo : R/W; bitpos: [31:0]; default: 0;
|
||||
* Low 32 bits of the value that a reload will load onto timer $x time-base
|
||||
* Counter.
|
||||
*/
|
||||
uint32_t tx_load_lo: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txloadlo_reg_t;
|
||||
|
||||
/** Type of txloadhi register
|
||||
* Timer $x reload value, high 22 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_load_hi : R/W; bitpos: [21:0]; default: 0;
|
||||
* High 22 bits of the value that a reload will load onto timer $x time-base
|
||||
* counter.
|
||||
*/
|
||||
uint32_t tx_load_hi: 22;
|
||||
uint32_t reserved_22: 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txloadhi_reg_t;
|
||||
|
||||
/** Type of txload register
|
||||
* Write to reload timer from TIMG_T$x_(LOADLOLOADHI)_REG
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tx_load : WT; bitpos: [31:0]; default: 0;
|
||||
*
|
||||
* Write any value to trigger a timer $x time-base counter reload.
|
||||
*/
|
||||
uint32_t tx_load: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_txload_reg_t;
|
||||
|
||||
|
||||
/** Group: WDT Control and configuration registers */
|
||||
/** Type of wdtconfig0 register
|
||||
* Watchdog timer configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0: 12;
|
||||
/** wdt_appcpu_reset_en : R/W; bitpos: [12]; default: 0;
|
||||
* WDT reset CPU enable.
|
||||
*/
|
||||
uint32_t wdt_appcpu_reset_en: 1;
|
||||
/** wdt_procpu_reset_en : R/W; bitpos: [13]; default: 0;
|
||||
* WDT reset CPU enable.
|
||||
*/
|
||||
uint32_t wdt_procpu_reset_en: 1;
|
||||
/** wdt_flashboot_mod_en : R/W; bitpos: [14]; default: 1;
|
||||
* When set, Flash boot protection is enabled.
|
||||
*/
|
||||
uint32_t wdt_flashboot_mod_en: 1;
|
||||
/** wdt_sys_reset_length : R/W; bitpos: [17:15]; default: 1;
|
||||
* System reset signal length selection. 0: 100 ns, 1: 200 ns,
|
||||
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
|
||||
*/
|
||||
uint32_t wdt_sys_reset_length: 3;
|
||||
/** wdt_cpu_reset_length : R/W; bitpos: [20:18]; default: 1;
|
||||
* CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
|
||||
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
|
||||
*/
|
||||
uint32_t wdt_cpu_reset_length: 3;
|
||||
/** wdt_use_xtal : R/W; bitpos: [21]; default: 0;
|
||||
* choose WDT clock:0-apb_clk; 1-xtal_clk.
|
||||
*/
|
||||
uint32_t wdt_use_xtal: 1;
|
||||
/** wdt_conf_update_en : WT; bitpos: [22]; default: 0;
|
||||
* update the WDT configuration registers
|
||||
*/
|
||||
uint32_t wdt_conf_update_en: 1;
|
||||
/** wdt_stg3 : R/W; bitpos: [24:23]; default: 0;
|
||||
* Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
|
||||
*/
|
||||
uint32_t wdt_stg3: 2;
|
||||
/** wdt_stg2 : R/W; bitpos: [26:25]; default: 0;
|
||||
* Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
|
||||
*/
|
||||
uint32_t wdt_stg2: 2;
|
||||
/** wdt_stg1 : R/W; bitpos: [28:27]; default: 0;
|
||||
* Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
|
||||
*/
|
||||
uint32_t wdt_stg1: 2;
|
||||
/** wdt_stg0 : R/W; bitpos: [30:29]; default: 0;
|
||||
* Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
|
||||
*/
|
||||
uint32_t wdt_stg0: 2;
|
||||
/** wdt_en : R/W; bitpos: [31]; default: 0;
|
||||
* When set, MWDT is enabled.
|
||||
*/
|
||||
uint32_t wdt_en: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_wdtconfig0_reg_t;
|
||||
|
||||
/** Type of wdtconfig1 register
|
||||
* Watchdog timer prescaler register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_divcnt_rst : WT; bitpos: [0]; default: 0;
|
||||
* When set, WDT 's clock divider counter will be reset.
|
||||
*/
|
||||
uint32_t wdt_divcnt_rst: 1;
|
||||
uint32_t reserved_1: 15;
|
||||
/** wdt_clk_prescale : R/W; bitpos: [31:16]; default: 1;
|
||||
* MWDT clock prescaler value. MWDT clock period = 12.5 ns *
|
||||
* TIMG_WDT_CLK_PRESCALE.
|
||||
*/
|
||||
uint32_t wdt_clk_prescale: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_wdtconfig1_reg_t;
|
||||
|
||||
/** Type of wdtconfig2 register
|
||||
* Watchdog timer stage 0 timeout value
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 26000000;
|
||||
* Stage 0 timeout value, in MWDT clock cycles.
|
||||
*/
|
||||
uint32_t wdt_stg0_hold: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_wdtconfig2_reg_t;
|
||||
|
||||
/** Type of wdtconfig3 register
|
||||
* Watchdog timer stage 1 timeout value
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 134217727;
|
||||
* Stage 1 timeout value, in MWDT clock cycles.
|
||||
*/
|
||||
uint32_t wdt_stg1_hold: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_wdtconfig3_reg_t;
|
||||
|
||||
/** Type of wdtconfig4 register
|
||||
* Watchdog timer stage 2 timeout value
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 1048575;
|
||||
* Stage 2 timeout value, in MWDT clock cycles.
|
||||
*/
|
||||
uint32_t wdt_stg2_hold: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_wdtconfig4_reg_t;
|
||||
|
||||
/** Type of wdtconfig5 register
|
||||
* Watchdog timer stage 3 timeout value
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 1048575;
|
||||
* Stage 3 timeout value, in MWDT clock cycles.
|
||||
*/
|
||||
uint32_t wdt_stg3_hold: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_wdtconfig5_reg_t;
|
||||
|
||||
/** Type of wdtfeed register
|
||||
* Write to feed the watchdog timer
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_feed : WT; bitpos: [31:0]; default: 0;
|
||||
* Write any value to feed the MWDT. (WO)
|
||||
*/
|
||||
uint32_t wdt_feed: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_wdtfeed_reg_t;
|
||||
|
||||
/** Type of wdtwprotect register
|
||||
* Watchdog write protect register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_wkey : R/W; bitpos: [31:0]; default: 1356348065;
|
||||
* If the register contains a different value than its reset value, write
|
||||
* protection is enabled.
|
||||
*/
|
||||
uint32_t wdt_wkey: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_wdtwprotect_reg_t;
|
||||
|
||||
|
||||
/** Group: RTC CALI Control and configuration registers */
|
||||
/** Type of rtccalicfg register
|
||||
* RTC calibration configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0: 12;
|
||||
/** rtc_cali_start_cycling : R/W; bitpos: [12]; default: 1;
|
||||
* Reserved
|
||||
*/
|
||||
uint32_t rtc_cali_start_cycling: 1;
|
||||
/** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 1;
|
||||
* 0:rtc slow clock. 1:clk_8m, 2:xtal_32k.
|
||||
*/
|
||||
uint32_t rtc_cali_clk_sel: 2;
|
||||
/** rtc_cali_rdy : RO; bitpos: [15]; default: 0;
|
||||
* Reserved
|
||||
*/
|
||||
uint32_t rtc_cali_rdy: 1;
|
||||
/** rtc_cali_max : R/W; bitpos: [30:16]; default: 1;
|
||||
* Reserved
|
||||
*/
|
||||
uint32_t rtc_cali_max: 15;
|
||||
/** rtc_cali_start : R/W; bitpos: [31]; default: 0;
|
||||
* Reserved
|
||||
*/
|
||||
uint32_t rtc_cali_start: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_rtccalicfg_reg_t;
|
||||
|
||||
/** Type of rtccalicfg1 register
|
||||
* RTC calibration configure1 register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** rtc_cali_cycling_data_vld : RO; bitpos: [0]; default: 0;
|
||||
* Reserved
|
||||
*/
|
||||
uint32_t rtc_cali_cycling_data_vld: 1;
|
||||
uint32_t reserved_1: 6;
|
||||
/** rtc_cali_value : RO; bitpos: [31:7]; default: 0;
|
||||
* Reserved
|
||||
*/
|
||||
uint32_t rtc_cali_value: 25;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_rtccalicfg1_reg_t;
|
||||
|
||||
/** Type of rtccalicfg2 register
|
||||
* Timer group calibration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** rtc_cali_timeout : RO; bitpos: [0]; default: 0;
|
||||
* RTC calibration timeout indicator
|
||||
*/
|
||||
uint32_t rtc_cali_timeout: 1;
|
||||
uint32_t reserved_1: 2;
|
||||
/** rtc_cali_timeout_rst_cnt : R/W; bitpos: [6:3]; default: 3;
|
||||
* Cycles that release calibration timeout reset
|
||||
*/
|
||||
uint32_t rtc_cali_timeout_rst_cnt: 4;
|
||||
/** rtc_cali_timeout_thres : R/W; bitpos: [31:7]; default: 33554431;
|
||||
* Threshold value for the RTC calibration timer. If the calibration timer's value
|
||||
* exceeds this threshold, a timeout is triggered.
|
||||
*/
|
||||
uint32_t rtc_cali_timeout_thres: 25;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_rtccalicfg2_reg_t;
|
||||
|
||||
|
||||
/** Group: Interrupt registers */
|
||||
/** Type of int_ena_timers register
|
||||
* Interrupt enable bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** t0_int_ena : R/W; bitpos: [0]; default: 0;
|
||||
* The interrupt enable bit for the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
uint32_t t0_int_ena: 1;
|
||||
/** wdt_int_ena : R/W; bitpos: [1]; default: 0;
|
||||
* The interrupt enable bit for the TIMG_WDT_INT interrupt.
|
||||
*/
|
||||
uint32_t wdt_int_ena: 1;
|
||||
uint32_t reserved_2: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_int_ena_timers_reg_t;
|
||||
|
||||
/** Type of int_raw_timers register
|
||||
* Raw interrupt status
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** t0_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
|
||||
* The raw interrupt status bit for the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
uint32_t t0_int_raw: 1;
|
||||
/** wdt_int_raw : R/SS/WTC; bitpos: [1]; default: 0;
|
||||
* The raw interrupt status bit for the TIMG_WDT_INT interrupt.
|
||||
*/
|
||||
uint32_t wdt_int_raw: 1;
|
||||
uint32_t reserved_2: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_int_raw_timers_reg_t;
|
||||
|
||||
/** Type of int_st_timers register
|
||||
* Masked interrupt status
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** t0_int_st : RO; bitpos: [0]; default: 0;
|
||||
* The masked interrupt status bit for the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
uint32_t t0_int_st: 1;
|
||||
/** wdt_int_st : RO; bitpos: [1]; default: 0;
|
||||
* The masked interrupt status bit for the TIMG_WDT_INT interrupt.
|
||||
*/
|
||||
uint32_t wdt_int_st: 1;
|
||||
uint32_t reserved_2: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_int_st_timers_reg_t;
|
||||
|
||||
/** Type of int_clr_timers register
|
||||
* Interrupt clear bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** t0_int_clr : WT; bitpos: [0]; default: 0;
|
||||
* Set this bit to clear the TIMG_T$x_INT interrupt.
|
||||
*/
|
||||
uint32_t t0_int_clr: 1;
|
||||
/** wdt_int_clr : WT; bitpos: [1]; default: 0;
|
||||
* Set this bit to clear the TIMG_WDT_INT interrupt.
|
||||
*/
|
||||
uint32_t wdt_int_clr: 1;
|
||||
uint32_t reserved_2: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_int_clr_timers_reg_t;
|
||||
|
||||
|
||||
/** Group: Version register */
|
||||
/** Type of ntimers_date register
|
||||
* Timer version control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** ntimgs_date : R/W; bitpos: [27:0]; default: 33579409;
|
||||
* Timer version control register
|
||||
*/
|
||||
uint32_t ntimgs_date: 28;
|
||||
uint32_t reserved_28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_ntimers_date_reg_t;
|
||||
|
||||
|
||||
/** Group: Clock configuration registers */
|
||||
/** Type of regclk register
|
||||
* Timer group clock gate register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0: 29;
|
||||
/** wdt_clk_is_active : R/W; bitpos: [29]; default: 1;
|
||||
* enable WDT's clock
|
||||
*/
|
||||
uint32_t wdt_clk_is_active: 1;
|
||||
/** timer_clk_is_active : R/W; bitpos: [30]; default: 1;
|
||||
* enable Timer $x's clock
|
||||
*/
|
||||
uint32_t timer_clk_is_active: 1;
|
||||
/** clk_en : R/W; bitpos: [31]; default: 0;
|
||||
* Register clock gate signal. 1: Registers can be read and written to by software. 0:
|
||||
* Registers can not be read or written to by software.
|
||||
*/
|
||||
uint32_t clk_en: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_regclk_reg_t;
|
||||
|
||||
typedef struct {
|
||||
volatile timg_txconfig_reg_t config;
|
||||
volatile timg_txlo_reg_t lo;
|
||||
volatile timg_txhi_reg_t hi;
|
||||
volatile timg_txupdate_reg_t update;
|
||||
volatile timg_txalarmlo_reg_t alarmlo;
|
||||
volatile timg_txalarmhi_reg_t alarmhi;
|
||||
volatile timg_txloadlo_reg_t loadlo;
|
||||
volatile timg_txloadhi_reg_t loadhi;
|
||||
volatile timg_txload_reg_t load;
|
||||
} timg_hwtimer_reg_t;
|
||||
|
||||
typedef struct timg_dev_t {
|
||||
volatile timg_hwtimer_reg_t hw_timer[1];
|
||||
uint32_t reserved_024[9];
|
||||
volatile timg_wdtconfig0_reg_t wdtconfig0;
|
||||
volatile timg_wdtconfig1_reg_t wdtconfig1;
|
||||
volatile timg_wdtconfig2_reg_t wdtconfig2;
|
||||
volatile timg_wdtconfig3_reg_t wdtconfig3;
|
||||
volatile timg_wdtconfig4_reg_t wdtconfig4;
|
||||
volatile timg_wdtconfig5_reg_t wdtconfig5;
|
||||
volatile timg_wdtfeed_reg_t wdtfeed;
|
||||
volatile timg_wdtwprotect_reg_t wdtwprotect;
|
||||
volatile timg_rtccalicfg_reg_t rtccalicfg;
|
||||
volatile timg_rtccalicfg1_reg_t rtccalicfg1;
|
||||
volatile timg_int_ena_timers_reg_t int_ena_timers;
|
||||
volatile timg_int_raw_timers_reg_t int_raw_timers;
|
||||
volatile timg_int_st_timers_reg_t int_st_timers;
|
||||
volatile timg_int_clr_timers_reg_t int_clr_timers;
|
||||
volatile timg_rtccalicfg2_reg_t rtccalicfg2;
|
||||
uint32_t reserved_084[29];
|
||||
volatile timg_ntimers_date_reg_t ntimers_date;
|
||||
volatile timg_regclk_reg_t regclk;
|
||||
} timg_dev_t;
|
||||
|
||||
extern timg_dev_t TIMERG0;
|
||||
extern timg_dev_t TIMERG1;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(timg_dev_t) == 0x100, "Invalid size of timg_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,209 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/* ---------------------------- Register Layout ------------------------------ */
|
||||
|
||||
/* The TWAI peripheral's registers are 8bits, however the ESP32-C3 can only access
|
||||
* peripheral registers every 32bits. Therefore each TWAI register is mapped to
|
||||
* the least significant byte of every 32bits.
|
||||
*/
|
||||
|
||||
typedef volatile struct twai_dev_s {
|
||||
//Configuration and Control Registers
|
||||
union {
|
||||
struct {
|
||||
uint32_t rm: 1; /* MOD.0 Reset Mode */
|
||||
uint32_t lom: 1; /* MOD.1 Listen Only Mode */
|
||||
uint32_t stm: 1; /* MOD.2 Self Test Mode */
|
||||
uint32_t afm: 1; /* MOD.3 Acceptance Filter Mode */
|
||||
uint32_t reserved4: 28; /* Internal Reserved. MOD.4 Sleep Mode not supported */
|
||||
};
|
||||
uint32_t val;
|
||||
} mode_reg; /* Address 0x0000 */
|
||||
union {
|
||||
struct {
|
||||
uint32_t tr: 1; /* CMR.0 Transmission Request */
|
||||
uint32_t at: 1; /* CMR.1 Abort Transmission */
|
||||
uint32_t rrb: 1; /* CMR.2 Release Receive Buffer */
|
||||
uint32_t cdo: 1; /* CMR.3 Clear Data Overrun */
|
||||
uint32_t srr: 1; /* CMR.4 Self Reception Request */
|
||||
uint32_t reserved5: 27; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} command_reg; /* Address 0x0004 */
|
||||
union {
|
||||
struct {
|
||||
uint32_t rbs: 1; /* SR.0 Receive Buffer Status */
|
||||
uint32_t dos: 1; /* SR.1 Data Overrun Status */
|
||||
uint32_t tbs: 1; /* SR.2 Transmit Buffer Status */
|
||||
uint32_t tcs: 1; /* SR.3 Transmission Complete Status */
|
||||
uint32_t rs: 1; /* SR.4 Receive Status */
|
||||
uint32_t ts: 1; /* SR.5 Transmit Status */
|
||||
uint32_t es: 1; /* SR.6 Error Status */
|
||||
uint32_t bs: 1; /* SR.7 Bus Status */
|
||||
uint32_t ms: 1; /* SR.8 Miss Status */
|
||||
uint32_t reserved9: 23; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} status_reg; /* Address 0x0008 */
|
||||
union {
|
||||
struct {
|
||||
uint32_t ri: 1; /* IR.0 Receive Interrupt */
|
||||
uint32_t ti: 1; /* IR.1 Transmit Interrupt */
|
||||
uint32_t ei: 1; /* IR.2 Error Interrupt */
|
||||
uint32_t doi: 1; /* IR.3 Data Overrun Interrupt */
|
||||
uint32_t reserved4: 1; /* Internal Reserved (Wake-up not supported) */
|
||||
uint32_t epi: 1; /* IR.5 Error Passive Interrupt */
|
||||
uint32_t ali: 1; /* IR.6 Arbitration Lost Interrupt */
|
||||
uint32_t bei: 1; /* IR.7 Bus Error Interrupt */
|
||||
uint32_t reserved8: 24; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} interrupt_reg; /* Address 0x000C */
|
||||
union {
|
||||
struct {
|
||||
uint32_t rie: 1; /* IER.0 Receive Interrupt Enable */
|
||||
uint32_t tie: 1; /* IER.1 Transmit Interrupt Enable */
|
||||
uint32_t eie: 1; /* IER.2 Error Interrupt Enable */
|
||||
uint32_t doie: 1; /* IER.3 Data Overrun Interrupt Enable */
|
||||
uint32_t reserved4: 1; /* Internal Reserved (Wake-up not supported) */
|
||||
uint32_t epie: 1; /* IER.5 Error Passive Interrupt Enable */
|
||||
uint32_t alie: 1; /* IER.6 Arbitration Lost Interrupt Enable */
|
||||
uint32_t beie: 1; /* IER.7 Bus Error Interrupt Enable */
|
||||
uint32_t reserved8: 24; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} interrupt_enable_reg; /* Address 0x0010 */
|
||||
uint32_t reserved_14;
|
||||
union {
|
||||
struct {
|
||||
uint32_t brp: 13; /* BTR0[12:0] Baud Rate Prescaler */
|
||||
uint32_t reserved13: 1; /* Internal Reserved */
|
||||
uint32_t sjw: 2; /* BTR0[15:14] Synchronization Jump Width*/
|
||||
uint32_t reserved16: 16; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} bus_timing_0_reg; /* Address 0x0018 */
|
||||
union {
|
||||
struct {
|
||||
uint32_t tseg1: 4; /* BTR1[3:0] Timing Segment 1 */
|
||||
uint32_t tseg2: 3; /* BTR1[6:4] Timing Segment 2 */
|
||||
uint32_t sam: 1; /* BTR1.7 Sampling*/
|
||||
uint32_t reserved8: 24; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} bus_timing_1_reg; /* Address 0x001C */
|
||||
uint32_t reserved_20; /* Address 0x0020 (Output control not supported) */
|
||||
uint32_t reserved_24; /* Address 0x0024 (Test Register not supported) */
|
||||
uint32_t reserved_28; /* Address 0x0028 */
|
||||
|
||||
//Capture and Counter Registers
|
||||
union {
|
||||
struct {
|
||||
uint32_t alc: 5; /* ALC[4:0] Arbitration lost capture */
|
||||
uint32_t reserved5: 27; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} arbitration_lost_captue_reg; /* Address 0x002C */
|
||||
union {
|
||||
struct {
|
||||
uint32_t seg: 5; /* ECC[4:0] Error Code Segment 0 to 5 */
|
||||
uint32_t dir: 1; /* ECC.5 Error Direction (TX/RX) */
|
||||
uint32_t errc: 2; /* ECC[7:6] Error Code */
|
||||
uint32_t reserved8: 24; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} error_code_capture_reg; /* Address 0x0030 */
|
||||
union {
|
||||
struct {
|
||||
uint32_t ewl: 8; /* EWL[7:0] Error Warning Limit */
|
||||
uint32_t reserved8: 24; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} error_warning_limit_reg; /* Address 0x0034 */
|
||||
union {
|
||||
struct {
|
||||
uint32_t rxerr: 8; /* RXERR[7:0] Receive Error Counter */
|
||||
uint32_t reserved8: 24; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} rx_error_counter_reg; /* Address 0x0038 */
|
||||
union {
|
||||
struct {
|
||||
uint32_t txerr: 8; /* TXERR[7:0] Receive Error Counter */
|
||||
uint32_t reserved8: 24; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} tx_error_counter_reg; /* Address 0x003C */
|
||||
|
||||
//Shared Registers (TX Buff/RX Buff/Acc Filter)
|
||||
union {
|
||||
struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t byte: 8; /* ACRx[7:0] Acceptance Code */
|
||||
uint32_t reserved8: 24; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} acr[4];
|
||||
union {
|
||||
struct {
|
||||
uint32_t byte: 8; /* AMRx[7:0] Acceptance Mask */
|
||||
uint32_t reserved8: 24; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} amr[4];
|
||||
uint32_t reserved_60;
|
||||
uint32_t reserved_64;
|
||||
uint32_t reserved_68;
|
||||
uint32_t reserved_6c;
|
||||
uint32_t reserved_70;
|
||||
} acceptance_filter;
|
||||
union {
|
||||
struct {
|
||||
uint32_t byte: 8; /* TX/RX Byte X [7:0] */
|
||||
uint32_t reserved24: 24; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} tx_rx_buffer[13];
|
||||
}; /* Address 0x0040 - 0x0070 */
|
||||
|
||||
//Misc Registers
|
||||
union {
|
||||
struct {
|
||||
uint32_t rmc: 7; /* RMC[6:0] RX Message Counter */
|
||||
uint32_t reserved7: 25; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} rx_message_counter_reg; /* Address 0x0074 */
|
||||
uint32_t reserved_78; /* Address 0x0078 (RX Buffer Start Address not supported) */
|
||||
union {
|
||||
struct {
|
||||
uint32_t cd: 8; /* CDR[7:0] CLKOUT frequency selector based of fOSC */
|
||||
uint32_t co: 1; /* CDR.8 CLKOUT enable/disable */
|
||||
uint32_t reserved9: 23; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} clock_divider_reg; /* Address 0x007C */
|
||||
} twai_dev_t;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(twai_dev_t) == 128, "TWAI registers should be 32 * 4 bytes");
|
||||
#endif
|
||||
|
||||
extern twai_dev_t TWAI;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,397 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct uart_dev_s {
|
||||
union {
|
||||
struct {
|
||||
uint32_t rw_byte; /*a*/
|
||||
};
|
||||
uint32_t val;
|
||||
} ahb_fifo;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rxfifo_full: 1; /*This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies.*/
|
||||
uint32_t txfifo_empty: 1; /*This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies .*/
|
||||
uint32_t parity_err: 1; /*This interrupt raw bit turns to high level when receiver detects a parity error in the data.*/
|
||||
uint32_t frm_err: 1; /*This interrupt raw bit turns to high level when receiver detects a data frame error .*/
|
||||
uint32_t rxfifo_ovf: 1; /*This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store.*/
|
||||
uint32_t dsr_chg: 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal.*/
|
||||
uint32_t cts_chg: 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal.*/
|
||||
uint32_t brk_det: 1; /*This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit.*/
|
||||
uint32_t rxfifo_tout: 1; /*This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.*/
|
||||
uint32_t sw_xon: 1; /*This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1.*/
|
||||
uint32_t sw_xoff: 1; /*This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1.*/
|
||||
uint32_t glitch_det: 1; /*This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit.*/
|
||||
uint32_t tx_brk_done: 1; /*This interrupt raw bit turns to high level when transmitter completes sending NULL characters after all data in Tx-FIFO are sent.*/
|
||||
uint32_t tx_brk_idle_done: 1; /*This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data.*/
|
||||
uint32_t tx_done: 1; /*This interrupt raw bit turns to high level when transmitter has send out all data in FIFO.*/
|
||||
uint32_t rs485_parity_err: 1; /*This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode.*/
|
||||
uint32_t rs485_frm_err: 1; /*This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode.*/
|
||||
uint32_t rs485_clash: 1; /*This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode.*/
|
||||
uint32_t at_cmd_char_det: 1; /*This interrupt raw bit turns to high level when receiver detects the configured at_cmd char.*/
|
||||
uint32_t wakeup: 1; /*This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode.*/
|
||||
uint32_t reserved20: 12; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rxfifo_full: 1; /*This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.*/
|
||||
uint32_t txfifo_empty: 1; /*This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1.*/
|
||||
uint32_t parity_err: 1; /*This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.*/
|
||||
uint32_t frm_err: 1; /*This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.*/
|
||||
uint32_t rxfifo_ovf: 1; /*This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.*/
|
||||
uint32_t dsr_chg: 1; /*This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/
|
||||
uint32_t cts_chg: 1; /*This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/
|
||||
uint32_t brk_det: 1; /*This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/
|
||||
uint32_t rxfifo_tout: 1; /*This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.*/
|
||||
uint32_t sw_xon: 1; /*This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/
|
||||
uint32_t sw_xoff: 1; /*This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/
|
||||
uint32_t glitch_det: 1; /*This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.*/
|
||||
uint32_t tx_brk_done: 1; /*This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.*/
|
||||
uint32_t tx_brk_idle_done: 1; /*This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.*/
|
||||
uint32_t tx_done: 1; /*This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/
|
||||
uint32_t rs485_parity_err: 1; /*This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.*/
|
||||
uint32_t rs485_frm_err: 1; /*This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1.*/
|
||||
uint32_t rs485_clash: 1; /*This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.*/
|
||||
uint32_t at_cmd_char_det: 1; /*This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.*/
|
||||
uint32_t wakeup: 1; /*This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.*/
|
||||
uint32_t reserved20: 12; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rxfifo_full: 1; /*This is the enable bit for rxfifo_full_int_st register.*/
|
||||
uint32_t txfifo_empty: 1; /*This is the enable bit for txfifo_empty_int_st register.*/
|
||||
uint32_t parity_err: 1; /*This is the enable bit for parity_err_int_st register.*/
|
||||
uint32_t frm_err: 1; /*This is the enable bit for frm_err_int_st register.*/
|
||||
uint32_t rxfifo_ovf: 1; /*This is the enable bit for rxfifo_ovf_int_st register.*/
|
||||
uint32_t dsr_chg: 1; /*This is the enable bit for dsr_chg_int_st register.*/
|
||||
uint32_t cts_chg: 1; /*This is the enable bit for cts_chg_int_st register.*/
|
||||
uint32_t brk_det: 1; /*This is the enable bit for brk_det_int_st register.*/
|
||||
uint32_t rxfifo_tout: 1; /*This is the enable bit for rxfifo_tout_int_st register.*/
|
||||
uint32_t sw_xon: 1; /*This is the enable bit for sw_xon_int_st register.*/
|
||||
uint32_t sw_xoff: 1; /*This is the enable bit for sw_xoff_int_st register.*/
|
||||
uint32_t glitch_det: 1; /*This is the enable bit for glitch_det_int_st register.*/
|
||||
uint32_t tx_brk_done: 1; /*This is the enable bit for tx_brk_done_int_st register.*/
|
||||
uint32_t tx_brk_idle_done: 1; /*This is the enable bit for tx_brk_idle_done_int_st register.*/
|
||||
uint32_t tx_done: 1; /*This is the enable bit for tx_done_int_st register.*/
|
||||
uint32_t rs485_parity_err: 1; /*This is the enable bit for rs485_parity_err_int_st register.*/
|
||||
uint32_t rs485_frm_err: 1; /*This is the enable bit for rs485_parity_err_int_st register.*/
|
||||
uint32_t rs485_clash: 1; /*This is the enable bit for rs485_clash_int_st register.*/
|
||||
uint32_t at_cmd_char_det: 1; /*This is the enable bit for at_cmd_char_det_int_st register.*/
|
||||
uint32_t wakeup: 1; /*This is the enable bit for uart_wakeup_int_st register.*/
|
||||
uint32_t reserved20: 12; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rxfifo_full: 1; /*Set this bit to clear the rxfifo_full_int_raw interrupt.*/
|
||||
uint32_t txfifo_empty: 1; /*Set this bit to clear txfifo_empty_int_raw interrupt.*/
|
||||
uint32_t parity_err: 1; /*Set this bit to clear parity_err_int_raw interrupt.*/
|
||||
uint32_t frm_err: 1; /*Set this bit to clear frm_err_int_raw interrupt.*/
|
||||
uint32_t rxfifo_ovf: 1; /*Set this bit to clear rxfifo_ovf_int_raw interrupt.*/
|
||||
uint32_t dsr_chg: 1; /*Set this bit to clear the dsr_chg_int_raw interrupt.*/
|
||||
uint32_t cts_chg: 1; /*Set this bit to clear the cts_chg_int_raw interrupt.*/
|
||||
uint32_t brk_det: 1; /*Set this bit to clear the brk_det_int_raw interrupt.*/
|
||||
uint32_t rxfifo_tout: 1; /*Set this bit to clear the rxfifo_tout_int_raw interrupt.*/
|
||||
uint32_t sw_xon: 1; /*Set this bit to clear the sw_xon_int_raw interrupt.*/
|
||||
uint32_t sw_xoff: 1; /*Set this bit to clear the sw_xoff_int_raw interrupt.*/
|
||||
uint32_t glitch_det: 1; /*Set this bit to clear the glitch_det_int_raw interrupt.*/
|
||||
uint32_t tx_brk_done: 1; /*Set this bit to clear the tx_brk_done_int_raw interrupt..*/
|
||||
uint32_t tx_brk_idle_done: 1; /*Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/
|
||||
uint32_t tx_done: 1; /*Set this bit to clear the tx_done_int_raw interrupt.*/
|
||||
uint32_t rs485_parity_err: 1; /*Set this bit to clear the rs485_parity_err_int_raw interrupt.*/
|
||||
uint32_t rs485_frm_err: 1; /*Set this bit to clear the rs485_frm_err_int_raw interrupt.*/
|
||||
uint32_t rs485_clash: 1; /*Set this bit to clear the rs485_clash_int_raw interrupt.*/
|
||||
uint32_t at_cmd_char_det: 1; /*Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/
|
||||
uint32_t wakeup: 1; /*Set this bit to clear the uart_wakeup_int_raw interrupt.*/
|
||||
uint32_t reserved20: 12; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t div_int: 12; /*The integral part of the frequency divider factor.*/
|
||||
uint32_t reserved12: 8;
|
||||
uint32_t div_frag: 4; /*The decimal part of the frequency divider factor.*/
|
||||
uint32_t reserved24: 8; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} clk_div;
|
||||
union {
|
||||
struct {
|
||||
uint32_t glitch_filt: 8; /*when input pulse width is lower than this value the pulse is ignored.*/
|
||||
uint32_t glitch_filt_en: 1; /*Set this bit to enable Rx signal filter.*/
|
||||
uint32_t reserved9: 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} rx_filt;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rxfifo_cnt:10; /*Stores the byte number of valid data in Rx-FIFO.*/
|
||||
uint32_t reserved10: 3;
|
||||
uint32_t dsrn: 1; /*The register represent the level value of the internal uart dsr signal.*/
|
||||
uint32_t ctsn: 1; /*This register represent the level value of the internal uart cts signal.*/
|
||||
uint32_t rxd: 1; /*This register represent the level value of the internal uart rxd signal.*/
|
||||
uint32_t txfifo_cnt:10; /*Stores the byte number of data in Tx-FIFO.*/
|
||||
uint32_t reserved26: 3; /*Reserved*/
|
||||
uint32_t dtrn: 1; /*This bit represents the level of the internal uart dtr signal.*/
|
||||
uint32_t rtsn: 1; /*This bit represents the level of the internal uart rts signal.*/
|
||||
uint32_t txd: 1; /*This bit represents the level of the internal uart txd signal.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} status;
|
||||
union {
|
||||
struct {
|
||||
uint32_t parity: 1; /*This register is used to configure the parity check mode.*/
|
||||
uint32_t parity_en: 1; /*Set this bit to enable uart parity check.*/
|
||||
uint32_t bit_num: 2; /*This register is used to set the length of data.*/
|
||||
uint32_t stop_bit_num: 2; /*This register is used to set the length of stop bit.*/
|
||||
uint32_t sw_rts: 1; /*This register is used to configure the software rts signal which is used in software flow control.*/
|
||||
uint32_t sw_dtr: 1; /*This register is used to configure the software dtr signal which is used in software flow control.*/
|
||||
uint32_t txd_brk: 1; /*Set this bit to enbale transmitter to send NULL when the process of sending data is done.*/
|
||||
uint32_t irda_dplx: 1; /*Set this bit to enable IrDA loopback mode.*/
|
||||
uint32_t irda_tx_en: 1; /*This is the start enable bit for IrDA transmitter.*/
|
||||
uint32_t irda_wctl: 1; /*1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0.*/
|
||||
uint32_t irda_tx_inv: 1; /*Set this bit to invert the level of IrDA transmitter.*/
|
||||
uint32_t irda_rx_inv: 1; /*Set this bit to invert the level of IrDA receiver.*/
|
||||
uint32_t loopback: 1; /*Set this bit to enable uart loopback test mode.*/
|
||||
uint32_t tx_flow_en: 1; /*Set this bit to enable flow control function for transmitter.*/
|
||||
uint32_t irda_en: 1; /*Set this bit to enable IrDA protocol.*/
|
||||
uint32_t rxfifo_rst: 1; /*Set this bit to reset the uart receive-FIFO.*/
|
||||
uint32_t txfifo_rst: 1; /*Set this bit to reset the uart transmit-FIFO.*/
|
||||
uint32_t rxd_inv: 1; /*Set this bit to inverse the level value of uart rxd signal.*/
|
||||
uint32_t cts_inv: 1; /*Set this bit to inverse the level value of uart cts signal.*/
|
||||
uint32_t dsr_inv: 1; /*Set this bit to inverse the level value of uart dsr signal.*/
|
||||
uint32_t txd_inv: 1; /*Set this bit to inverse the level value of uart txd signal.*/
|
||||
uint32_t rts_inv: 1; /*Set this bit to inverse the level value of uart rts signal.*/
|
||||
uint32_t dtr_inv: 1; /*Set this bit to inverse the level value of uart dtr signal.*/
|
||||
uint32_t clk_en: 1; /*1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.*/
|
||||
uint32_t err_wr_mask: 1; /*1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong.*/
|
||||
uint32_t autobaud_en: 1; /*This is the enable bit for detecting baudrate.*/
|
||||
uint32_t mem_clk_en: 1; /*UART memory clock gate enable signal.*/
|
||||
uint32_t reserved29: 3;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rxfifo_full_thrhd: 9; /*It will produce rxfifo_full_int interrupt when receiver receives more data than this register value.*/
|
||||
uint32_t txfifo_empty_thrhd: 9; /*It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value.*/
|
||||
uint32_t dis_rx_dat_ovf: 1; /*Disable UART Rx data overflow detect.*/
|
||||
uint32_t rx_tout_flow_dis: 1; /*Set this bit to stop accumulating idle_cnt when hardware flow control works.*/
|
||||
uint32_t rx_flow_en: 1; /*This is the flow enable bit for UART receiver.*/
|
||||
uint32_t rx_tout_en: 1; /*This is the enble bit for uart receiver's timeout function.*/
|
||||
uint32_t reserved22: 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t min_cnt: 12; /*This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process.*/
|
||||
uint32_t reserved12: 20; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} lowpulse;
|
||||
union {
|
||||
struct {
|
||||
uint32_t min_cnt: 12; /*This register stores the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process.*/
|
||||
uint32_t reserved12: 20; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} highpulse;
|
||||
union {
|
||||
struct {
|
||||
uint32_t edge_cnt: 10; /*This register stores the count of rxd edge change. It is used in baud rate-detect process.*/
|
||||
uint32_t reserved10: 22; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} rxd_cnt;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sw_flow_con_en: 1; /*Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff.*/
|
||||
uint32_t xonoff_del: 1; /*Set this bit to remove flow control char from the received data.*/
|
||||
uint32_t force_xon: 1; /*Set this bit to enable the transmitter to go on sending data.*/
|
||||
uint32_t force_xoff: 1; /*Set this bit to stop the transmitter from sending data.*/
|
||||
uint32_t send_xon: 1; /*Set this bit to send Xon char. It is cleared by hardware automatically.*/
|
||||
uint32_t send_xoff: 1; /*Set this bit to send Xoff char. It is cleared by hardware automatically.*/
|
||||
uint32_t reserved6: 26; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} flow_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t active_threshold:10; /*The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value.*/
|
||||
uint32_t reserved10: 22; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} sleep_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t xoff_threshold: 9; /*When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1 it will send a Xoff char.*/
|
||||
uint32_t xoff_char: 8; /*This register stores the Xoff flow control char.*/
|
||||
uint32_t reserved17: 15; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} swfc_conf0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t xon_threshold: 9; /*When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1 it will send a Xon char.*/
|
||||
uint32_t xon_char: 8; /*This register stores the Xon flow control char.*/
|
||||
uint32_t reserved17: 15; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} swfc_conf1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tx_brk_num: 8; /*This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1.*/
|
||||
uint32_t reserved8: 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} txbrk_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_idle_thrhd:10; /*It will produce frame end signal when receiver takes more time to receive one byte data than this register value.*/
|
||||
uint32_t tx_idle_num: 10; /*This register is used to configure the duration time between transfers.*/
|
||||
uint32_t reserved20: 12; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} idle_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t en: 1; /*Set this bit to choose the rs485 mode.*/
|
||||
uint32_t dl0_en: 1; /*Set this bit to delay the stop bit by 1 bit.*/
|
||||
uint32_t dl1_en: 1; /*Set this bit to delay the stop bit by 1 bit.*/
|
||||
uint32_t tx_rx_en: 1; /*Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode.*/
|
||||
uint32_t rx_busy_tx_en: 1; /*1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.*/
|
||||
uint32_t rx_dly_num: 1; /*This register is used to delay the receiver's internal data signal.*/
|
||||
uint32_t tx_dly_num: 4; /*This register is used to delay the transmitter's internal data signal.*/
|
||||
uint32_t reserved10: 22; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} rs485_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t pre_idle_num:16; /*This register is used to configure the idle duration time before the first at_cmd is received by receiver.*/
|
||||
uint32_t reserved16: 16; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} at_cmd_precnt;
|
||||
union {
|
||||
struct {
|
||||
uint32_t post_idle_num:16; /*This register is used to configure the duration time between the last at_cmd and the next data.*/
|
||||
uint32_t reserved16: 16; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} at_cmd_postcnt;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_gap_tout:16; /*This register is used to configure the duration time between the at_cmd chars.*/
|
||||
uint32_t reserved16: 16; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} at_cmd_gaptout;
|
||||
union {
|
||||
struct {
|
||||
uint32_t data: 8; /*This register is used to configure the content of at_cmd char.*/
|
||||
uint32_t char_num: 8; /*This register is used to configure the num of continuous at_cmd chars received by receiver.*/
|
||||
uint32_t reserved16: 16; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} at_cmd_char;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 1;
|
||||
uint32_t rx_size: 3; /*This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes.*/
|
||||
uint32_t tx_size: 3; /*This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes.*/
|
||||
uint32_t rx_flow_thrhd: 9; /*This register is used to configure the maximum amount of data that can be received when hardware flow control works.*/
|
||||
uint32_t rx_tout_thrhd:10; /*This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1.*/
|
||||
uint32_t force_pd: 1; /*Set this bit to force power down UART memory.*/
|
||||
uint32_t force_pu: 1; /*Set this bit to force power up UART memory.*/
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} mem_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t apb_tx_waddr:10; /*This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via APB.*/
|
||||
uint32_t reserved10: 1; /*Reserved*/
|
||||
uint32_t tx_raddr: 10; /*This register stores the offset address in Tx-FIFO when Tx-FSM reads data via Tx-FIFO_Ctrl.*/
|
||||
uint32_t reserved21: 11; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} mem_tx_status;
|
||||
union {
|
||||
struct {
|
||||
uint32_t apb_rx_raddr:10; /*This register stores the offset address in RX-FIFO when software reads data from Rx-FIFO via APB. UART0 is 10'h100. UART1 is 10'h180.*/
|
||||
uint32_t reserved10: 1; /*Reserved*/
|
||||
uint32_t rx_waddr: 10; /*This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes Rx-FIFO. UART0 is 10'h100. UART1 is 10'h180.*/
|
||||
uint32_t reserved21: 11; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} mem_rx_status;
|
||||
union {
|
||||
struct {
|
||||
uint32_t st_urx_out: 4; /*This is the status register of receiver.*/
|
||||
uint32_t st_utx_out: 4; /*This is the status register of transmitter.*/
|
||||
uint32_t reserved8: 24; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} fsm_status;
|
||||
union {
|
||||
struct {
|
||||
uint32_t min_cnt: 12; /*This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process.*/
|
||||
uint32_t reserved12: 20; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} pospulse;
|
||||
union {
|
||||
struct {
|
||||
uint32_t min_cnt: 12; /*This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process.*/
|
||||
uint32_t reserved12: 20; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} negpulse;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sclk_div_b: 6; /*The denominator of the frequency divider factor.*/
|
||||
uint32_t sclk_div_a: 6; /*The numerator of the frequency divider factor.*/
|
||||
uint32_t sclk_div_num: 8; /*The integral part of the frequency divider factor.*/
|
||||
uint32_t sclk_sel: 2; /*UART clock source select. 1: 80Mhz 2: 8Mhz 3: XTAL.*/
|
||||
uint32_t sclk_en: 1; /*Set this bit to enable UART Tx/Rx clock.*/
|
||||
uint32_t rst_core: 1; /*Write 1 then write 0 to this bit reset UART Tx/Rx.*/
|
||||
uint32_t tx_sclk_en: 1; /*Set this bit to enable UART Tx clock.*/
|
||||
uint32_t rx_sclk_en: 1; /*Set this bit to enable UART Rx clock.*/
|
||||
uint32_t tx_rst_core: 1; /*Write 1 then write 0 to this bit reset UART Tx.*/
|
||||
uint32_t rx_rst_core: 1; /*Write 1 then write 0 to this bit reset UART Rx.*/
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} clk_conf;
|
||||
uint32_t date; /*UART Version register*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t id : 30; /*This register is used to configure the uart_id.*/
|
||||
uint32_t high_speed : 1; /*This bit used to select synchronize mode. 1: Registers are auto synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize registers. */
|
||||
uint32_t update : 1; /*Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} id;
|
||||
} uart_dev_t;
|
||||
extern uart_dev_t UART0;
|
||||
extern uart_dev_t UART1;
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,748 +0,0 @@
|
||||
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_UHCI_REG_H_
|
||||
#define _SOC_UHCI_REG_H_
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#include "soc.h"
|
||||
#define UHCI_CONF0_REG(i) (REG_UHCI_BASE(i) + 0x0)
|
||||
/* UHCI_UART_RX_BRK_EOF_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
|
||||
/*description: If this bit is set to 1 UHCI will end payload receive process
|
||||
when NULL frame is received by UART.*/
|
||||
#define UHCI_UART_RX_BRK_EOF_EN (BIT(12))
|
||||
#define UHCI_UART_RX_BRK_EOF_EN_M (BIT(12))
|
||||
#define UHCI_UART_RX_BRK_EOF_EN_V 0x1
|
||||
#define UHCI_UART_RX_BRK_EOF_EN_S 12
|
||||
/* UHCI_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
|
||||
/*description: 1'b1: Force clock on for register. 1'b0: Support clock only when
|
||||
application writes registers.*/
|
||||
#define UHCI_CLK_EN (BIT(11))
|
||||
#define UHCI_CLK_EN_M (BIT(11))
|
||||
#define UHCI_CLK_EN_V 0x1
|
||||
#define UHCI_CLK_EN_S 11
|
||||
/* UHCI_ENCODE_CRC_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */
|
||||
/*description: Set this bit to enable data integrity checking by appending a
|
||||
16 bit CCITT-CRC to end of the payload.*/
|
||||
#define UHCI_ENCODE_CRC_EN (BIT(10))
|
||||
#define UHCI_ENCODE_CRC_EN_M (BIT(10))
|
||||
#define UHCI_ENCODE_CRC_EN_V 0x1
|
||||
#define UHCI_ENCODE_CRC_EN_S 10
|
||||
/* UHCI_LEN_EOF_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */
|
||||
/*description: If this bit is set to 1 UHCI decoder receiving payload data
|
||||
is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder receiving payload data is end when 0xc0 is received.*/
|
||||
#define UHCI_LEN_EOF_EN (BIT(9))
|
||||
#define UHCI_LEN_EOF_EN_M (BIT(9))
|
||||
#define UHCI_LEN_EOF_EN_V 0x1
|
||||
#define UHCI_LEN_EOF_EN_S 9
|
||||
/* UHCI_UART_IDLE_EOF_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: If this bit is set to 1 UHCI will end the payload receiving
|
||||
process when UART has been in idle state.*/
|
||||
#define UHCI_UART_IDLE_EOF_EN (BIT(8))
|
||||
#define UHCI_UART_IDLE_EOF_EN_M (BIT(8))
|
||||
#define UHCI_UART_IDLE_EOF_EN_V 0x1
|
||||
#define UHCI_UART_IDLE_EOF_EN_S 8
|
||||
/* UHCI_CRC_REC_EN : R/W ;bitpos:[7] ;default: 1'b1 ; */
|
||||
/*description: Set this bit to enable UHCI to receive the 16 bit CRC.*/
|
||||
#define UHCI_CRC_REC_EN (BIT(7))
|
||||
#define UHCI_CRC_REC_EN_M (BIT(7))
|
||||
#define UHCI_CRC_REC_EN_V 0x1
|
||||
#define UHCI_CRC_REC_EN_S 7
|
||||
/* UHCI_HEAD_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */
|
||||
/*description: Set this bit to encode the data packet with a formatting header.*/
|
||||
#define UHCI_HEAD_EN (BIT(6))
|
||||
#define UHCI_HEAD_EN_M (BIT(6))
|
||||
#define UHCI_HEAD_EN_V 0x1
|
||||
#define UHCI_HEAD_EN_S 6
|
||||
/* UHCI_SEPER_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */
|
||||
/*description: Set this bit to separate the data frame using a special char.*/
|
||||
#define UHCI_SEPER_EN (BIT(5))
|
||||
#define UHCI_SEPER_EN_M (BIT(5))
|
||||
#define UHCI_SEPER_EN_V 0x1
|
||||
#define UHCI_SEPER_EN_S 5
|
||||
/* UHCI_UART1_CE : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to link up HCI and UART1.*/
|
||||
#define UHCI_UART1_CE (BIT(3))
|
||||
#define UHCI_UART1_CE_M (BIT(3))
|
||||
#define UHCI_UART1_CE_V 0x1
|
||||
#define UHCI_UART1_CE_S 3
|
||||
/* UHCI_UART0_CE : R/W ;bitpos:[2] ;default: 1'h0 ; */
|
||||
/*description: Set this bit to link up HCI and UART0.*/
|
||||
#define UHCI_UART0_CE (BIT(2))
|
||||
#define UHCI_UART0_CE_M (BIT(2))
|
||||
#define UHCI_UART0_CE_V 0x1
|
||||
#define UHCI_UART0_CE_S 2
|
||||
/* UHCI_RX_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: Write 1 then write 0 to this bit to reset encode state machine.*/
|
||||
#define UHCI_RX_RST (BIT(1))
|
||||
#define UHCI_RX_RST_M (BIT(1))
|
||||
#define UHCI_RX_RST_V 0x1
|
||||
#define UHCI_RX_RST_S 1
|
||||
/* UHCI_TX_RST : R/W ;bitpos:[0] ;default: 1'h0 ; */
|
||||
/*description: Write 1 then write 0 to this bit to reset decode state machine.*/
|
||||
#define UHCI_TX_RST (BIT(0))
|
||||
#define UHCI_TX_RST_M (BIT(0))
|
||||
#define UHCI_TX_RST_V 0x1
|
||||
#define UHCI_TX_RST_S 0
|
||||
|
||||
#define UHCI_INT_RAW_REG(i) (REG_UHCI_BASE(i) + 0x4)
|
||||
/* UHCI_APP_CTRL1_INT_RAW : R/W ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: Soft control int raw bit.*/
|
||||
#define UHCI_APP_CTRL1_INT_RAW (BIT(8))
|
||||
#define UHCI_APP_CTRL1_INT_RAW_M (BIT(8))
|
||||
#define UHCI_APP_CTRL1_INT_RAW_V 0x1
|
||||
#define UHCI_APP_CTRL1_INT_RAW_S 8
|
||||
/* UHCI_APP_CTRL0_INT_RAW : R/W ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: Soft control int raw bit.*/
|
||||
#define UHCI_APP_CTRL0_INT_RAW (BIT(7))
|
||||
#define UHCI_APP_CTRL0_INT_RAW_M (BIT(7))
|
||||
#define UHCI_APP_CTRL0_INT_RAW_V 0x1
|
||||
#define UHCI_APP_CTRL0_INT_RAW_S 7
|
||||
/* UHCI_OUTLINK_EOF_ERR_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: This is the interrupt raw bit. Triggered when there are some
|
||||
errors in EOF in the*/
|
||||
#define UHCI_OUTLINK_EOF_ERR_INT_RAW (BIT(6))
|
||||
#define UHCI_OUTLINK_EOF_ERR_INT_RAW_M (BIT(6))
|
||||
#define UHCI_OUTLINK_EOF_ERR_INT_RAW_V 0x1
|
||||
#define UHCI_OUTLINK_EOF_ERR_INT_RAW_S 6
|
||||
/* UHCI_SEND_A_Q_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_SEND_A_Q_INT_RAW (BIT(5))
|
||||
#define UHCI_SEND_A_Q_INT_RAW_M (BIT(5))
|
||||
#define UHCI_SEND_A_Q_INT_RAW_V 0x1
|
||||
#define UHCI_SEND_A_Q_INT_RAW_S 5
|
||||
/* UHCI_SEND_S_Q_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_SEND_S_Q_INT_RAW (BIT(4))
|
||||
#define UHCI_SEND_S_Q_INT_RAW_M (BIT(4))
|
||||
#define UHCI_SEND_S_Q_INT_RAW_V 0x1
|
||||
#define UHCI_SEND_S_Q_INT_RAW_S 4
|
||||
/* UHCI_TX_HUNG_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_TX_HUNG_INT_RAW (BIT(3))
|
||||
#define UHCI_TX_HUNG_INT_RAW_M (BIT(3))
|
||||
#define UHCI_TX_HUNG_INT_RAW_V 0x1
|
||||
#define UHCI_TX_HUNG_INT_RAW_S 3
|
||||
/* UHCI_RX_HUNG_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_RX_HUNG_INT_RAW (BIT(2))
|
||||
#define UHCI_RX_HUNG_INT_RAW_M (BIT(2))
|
||||
#define UHCI_RX_HUNG_INT_RAW_V 0x1
|
||||
#define UHCI_RX_HUNG_INT_RAW_S 2
|
||||
/* UHCI_TX_START_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_TX_START_INT_RAW (BIT(1))
|
||||
#define UHCI_TX_START_INT_RAW_M (BIT(1))
|
||||
#define UHCI_TX_START_INT_RAW_V 0x1
|
||||
#define UHCI_TX_START_INT_RAW_S 1
|
||||
/* UHCI_RX_START_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_RX_START_INT_RAW (BIT(0))
|
||||
#define UHCI_RX_START_INT_RAW_M (BIT(0))
|
||||
#define UHCI_RX_START_INT_RAW_V 0x1
|
||||
#define UHCI_RX_START_INT_RAW_S 0
|
||||
|
||||
#define UHCI_INT_ST_REG(i) (REG_UHCI_BASE(i) + 0x8)
|
||||
/* UHCI_APP_CTRL1_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_APP_CTRL1_INT_ST (BIT(8))
|
||||
#define UHCI_APP_CTRL1_INT_ST_M (BIT(8))
|
||||
#define UHCI_APP_CTRL1_INT_ST_V 0x1
|
||||
#define UHCI_APP_CTRL1_INT_ST_S 8
|
||||
/* UHCI_APP_CTRL0_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_APP_CTRL0_INT_ST (BIT(7))
|
||||
#define UHCI_APP_CTRL0_INT_ST_M (BIT(7))
|
||||
#define UHCI_APP_CTRL0_INT_ST_V 0x1
|
||||
#define UHCI_APP_CTRL0_INT_ST_S 7
|
||||
/* UHCI_OUTLINK_EOF_ERR_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_OUTLINK_EOF_ERR_INT_ST (BIT(6))
|
||||
#define UHCI_OUTLINK_EOF_ERR_INT_ST_M (BIT(6))
|
||||
#define UHCI_OUTLINK_EOF_ERR_INT_ST_V 0x1
|
||||
#define UHCI_OUTLINK_EOF_ERR_INT_ST_S 6
|
||||
/* UHCI_SEND_A_Q_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_SEND_A_Q_INT_ST (BIT(5))
|
||||
#define UHCI_SEND_A_Q_INT_ST_M (BIT(5))
|
||||
#define UHCI_SEND_A_Q_INT_ST_V 0x1
|
||||
#define UHCI_SEND_A_Q_INT_ST_S 5
|
||||
/* UHCI_SEND_S_Q_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_SEND_S_Q_INT_ST (BIT(4))
|
||||
#define UHCI_SEND_S_Q_INT_ST_M (BIT(4))
|
||||
#define UHCI_SEND_S_Q_INT_ST_V 0x1
|
||||
#define UHCI_SEND_S_Q_INT_ST_S 4
|
||||
/* UHCI_TX_HUNG_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_TX_HUNG_INT_ST (BIT(3))
|
||||
#define UHCI_TX_HUNG_INT_ST_M (BIT(3))
|
||||
#define UHCI_TX_HUNG_INT_ST_V 0x1
|
||||
#define UHCI_TX_HUNG_INT_ST_S 3
|
||||
/* UHCI_RX_HUNG_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_RX_HUNG_INT_ST (BIT(2))
|
||||
#define UHCI_RX_HUNG_INT_ST_M (BIT(2))
|
||||
#define UHCI_RX_HUNG_INT_ST_V 0x1
|
||||
#define UHCI_RX_HUNG_INT_ST_S 2
|
||||
/* UHCI_TX_START_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_TX_START_INT_ST (BIT(1))
|
||||
#define UHCI_TX_START_INT_ST_M (BIT(1))
|
||||
#define UHCI_TX_START_INT_ST_V 0x1
|
||||
#define UHCI_TX_START_INT_ST_S 1
|
||||
/* UHCI_RX_START_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_RX_START_INT_ST (BIT(0))
|
||||
#define UHCI_RX_START_INT_ST_M (BIT(0))
|
||||
#define UHCI_RX_START_INT_ST_V 0x1
|
||||
#define UHCI_RX_START_INT_ST_S 0
|
||||
|
||||
#define UHCI_INT_ENA_REG(i) (REG_UHCI_BASE(i) + 0xC)
|
||||
/* UHCI_APP_CTRL1_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_APP_CTRL1_INT_ENA (BIT(8))
|
||||
#define UHCI_APP_CTRL1_INT_ENA_M (BIT(8))
|
||||
#define UHCI_APP_CTRL1_INT_ENA_V 0x1
|
||||
#define UHCI_APP_CTRL1_INT_ENA_S 8
|
||||
/* UHCI_APP_CTRL0_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_APP_CTRL0_INT_ENA (BIT(7))
|
||||
#define UHCI_APP_CTRL0_INT_ENA_M (BIT(7))
|
||||
#define UHCI_APP_CTRL0_INT_ENA_V 0x1
|
||||
#define UHCI_APP_CTRL0_INT_ENA_S 7
|
||||
/* UHCI_OUTLINK_EOF_ERR_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_OUTLINK_EOF_ERR_INT_ENA (BIT(6))
|
||||
#define UHCI_OUTLINK_EOF_ERR_INT_ENA_M (BIT(6))
|
||||
#define UHCI_OUTLINK_EOF_ERR_INT_ENA_V 0x1
|
||||
#define UHCI_OUTLINK_EOF_ERR_INT_ENA_S 6
|
||||
/* UHCI_SEND_A_Q_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_SEND_A_Q_INT_ENA (BIT(5))
|
||||
#define UHCI_SEND_A_Q_INT_ENA_M (BIT(5))
|
||||
#define UHCI_SEND_A_Q_INT_ENA_V 0x1
|
||||
#define UHCI_SEND_A_Q_INT_ENA_S 5
|
||||
/* UHCI_SEND_S_Q_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_SEND_S_Q_INT_ENA (BIT(4))
|
||||
#define UHCI_SEND_S_Q_INT_ENA_M (BIT(4))
|
||||
#define UHCI_SEND_S_Q_INT_ENA_V 0x1
|
||||
#define UHCI_SEND_S_Q_INT_ENA_S 4
|
||||
/* UHCI_TX_HUNG_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_TX_HUNG_INT_ENA (BIT(3))
|
||||
#define UHCI_TX_HUNG_INT_ENA_M (BIT(3))
|
||||
#define UHCI_TX_HUNG_INT_ENA_V 0x1
|
||||
#define UHCI_TX_HUNG_INT_ENA_S 3
|
||||
/* UHCI_RX_HUNG_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_RX_HUNG_INT_ENA (BIT(2))
|
||||
#define UHCI_RX_HUNG_INT_ENA_M (BIT(2))
|
||||
#define UHCI_RX_HUNG_INT_ENA_V 0x1
|
||||
#define UHCI_RX_HUNG_INT_ENA_S 2
|
||||
/* UHCI_TX_START_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_TX_START_INT_ENA (BIT(1))
|
||||
#define UHCI_TX_START_INT_ENA_M (BIT(1))
|
||||
#define UHCI_TX_START_INT_ENA_V 0x1
|
||||
#define UHCI_TX_START_INT_ENA_S 1
|
||||
/* UHCI_RX_START_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_RX_START_INT_ENA (BIT(0))
|
||||
#define UHCI_RX_START_INT_ENA_M (BIT(0))
|
||||
#define UHCI_RX_START_INT_ENA_V 0x1
|
||||
#define UHCI_RX_START_INT_ENA_S 0
|
||||
|
||||
#define UHCI_INT_CLR_REG(i) (REG_UHCI_BASE(i) + 0x10)
|
||||
/* UHCI_APP_CTRL1_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_APP_CTRL1_INT_CLR (BIT(8))
|
||||
#define UHCI_APP_CTRL1_INT_CLR_M (BIT(8))
|
||||
#define UHCI_APP_CTRL1_INT_CLR_V 0x1
|
||||
#define UHCI_APP_CTRL1_INT_CLR_S 8
|
||||
/* UHCI_APP_CTRL0_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_APP_CTRL0_INT_CLR (BIT(7))
|
||||
#define UHCI_APP_CTRL0_INT_CLR_M (BIT(7))
|
||||
#define UHCI_APP_CTRL0_INT_CLR_V 0x1
|
||||
#define UHCI_APP_CTRL0_INT_CLR_S 7
|
||||
/* UHCI_OUTLINK_EOF_ERR_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_OUTLINK_EOF_ERR_INT_CLR (BIT(6))
|
||||
#define UHCI_OUTLINK_EOF_ERR_INT_CLR_M (BIT(6))
|
||||
#define UHCI_OUTLINK_EOF_ERR_INT_CLR_V 0x1
|
||||
#define UHCI_OUTLINK_EOF_ERR_INT_CLR_S 6
|
||||
/* UHCI_SEND_A_Q_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_SEND_A_Q_INT_CLR (BIT(5))
|
||||
#define UHCI_SEND_A_Q_INT_CLR_M (BIT(5))
|
||||
#define UHCI_SEND_A_Q_INT_CLR_V 0x1
|
||||
#define UHCI_SEND_A_Q_INT_CLR_S 5
|
||||
/* UHCI_SEND_S_Q_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_SEND_S_Q_INT_CLR (BIT(4))
|
||||
#define UHCI_SEND_S_Q_INT_CLR_M (BIT(4))
|
||||
#define UHCI_SEND_S_Q_INT_CLR_V 0x1
|
||||
#define UHCI_SEND_S_Q_INT_CLR_S 4
|
||||
/* UHCI_TX_HUNG_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_TX_HUNG_INT_CLR (BIT(3))
|
||||
#define UHCI_TX_HUNG_INT_CLR_M (BIT(3))
|
||||
#define UHCI_TX_HUNG_INT_CLR_V 0x1
|
||||
#define UHCI_TX_HUNG_INT_CLR_S 3
|
||||
/* UHCI_RX_HUNG_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_RX_HUNG_INT_CLR (BIT(2))
|
||||
#define UHCI_RX_HUNG_INT_CLR_M (BIT(2))
|
||||
#define UHCI_RX_HUNG_INT_CLR_V 0x1
|
||||
#define UHCI_RX_HUNG_INT_CLR_S 2
|
||||
/* UHCI_TX_START_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_TX_START_INT_CLR (BIT(1))
|
||||
#define UHCI_TX_START_INT_CLR_M (BIT(1))
|
||||
#define UHCI_TX_START_INT_CLR_V 0x1
|
||||
#define UHCI_TX_START_INT_CLR_S 1
|
||||
/* UHCI_RX_START_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_RX_START_INT_CLR (BIT(0))
|
||||
#define UHCI_RX_START_INT_CLR_M (BIT(0))
|
||||
#define UHCI_RX_START_INT_CLR_V 0x1
|
||||
#define UHCI_RX_START_INT_CLR_S 0
|
||||
|
||||
#define UHCI_CONF1_REG(i) (REG_UHCI_BASE(i) + 0x14)
|
||||
/* UHCI_SW_START : R/W/SC ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_SW_START (BIT(8))
|
||||
#define UHCI_SW_START_M (BIT(8))
|
||||
#define UHCI_SW_START_V 0x1
|
||||
#define UHCI_SW_START_S 8
|
||||
/* UHCI_WAIT_SW_START : R/W ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_WAIT_SW_START (BIT(7))
|
||||
#define UHCI_WAIT_SW_START_M (BIT(7))
|
||||
#define UHCI_WAIT_SW_START_V 0x1
|
||||
#define UHCI_WAIT_SW_START_S 7
|
||||
/* UHCI_TX_ACK_NUM_RE : R/W ;bitpos:[5] ;default: 1'b1 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_TX_ACK_NUM_RE (BIT(5))
|
||||
#define UHCI_TX_ACK_NUM_RE_M (BIT(5))
|
||||
#define UHCI_TX_ACK_NUM_RE_V 0x1
|
||||
#define UHCI_TX_ACK_NUM_RE_S 5
|
||||
/* UHCI_TX_CHECK_SUM_RE : R/W ;bitpos:[4] ;default: 1'b1 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_TX_CHECK_SUM_RE (BIT(4))
|
||||
#define UHCI_TX_CHECK_SUM_RE_M (BIT(4))
|
||||
#define UHCI_TX_CHECK_SUM_RE_V 0x1
|
||||
#define UHCI_TX_CHECK_SUM_RE_S 4
|
||||
/* UHCI_SAVE_HEAD : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_SAVE_HEAD (BIT(3))
|
||||
#define UHCI_SAVE_HEAD_M (BIT(3))
|
||||
#define UHCI_SAVE_HEAD_V 0x1
|
||||
#define UHCI_SAVE_HEAD_S 3
|
||||
/* UHCI_CRC_DISABLE : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_CRC_DISABLE (BIT(2))
|
||||
#define UHCI_CRC_DISABLE_M (BIT(2))
|
||||
#define UHCI_CRC_DISABLE_V 0x1
|
||||
#define UHCI_CRC_DISABLE_S 2
|
||||
/* UHCI_CHECK_SEQ_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_CHECK_SEQ_EN (BIT(1))
|
||||
#define UHCI_CHECK_SEQ_EN_M (BIT(1))
|
||||
#define UHCI_CHECK_SEQ_EN_V 0x1
|
||||
#define UHCI_CHECK_SEQ_EN_S 1
|
||||
/* UHCI_CHECK_SUM_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_CHECK_SUM_EN (BIT(0))
|
||||
#define UHCI_CHECK_SUM_EN_M (BIT(0))
|
||||
#define UHCI_CHECK_SUM_EN_V 0x1
|
||||
#define UHCI_CHECK_SUM_EN_S 0
|
||||
|
||||
#define UHCI_STATE0_REG(i) (REG_UHCI_BASE(i) + 0x18)
|
||||
/* UHCI_DECODE_STATE : RO ;bitpos:[5:3] ;default: 3'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_DECODE_STATE 0x00000007
|
||||
#define UHCI_DECODE_STATE_M ((UHCI_DECODE_STATE_V)<<(UHCI_DECODE_STATE_S))
|
||||
#define UHCI_DECODE_STATE_V 0x7
|
||||
#define UHCI_DECODE_STATE_S 3
|
||||
/* UHCI_RX_ERR_CAUSE : RO ;bitpos:[2:0] ;default: 3'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_RX_ERR_CAUSE 0x00000007
|
||||
#define UHCI_RX_ERR_CAUSE_M ((UHCI_RX_ERR_CAUSE_V)<<(UHCI_RX_ERR_CAUSE_S))
|
||||
#define UHCI_RX_ERR_CAUSE_V 0x7
|
||||
#define UHCI_RX_ERR_CAUSE_S 0
|
||||
|
||||
#define UHCI_STATE1_REG(i) (REG_UHCI_BASE(i) + 0x1C)
|
||||
/* UHCI_ENCODE_STATE : RO ;bitpos:[2:0] ;default: 3'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_ENCODE_STATE 0x00000007
|
||||
#define UHCI_ENCODE_STATE_M ((UHCI_ENCODE_STATE_V)<<(UHCI_ENCODE_STATE_S))
|
||||
#define UHCI_ENCODE_STATE_V 0x7
|
||||
#define UHCI_ENCODE_STATE_S 0
|
||||
|
||||
#define UHCI_ESCAPE_CONF_REG(i) (REG_UHCI_BASE(i) + 0x20)
|
||||
/* UHCI_RX_13_ESC_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_RX_13_ESC_EN (BIT(7))
|
||||
#define UHCI_RX_13_ESC_EN_M (BIT(7))
|
||||
#define UHCI_RX_13_ESC_EN_V 0x1
|
||||
#define UHCI_RX_13_ESC_EN_S 7
|
||||
/* UHCI_RX_11_ESC_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_RX_11_ESC_EN (BIT(6))
|
||||
#define UHCI_RX_11_ESC_EN_M (BIT(6))
|
||||
#define UHCI_RX_11_ESC_EN_V 0x1
|
||||
#define UHCI_RX_11_ESC_EN_S 6
|
||||
/* UHCI_RX_DB_ESC_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_RX_DB_ESC_EN (BIT(5))
|
||||
#define UHCI_RX_DB_ESC_EN_M (BIT(5))
|
||||
#define UHCI_RX_DB_ESC_EN_V 0x1
|
||||
#define UHCI_RX_DB_ESC_EN_S 5
|
||||
/* UHCI_RX_C0_ESC_EN : R/W ;bitpos:[4] ;default: 1'b1 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_RX_C0_ESC_EN (BIT(4))
|
||||
#define UHCI_RX_C0_ESC_EN_M (BIT(4))
|
||||
#define UHCI_RX_C0_ESC_EN_V 0x1
|
||||
#define UHCI_RX_C0_ESC_EN_S 4
|
||||
/* UHCI_TX_13_ESC_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_TX_13_ESC_EN (BIT(3))
|
||||
#define UHCI_TX_13_ESC_EN_M (BIT(3))
|
||||
#define UHCI_TX_13_ESC_EN_V 0x1
|
||||
#define UHCI_TX_13_ESC_EN_S 3
|
||||
/* UHCI_TX_11_ESC_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_TX_11_ESC_EN (BIT(2))
|
||||
#define UHCI_TX_11_ESC_EN_M (BIT(2))
|
||||
#define UHCI_TX_11_ESC_EN_V 0x1
|
||||
#define UHCI_TX_11_ESC_EN_S 2
|
||||
/* UHCI_TX_DB_ESC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_TX_DB_ESC_EN (BIT(1))
|
||||
#define UHCI_TX_DB_ESC_EN_M (BIT(1))
|
||||
#define UHCI_TX_DB_ESC_EN_V 0x1
|
||||
#define UHCI_TX_DB_ESC_EN_S 1
|
||||
/* UHCI_TX_C0_ESC_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_TX_C0_ESC_EN (BIT(0))
|
||||
#define UHCI_TX_C0_ESC_EN_M (BIT(0))
|
||||
#define UHCI_TX_C0_ESC_EN_V 0x1
|
||||
#define UHCI_TX_C0_ESC_EN_S 0
|
||||
|
||||
#define UHCI_HUNG_CONF_REG(i) (REG_UHCI_BASE(i) + 0x24)
|
||||
/* UHCI_RXFIFO_TIMEOUT_ENA : R/W ;bitpos:[23] ;default: 1'b1 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_RXFIFO_TIMEOUT_ENA (BIT(23))
|
||||
#define UHCI_RXFIFO_TIMEOUT_ENA_M (BIT(23))
|
||||
#define UHCI_RXFIFO_TIMEOUT_ENA_V 0x1
|
||||
#define UHCI_RXFIFO_TIMEOUT_ENA_S 23
|
||||
/* UHCI_RXFIFO_TIMEOUT_SHIFT : R/W ;bitpos:[22:20] ;default: 3'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_RXFIFO_TIMEOUT_SHIFT 0x00000007
|
||||
#define UHCI_RXFIFO_TIMEOUT_SHIFT_M ((UHCI_RXFIFO_TIMEOUT_SHIFT_V)<<(UHCI_RXFIFO_TIMEOUT_SHIFT_S))
|
||||
#define UHCI_RXFIFO_TIMEOUT_SHIFT_V 0x7
|
||||
#define UHCI_RXFIFO_TIMEOUT_SHIFT_S 20
|
||||
/* UHCI_RXFIFO_TIMEOUT : R/W ;bitpos:[19:12] ;default: 8'h10 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_RXFIFO_TIMEOUT 0x000000FF
|
||||
#define UHCI_RXFIFO_TIMEOUT_M ((UHCI_RXFIFO_TIMEOUT_V)<<(UHCI_RXFIFO_TIMEOUT_S))
|
||||
#define UHCI_RXFIFO_TIMEOUT_V 0xFF
|
||||
#define UHCI_RXFIFO_TIMEOUT_S 12
|
||||
/* UHCI_TXFIFO_TIMEOUT_ENA : R/W ;bitpos:[11] ;default: 1'b1 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_TXFIFO_TIMEOUT_ENA (BIT(11))
|
||||
#define UHCI_TXFIFO_TIMEOUT_ENA_M (BIT(11))
|
||||
#define UHCI_TXFIFO_TIMEOUT_ENA_V 0x1
|
||||
#define UHCI_TXFIFO_TIMEOUT_ENA_S 11
|
||||
/* UHCI_TXFIFO_TIMEOUT_SHIFT : R/W ;bitpos:[10:8] ;default: 3'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_TXFIFO_TIMEOUT_SHIFT 0x00000007
|
||||
#define UHCI_TXFIFO_TIMEOUT_SHIFT_M ((UHCI_TXFIFO_TIMEOUT_SHIFT_V)<<(UHCI_TXFIFO_TIMEOUT_SHIFT_S))
|
||||
#define UHCI_TXFIFO_TIMEOUT_SHIFT_V 0x7
|
||||
#define UHCI_TXFIFO_TIMEOUT_SHIFT_S 8
|
||||
/* UHCI_TXFIFO_TIMEOUT : R/W ;bitpos:[7:0] ;default: 8'h10 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_TXFIFO_TIMEOUT 0x000000FF
|
||||
#define UHCI_TXFIFO_TIMEOUT_M ((UHCI_TXFIFO_TIMEOUT_V)<<(UHCI_TXFIFO_TIMEOUT_S))
|
||||
#define UHCI_TXFIFO_TIMEOUT_V 0xFF
|
||||
#define UHCI_TXFIFO_TIMEOUT_S 0
|
||||
|
||||
#define UHCI_ACK_NUM_REG(i) (REG_UHCI_BASE(i) + 0x28)
|
||||
/* UHCI_ACK_NUM_LOAD : WT ;bitpos:[3] ;default: 1'b1 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_ACK_NUM_LOAD (BIT(3))
|
||||
#define UHCI_ACK_NUM_LOAD_M (BIT(3))
|
||||
#define UHCI_ACK_NUM_LOAD_V 0x1
|
||||
#define UHCI_ACK_NUM_LOAD_S 3
|
||||
/* UHCI_ACK_NUM : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
|
||||
/*description: */
|
||||
#define UHCI_ACK_NUM 0x00000007
|
||||
#define UHCI_ACK_NUM_M ((UHCI_ACK_NUM_V)<<(UHCI_ACK_NUM_S))
|
||||
#define UHCI_ACK_NUM_V 0x7
|
||||
#define UHCI_ACK_NUM_S 0
|
||||
|
||||
#define UHCI_RX_HEAD_REG(i) (REG_UHCI_BASE(i) + 0x2C)
|
||||
/* UHCI_RX_HEAD : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_RX_HEAD 0xFFFFFFFF
|
||||
#define UHCI_RX_HEAD_M ((UHCI_RX_HEAD_V)<<(UHCI_RX_HEAD_S))
|
||||
#define UHCI_RX_HEAD_V 0xFFFFFFFF
|
||||
#define UHCI_RX_HEAD_S 0
|
||||
|
||||
#define UHCI_QUICK_SENT_REG(i) (REG_UHCI_BASE(i) + 0x30)
|
||||
/* UHCI_ALWAYS_SEND_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_ALWAYS_SEND_EN (BIT(7))
|
||||
#define UHCI_ALWAYS_SEND_EN_M (BIT(7))
|
||||
#define UHCI_ALWAYS_SEND_EN_V 0x1
|
||||
#define UHCI_ALWAYS_SEND_EN_S 7
|
||||
/* UHCI_ALWAYS_SEND_NUM : R/W ;bitpos:[6:4] ;default: 3'h0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_ALWAYS_SEND_NUM 0x00000007
|
||||
#define UHCI_ALWAYS_SEND_NUM_M ((UHCI_ALWAYS_SEND_NUM_V)<<(UHCI_ALWAYS_SEND_NUM_S))
|
||||
#define UHCI_ALWAYS_SEND_NUM_V 0x7
|
||||
#define UHCI_ALWAYS_SEND_NUM_S 4
|
||||
/* UHCI_SINGLE_SEND_EN : R/W/SC ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_SINGLE_SEND_EN (BIT(3))
|
||||
#define UHCI_SINGLE_SEND_EN_M (BIT(3))
|
||||
#define UHCI_SINGLE_SEND_EN_V 0x1
|
||||
#define UHCI_SINGLE_SEND_EN_S 3
|
||||
/* UHCI_SINGLE_SEND_NUM : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_SINGLE_SEND_NUM 0x00000007
|
||||
#define UHCI_SINGLE_SEND_NUM_M ((UHCI_SINGLE_SEND_NUM_V)<<(UHCI_SINGLE_SEND_NUM_S))
|
||||
#define UHCI_SINGLE_SEND_NUM_V 0x7
|
||||
#define UHCI_SINGLE_SEND_NUM_S 0
|
||||
|
||||
#define UHCI_Q0_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x34)
|
||||
/* UHCI_SEND_Q0_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_SEND_Q0_WORD0 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q0_WORD0_M ((UHCI_SEND_Q0_WORD0_V)<<(UHCI_SEND_Q0_WORD0_S))
|
||||
#define UHCI_SEND_Q0_WORD0_V 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q0_WORD0_S 0
|
||||
|
||||
#define UHCI_Q0_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x38)
|
||||
/* UHCI_SEND_Q0_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_SEND_Q0_WORD1 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q0_WORD1_M ((UHCI_SEND_Q0_WORD1_V)<<(UHCI_SEND_Q0_WORD1_S))
|
||||
#define UHCI_SEND_Q0_WORD1_V 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q0_WORD1_S 0
|
||||
|
||||
#define UHCI_Q1_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x3C)
|
||||
/* UHCI_SEND_Q1_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_SEND_Q1_WORD0 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q1_WORD0_M ((UHCI_SEND_Q1_WORD0_V)<<(UHCI_SEND_Q1_WORD0_S))
|
||||
#define UHCI_SEND_Q1_WORD0_V 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q1_WORD0_S 0
|
||||
|
||||
#define UHCI_Q1_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x40)
|
||||
/* UHCI_SEND_Q1_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_SEND_Q1_WORD1 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q1_WORD1_M ((UHCI_SEND_Q1_WORD1_V)<<(UHCI_SEND_Q1_WORD1_S))
|
||||
#define UHCI_SEND_Q1_WORD1_V 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q1_WORD1_S 0
|
||||
|
||||
#define UHCI_Q2_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x44)
|
||||
/* UHCI_SEND_Q2_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_SEND_Q2_WORD0 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q2_WORD0_M ((UHCI_SEND_Q2_WORD0_V)<<(UHCI_SEND_Q2_WORD0_S))
|
||||
#define UHCI_SEND_Q2_WORD0_V 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q2_WORD0_S 0
|
||||
|
||||
#define UHCI_Q2_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x48)
|
||||
/* UHCI_SEND_Q2_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_SEND_Q2_WORD1 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q2_WORD1_M ((UHCI_SEND_Q2_WORD1_V)<<(UHCI_SEND_Q2_WORD1_S))
|
||||
#define UHCI_SEND_Q2_WORD1_V 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q2_WORD1_S 0
|
||||
|
||||
#define UHCI_Q3_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x4C)
|
||||
/* UHCI_SEND_Q3_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_SEND_Q3_WORD0 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q3_WORD0_M ((UHCI_SEND_Q3_WORD0_V)<<(UHCI_SEND_Q3_WORD0_S))
|
||||
#define UHCI_SEND_Q3_WORD0_V 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q3_WORD0_S 0
|
||||
|
||||
#define UHCI_Q3_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x50)
|
||||
/* UHCI_SEND_Q3_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_SEND_Q3_WORD1 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q3_WORD1_M ((UHCI_SEND_Q3_WORD1_V)<<(UHCI_SEND_Q3_WORD1_S))
|
||||
#define UHCI_SEND_Q3_WORD1_V 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q3_WORD1_S 0
|
||||
|
||||
#define UHCI_Q4_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x54)
|
||||
/* UHCI_SEND_Q4_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_SEND_Q4_WORD0 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q4_WORD0_M ((UHCI_SEND_Q4_WORD0_V)<<(UHCI_SEND_Q4_WORD0_S))
|
||||
#define UHCI_SEND_Q4_WORD0_V 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q4_WORD0_S 0
|
||||
|
||||
#define UHCI_Q4_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x58)
|
||||
/* UHCI_SEND_Q4_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_SEND_Q4_WORD1 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q4_WORD1_M ((UHCI_SEND_Q4_WORD1_V)<<(UHCI_SEND_Q4_WORD1_S))
|
||||
#define UHCI_SEND_Q4_WORD1_V 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q4_WORD1_S 0
|
||||
|
||||
#define UHCI_Q5_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x5C)
|
||||
/* UHCI_SEND_Q5_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_SEND_Q5_WORD0 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q5_WORD0_M ((UHCI_SEND_Q5_WORD0_V)<<(UHCI_SEND_Q5_WORD0_S))
|
||||
#define UHCI_SEND_Q5_WORD0_V 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q5_WORD0_S 0
|
||||
|
||||
#define UHCI_Q5_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x60)
|
||||
/* UHCI_SEND_Q5_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_SEND_Q5_WORD1 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q5_WORD1_M ((UHCI_SEND_Q5_WORD1_V)<<(UHCI_SEND_Q5_WORD1_S))
|
||||
#define UHCI_SEND_Q5_WORD1_V 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q5_WORD1_S 0
|
||||
|
||||
#define UHCI_Q6_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x64)
|
||||
/* UHCI_SEND_Q6_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_SEND_Q6_WORD0 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q6_WORD0_M ((UHCI_SEND_Q6_WORD0_V)<<(UHCI_SEND_Q6_WORD0_S))
|
||||
#define UHCI_SEND_Q6_WORD0_V 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q6_WORD0_S 0
|
||||
|
||||
#define UHCI_Q6_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x68)
|
||||
/* UHCI_SEND_Q6_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_SEND_Q6_WORD1 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q6_WORD1_M ((UHCI_SEND_Q6_WORD1_V)<<(UHCI_SEND_Q6_WORD1_S))
|
||||
#define UHCI_SEND_Q6_WORD1_V 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q6_WORD1_S 0
|
||||
|
||||
#define UHCI_ESC_CONF0_REG(i) (REG_UHCI_BASE(i) + 0x6C)
|
||||
/* UHCI_SEPER_ESC_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdc ; */
|
||||
/*description: a*/
|
||||
#define UHCI_SEPER_ESC_CHAR1 0x000000FF
|
||||
#define UHCI_SEPER_ESC_CHAR1_M ((UHCI_SEPER_ESC_CHAR1_V)<<(UHCI_SEPER_ESC_CHAR1_S))
|
||||
#define UHCI_SEPER_ESC_CHAR1_V 0xFF
|
||||
#define UHCI_SEPER_ESC_CHAR1_S 16
|
||||
/* UHCI_SEPER_ESC_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */
|
||||
/*description: a*/
|
||||
#define UHCI_SEPER_ESC_CHAR0 0x000000FF
|
||||
#define UHCI_SEPER_ESC_CHAR0_M ((UHCI_SEPER_ESC_CHAR0_V)<<(UHCI_SEPER_ESC_CHAR0_S))
|
||||
#define UHCI_SEPER_ESC_CHAR0_V 0xFF
|
||||
#define UHCI_SEPER_ESC_CHAR0_S 8
|
||||
/* UHCI_SEPER_CHAR : R/W ;bitpos:[7:0] ;default: 8'hc0 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_SEPER_CHAR 0x000000FF
|
||||
#define UHCI_SEPER_CHAR_M ((UHCI_SEPER_CHAR_V)<<(UHCI_SEPER_CHAR_S))
|
||||
#define UHCI_SEPER_CHAR_V 0xFF
|
||||
#define UHCI_SEPER_CHAR_S 0
|
||||
|
||||
#define UHCI_ESC_CONF1_REG(i) (REG_UHCI_BASE(i) + 0x70)
|
||||
/* UHCI_ESC_SEQ0_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdd ; */
|
||||
/*description: a*/
|
||||
#define UHCI_ESC_SEQ0_CHAR1 0x000000FF
|
||||
#define UHCI_ESC_SEQ0_CHAR1_M ((UHCI_ESC_SEQ0_CHAR1_V)<<(UHCI_ESC_SEQ0_CHAR1_S))
|
||||
#define UHCI_ESC_SEQ0_CHAR1_V 0xFF
|
||||
#define UHCI_ESC_SEQ0_CHAR1_S 16
|
||||
/* UHCI_ESC_SEQ0_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */
|
||||
/*description: a*/
|
||||
#define UHCI_ESC_SEQ0_CHAR0 0x000000FF
|
||||
#define UHCI_ESC_SEQ0_CHAR0_M ((UHCI_ESC_SEQ0_CHAR0_V)<<(UHCI_ESC_SEQ0_CHAR0_S))
|
||||
#define UHCI_ESC_SEQ0_CHAR0_V 0xFF
|
||||
#define UHCI_ESC_SEQ0_CHAR0_S 8
|
||||
/* UHCI_ESC_SEQ0 : R/W ;bitpos:[7:0] ;default: 8'hdb ; */
|
||||
/*description: a*/
|
||||
#define UHCI_ESC_SEQ0 0x000000FF
|
||||
#define UHCI_ESC_SEQ0_M ((UHCI_ESC_SEQ0_V)<<(UHCI_ESC_SEQ0_S))
|
||||
#define UHCI_ESC_SEQ0_V 0xFF
|
||||
#define UHCI_ESC_SEQ0_S 0
|
||||
|
||||
#define UHCI_ESC_CONF2_REG(i) (REG_UHCI_BASE(i) + 0x74)
|
||||
/* UHCI_ESC_SEQ1_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hde ; */
|
||||
/*description: a*/
|
||||
#define UHCI_ESC_SEQ1_CHAR1 0x000000FF
|
||||
#define UHCI_ESC_SEQ1_CHAR1_M ((UHCI_ESC_SEQ1_CHAR1_V)<<(UHCI_ESC_SEQ1_CHAR1_S))
|
||||
#define UHCI_ESC_SEQ1_CHAR1_V 0xFF
|
||||
#define UHCI_ESC_SEQ1_CHAR1_S 16
|
||||
/* UHCI_ESC_SEQ1_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */
|
||||
/*description: a*/
|
||||
#define UHCI_ESC_SEQ1_CHAR0 0x000000FF
|
||||
#define UHCI_ESC_SEQ1_CHAR0_M ((UHCI_ESC_SEQ1_CHAR0_V)<<(UHCI_ESC_SEQ1_CHAR0_S))
|
||||
#define UHCI_ESC_SEQ1_CHAR0_V 0xFF
|
||||
#define UHCI_ESC_SEQ1_CHAR0_S 8
|
||||
/* UHCI_ESC_SEQ1 : R/W ;bitpos:[7:0] ;default: 8'h11 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_ESC_SEQ1 0x000000FF
|
||||
#define UHCI_ESC_SEQ1_M ((UHCI_ESC_SEQ1_V)<<(UHCI_ESC_SEQ1_S))
|
||||
#define UHCI_ESC_SEQ1_V 0xFF
|
||||
#define UHCI_ESC_SEQ1_S 0
|
||||
|
||||
#define UHCI_ESC_CONF3_REG(i) (REG_UHCI_BASE(i) + 0x78)
|
||||
/* UHCI_ESC_SEQ2_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdf ; */
|
||||
/*description: a*/
|
||||
#define UHCI_ESC_SEQ2_CHAR1 0x000000FF
|
||||
#define UHCI_ESC_SEQ2_CHAR1_M ((UHCI_ESC_SEQ2_CHAR1_V)<<(UHCI_ESC_SEQ2_CHAR1_S))
|
||||
#define UHCI_ESC_SEQ2_CHAR1_V 0xFF
|
||||
#define UHCI_ESC_SEQ2_CHAR1_S 16
|
||||
/* UHCI_ESC_SEQ2_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */
|
||||
/*description: a*/
|
||||
#define UHCI_ESC_SEQ2_CHAR0 0x000000FF
|
||||
#define UHCI_ESC_SEQ2_CHAR0_M ((UHCI_ESC_SEQ2_CHAR0_V)<<(UHCI_ESC_SEQ2_CHAR0_S))
|
||||
#define UHCI_ESC_SEQ2_CHAR0_V 0xFF
|
||||
#define UHCI_ESC_SEQ2_CHAR0_S 8
|
||||
/* UHCI_ESC_SEQ2 : R/W ;bitpos:[7:0] ;default: 8'h13 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_ESC_SEQ2 0x000000FF
|
||||
#define UHCI_ESC_SEQ2_M ((UHCI_ESC_SEQ2_V)<<(UHCI_ESC_SEQ2_S))
|
||||
#define UHCI_ESC_SEQ2_V 0xFF
|
||||
#define UHCI_ESC_SEQ2_S 0
|
||||
|
||||
#define UHCI_PKT_THRES_REG(i) (REG_UHCI_BASE(i) + 0x7C)
|
||||
/* UHCI_PKT_THRS : R/W ;bitpos:[12:0] ;default: 13'h80 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_PKT_THRS 0x00001FFF
|
||||
#define UHCI_PKT_THRS_M ((UHCI_PKT_THRS_V)<<(UHCI_PKT_THRS_S))
|
||||
#define UHCI_PKT_THRS_V 0x1FFF
|
||||
#define UHCI_PKT_THRS_S 0
|
||||
|
||||
#define UHCI_DATE_REG(i) (REG_UHCI_BASE(i) + 0x80)
|
||||
/* UHCI_DATE : R/W ;bitpos:[31:0] ;default: 32'h2007170 ; */
|
||||
/*description: a*/
|
||||
#define UHCI_DATE 0xFFFFFFFF
|
||||
#define UHCI_DATE_M ((UHCI_DATE_V)<<(UHCI_DATE_S))
|
||||
#define UHCI_DATE_V 0xFFFFFFFF
|
||||
#define UHCI_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /*_SOC_UHCI_REG_H_ */
|
||||
@@ -1,220 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct uhci_dev_s {
|
||||
union {
|
||||
struct {
|
||||
uint32_t tx_rst: 1; /*Write 1 then write 0 to this bit to reset decode state machine.*/
|
||||
uint32_t rx_rst: 1; /*Write 1 then write 0 to this bit to reset encode state machine.*/
|
||||
uint32_t uart0_ce: 1; /*Set this bit to link up HCI and UART0.*/
|
||||
uint32_t uart1_ce: 1; /*Set this bit to link up HCI and UART1.*/
|
||||
uint32_t reserved4: 1;
|
||||
uint32_t seper_en: 1; /*Set this bit to separate the data frame using a special char.*/
|
||||
uint32_t head_en: 1; /*Set this bit to encode the data packet with a formatting header.*/
|
||||
uint32_t crc_rec_en: 1; /*Set this bit to enable UHCI to receive the 16 bit CRC.*/
|
||||
uint32_t uart_idle_eof_en: 1; /*If this bit is set to 1 UHCI will end the payload receiving process when UART has been in idle state.*/
|
||||
uint32_t len_eof_en: 1; /*If this bit is set to 1 UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0 UHCI decoder receiving payload data is end when 0xc0 is received.*/
|
||||
uint32_t encode_crc_en: 1; /*Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload.*/
|
||||
uint32_t clk_en: 1; /*1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers.*/
|
||||
uint32_t uart_rx_brk_eof_en: 1; /*If this bit is set to 1 UHCI will end payload receive process when NULL frame is received by UART.*/
|
||||
uint32_t reserved13: 19;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_start: 1; /*a*/
|
||||
uint32_t tx_start: 1; /*a*/
|
||||
uint32_t rx_hung: 1; /*a*/
|
||||
uint32_t tx_hung: 1; /*a*/
|
||||
uint32_t send_s_q: 1; /*a*/
|
||||
uint32_t send_a_q: 1; /*a*/
|
||||
uint32_t outlink_eof_err: 1; /*This is the interrupt raw bit. Triggered when there are some errors in EOF in the*/
|
||||
uint32_t app_ctrl0: 1; /*Soft control int raw bit.*/
|
||||
uint32_t app_ctrl1: 1; /*Soft control int raw bit.*/
|
||||
uint32_t reserved9: 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_start: 1; /*a*/
|
||||
uint32_t tx_start: 1; /*a*/
|
||||
uint32_t rx_hung: 1; /*a*/
|
||||
uint32_t tx_hung: 1; /*a*/
|
||||
uint32_t send_s_q: 1; /*a*/
|
||||
uint32_t send_a_q: 1; /*a*/
|
||||
uint32_t outlink_eof_err: 1; /*a*/
|
||||
uint32_t app_ctrl0: 1; /*a*/
|
||||
uint32_t app_ctrl1: 1; /*a*/
|
||||
uint32_t reserved9: 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_start: 1; /*a*/
|
||||
uint32_t tx_start: 1; /*a*/
|
||||
uint32_t rx_hung: 1; /*a*/
|
||||
uint32_t tx_hung: 1; /*a*/
|
||||
uint32_t send_s_q: 1; /*a*/
|
||||
uint32_t send_a_q: 1; /*a*/
|
||||
uint32_t outlink_eof_err: 1; /*a*/
|
||||
uint32_t app_ctrl0: 1; /*a*/
|
||||
uint32_t app_ctrl1: 1; /*a*/
|
||||
uint32_t reserved9: 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_start: 1; /*a*/
|
||||
uint32_t tx_start: 1; /*a*/
|
||||
uint32_t rx_hung: 1; /*a*/
|
||||
uint32_t tx_hung: 1; /*a*/
|
||||
uint32_t send_s_q: 1; /*a*/
|
||||
uint32_t send_a_q: 1; /*a*/
|
||||
uint32_t outlink_eof_err: 1; /*a*/
|
||||
uint32_t app_ctrl0: 1; /*a*/
|
||||
uint32_t app_ctrl1: 1; /*a*/
|
||||
uint32_t reserved9: 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t check_sum_en: 1; /*a*/
|
||||
uint32_t check_seq_en: 1; /*a*/
|
||||
uint32_t crc_disable: 1; /*a*/
|
||||
uint32_t save_head: 1; /*a*/
|
||||
uint32_t tx_check_sum_re: 1; /*a*/
|
||||
uint32_t tx_ack_num_re: 1; /*a*/
|
||||
uint32_t reserved6: 1;
|
||||
uint32_t wait_sw_start: 1; /*a*/
|
||||
uint32_t sw_start: 1; /*a*/
|
||||
uint32_t reserved9: 12;
|
||||
uint32_t reserved21: 11;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_err_cause: 3; /*a*/
|
||||
uint32_t decode_state: 3; /*a*/
|
||||
uint32_t reserved6: 26;
|
||||
};
|
||||
uint32_t val;
|
||||
} state0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t encode_state: 3; /*a*/
|
||||
uint32_t reserved3: 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} state1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tx_c0_esc_en: 1; /*a*/
|
||||
uint32_t tx_db_esc_en: 1; /*a*/
|
||||
uint32_t tx_11_esc_en: 1; /*a*/
|
||||
uint32_t tx_13_esc_en: 1; /*a*/
|
||||
uint32_t rx_c0_esc_en: 1; /*a*/
|
||||
uint32_t rx_db_esc_en: 1; /*a*/
|
||||
uint32_t rx_11_esc_en: 1; /*a*/
|
||||
uint32_t rx_13_esc_en: 1; /*a*/
|
||||
uint32_t reserved8: 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} escape_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t txfifo_timeout: 8; /*a*/
|
||||
uint32_t txfifo_timeout_shift: 3; /*a*/
|
||||
uint32_t txfifo_timeout_ena: 1; /*a*/
|
||||
uint32_t rxfifo_timeout: 8; /*a*/
|
||||
uint32_t rxfifo_timeout_shift: 3; /*a*/
|
||||
uint32_t rxfifo_timeout_ena: 1; /*a*/
|
||||
uint32_t reserved24: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} hung_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t ack_num: 3;
|
||||
uint32_t ack_num_load: 1; /*a*/
|
||||
uint32_t reserved4: 28;
|
||||
};
|
||||
uint32_t val;
|
||||
} ack_num;
|
||||
uint32_t rx_head; /*a*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t single_send_num: 3; /*a*/
|
||||
uint32_t single_send_en: 1; /*a*/
|
||||
uint32_t always_send_num: 3; /*a*/
|
||||
uint32_t always_send_en: 1; /*a*/
|
||||
uint32_t reserved8: 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} quick_sent;
|
||||
struct {
|
||||
uint32_t w_data[2]; /*a*/
|
||||
} q_data[7];
|
||||
union {
|
||||
struct {
|
||||
uint32_t seper_char: 8; /*a*/
|
||||
uint32_t seper_esc_char0: 8; /*a*/
|
||||
uint32_t seper_esc_char1: 8; /*a*/
|
||||
uint32_t reserved24: 8; /*a*/
|
||||
};
|
||||
uint32_t val;
|
||||
} esc_conf0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t seq0: 8; /*a*/
|
||||
uint32_t seq0_char0: 8; /*a*/
|
||||
uint32_t seq0_char1: 8; /*a*/
|
||||
uint32_t reserved24: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} esc_conf1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t seq1: 8; /*a*/
|
||||
uint32_t seq1_char0: 8; /*a*/
|
||||
uint32_t seq1_char1: 8; /*a*/
|
||||
uint32_t reserved24: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} esc_conf2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t seq2: 8; /*a*/
|
||||
uint32_t seq2_char0: 8; /*a*/
|
||||
uint32_t seq2_char1: 8; /*a*/
|
||||
uint32_t reserved24: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} esc_conf3;
|
||||
union {
|
||||
struct {
|
||||
uint32_t thrs: 13; /*a*/
|
||||
uint32_t reserved13:19;
|
||||
};
|
||||
uint32_t val;
|
||||
} pkt_thres;
|
||||
uint32_t date; /*a*/
|
||||
} uhci_dev_t;
|
||||
extern uhci_dev_t UHCI0;
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,993 +0,0 @@
|
||||
|
||||
/** Copyright 2021 Espressif Systems (Shanghai) Co. Ltd.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
/** Configuration Registers */
|
||||
|
||||
/** USB_SERIAL_JTAG_EP1_REG register
|
||||
* USB_SERIAL_JTAG_EP1_REG.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0)
|
||||
/* USB_SERIAL_JTAG_RDWR_BYTE : R/W; bitpos: [8:0]; default: 0;
|
||||
* Write and read byte data to/from UART Tx/Rx FIFO through this field.
|
||||
* When USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set then user can write
|
||||
* data (up to 64 bytes) into UART Tx FIFO. When
|
||||
* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user can check
|
||||
* USB_SERIAL_JTAG_OUT_EP1_WR_ADDR and USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to
|
||||
* know how many data is received, then read that amount of data from UART
|
||||
* Rx
|
||||
* FIFO.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_RDWR_BYTE 0x000000FF
|
||||
#define USB_SERIAL_JTAG_RDWR_BYTE_M (USB_SERIAL_JTAG_RDWR_BYTE_V << USB_SERIAL_JTAG_RDWR_BYTE_S)
|
||||
#define USB_SERIAL_JTAG_RDWR_BYTE_V 0x000000FF
|
||||
#define USB_SERIAL_JTAG_RDWR_BYTE_S 0
|
||||
|
||||
/** USB_SERIAL_JTAG_CONF0_REG register
|
||||
* USB_SERIAL_JTAG_CONF0_REG.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18)
|
||||
/* USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0;
|
||||
* Select internal/external PHY. 1’b0: internal PHY, 1’b1: external
|
||||
* PHY
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_PHY_SEL (BIT(0))
|
||||
#define USB_SERIAL_JTAG_PHY_SEL_M (USB_SERIAL_JTAG_PHY_SEL_V << USB_SERIAL_JTAG_PHY_SEL_S)
|
||||
#define USB_SERIAL_JTAG_PHY_SEL_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_PHY_SEL_S 0
|
||||
/* USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W; bitpos: [1]; default: 0;
|
||||
* Enable software control USB D+ D-
|
||||
* exchange
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE (BIT(1))
|
||||
#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_M (USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V << USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S)
|
||||
#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S 1
|
||||
/* USB_SERIAL_JTAG_EXCHG_PINS : R/W; bitpos: [2]; default: 0;
|
||||
* USB D+ D-
|
||||
* exchange
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_EXCHG_PINS (BIT(2))
|
||||
#define USB_SERIAL_JTAG_EXCHG_PINS_M (USB_SERIAL_JTAG_EXCHG_PINS_V << USB_SERIAL_JTAG_EXCHG_PINS_S)
|
||||
#define USB_SERIAL_JTAG_EXCHG_PINS_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_EXCHG_PINS_S 2
|
||||
/* USB_SERIAL_JTAG_VREFL : R/W; bitpos: [5:3]; default: 0;
|
||||
* Control single-end input high threshold. 1.76V to 2V, step
|
||||
* 80mV
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_VREFL 0x00000003
|
||||
#define USB_SERIAL_JTAG_VREFL_M (USB_SERIAL_JTAG_VREFL_V << USB_SERIAL_JTAG_VREFL_S)
|
||||
#define USB_SERIAL_JTAG_VREFL_V 0x00000003
|
||||
#define USB_SERIAL_JTAG_VREFL_S 3
|
||||
/* USB_SERIAL_JTAG_VREFH : R/W; bitpos: [7:5]; default: 0;
|
||||
* Control single-end input low threshold. 0.8V to 1.04V, step
|
||||
* 80mV
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_VREFH 0x00000003
|
||||
#define USB_SERIAL_JTAG_VREFH_M (USB_SERIAL_JTAG_VREFH_V << USB_SERIAL_JTAG_VREFH_S)
|
||||
#define USB_SERIAL_JTAG_VREFH_V 0x00000003
|
||||
#define USB_SERIAL_JTAG_VREFH_S 5
|
||||
/* USB_SERIAL_JTAG_VREF_OVERRIDE : R/W; bitpos: [7]; default: 0;
|
||||
* Enable software control input
|
||||
* threshold
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_VREF_OVERRIDE (BIT(7))
|
||||
#define USB_SERIAL_JTAG_VREF_OVERRIDE_M (USB_SERIAL_JTAG_VREF_OVERRIDE_V << USB_SERIAL_JTAG_VREF_OVERRIDE_S)
|
||||
#define USB_SERIAL_JTAG_VREF_OVERRIDE_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_VREF_OVERRIDE_S 7
|
||||
/* USB_SERIAL_JTAG_PAD_PULL_OVERRIDE : R/W; bitpos: [8]; default: 0;
|
||||
* Enable software control USB D+ D- pullup
|
||||
* pulldown
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE (BIT(8))
|
||||
#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_M (USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V << USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S)
|
||||
#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S 8
|
||||
/* USB_SERIAL_JTAG_DP_PULLUP : R/W; bitpos: [9]; default: 1;
|
||||
* Control USB D+ pull
|
||||
* up.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_DP_PULLUP (BIT(9))
|
||||
#define USB_SERIAL_JTAG_DP_PULLUP_M (USB_SERIAL_JTAG_DP_PULLUP_V << USB_SERIAL_JTAG_DP_PULLUP_S)
|
||||
#define USB_SERIAL_JTAG_DP_PULLUP_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_DP_PULLUP_S 9
|
||||
/* USB_SERIAL_JTAG_DP_PULLDOWN : R/W; bitpos: [10]; default: 0;
|
||||
* Control USB D+ pull
|
||||
* down.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_DP_PULLDOWN (BIT(10))
|
||||
#define USB_SERIAL_JTAG_DP_PULLDOWN_M (USB_SERIAL_JTAG_DP_PULLDOWN_V << USB_SERIAL_JTAG_DP_PULLDOWN_S)
|
||||
#define USB_SERIAL_JTAG_DP_PULLDOWN_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_DP_PULLDOWN_S 10
|
||||
/* USB_SERIAL_JTAG_DM_PULLUP : R/W; bitpos: [11]; default: 0;
|
||||
* Control USB D- pull
|
||||
* up.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_DM_PULLUP (BIT(11))
|
||||
#define USB_SERIAL_JTAG_DM_PULLUP_M (USB_SERIAL_JTAG_DM_PULLUP_V << USB_SERIAL_JTAG_DM_PULLUP_S)
|
||||
#define USB_SERIAL_JTAG_DM_PULLUP_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_DM_PULLUP_S 11
|
||||
/* USB_SERIAL_JTAG_DM_PULLDOWN : R/W; bitpos: [12]; default: 0;
|
||||
* Control USB D- pull
|
||||
* down.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_DM_PULLDOWN (BIT(12))
|
||||
#define USB_SERIAL_JTAG_DM_PULLDOWN_M (USB_SERIAL_JTAG_DM_PULLDOWN_V << USB_SERIAL_JTAG_DM_PULLDOWN_S)
|
||||
#define USB_SERIAL_JTAG_DM_PULLDOWN_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_DM_PULLDOWN_S 12
|
||||
/* USB_SERIAL_JTAG_PULLUP_VALUE : R/W; bitpos: [13]; default: 0;
|
||||
* Control pull up
|
||||
* value.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_PULLUP_VALUE (BIT(13))
|
||||
#define USB_SERIAL_JTAG_PULLUP_VALUE_M (USB_SERIAL_JTAG_PULLUP_VALUE_V << USB_SERIAL_JTAG_PULLUP_VALUE_S)
|
||||
#define USB_SERIAL_JTAG_PULLUP_VALUE_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_PULLUP_VALUE_S 13
|
||||
/* USB_SERIAL_JTAG_USB_PAD_ENABLE : R/W; bitpos: [14]; default: 1;
|
||||
* Enable USB pad
|
||||
* function.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_USB_PAD_ENABLE (BIT(14))
|
||||
#define USB_SERIAL_JTAG_USB_PAD_ENABLE_M (USB_SERIAL_JTAG_USB_PAD_ENABLE_V << USB_SERIAL_JTAG_USB_PAD_ENABLE_S)
|
||||
#define USB_SERIAL_JTAG_USB_PAD_ENABLE_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_USB_PAD_ENABLE_S 14
|
||||
|
||||
/** USB_SERIAL_JTAG_TEST_REG register
|
||||
* USB_SERIAL_JTAG_TEST_REG.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x1c)
|
||||
/* USB_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0;
|
||||
* Enable test of the USB
|
||||
* pad
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_TEST_ENABLE (BIT(0))
|
||||
#define USB_SERIAL_JTAG_TEST_ENABLE_M (USB_SERIAL_JTAG_TEST_ENABLE_V << USB_SERIAL_JTAG_TEST_ENABLE_S)
|
||||
#define USB_SERIAL_JTAG_TEST_ENABLE_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_TEST_ENABLE_S 0
|
||||
/* USB_SERIAL_JTAG_TEST_USB_OE : R/W; bitpos: [1]; default: 0;
|
||||
* USB pad oen in
|
||||
* test
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_TEST_USB_OE (BIT(1))
|
||||
#define USB_SERIAL_JTAG_TEST_USB_OE_M (USB_SERIAL_JTAG_TEST_USB_OE_V << USB_SERIAL_JTAG_TEST_USB_OE_S)
|
||||
#define USB_SERIAL_JTAG_TEST_USB_OE_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_TEST_USB_OE_S 1
|
||||
/* USB_SERIAL_JTAG_TEST_TX_DP : R/W; bitpos: [2]; default: 0;
|
||||
* USB D+ tx value in
|
||||
* test
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_TEST_TX_DP (BIT(2))
|
||||
#define USB_SERIAL_JTAG_TEST_TX_DP_M (USB_SERIAL_JTAG_TEST_TX_DP_V << USB_SERIAL_JTAG_TEST_TX_DP_S)
|
||||
#define USB_SERIAL_JTAG_TEST_TX_DP_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_TEST_TX_DP_S 2
|
||||
/* USB_SERIAL_JTAG_TEST_TX_DM : R/W; bitpos: [3]; default: 0;
|
||||
* USB D- tx value in
|
||||
* test
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_TEST_TX_DM (BIT(3))
|
||||
#define USB_SERIAL_JTAG_TEST_TX_DM_M (USB_SERIAL_JTAG_TEST_TX_DM_V << USB_SERIAL_JTAG_TEST_TX_DM_S)
|
||||
#define USB_SERIAL_JTAG_TEST_TX_DM_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_TEST_TX_DM_S 3
|
||||
|
||||
/** USB_SERIAL_JTAG_MISC_CONF_REG register
|
||||
* USB_SERIAL_JTAG_MISC_CONF_REG.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x44)
|
||||
/* USB_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0;
|
||||
* 1'h1: Force clock on for register. 1'h0: Support clock only when
|
||||
* application writes
|
||||
* registers.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_CLK_EN (BIT(0))
|
||||
#define USB_SERIAL_JTAG_CLK_EN_M (USB_SERIAL_JTAG_CLK_EN_V << USB_SERIAL_JTAG_CLK_EN_S)
|
||||
#define USB_SERIAL_JTAG_CLK_EN_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_CLK_EN_S 0
|
||||
|
||||
/** USB_SERIAL_JTAG_MEM_CONF_REG register
|
||||
* USB_SERIAL_JTAG_MEM_CONF_REG.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x48)
|
||||
/* USB_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0;
|
||||
* 1: power down usb
|
||||
* memory.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_USB_MEM_PD (BIT(0))
|
||||
#define USB_SERIAL_JTAG_USB_MEM_PD_M (USB_SERIAL_JTAG_USB_MEM_PD_V << USB_SERIAL_JTAG_USB_MEM_PD_S)
|
||||
#define USB_SERIAL_JTAG_USB_MEM_PD_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_USB_MEM_PD_S 0
|
||||
/* USB_SERIAL_JTAG_USB_MEM_CLK_EN : R/W; bitpos: [1]; default: 1;
|
||||
* 1: Force clock on for usb
|
||||
* memory.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_USB_MEM_CLK_EN (BIT(1))
|
||||
#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_M (USB_SERIAL_JTAG_USB_MEM_CLK_EN_V << USB_SERIAL_JTAG_USB_MEM_CLK_EN_S)
|
||||
#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_S 1
|
||||
|
||||
|
||||
/** Status Registers */
|
||||
|
||||
/** USB_SERIAL_JTAG_EP1_CONF_REG register
|
||||
* USB_SERIAL_JTAG_EP1_CONF_REG.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4)
|
||||
/* USB_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0;
|
||||
* Set this bit to indicate writing byte data to UART Tx FIFO is done.
|
||||
* This bit then stays 0 until data in UART Tx FIFO is read by the USB
|
||||
* Host.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_WR_DONE (BIT(0))
|
||||
#define USB_SERIAL_JTAG_WR_DONE_M (USB_SERIAL_JTAG_WR_DONE_V << USB_SERIAL_JTAG_WR_DONE_S)
|
||||
#define USB_SERIAL_JTAG_WR_DONE_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_WR_DONE_S 0
|
||||
/* USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO; bitpos: [1]; default: 1;
|
||||
* 1'b1: Indicate UART Tx FIFO is not full and data can be written into
|
||||
* in. After writing USB_SERIAL_JTAG_WR_DONE, this will be 1’b0 until the
|
||||
* data is sent to the USB
|
||||
* Host.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE (BIT(1))
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M (USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V << USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S)
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S 1
|
||||
/* USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO; bitpos: [2]; default: 0;
|
||||
* 1'b1: Indicate there is data in UART Rx
|
||||
* FIFO.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL (BIT(2))
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M (USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V << USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S)
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S 2
|
||||
|
||||
/** USB_SERIAL_JTAG_JFIFO_ST_REG register
|
||||
* USB_SERIAL_JTAG_JFIFO_ST_REG.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x20)
|
||||
/* USB_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [2:0]; default: 0;
|
||||
* JTAG in fifo
|
||||
* counter.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_CNT 0x00000003
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_CNT_M (USB_SERIAL_JTAG_IN_FIFO_CNT_V << USB_SERIAL_JTAG_IN_FIFO_CNT_S)
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_CNT_V 0x00000003
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_CNT_S 0
|
||||
/* USB_SERIAL_JTAG_IN_FIFO_EMPTY : RO; bitpos: [2]; default: 1;
|
||||
* 1: JTAG in fifo is
|
||||
* empty.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_EMPTY (BIT(2))
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_M (USB_SERIAL_JTAG_IN_FIFO_EMPTY_V << USB_SERIAL_JTAG_IN_FIFO_EMPTY_S)
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_S 2
|
||||
/* USB_SERIAL_JTAG_IN_FIFO_FULL : RO; bitpos: [3]; default: 0;
|
||||
* 1: JTAG in fifo is
|
||||
* full.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_FULL (BIT(3))
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_FULL_M (USB_SERIAL_JTAG_IN_FIFO_FULL_V << USB_SERIAL_JTAG_IN_FIFO_FULL_S)
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_FULL_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_FULL_S 3
|
||||
/* USB_SERIAL_JTAG_OUT_FIFO_CNT : RO; bitpos: [6:4]; default: 0;
|
||||
* JTAT out fifo
|
||||
* counter.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_CNT 0x00000003
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_CNT_M (USB_SERIAL_JTAG_OUT_FIFO_CNT_V << USB_SERIAL_JTAG_OUT_FIFO_CNT_S)
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_CNT_V 0x00000003
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_CNT_S 4
|
||||
/* USB_SERIAL_JTAG_OUT_FIFO_EMPTY : RO; bitpos: [6]; default: 1;
|
||||
* 1: JTAG out fifo is
|
||||
* empty.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY (BIT(6))
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_M (USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V << USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S)
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S 6
|
||||
/* USB_SERIAL_JTAG_OUT_FIFO_FULL : RO; bitpos: [7]; default: 0;
|
||||
* 1: JTAG out fifo is
|
||||
* full.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_FULL (BIT(7))
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_FULL_M (USB_SERIAL_JTAG_OUT_FIFO_FULL_V << USB_SERIAL_JTAG_OUT_FIFO_FULL_S)
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_FULL_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_FULL_S 7
|
||||
/* USB_SERIAL_JTAG_IN_FIFO_RESET : R/W; bitpos: [8]; default: 0;
|
||||
* Write 1 to reset JTAG in
|
||||
* fifo.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_RESET (BIT(8))
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_RESET_M (USB_SERIAL_JTAG_IN_FIFO_RESET_V << USB_SERIAL_JTAG_IN_FIFO_RESET_S)
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_RESET_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_RESET_S 8
|
||||
/* USB_SERIAL_JTAG_OUT_FIFO_RESET : R/W; bitpos: [9]; default: 0;
|
||||
* Write 1 to reset JTAG out
|
||||
* fifo.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_RESET (BIT(9))
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_RESET_M (USB_SERIAL_JTAG_OUT_FIFO_RESET_V << USB_SERIAL_JTAG_OUT_FIFO_RESET_S)
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_RESET_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_RESET_S 9
|
||||
|
||||
/** USB_SERIAL_JTAG_FRAM_NUM_REG register
|
||||
* USB_SERIAL_JTAG_FRAM_NUM_REG.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x24)
|
||||
/* USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [11:0]; default: 0;
|
||||
* Frame index of received SOF
|
||||
* frame.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_SOF_FRAME_INDEX 0x000007FF
|
||||
#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_M (USB_SERIAL_JTAG_SOF_FRAME_INDEX_V << USB_SERIAL_JTAG_SOF_FRAME_INDEX_S)
|
||||
#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V 0x000007FF
|
||||
#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S 0
|
||||
|
||||
/** USB_SERIAL_JTAG_IN_EP0_ST_REG register
|
||||
* USB_SERIAL_JTAG_IN_EP0_ST_REG.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x28)
|
||||
/* USB_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [2:0]; default: 1;
|
||||
* State of IN Endpoint
|
||||
* 0.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_IN_EP0_STATE 0x00000003
|
||||
#define USB_SERIAL_JTAG_IN_EP0_STATE_M (USB_SERIAL_JTAG_IN_EP0_STATE_V << USB_SERIAL_JTAG_IN_EP0_STATE_S)
|
||||
#define USB_SERIAL_JTAG_IN_EP0_STATE_V 0x00000003
|
||||
#define USB_SERIAL_JTAG_IN_EP0_STATE_S 0
|
||||
/* USB_SERIAL_JTAG_IN_EP0_WR_ADDR : RO; bitpos: [9:2]; default: 0;
|
||||
* Write data address of IN endpoint
|
||||
* 0.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR 0x0000007F
|
||||
#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S)
|
||||
#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V 0x0000007F
|
||||
#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S 2
|
||||
/* USB_SERIAL_JTAG_IN_EP0_RD_ADDR : RO; bitpos: [16:9]; default: 0;
|
||||
* Read data address of IN endpoint
|
||||
* 0.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR 0x0000007F
|
||||
#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S)
|
||||
#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V 0x0000007F
|
||||
#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S 9
|
||||
|
||||
/** USB_SERIAL_JTAG_IN_EP1_ST_REG register
|
||||
* USB_SERIAL_JTAG_IN_EP1_ST_REG.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x2c)
|
||||
/* USB_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [2:0]; default: 1;
|
||||
* State of IN Endpoint
|
||||
* 1.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_IN_EP1_STATE 0x00000003
|
||||
#define USB_SERIAL_JTAG_IN_EP1_STATE_M (USB_SERIAL_JTAG_IN_EP1_STATE_V << USB_SERIAL_JTAG_IN_EP1_STATE_S)
|
||||
#define USB_SERIAL_JTAG_IN_EP1_STATE_V 0x00000003
|
||||
#define USB_SERIAL_JTAG_IN_EP1_STATE_S 0
|
||||
/* USB_SERIAL_JTAG_IN_EP1_WR_ADDR : RO; bitpos: [9:2]; default: 0;
|
||||
* Write data address of IN endpoint
|
||||
* 1.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR 0x0000007F
|
||||
#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S)
|
||||
#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V 0x0000007F
|
||||
#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S 2
|
||||
/* USB_SERIAL_JTAG_IN_EP1_RD_ADDR : RO; bitpos: [16:9]; default: 0;
|
||||
* Read data address of IN endpoint
|
||||
* 1.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR 0x0000007F
|
||||
#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S)
|
||||
#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V 0x0000007F
|
||||
#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S 9
|
||||
|
||||
/** USB_SERIAL_JTAG_IN_EP2_ST_REG register
|
||||
* USB_SERIAL_JTAG_IN_EP2_ST_REG.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x30)
|
||||
/* USB_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [2:0]; default: 1;
|
||||
* State of IN Endpoint
|
||||
* 2.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_IN_EP2_STATE 0x00000003
|
||||
#define USB_SERIAL_JTAG_IN_EP2_STATE_M (USB_SERIAL_JTAG_IN_EP2_STATE_V << USB_SERIAL_JTAG_IN_EP2_STATE_S)
|
||||
#define USB_SERIAL_JTAG_IN_EP2_STATE_V 0x00000003
|
||||
#define USB_SERIAL_JTAG_IN_EP2_STATE_S 0
|
||||
/* USB_SERIAL_JTAG_IN_EP2_WR_ADDR : RO; bitpos: [9:2]; default: 0;
|
||||
* Write data address of IN endpoint
|
||||
* 2.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR 0x0000007F
|
||||
#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S)
|
||||
#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V 0x0000007F
|
||||
#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S 2
|
||||
/* USB_SERIAL_JTAG_IN_EP2_RD_ADDR : RO; bitpos: [16:9]; default: 0;
|
||||
* Read data address of IN endpoint
|
||||
* 2.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR 0x0000007F
|
||||
#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S)
|
||||
#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V 0x0000007F
|
||||
#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S 9
|
||||
|
||||
/** USB_SERIAL_JTAG_IN_EP3_ST_REG register
|
||||
* USB_SERIAL_JTAG_IN_EP3_ST_REG.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x34)
|
||||
/* USB_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [2:0]; default: 1;
|
||||
* State of IN Endpoint
|
||||
* 3.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_IN_EP3_STATE 0x00000003
|
||||
#define USB_SERIAL_JTAG_IN_EP3_STATE_M (USB_SERIAL_JTAG_IN_EP3_STATE_V << USB_SERIAL_JTAG_IN_EP3_STATE_S)
|
||||
#define USB_SERIAL_JTAG_IN_EP3_STATE_V 0x00000003
|
||||
#define USB_SERIAL_JTAG_IN_EP3_STATE_S 0
|
||||
/* USB_SERIAL_JTAG_IN_EP3_WR_ADDR : RO; bitpos: [9:2]; default: 0;
|
||||
* Write data address of IN endpoint
|
||||
* 3.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR 0x0000007F
|
||||
#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_M (USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V << USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S)
|
||||
#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V 0x0000007F
|
||||
#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S 2
|
||||
/* USB_SERIAL_JTAG_IN_EP3_RD_ADDR : RO; bitpos: [16:9]; default: 0;
|
||||
* Read data address of IN endpoint
|
||||
* 3.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR 0x0000007F
|
||||
#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_M (USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V << USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S)
|
||||
#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V 0x0000007F
|
||||
#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S 9
|
||||
|
||||
/** USB_SERIAL_JTAG_OUT_EP0_ST_REG register
|
||||
* USB_SERIAL_JTAG_OUT_EP0_ST_REG.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x38)
|
||||
/* USB_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [2:0]; default: 0;
|
||||
* State of OUT Endpoint
|
||||
* 0.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP0_STATE 0x00000003
|
||||
#define USB_SERIAL_JTAG_OUT_EP0_STATE_M (USB_SERIAL_JTAG_OUT_EP0_STATE_V << USB_SERIAL_JTAG_OUT_EP0_STATE_S)
|
||||
#define USB_SERIAL_JTAG_OUT_EP0_STATE_V 0x00000003
|
||||
#define USB_SERIAL_JTAG_OUT_EP0_STATE_S 0
|
||||
/* USB_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO; bitpos: [9:2]; default: 0;
|
||||
* Write data address of OUT endpoint 0. When
|
||||
* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected. there are
|
||||
* USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT
|
||||
* EP0.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR 0x0000007F
|
||||
#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S)
|
||||
#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V 0x0000007F
|
||||
#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S 2
|
||||
/* USB_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO; bitpos: [16:9]; default: 0;
|
||||
* Read data address of OUT endpoint
|
||||
* 0.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR 0x0000007F
|
||||
#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S)
|
||||
#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V 0x0000007F
|
||||
#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S 9
|
||||
|
||||
/** USB_SERIAL_JTAG_OUT_EP1_ST_REG register
|
||||
* USB_SERIAL_JTAG_OUT_EP1_ST_REG.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x3c)
|
||||
/* USB_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [2:0]; default: 0;
|
||||
* State of OUT Endpoint
|
||||
* 1.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_STATE 0x00000003
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_STATE_M (USB_SERIAL_JTAG_OUT_EP1_STATE_V << USB_SERIAL_JTAG_OUT_EP1_STATE_S)
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_STATE_V 0x00000003
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_STATE_S 0
|
||||
/* USB_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO; bitpos: [9:2]; default: 0;
|
||||
* Write data address of OUT endpoint 1. When
|
||||
* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected. there are
|
||||
* USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT
|
||||
* EP1.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR 0x0000007F
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S)
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V 0x0000007F
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S 2
|
||||
/* USB_SERIAL_JTAG_OUT_EP1_RD_ADDR : RO; bitpos: [16:9]; default: 0;
|
||||
* Read data address of OUT endpoint
|
||||
* 1.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR 0x0000007F
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S)
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V 0x0000007F
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S 9
|
||||
/* USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO; bitpos: [23:16]; default: 0;
|
||||
* Data count in OUT endpoint 1 when one packet is
|
||||
* received.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT 0x0000007F
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_M (USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V << USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S)
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V 0x0000007F
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S 16
|
||||
|
||||
/** USB_SERIAL_JTAG_OUT_EP2_ST_REG register
|
||||
* USB_SERIAL_JTAG_OUT_EP2_ST_REG.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x40)
|
||||
/* USB_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [2:0]; default: 0;
|
||||
* State of OUT Endpoint
|
||||
* 2.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_STATE 0x00000003
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_STATE_M (USB_SERIAL_JTAG_OUT_EP2_STATE_V << USB_SERIAL_JTAG_OUT_EP2_STATE_S)
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_STATE_V 0x00000003
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_STATE_S 0
|
||||
/* USB_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO; bitpos: [9:2]; default: 0;
|
||||
* Write data address of OUT endpoint 2. When
|
||||
* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected. there are
|
||||
* USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT
|
||||
* EP2.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR 0x0000007F
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_M (USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S)
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V 0x0000007F
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S 2
|
||||
/* USB_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO; bitpos: [16:9]; default: 0;
|
||||
* Read data address of OUT endpoint
|
||||
* 2.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR 0x0000007F
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_M (USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V << USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S)
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V 0x0000007F
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S 9
|
||||
|
||||
|
||||
/** Interrupt Registers */
|
||||
|
||||
/** USB_SERIAL_JTAG_INT_RAW_REG register
|
||||
* USB_SERIAL_JTAG_INT_RAW_REG.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x8)
|
||||
/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
|
||||
* The raw interrupt bit turns to high level when a flush command is
|
||||
* received for IN endpoint 2 of
|
||||
* JTAG.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW (BIT(0))
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S)
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S 0
|
||||
/* USB_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
|
||||
* The raw interrupt bit turns to high level when a SOF frame is
|
||||
* received.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_SOF_INT_RAW (BIT(1))
|
||||
#define USB_SERIAL_JTAG_SOF_INT_RAW_M (USB_SERIAL_JTAG_SOF_INT_RAW_V << USB_SERIAL_JTAG_SOF_INT_RAW_S)
|
||||
#define USB_SERIAL_JTAG_SOF_INT_RAW_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_SOF_INT_RAW_S 1
|
||||
/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
|
||||
* The raw interrupt bit turns to high level when the Serial Port OUT
|
||||
* Endpoint received one
|
||||
* packet.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW (BIT(2))
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S)
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S 2
|
||||
/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS; bitpos: [3]; default: 1;
|
||||
* The raw interrupt bit turns to high level when the Serial Port IN
|
||||
* Endpoint is
|
||||
* empty.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW (BIT(3))
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S)
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S 3
|
||||
/* USB_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0;
|
||||
* The raw interrupt bit turns to high level when a PID error is
|
||||
* detected.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_RAW (BIT(4))
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_M (USB_SERIAL_JTAG_PID_ERR_INT_RAW_V << USB_SERIAL_JTAG_PID_ERR_INT_RAW_S)
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_S 4
|
||||
/* USB_SERIAL_JTAG_CRC5_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0;
|
||||
* The raw interrupt bit turns to high level when a CRC5 error is
|
||||
* detected.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW (BIT(5))
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_M (USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S)
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S 5
|
||||
/* USB_SERIAL_JTAG_CRC16_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
|
||||
* The raw interrupt bit turns to high level when a CRC16 error is
|
||||
* detected.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW (BIT(6))
|
||||
#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_M (USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V << USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S)
|
||||
#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S 6
|
||||
/* USB_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0;
|
||||
* The raw interrupt bit turns to high level when a bit stuffing error is
|
||||
* detected.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW (BIT(7))
|
||||
#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_M (USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V << USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S)
|
||||
#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S 7
|
||||
/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0;
|
||||
* The raw interrupt bit turns to high level when an IN token for IN
|
||||
* endpoint 1 is
|
||||
* received.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW (BIT(8))
|
||||
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S)
|
||||
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S 8
|
||||
/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
|
||||
* The raw interrupt bit turns to high level when a USB bus reset is
|
||||
* detected.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW (BIT(9))
|
||||
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S)
|
||||
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S 9
|
||||
/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0;
|
||||
* The raw interrupt bit turns to high level when OUT endpoint 1 received
|
||||
* packet with zero
|
||||
* payload.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW (BIT(10))
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S)
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S 10
|
||||
/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0;
|
||||
* The raw interrupt bit turns to high level when OUT endpoint 2 received
|
||||
* packet with zero
|
||||
* payload.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW (BIT(11))
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S)
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S 11
|
||||
|
||||
/** USB_SERIAL_JTAG_INT_ST_REG register
|
||||
* USB_SERIAL_JTAG_INT_ST_REG.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0xc)
|
||||
/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0;
|
||||
* The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT
|
||||
* interrupt.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST (BIT(0))
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S)
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S 0
|
||||
/* USB_SERIAL_JTAG_SOF_INT_ST : RO; bitpos: [1]; default: 0;
|
||||
* The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT
|
||||
* interrupt.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_SOF_INT_ST (BIT(1))
|
||||
#define USB_SERIAL_JTAG_SOF_INT_ST_M (USB_SERIAL_JTAG_SOF_INT_ST_V << USB_SERIAL_JTAG_SOF_INT_ST_S)
|
||||
#define USB_SERIAL_JTAG_SOF_INT_ST_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_SOF_INT_ST_S 1
|
||||
/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO; bitpos: [2]; default: 0;
|
||||
* The raw interrupt status bit for the
|
||||
* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
|
||||
* interrupt.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST (BIT(2))
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S)
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S 2
|
||||
/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO; bitpos: [3]; default: 0;
|
||||
* The raw interrupt status bit for the
|
||||
* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT
|
||||
* interrupt.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST (BIT(3))
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S)
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S 3
|
||||
/* USB_SERIAL_JTAG_PID_ERR_INT_ST : RO; bitpos: [4]; default: 0;
|
||||
* The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT
|
||||
* interrupt.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_ST (BIT(4))
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_ST_M (USB_SERIAL_JTAG_PID_ERR_INT_ST_V << USB_SERIAL_JTAG_PID_ERR_INT_ST_S)
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_ST_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_ST_S 4
|
||||
/* USB_SERIAL_JTAG_CRC5_ERR_INT_ST : RO; bitpos: [5]; default: 0;
|
||||
* The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT
|
||||
* interrupt.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST (BIT(5))
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_M (USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S)
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S 5
|
||||
/* USB_SERIAL_JTAG_CRC16_ERR_INT_ST : RO; bitpos: [6]; default: 0;
|
||||
* The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT
|
||||
* interrupt.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST (BIT(6))
|
||||
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_M (USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S)
|
||||
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S 6
|
||||
/* USB_SERIAL_JTAG_STUFF_ERR_INT_ST : RO; bitpos: [7]; default: 0;
|
||||
* The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT
|
||||
* interrupt.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST (BIT(7))
|
||||
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_M (USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S)
|
||||
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S 7
|
||||
/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO; bitpos: [8]; default: 0;
|
||||
* The raw interrupt status bit for the
|
||||
* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT
|
||||
* interrupt.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST (BIT(8))
|
||||
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S)
|
||||
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S 8
|
||||
/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO; bitpos: [9]; default: 0;
|
||||
* The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT
|
||||
* interrupt.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST (BIT(9))
|
||||
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S)
|
||||
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S 9
|
||||
/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO; bitpos: [10]; default: 0;
|
||||
* The raw interrupt status bit for the
|
||||
* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT
|
||||
* interrupt.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST (BIT(10))
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S)
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S 10
|
||||
/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO; bitpos: [11]; default: 0;
|
||||
* The raw interrupt status bit for the
|
||||
* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT
|
||||
* interrupt.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST (BIT(11))
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S)
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S 11
|
||||
|
||||
/** USB_SERIAL_JTAG_INT_ENA_REG register
|
||||
* USB_SERIAL_JTAG_INT_ENA_REG.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x10)
|
||||
/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0;
|
||||
* The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT
|
||||
* interrupt.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA (BIT(0))
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S)
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S 0
|
||||
/* USB_SERIAL_JTAG_SOF_INT_ENA : R/W; bitpos: [1]; default: 0;
|
||||
* The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT
|
||||
* interrupt.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_SOF_INT_ENA (BIT(1))
|
||||
#define USB_SERIAL_JTAG_SOF_INT_ENA_M (USB_SERIAL_JTAG_SOF_INT_ENA_V << USB_SERIAL_JTAG_SOF_INT_ENA_S)
|
||||
#define USB_SERIAL_JTAG_SOF_INT_ENA_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_SOF_INT_ENA_S 1
|
||||
/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : R/W; bitpos: [2]; default: 0;
|
||||
* The interrupt enable bit for the
|
||||
* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
|
||||
* interrupt.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA (BIT(2))
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S)
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S 2
|
||||
/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W; bitpos: [3]; default: 0;
|
||||
* The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT
|
||||
* interrupt.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA (BIT(3))
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S)
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S 3
|
||||
/* USB_SERIAL_JTAG_PID_ERR_INT_ENA : R/W; bitpos: [4]; default: 0;
|
||||
* The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT
|
||||
* interrupt.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_ENA (BIT(4))
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_M (USB_SERIAL_JTAG_PID_ERR_INT_ENA_V << USB_SERIAL_JTAG_PID_ERR_INT_ENA_S)
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_S 4
|
||||
/* USB_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W; bitpos: [5]; default: 0;
|
||||
* The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT
|
||||
* interrupt.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA (BIT(5))
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_M (USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S)
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S 5
|
||||
/* USB_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W; bitpos: [6]; default: 0;
|
||||
* The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT
|
||||
* interrupt.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA (BIT(6))
|
||||
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_M (USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V << USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S)
|
||||
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S 6
|
||||
/* USB_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W; bitpos: [7]; default: 0;
|
||||
* The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT
|
||||
* interrupt.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA (BIT(7))
|
||||
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_M (USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V << USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S)
|
||||
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S 7
|
||||
/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W; bitpos: [8]; default: 0;
|
||||
* The interrupt enable bit for the
|
||||
* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT
|
||||
* interrupt.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA (BIT(8))
|
||||
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S)
|
||||
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S 8
|
||||
/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W; bitpos: [9]; default: 0;
|
||||
* The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT
|
||||
* interrupt.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA (BIT(9))
|
||||
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S)
|
||||
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S 9
|
||||
/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [10]; default: 0;
|
||||
* The interrupt enable bit for the
|
||||
* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT
|
||||
* interrupt.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA (BIT(10))
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S)
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S 10
|
||||
/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W; bitpos: [11]; default: 0;
|
||||
* The interrupt enable bit for the
|
||||
* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT
|
||||
* interrupt.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA (BIT(11))
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S)
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S 11
|
||||
|
||||
/** USB_SERIAL_JTAG_INT_CLR_REG register
|
||||
* USB_SERIAL_JTAG_INT_CLR_REG.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x14)
|
||||
/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0;
|
||||
* Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT
|
||||
* interrupt.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR (BIT(0))
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M (USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V << USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S)
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S 0
|
||||
/* USB_SERIAL_JTAG_SOF_INT_CLR : WT; bitpos: [1]; default: 0;
|
||||
* Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT
|
||||
* interrupt.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_SOF_INT_CLR (BIT(1))
|
||||
#define USB_SERIAL_JTAG_SOF_INT_CLR_M (USB_SERIAL_JTAG_SOF_INT_CLR_V << USB_SERIAL_JTAG_SOF_INT_CLR_S)
|
||||
#define USB_SERIAL_JTAG_SOF_INT_CLR_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_SOF_INT_CLR_S 1
|
||||
/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT; bitpos: [2]; default: 0;
|
||||
* Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT
|
||||
* interrupt.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR (BIT(2))
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M (USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S)
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S 2
|
||||
/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT; bitpos: [3]; default: 0;
|
||||
* Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT
|
||||
* interrupt.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR (BIT(3))
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M (USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V << USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S)
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S 3
|
||||
/* USB_SERIAL_JTAG_PID_ERR_INT_CLR : WT; bitpos: [4]; default: 0;
|
||||
* Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT
|
||||
* interrupt.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_CLR (BIT(4))
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_M (USB_SERIAL_JTAG_PID_ERR_INT_CLR_V << USB_SERIAL_JTAG_PID_ERR_INT_CLR_S)
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_S 4
|
||||
/* USB_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT; bitpos: [5]; default: 0;
|
||||
* Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT
|
||||
* interrupt.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR (BIT(5))
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_M (USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S)
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S 5
|
||||
/* USB_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT; bitpos: [6]; default: 0;
|
||||
* Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT
|
||||
* interrupt.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR (BIT(6))
|
||||
#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_M (USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V << USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S)
|
||||
#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S 6
|
||||
/* USB_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT; bitpos: [7]; default: 0;
|
||||
* Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT
|
||||
* interrupt.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR (BIT(7))
|
||||
#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_M (USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V << USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S)
|
||||
#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S 7
|
||||
/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT; bitpos: [8]; default: 0;
|
||||
* Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT
|
||||
* interrupt.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR (BIT(8))
|
||||
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M (USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V << USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S)
|
||||
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S 8
|
||||
/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT; bitpos: [9]; default: 0;
|
||||
* Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT
|
||||
* interrupt.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR (BIT(9))
|
||||
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M (USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V << USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S)
|
||||
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S 9
|
||||
/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [10]; default: 0;
|
||||
* Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT
|
||||
* interrupt.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR (BIT(10))
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M (USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S)
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S 10
|
||||
/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT; bitpos: [11]; default: 0;
|
||||
* Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT
|
||||
* interrupt.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR (BIT(11))
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M (USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V << USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S)
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V 0x00000001
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S 11
|
||||
|
||||
|
||||
/** Version Registers */
|
||||
|
||||
/** USB_SERIAL_JTAG_DATE_REG register
|
||||
* USB_SERIAL_JTAG_DATE_REG.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80)
|
||||
/* USB_SERIAL_JTAG_DATE : R/W; bitpos: [32:0]; default: 33583872;
|
||||
* register
|
||||
* version.
|
||||
*/
|
||||
#define USB_SERIAL_JTAG_DATE 0xFFFFFFFF
|
||||
#define USB_SERIAL_JTAG_DATE_M (USB_SERIAL_JTAG_DATE_V << USB_SERIAL_JTAG_DATE_S)
|
||||
#define USB_SERIAL_JTAG_DATE_V 0xFFFFFFFF
|
||||
#define USB_SERIAL_JTAG_DATE_S 0
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,262 +0,0 @@
|
||||
// Copyright 2021 Espressif Systems (Shanghai) Co. Ltd.
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_USB_SERIAL_JTAG_STRUCT_H_
|
||||
#define _SOC_USB_SERIAL_JTAG_STRUCT_H_
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#include "soc.h"
|
||||
|
||||
typedef volatile struct usb_serial_jtag_dev_s {
|
||||
union {
|
||||
struct {
|
||||
uint32_t rdwr_byte : 32; /*Although only low 8-bits is valid, but change it to 32bits to avoid there's no read/modify/write behaviour*/ /*Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT is set then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_SERIAL_JTAG_OUT_EP1_WR_ADDR and USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know how many data is received, then read that amount of data from UART Rx FIFO. */
|
||||
};
|
||||
uint32_t val;
|
||||
} ep1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t wr_done : 1; /*Set this bit to indicate writing byte data to UART Tx FIFO is done. This bit then stays 0 until data in UART Tx FIFO is read by the USB Host.*/
|
||||
uint32_t serial_in_ep_data_free : 1; /*1'b1: Indicate UART Tx FIFO is not full and data can be written into in. After writing USB_SERIAL_JTAG_WR_DONE, this will be 1’b0 until the data is sent to the USB Host.*/
|
||||
uint32_t serial_out_ep_data_avail : 1; /*1'b1: Indicate there is data in UART Rx FIFO.*/
|
||||
uint32_t reserved3 : 29; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} ep1_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t jtag_in_flush_int_raw : 1; /*The raw interrupt bit turns to high level when a flush command is received for IN endpoint 2 of JTAG.*/
|
||||
uint32_t sof_int_raw : 1; /*The raw interrupt bit turns to high level when a SOF frame is received.*/
|
||||
uint32_t serial_out_recv_pkt_int_raw : 1; /*The raw interrupt bit turns to high level when the Serial Port OUT Endpoint received one packet.*/
|
||||
uint32_t serial_in_empty_int_raw : 1; /*The raw interrupt bit turns to high level when the Serial Port IN Endpoint is empty.*/
|
||||
uint32_t pid_err_int_raw : 1; /*The raw interrupt bit turns to high level when a PID error is detected.*/
|
||||
uint32_t crc5_err_int_raw : 1; /*The raw interrupt bit turns to high level when a CRC5 error is detected.*/
|
||||
uint32_t crc16_err_int_raw : 1; /*The raw interrupt bit turns to high level when a CRC16 error is detected.*/
|
||||
uint32_t stuff_err_int_raw : 1; /*The raw interrupt bit turns to high level when a bit stuffing error is detected.*/
|
||||
uint32_t in_token_rec_in_ep1_int_raw : 1; /*The raw interrupt bit turns to high level when an IN token for IN endpoint 1 is received.*/
|
||||
uint32_t usb_bus_reset_int_raw : 1; /*The raw interrupt bit turns to high level when a USB bus reset is detected.*/
|
||||
uint32_t out_ep1_zero_payload_int_raw : 1; /*The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero payload.*/
|
||||
uint32_t out_ep2_zero_payload_int_raw : 1; /*The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero payload.*/
|
||||
uint32_t reserved12 : 20; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t jtag_in_flush_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.*/
|
||||
uint32_t sof_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt.*/
|
||||
uint32_t serial_out_recv_pkt_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.*/
|
||||
uint32_t serial_in_empty_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.*/
|
||||
uint32_t pid_err_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.*/
|
||||
uint32_t crc5_err_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.*/
|
||||
uint32_t crc16_err_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.*/
|
||||
uint32_t stuff_err_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.*/
|
||||
uint32_t in_token_rec_in_ep1_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt.*/
|
||||
uint32_t usb_bus_reset_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.*/
|
||||
uint32_t out_ep1_zero_payload_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.*/
|
||||
uint32_t out_ep2_zero_payload_int_st : 1; /*The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.*/
|
||||
uint32_t reserved12 : 20; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t jtag_in_flush_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.*/
|
||||
uint32_t sof_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt.*/
|
||||
uint32_t serial_out_recv_pkt_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.*/
|
||||
uint32_t serial_in_empty_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.*/
|
||||
uint32_t pid_err_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt.*/
|
||||
uint32_t crc5_err_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.*/
|
||||
uint32_t crc16_err_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.*/
|
||||
uint32_t stuff_err_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.*/
|
||||
uint32_t in_token_rec_in_ep1_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt.*/
|
||||
uint32_t usb_bus_reset_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.*/
|
||||
uint32_t out_ep1_zero_payload_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.*/
|
||||
uint32_t out_ep2_zero_payload_int_ena : 1; /*The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.*/
|
||||
uint32_t reserved12 : 20; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t jtag_in_flush_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt.*/
|
||||
uint32_t sof_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt.*/
|
||||
uint32_t serial_out_recv_pkt_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt.*/
|
||||
uint32_t serial_in_empty_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt.*/
|
||||
uint32_t pid_err_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt.*/
|
||||
uint32_t crc5_err_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt.*/
|
||||
uint32_t crc16_err_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt.*/
|
||||
uint32_t stuff_err_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt.*/
|
||||
uint32_t in_token_rec_in_ep1_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt.*/
|
||||
uint32_t usb_bus_reset_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt.*/
|
||||
uint32_t out_ep1_zero_payload_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt.*/
|
||||
uint32_t out_ep2_zero_payload_int_clr : 1; /*Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt.*/
|
||||
uint32_t reserved12 : 20; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t phy_sel : 1; /*Select internal/external PHY. 1’b0: internal PHY, 1’b1: external PHY*/
|
||||
uint32_t exchg_pins_override : 1; /*Enable software control USB D+ D- exchange*/
|
||||
uint32_t exchg_pins : 1; /*USB D+ D- exchange*/
|
||||
uint32_t vrefh : 2; /*Control single-end input high threshold. 1.76V to 2V, step 80mV */
|
||||
uint32_t vrefl : 2; /*Control single-end input low threshold. 0.8V to 1.04V, step 80mV*/
|
||||
uint32_t vref_override : 1; /*Enable software control input threshold*/
|
||||
uint32_t pad_pull_override : 1; /*Enable software control USB D+ D- pullup pulldown*/
|
||||
uint32_t dp_pullup : 1; /*Control USB D+ pull up.*/
|
||||
uint32_t dp_pulldown : 1; /*Control USB D+ pull down.*/
|
||||
uint32_t dm_pullup : 1; /*Control USB D- pull up.*/
|
||||
uint32_t dm_pulldown : 1; /*Control USB D- pull down.*/
|
||||
uint32_t pullup_value : 1; /*Control pull up value.*/
|
||||
uint32_t usb_pad_enable : 1; /*Enable USB pad function.*/
|
||||
uint32_t reserved15 : 17;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t test_enable : 1; /*Enable test of the USB pad*/
|
||||
uint32_t test_usb_oe : 1; /*USB pad oen in test*/
|
||||
uint32_t test_tx_dp : 1; /*USB D+ tx value in test*/
|
||||
uint32_t test_tx_dm : 1; /*USB D- tx value in test*/
|
||||
uint32_t reserved4 : 28;
|
||||
};
|
||||
uint32_t val;
|
||||
} test;
|
||||
union {
|
||||
struct {
|
||||
uint32_t in_fifo_cnt : 2; /*JTAG in fifo counter.*/
|
||||
uint32_t in_fifo_empty : 1; /*1: JTAG in fifo is empty.*/
|
||||
uint32_t in_fifo_full : 1; /*1: JTAG in fifo is full.*/
|
||||
uint32_t out_fifo_cnt : 2; /*JTAT out fifo counter.*/
|
||||
uint32_t out_fifo_empty : 1; /*1: JTAG out fifo is empty.*/
|
||||
uint32_t out_fifo_full : 1; /*1: JTAG out fifo is full.*/
|
||||
uint32_t in_fifo_reset : 1; /*Write 1 to reset JTAG in fifo.*/
|
||||
uint32_t out_fifo_reset : 1; /*Write 1 to reset JTAG out fifo.*/
|
||||
uint32_t reserved10 : 22;
|
||||
};
|
||||
uint32_t val;
|
||||
} jfifo_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sof_frame_index : 11; /*Frame index of received SOF frame.*/
|
||||
uint32_t reserved11 : 21;
|
||||
};
|
||||
uint32_t val;
|
||||
} fram_num;
|
||||
union {
|
||||
struct {
|
||||
uint32_t in_ep0_state : 2; /*State of IN Endpoint 0.*/
|
||||
uint32_t in_ep0_wr_addr : 7; /*Write data address of IN endpoint 0.*/
|
||||
uint32_t in_ep0_rd_addr : 7; /*Read data address of IN endpoint 0.*/
|
||||
uint32_t reserved16 : 16; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} in_ep0_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t in_ep1_state : 2; /*State of IN Endpoint 1.*/
|
||||
uint32_t in_ep1_wr_addr : 7; /*Write data address of IN endpoint 1.*/
|
||||
uint32_t in_ep1_rd_addr : 7; /*Read data address of IN endpoint 1.*/
|
||||
uint32_t reserved16 : 16; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} in_ep1_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t in_ep2_state : 2; /*State of IN Endpoint 2.*/
|
||||
uint32_t in_ep2_wr_addr : 7; /*Write data address of IN endpoint 2.*/
|
||||
uint32_t in_ep2_rd_addr : 7; /*Read data address of IN endpoint 2.*/
|
||||
uint32_t reserved16 : 16; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} in_ep2_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t in_ep3_state : 2; /*State of IN Endpoint 3.*/
|
||||
uint32_t in_ep3_wr_addr : 7; /*Write data address of IN endpoint 3.*/
|
||||
uint32_t in_ep3_rd_addr : 7; /*Read data address of IN endpoint 3.*/
|
||||
uint32_t reserved16 : 16; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} in_ep3_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t out_ep0_state : 2; /*State of OUT Endpoint 0.*/
|
||||
uint32_t out_ep0_wr_addr : 7; /*Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected. there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0. */
|
||||
uint32_t out_ep0_rd_addr : 7; /*Read data address of OUT endpoint 0.*/
|
||||
uint32_t reserved16 : 16; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} out_ep0_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t out_ep1_state : 2; /*State of OUT Endpoint 1.*/
|
||||
uint32_t out_ep1_wr_addr : 7; /*Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected. there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.*/
|
||||
uint32_t out_ep1_rd_addr : 7; /*Read data address of OUT endpoint 1.*/
|
||||
uint32_t out_ep1_rec_data_cnt : 7; /*Data count in OUT endpoint 1 when one packet is received.*/
|
||||
uint32_t reserved23 : 9; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} out_ep1_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t out_ep2_state : 2; /*State of OUT Endpoint 2.*/
|
||||
uint32_t out_ep2_wr_addr : 7; /*Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is detected. there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.*/
|
||||
uint32_t out_ep2_rd_addr : 7; /*Read data address of OUT endpoint 2.*/
|
||||
uint32_t reserved16 : 16; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} out_ep2_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_en : 1; /*1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.*/
|
||||
uint32_t reserved1 : 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} misc_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t usb_mem_pd : 1; /*1: power down usb memory.*/
|
||||
uint32_t usb_mem_clk_en : 1; /*1: Force clock on for usb memory.*/
|
||||
uint32_t reserved2 : 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} mem_conf;
|
||||
uint32_t reserved_4c;
|
||||
uint32_t reserved_50;
|
||||
uint32_t reserved_54;
|
||||
uint32_t reserved_58;
|
||||
uint32_t reserved_5c;
|
||||
uint32_t reserved_60;
|
||||
uint32_t reserved_64;
|
||||
uint32_t reserved_68;
|
||||
uint32_t reserved_6c;
|
||||
uint32_t reserved_70;
|
||||
uint32_t reserved_74;
|
||||
uint32_t reserved_78;
|
||||
uint32_t reserved_7c;
|
||||
uint32_t date;
|
||||
} usb_serial_jtag_dev_t;
|
||||
extern usb_serial_jtag_dev_t USB_SERIAL_JTAG;
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /*_SOC_USB_SERIAL_JTAG_STRUCT_H_ */
|
||||
@@ -1,135 +0,0 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** XTS_AES_PLAIN_MEM register
|
||||
* The memory that stores plaintext
|
||||
*/
|
||||
#define XTS_AES_PLAIN_MEM (DR_REG_XTS_AES_BASE + 0x0)
|
||||
#define XTS_AES_PLAIN_MEM_SIZE_BYTES 16
|
||||
|
||||
/** XTS_AES_LINESIZE_REG register
|
||||
* XTS-AES line-size register
|
||||
*/
|
||||
#define XTS_AES_LINESIZE_REG (DR_REG_XTS_AES_BASE + 0x40)
|
||||
/** XTS_AES_LINESIZE : R/W; bitpos: [0]; default: 0;
|
||||
* This bit stores the line size parameter. 0: 16Byte, 1: 32Byte.
|
||||
*/
|
||||
#define XTS_AES_LINESIZE (BIT(0))
|
||||
#define XTS_AES_LINESIZE_M (XTS_AES_LINESIZE_V << XTS_AES_LINESIZE_S)
|
||||
#define XTS_AES_LINESIZE_V 0x00000001U
|
||||
#define XTS_AES_LINESIZE_S 0
|
||||
|
||||
/** XTS_AES_DESTINATION_REG register
|
||||
* XTS-AES destination register
|
||||
*/
|
||||
#define XTS_AES_DESTINATION_REG (DR_REG_XTS_AES_BASE + 0x44)
|
||||
/** XTS_AES_DESTINATION : R/W; bitpos: [0]; default: 0;
|
||||
* This bit stores the destination. 0: flash(default). 1: reserved.
|
||||
*/
|
||||
#define XTS_AES_DESTINATION (BIT(0))
|
||||
#define XTS_AES_DESTINATION_M (XTS_AES_DESTINATION_V << XTS_AES_DESTINATION_S)
|
||||
#define XTS_AES_DESTINATION_V 0x00000001U
|
||||
#define XTS_AES_DESTINATION_S 0
|
||||
|
||||
/** XTS_AES_PHYSICAL_ADDRESS_REG register
|
||||
* XTS-AES physical address register
|
||||
*/
|
||||
#define XTS_AES_PHYSICAL_ADDRESS_REG (DR_REG_XTS_AES_BASE + 0x48)
|
||||
/** XTS_AES_PHYSICAL_ADDRESS : R/W; bitpos: [29:0]; default: 0;
|
||||
* Those bits stores the physical address. If linesize is 16-byte, the physical
|
||||
* address should be aligned of 16 bytes. If linesize is 32-byte, the physical address
|
||||
* should be aligned of 32 bytes.
|
||||
*/
|
||||
#define XTS_AES_PHYSICAL_ADDRESS 0x3FFFFFFFU
|
||||
#define XTS_AES_PHYSICAL_ADDRESS_M (XTS_AES_PHYSICAL_ADDRESS_V << XTS_AES_PHYSICAL_ADDRESS_S)
|
||||
#define XTS_AES_PHYSICAL_ADDRESS_V 0x3FFFFFFFU
|
||||
#define XTS_AES_PHYSICAL_ADDRESS_S 0
|
||||
|
||||
/** XTS_AES_TRIGGER_REG register
|
||||
* XTS-AES trigger register
|
||||
*/
|
||||
#define XTS_AES_TRIGGER_REG (DR_REG_XTS_AES_BASE + 0x4c)
|
||||
/** XTS_AES_TRIGGER : WT; bitpos: [0]; default: 0;
|
||||
* Set this bit to start manual encryption calculation
|
||||
*/
|
||||
#define XTS_AES_TRIGGER (BIT(0))
|
||||
#define XTS_AES_TRIGGER_M (XTS_AES_TRIGGER_V << XTS_AES_TRIGGER_S)
|
||||
#define XTS_AES_TRIGGER_V 0x00000001U
|
||||
#define XTS_AES_TRIGGER_S 0
|
||||
|
||||
/** XTS_AES_RELEASE_REG register
|
||||
* XTS-AES release register
|
||||
*/
|
||||
#define XTS_AES_RELEASE_REG (DR_REG_XTS_AES_BASE + 0x50)
|
||||
/** XTS_AES_RELEASE : WT; bitpos: [0]; default: 0;
|
||||
* Set this bit to release the manual encrypted result, after that the result will be
|
||||
* visible to spi
|
||||
*/
|
||||
#define XTS_AES_RELEASE (BIT(0))
|
||||
#define XTS_AES_RELEASE_M (XTS_AES_RELEASE_V << XTS_AES_RELEASE_S)
|
||||
#define XTS_AES_RELEASE_V 0x00000001U
|
||||
#define XTS_AES_RELEASE_S 0
|
||||
|
||||
/** XTS_AES_DESTROY_REG register
|
||||
* XTS-AES destroy register
|
||||
*/
|
||||
#define XTS_AES_DESTROY_REG (DR_REG_XTS_AES_BASE + 0x54)
|
||||
/** XTS_AES_DESTROY : WT; bitpos: [0]; default: 0;
|
||||
* Set this bit to destroy XTS-AES result.
|
||||
*/
|
||||
#define XTS_AES_DESTROY (BIT(0))
|
||||
#define XTS_AES_DESTROY_M (XTS_AES_DESTROY_V << XTS_AES_DESTROY_S)
|
||||
#define XTS_AES_DESTROY_V 0x00000001U
|
||||
#define XTS_AES_DESTROY_S 0
|
||||
|
||||
/** XTS_AES_STATE_REG register
|
||||
* XTS-AES status register
|
||||
*/
|
||||
#define XTS_AES_STATE_REG (DR_REG_XTS_AES_BASE + 0x58)
|
||||
/** XTS_AES_STATE : RO; bitpos: [1:0]; default: 0;
|
||||
* Those bits shows XTS-AES status. 0=IDLE, 1=WORK, 2=RELEASE, 3=USE. IDLE means that
|
||||
* XTS-AES is idle. WORK means that XTS-AES is busy with calculation. RELEASE means
|
||||
* the encrypted result is generated but not visible to mspi. USE means that the
|
||||
* encrypted result is visible to mspi.
|
||||
*/
|
||||
#define XTS_AES_STATE 0x00000003U
|
||||
#define XTS_AES_STATE_M (XTS_AES_STATE_V << XTS_AES_STATE_S)
|
||||
#define XTS_AES_STATE_V 0x00000003U
|
||||
#define XTS_AES_STATE_S 0
|
||||
|
||||
/** XTS_AES_DATE_REG register
|
||||
* XTS-AES version control register
|
||||
*/
|
||||
#define XTS_AES_DATE_REG (DR_REG_XTS_AES_BASE + 0x5c)
|
||||
/** XTS_AES_DATE : R/W; bitpos: [29:0]; default: 538969635;
|
||||
* Those bits stores the version information of XTS-AES.
|
||||
*/
|
||||
#define XTS_AES_DATE 0x3FFFFFFFU
|
||||
#define XTS_AES_DATE_M (XTS_AES_DATE_V << XTS_AES_DATE_S)
|
||||
#define XTS_AES_DATE_V 0x3FFFFFFFU
|
||||
#define XTS_AES_DATE_S 0
|
||||
|
||||
/* For backward compatability with the older register names */
|
||||
#define AES_XTS_PLAIN_BASE XTS_AES_PLAIN_MEM
|
||||
#define AES_XTS_SIZE_REG XTS_AES_LINESIZE_REG
|
||||
#define AES_XTS_DESTINATION_REG XTS_AES_DESTINATION_REG
|
||||
#define AES_XTS_PHYSICAL_ADDR_REG XTS_AES_PHYSICAL_ADDRESS_REG
|
||||
#define AES_XTS_TRIGGER_REG XTS_AES_TRIGGER_REG
|
||||
#define AES_XTS_RELEASE_REG XTS_AES_RELEASE_REG
|
||||
#define AES_XTS_DESTROY_REG XTS_AES_DESTROY_REG
|
||||
#define AES_XTS_STATE_REG XTS_AES_STATE_REG
|
||||
#define AES_XTS_DATE_REG XTS_AES_DATE_REG
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
Reference in New Issue
Block a user