diff --git a/components/bootloader_support/bootloader_flash/include/esp_private/bootloader_flash_internal.h b/components/bootloader_support/bootloader_flash/include/esp_private/bootloader_flash_internal.h new file mode 100644 index 0000000000..4bff3f9dea --- /dev/null +++ b/components/bootloader_support/bootloader_flash/include/esp_private/bootloader_flash_internal.h @@ -0,0 +1,23 @@ +/* + * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Initialize spi_flash in bootloader and print flash info + * + * @return ESP_OK on success, otherwise see esp_err_t + */ +esp_err_t bootloader_init_spi_flash(void); + +#ifdef __cplusplus +} +#endif diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash.c index 26994f7291..da0b959e96 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash.c @@ -61,7 +61,7 @@ uint32_t bootloader_mmap_get_free_pages(void) const void *bootloader_mmap(uint32_t src_addr, uint32_t size) { if (map) { - ESP_LOGE(TAG, "tried to bootloader_mmap twice"); + ESP_EARLY_LOGE(TAG, "tried to bootloader_mmap twice"); return NULL; /* existing mapping in use... */ } const void *result = NULL; @@ -69,7 +69,7 @@ const void *bootloader_mmap(uint32_t src_addr, uint32_t size) size += (src_addr - src_page); esp_err_t err = spi_flash_mmap(src_page, size, SPI_FLASH_MMAP_DATA, &result, &map); if (err != ESP_OK) { - ESP_LOGE(TAG, "spi_flash_mmap failed: 0x%x", err); + ESP_EARLY_LOGE(TAG, "spi_flash_mmap failed: 0x%x", err); return NULL; } return (void *)((intptr_t)result + (src_addr - src_page)); @@ -334,15 +334,15 @@ static esp_err_t bootloader_flash_read_allow_decrypt(size_t src_addr, void *dest esp_err_t bootloader_flash_read(size_t src_addr, void *dest, size_t size, bool allow_decrypt) { if (src_addr & 3) { - ESP_LOGE(TAG, "bootloader_flash_read src_addr 0x%x not 4-byte aligned", src_addr); + ESP_EARLY_LOGE(TAG, "bootloader_flash_read src_addr 0x%x not 4-byte aligned", src_addr); return ESP_FAIL; } if (size & 3) { - ESP_LOGE(TAG, "bootloader_flash_read size 0x%x not 4-byte aligned", size); + ESP_EARLY_LOGE(TAG, "bootloader_flash_read size 0x%x not 4-byte aligned", size); return ESP_FAIL; } if ((intptr_t)dest & 3) { - ESP_LOGE(TAG, "bootloader_flash_read dest 0x%x not 4-byte aligned", (intptr_t)dest); + ESP_EARLY_LOGE(TAG, "bootloader_flash_read dest 0x%x not 4-byte aligned", (intptr_t)dest); return ESP_FAIL; } @@ -358,15 +358,15 @@ esp_err_t bootloader_flash_write(size_t dest_addr, void *src, size_t size, bool esp_err_t err; size_t alignment = write_encrypted ? 32 : 4; if ((dest_addr % alignment) != 0) { - ESP_LOGE(TAG, "bootloader_flash_write dest_addr 0x%x not %d-byte aligned", dest_addr, alignment); + ESP_EARLY_LOGE(TAG, "bootloader_flash_write dest_addr 0x%x not %d-byte aligned", dest_addr, alignment); return ESP_FAIL; } if ((size % alignment) != 0) { - ESP_LOGE(TAG, "bootloader_flash_write size 0x%x not %d-byte aligned", size, alignment); + ESP_EARLY_LOGE(TAG, "bootloader_flash_write size 0x%x not %d-byte aligned", size, alignment); return ESP_FAIL; } if (((intptr_t)src % 4) != 0) { - ESP_LOGE(TAG, "bootloader_flash_write src 0x%x not 4 byte aligned", (intptr_t)src); + ESP_EARLY_LOGE(TAG, "bootloader_flash_write src 0x%x not 4 byte aligned", (intptr_t)src); return ESP_FAIL; } @@ -650,7 +650,7 @@ esp_err_t bootloader_flash_wrap_set(spi_flash_wrap_mode_t mode) #define XMC_VENDOR_ID 0x20 #if BOOTLOADER_BUILD -#define BOOTLOADER_FLASH_LOG(level, ...) ESP_LOG##level(TAG, ##__VA_ARGS__) +#define BOOTLOADER_FLASH_LOG(level, ...) ESP_EARLY_LOG##level(TAG, ##__VA_ARGS__) #else static DRAM_ATTR char bootloader_flash_tag[] = "bootloader_flash"; #define BOOTLOADER_FLASH_LOG(level, ...) ESP_DRAM_LOG##level(bootloader_flash_tag, ##__VA_ARGS__) diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32.c index 9bda18434d..405d5c4582 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32.c @@ -12,6 +12,7 @@ #include "esp_rom_gpio.h" #include "esp_rom_efuse.h" #include "esp32/rom/spi_flash.h" +#include "esp32/rom/cache.h" #include "soc/gpio_periph.h" #include "soc/efuse_reg.h" #include "soc/spi_reg.h" @@ -23,6 +24,15 @@ #include "flash_qio_mode.h" #include "bootloader_common.h" #include "bootloader_flash_config.h" +#include "bootloader_flash_priv.h" +#include "bootloader_init.h" + +#define FLASH_CLK_IO SPI_CLK_GPIO_NUM +#define FLASH_CS_IO SPI_CS0_GPIO_NUM +#define FLASH_SPIQ_IO SPI_Q_GPIO_NUM +#define FLASH_SPID_IO SPI_D_GPIO_NUM +#define FLASH_SPIWP_IO SPI_WP_GPIO_NUM +#define FLASH_SPIHD_IO SPI_HD_GPIO_NUM void bootloader_flash_update_id(void) { @@ -183,3 +193,187 @@ int bootloader_flash_get_wp_pin(void) } #endif } + +static const char *TAG = "boot.esp32"; + +void bootloader_configure_spi_pins(int drv) +{ + uint32_t pkg_ver = bootloader_common_get_chip_ver_pkg(); + + if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 || + pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 || + pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 || + pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302) { + // For ESP32D2WD or ESP32-PICO series,the SPI pins are already configured + // flash clock signal should come from IO MUX. + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK); + SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S); + } else { + const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); + if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) { + esp_rom_gpio_connect_out_signal(FLASH_CS_IO, SPICS0_OUT_IDX, 0, 0); + esp_rom_gpio_connect_out_signal(FLASH_SPIQ_IO, SPIQ_OUT_IDX, 0, 0); + esp_rom_gpio_connect_in_signal(FLASH_SPIQ_IO, SPIQ_IN_IDX, 0); + esp_rom_gpio_connect_out_signal(FLASH_SPID_IO, SPID_OUT_IDX, 0, 0); + esp_rom_gpio_connect_in_signal(FLASH_SPID_IO, SPID_IN_IDX, 0); + esp_rom_gpio_connect_out_signal(FLASH_SPIWP_IO, SPIWP_OUT_IDX, 0, 0); + esp_rom_gpio_connect_in_signal(FLASH_SPIWP_IO, SPIWP_IN_IDX, 0); + esp_rom_gpio_connect_out_signal(FLASH_SPIHD_IO, SPIHD_OUT_IDX, 0, 0); + esp_rom_gpio_connect_in_signal(FLASH_SPIHD_IO, SPIHD_IN_IDX, 0); + //select pin function gpio + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA0_U, PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA1_U, PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA2_U, PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA3_U, PIN_FUNC_GPIO); + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CMD_U, PIN_FUNC_GPIO); + // flash clock signal should come from IO MUX. + // set drive ability for clock + gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK); + SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S); + +#if CONFIG_SPIRAM_TYPE_ESPPSRAM32 || CONFIG_SPIRAM_TYPE_ESPPSRAM64 + uint32_t flash_id = g_rom_flashchip.device_id; + if (flash_id == FLASH_ID_GD25LQ32C) { + // Set drive ability for 1.8v flash in 80Mhz. + SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_DATA0_U, FUN_DRV, 3, FUN_DRV_S); + SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_DATA1_U, FUN_DRV, 3, FUN_DRV_S); + SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_DATA2_U, FUN_DRV, 3, FUN_DRV_S); + SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_DATA3_U, FUN_DRV, 3, FUN_DRV_S); + SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CMD_U, FUN_DRV, 3, FUN_DRV_S); + SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, 3, FUN_DRV_S); + } +#endif + } + } +} + +static void update_flash_config(const esp_image_header_t *bootloader_hdr) +{ + uint32_t size; + switch (bootloader_hdr->spi_size) { + case ESP_IMAGE_FLASH_SIZE_1MB: + size = 1; + break; + case ESP_IMAGE_FLASH_SIZE_2MB: + size = 2; + break; + case ESP_IMAGE_FLASH_SIZE_4MB: + size = 4; + break; + case ESP_IMAGE_FLASH_SIZE_8MB: + size = 8; + break; + case ESP_IMAGE_FLASH_SIZE_16MB: + size = 16; + break; + default: + size = 2; + } + Cache_Read_Disable(0); + // Set flash chip size + esp_rom_spiflash_config_param(g_rom_flashchip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff); + // TODO: set mode + // TODO: set frequency + Cache_Flush(0); + Cache_Read_Enable(0); +} + +static void print_flash_info(const esp_image_header_t *bootloader_hdr) +{ + ESP_EARLY_LOGD(TAG, "magic %02x", bootloader_hdr->magic); + ESP_EARLY_LOGD(TAG, "segments %02x", bootloader_hdr->segment_count); + ESP_EARLY_LOGD(TAG, "spi_mode %02x", bootloader_hdr->spi_mode); + ESP_EARLY_LOGD(TAG, "spi_speed %02x", bootloader_hdr->spi_speed); + ESP_EARLY_LOGD(TAG, "spi_size %02x", bootloader_hdr->spi_size); + + const char *str; + switch (bootloader_hdr->spi_speed) { + case ESP_IMAGE_SPI_SPEED_DIV_2: + str = "40MHz"; + break; + case ESP_IMAGE_SPI_SPEED_DIV_3: + str = "26.7MHz"; + break; + case ESP_IMAGE_SPI_SPEED_DIV_4: + str = "20MHz"; + break; + case ESP_IMAGE_SPI_SPEED_DIV_1: + str = "80MHz"; + break; + default: + str = "20MHz"; + break; + } + ESP_EARLY_LOGI(TAG, "SPI Speed : %s", str); + + /* SPI mode could have been set to QIO during boot already, + so test the SPI registers not the flash header */ + uint32_t spi_ctrl = REG_READ(SPI_CTRL_REG(0)); + if (spi_ctrl & SPI_FREAD_QIO) { + str = "QIO"; + } else if (spi_ctrl & SPI_FREAD_QUAD) { + str = "QOUT"; + } else if (spi_ctrl & SPI_FREAD_DIO) { + str = "DIO"; + } else if (spi_ctrl & SPI_FREAD_DUAL) { + str = "DOUT"; + } else if (spi_ctrl & SPI_FASTRD_MODE) { + str = "FAST READ"; + } else { + str = "SLOW READ"; + } + ESP_EARLY_LOGI(TAG, "SPI Mode : %s", str); + + switch (bootloader_hdr->spi_size) { + case ESP_IMAGE_FLASH_SIZE_1MB: + str = "1MB"; + break; + case ESP_IMAGE_FLASH_SIZE_2MB: + str = "2MB"; + break; + case ESP_IMAGE_FLASH_SIZE_4MB: + str = "4MB"; + break; + case ESP_IMAGE_FLASH_SIZE_8MB: + str = "8MB"; + break; + case ESP_IMAGE_FLASH_SIZE_16MB: + str = "16MB"; + break; + default: + str = "2MB"; + break; + } + ESP_EARLY_LOGI(TAG, "SPI Flash Size : %s", str); +} + +static void IRAM_ATTR bootloader_init_flash_configure(void) +{ + bootloader_flash_gpio_config(&bootloader_image_hdr); + bootloader_flash_dummy_config(&bootloader_image_hdr); + bootloader_flash_cs_timing_config(); +} + +esp_err_t bootloader_init_spi_flash(void) +{ + bootloader_init_flash_configure(); +#ifndef CONFIG_SPI_FLASH_ROM_DRIVER_PATCH + const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); + if (spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_SPI && spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI) { + ESP_EARLY_LOGE(TAG, "SPI flash pins are overridden. Enable CONFIG_SPI_FLASH_ROM_DRIVER_PATCH in menuconfig"); + return ESP_FAIL; + } +#endif + + bootloader_flash_unlock(); + +#if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT + bootloader_enable_qio_mode(); +#endif + + print_flash_info(&bootloader_image_hdr); + update_flash_config(&bootloader_image_hdr); + //ensure the flash is write-protected + bootloader_enable_wp(); + return ESP_OK; +} diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c2.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c2.c index 809ab48e09..a18ccbd519 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c2.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c2.c @@ -9,6 +9,7 @@ #include "sdkconfig.h" #include "esp_err.h" #include "esp_log.h" +#include "esp_rom_gpio.h" #include "esp32c2/rom/gpio.h" #include "esp32c2/rom/spi_flash.h" #include "esp32c2/rom/efuse.h" @@ -20,6 +21,11 @@ #include "flash_qio_mode.h" #include "bootloader_flash_config.h" #include "bootloader_common.h" +#include "bootloader_flash_priv.h" +#include "bootloader_init.h" +#include "hal/mmu_hal.h" +#include "hal/cache_hal.h" +#include "hal/mmu_ll.h" #define FLASH_IO_MATRIX_DUMMY_40M 0 #define FLASH_IO_MATRIX_DUMMY_80M 0 @@ -70,3 +76,168 @@ void IRAM_ATTR bootloader_flash_dummy_config(const esp_image_header_t *pfhdr) bootloader_configure_spi_pins(1); bootloader_flash_set_dummy_out(); } + +static const char *TAG = "boot.esp32c2"; + + +void IRAM_ATTR bootloader_configure_spi_pins(int drv) +{ + // IDF-4066 + const uint32_t spiconfig = 0; + uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM; + uint8_t q_gpio_num = SPI_Q_GPIO_NUM; + uint8_t d_gpio_num = SPI_D_GPIO_NUM; + uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM; + uint8_t hd_gpio_num = SPI_HD_GPIO_NUM; + uint8_t wp_gpio_num = SPI_WP_GPIO_NUM; + if (spiconfig == 0) { + + } + esp_rom_gpio_pad_set_drv(clk_gpio_num, drv); + esp_rom_gpio_pad_set_drv(q_gpio_num, drv); + esp_rom_gpio_pad_set_drv(d_gpio_num, drv); + esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv); + if (hd_gpio_num <= MAX_PAD_GPIO_NUM) { + esp_rom_gpio_pad_set_drv(hd_gpio_num, drv); + } + if (wp_gpio_num <= MAX_PAD_GPIO_NUM) { + esp_rom_gpio_pad_set_drv(wp_gpio_num, drv); + } +} + +static void update_flash_config(const esp_image_header_t *bootloader_hdr) +{ + uint32_t size; + switch (bootloader_hdr->spi_size) { + case ESP_IMAGE_FLASH_SIZE_1MB: + size = 1; + break; + case ESP_IMAGE_FLASH_SIZE_2MB: + size = 2; + break; + case ESP_IMAGE_FLASH_SIZE_4MB: + size = 4; + break; + case ESP_IMAGE_FLASH_SIZE_8MB: + size = 8; + break; + case ESP_IMAGE_FLASH_SIZE_16MB: + size = 16; + break; + default: + size = 2; + } + cache_hal_disable(CACHE_TYPE_ALL); + // Set flash chip size + esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff); // TODO: set mode + cache_hal_enable(CACHE_TYPE_ALL); +} + +static void print_flash_info(const esp_image_header_t *bootloader_hdr) +{ + ESP_EARLY_LOGD(TAG, "magic %02x", bootloader_hdr->magic); + ESP_EARLY_LOGD(TAG, "segments %02x", bootloader_hdr->segment_count); + ESP_EARLY_LOGD(TAG, "spi_mode %02x", bootloader_hdr->spi_mode); + ESP_EARLY_LOGD(TAG, "spi_speed %02x", bootloader_hdr->spi_speed); + ESP_EARLY_LOGD(TAG, "spi_size %02x", bootloader_hdr->spi_size); + + const char *str; + switch (bootloader_hdr->spi_speed) { + case ESP_IMAGE_SPI_SPEED_DIV_2: + str = "30MHz"; + break; + case ESP_IMAGE_SPI_SPEED_DIV_3: + str = "20MHz"; + break; + case ESP_IMAGE_SPI_SPEED_DIV_4: + str = "15MHz"; + break; + case ESP_IMAGE_SPI_SPEED_DIV_1: + str = "60MHz"; + break; + default: + str = "15MHz"; + break; + } + ESP_EARLY_LOGI(TAG, "SPI Speed : %s", str); + + /* SPI mode could have been set to QIO during boot already, + so test the SPI registers not the flash header */ + uint32_t spi_ctrl = REG_READ(SPI_MEM_CTRL_REG(0)); + if (spi_ctrl & SPI_MEM_FREAD_QIO) { + str = "QIO"; + } else if (spi_ctrl & SPI_MEM_FREAD_QUAD) { + str = "QOUT"; + } else if (spi_ctrl & SPI_MEM_FREAD_DIO) { + str = "DIO"; + } else if (spi_ctrl & SPI_MEM_FREAD_DUAL) { + str = "DOUT"; + } else if (spi_ctrl & SPI_MEM_FASTRD_MODE) { + str = "FAST READ"; + } else { + str = "SLOW READ"; + } + ESP_EARLY_LOGI(TAG, "SPI Mode : %s", str); + + switch (bootloader_hdr->spi_size) { + case ESP_IMAGE_FLASH_SIZE_1MB: + str = "1MB"; + break; + case ESP_IMAGE_FLASH_SIZE_2MB: + str = "2MB"; + break; + case ESP_IMAGE_FLASH_SIZE_4MB: + str = "4MB"; + break; + case ESP_IMAGE_FLASH_SIZE_8MB: + str = "8MB"; + break; + case ESP_IMAGE_FLASH_SIZE_16MB: + str = "16MB"; + break; + default: + str = "2MB"; + break; + } + ESP_EARLY_LOGI(TAG, "SPI Flash Size : %s", str); +} + +static void bootloader_print_mmu_page_size(void) +{ + mmu_page_size_t page_size = mmu_ll_get_page_size(0); + int size = (page_size == MMU_PAGE_16KB ? 16 : + page_size == MMU_PAGE_32KB ? 32 : + page_size == MMU_PAGE_64KB ? 64 : 0); + ESP_EARLY_LOGI(TAG, "MMU Page Size : %dK", size); +} + +static void IRAM_ATTR bootloader_init_flash_configure(void) +{ + bootloader_flash_dummy_config(&bootloader_image_hdr); + bootloader_flash_cs_timing_config(); +} + +static void bootloader_spi_flash_resume(void) +{ + bootloader_execute_flash_command(CMD_RESUME, 0, 0, 0); + esp_rom_spiflash_wait_idle(&g_rom_flashchip); +} + +esp_err_t bootloader_init_spi_flash(void) +{ + bootloader_init_flash_configure(); + + bootloader_spi_flash_resume(); + bootloader_flash_unlock(); + +#if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT + bootloader_enable_qio_mode(); +#endif + + bootloader_print_mmu_page_size(); + print_flash_info(&bootloader_image_hdr); + update_flash_config(&bootloader_image_hdr); + //ensure the flash is write-protected + bootloader_enable_wp(); + return ESP_OK; +} diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c3.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c3.c index 52aecec883..b89eaa4a86 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c3.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c3.c @@ -9,6 +9,8 @@ #include "sdkconfig.h" #include "esp_err.h" #include "esp_log.h" +#include "esp_rom_gpio.h" +#include "esp_rom_efuse.h" #include "esp32c3/rom/gpio.h" #include "esp32c3/rom/spi_flash.h" #include "esp32c3/rom/efuse.h" @@ -20,6 +22,11 @@ #include "flash_qio_mode.h" #include "bootloader_flash_config.h" #include "bootloader_common.h" +#include "bootloader_flash_priv.h" +#include "bootloader_init.h" +#include "hal/mmu_hal.h" +#include "hal/cache_hal.h" +#include "hal/mmu_ll.h" #define FLASH_IO_MATRIX_DUMMY_40M 0 #define FLASH_IO_MATRIX_DUMMY_80M 0 @@ -73,3 +80,172 @@ void IRAM_ATTR bootloader_flash_dummy_config(const esp_image_header_t *pfhdr) bootloader_configure_spi_pins(1); bootloader_flash_set_dummy_out(); } + +static const char *TAG = "boot.esp32c3"; + + +void IRAM_ATTR bootloader_configure_spi_pins(int drv) +{ + const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); + uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio(); + uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM; + uint8_t q_gpio_num = SPI_Q_GPIO_NUM; + uint8_t d_gpio_num = SPI_D_GPIO_NUM; + uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM; + uint8_t hd_gpio_num = SPI_HD_GPIO_NUM; + uint8_t wp_gpio_num = SPI_WP_GPIO_NUM; + if (spiconfig == 0) { + + } else { + clk_gpio_num = spiconfig & 0x3f; + q_gpio_num = (spiconfig >> 6) & 0x3f; + d_gpio_num = (spiconfig >> 12) & 0x3f; + cs0_gpio_num = (spiconfig >> 18) & 0x3f; + hd_gpio_num = (spiconfig >> 24) & 0x3f; + wp_gpio_num = wp_pin; + } + esp_rom_gpio_pad_set_drv(clk_gpio_num, drv); + esp_rom_gpio_pad_set_drv(q_gpio_num, drv); + esp_rom_gpio_pad_set_drv(d_gpio_num, drv); + esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv); + if (hd_gpio_num <= MAX_PAD_GPIO_NUM) { + esp_rom_gpio_pad_set_drv(hd_gpio_num, drv); + } + if (wp_gpio_num <= MAX_PAD_GPIO_NUM) { + esp_rom_gpio_pad_set_drv(wp_gpio_num, drv); + } +} + +static void update_flash_config(const esp_image_header_t *bootloader_hdr) +{ + uint32_t size; + switch (bootloader_hdr->spi_size) { + case ESP_IMAGE_FLASH_SIZE_1MB: + size = 1; + break; + case ESP_IMAGE_FLASH_SIZE_2MB: + size = 2; + break; + case ESP_IMAGE_FLASH_SIZE_4MB: + size = 4; + break; + case ESP_IMAGE_FLASH_SIZE_8MB: + size = 8; + break; + case ESP_IMAGE_FLASH_SIZE_16MB: + size = 16; + break; + default: + size = 2; + } + cache_hal_disable(CACHE_TYPE_ALL); + // Set flash chip size + esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff); // TODO: set mode + cache_hal_enable(CACHE_TYPE_ALL); +} + +static void print_flash_info(const esp_image_header_t *bootloader_hdr) +{ + ESP_EARLY_LOGD(TAG, "magic %02x", bootloader_hdr->magic); + ESP_EARLY_LOGD(TAG, "segments %02x", bootloader_hdr->segment_count); + ESP_EARLY_LOGD(TAG, "spi_mode %02x", bootloader_hdr->spi_mode); + ESP_EARLY_LOGD(TAG, "spi_speed %02x", bootloader_hdr->spi_speed); + ESP_EARLY_LOGD(TAG, "spi_size %02x", bootloader_hdr->spi_size); + + const char *str; + switch (bootloader_hdr->spi_speed) { + case ESP_IMAGE_SPI_SPEED_DIV_2: + str = "40MHz"; + break; + case ESP_IMAGE_SPI_SPEED_DIV_3: + str = "26.7MHz"; + break; + case ESP_IMAGE_SPI_SPEED_DIV_4: + str = "20MHz"; + break; + case ESP_IMAGE_SPI_SPEED_DIV_1: + str = "80MHz"; + break; + default: + str = "20MHz"; + break; + } + ESP_EARLY_LOGI(TAG, "SPI Speed : %s", str); + + /* SPI mode could have been set to QIO during boot already, + so test the SPI registers not the flash header */ + uint32_t spi_ctrl = REG_READ(SPI_MEM_CTRL_REG(0)); + if (spi_ctrl & SPI_MEM_FREAD_QIO) { + str = "QIO"; + } else if (spi_ctrl & SPI_MEM_FREAD_QUAD) { + str = "QOUT"; + } else if (spi_ctrl & SPI_MEM_FREAD_DIO) { + str = "DIO"; + } else if (spi_ctrl & SPI_MEM_FREAD_DUAL) { + str = "DOUT"; + } else if (spi_ctrl & SPI_MEM_FASTRD_MODE) { + str = "FAST READ"; + } else { + str = "SLOW READ"; + } + ESP_EARLY_LOGI(TAG, "SPI Mode : %s", str); + + switch (bootloader_hdr->spi_size) { + case ESP_IMAGE_FLASH_SIZE_1MB: + str = "1MB"; + break; + case ESP_IMAGE_FLASH_SIZE_2MB: + str = "2MB"; + break; + case ESP_IMAGE_FLASH_SIZE_4MB: + str = "4MB"; + break; + case ESP_IMAGE_FLASH_SIZE_8MB: + str = "8MB"; + break; + case ESP_IMAGE_FLASH_SIZE_16MB: + str = "16MB"; + break; + default: + str = "2MB"; + break; + } + ESP_EARLY_LOGI(TAG, "SPI Flash Size : %s", str); +} + +static void IRAM_ATTR bootloader_init_flash_configure(void) +{ + bootloader_flash_dummy_config(&bootloader_image_hdr); + bootloader_flash_cs_timing_config(); +} + +static void bootloader_spi_flash_resume(void) +{ + bootloader_execute_flash_command(CMD_RESUME, 0, 0, 0); + esp_rom_spiflash_wait_idle(&g_rom_flashchip); +} + +esp_err_t bootloader_init_spi_flash(void) +{ + bootloader_init_flash_configure(); +#ifndef CONFIG_SPI_FLASH_ROM_DRIVER_PATCH + const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); + if (spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_SPI && spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI) { + ESP_EARLY_LOGE(TAG, "SPI flash pins are overridden. Enable CONFIG_SPI_FLASH_ROM_DRIVER_PATCH in menuconfig"); + return ESP_FAIL; + } +#endif + + bootloader_spi_flash_resume(); + bootloader_flash_unlock(); + +#if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT + bootloader_enable_qio_mode(); +#endif + + print_flash_info(&bootloader_image_hdr); + update_flash_config(&bootloader_image_hdr); + //ensure the flash is write-protected + bootloader_enable_wp(); + return ESP_OK; +} diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c6.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c6.c index 8fc1806ccd..a3bfb4607d 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c6.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c6.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,6 +9,8 @@ #include "sdkconfig.h" #include "esp_err.h" #include "esp_log.h" +#include "esp_rom_gpio.h" +#include "esp_rom_efuse.h" #include "esp32c6/rom/gpio.h" #include "esp32c6/rom/spi_flash.h" #include "esp32c6/rom/efuse.h" @@ -20,6 +22,11 @@ #include "flash_qio_mode.h" #include "bootloader_flash_config.h" #include "bootloader_common.h" +#include "bootloader_flash_priv.h" +#include "bootloader_init.h" +#include "hal/mmu_hal.h" +#include "hal/cache_hal.h" +#include "hal/mmu_ll.h" void bootloader_flash_update_id() { @@ -55,3 +62,147 @@ void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr) } esp_rom_spiflash_config_clk(spi_clk_div, 0); } + +static const char *TAG = "boot.esp32c6"; + +void IRAM_ATTR bootloader_configure_spi_pins(int drv) +{ + uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM; + uint8_t q_gpio_num = SPI_Q_GPIO_NUM; + uint8_t d_gpio_num = SPI_D_GPIO_NUM; + uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM; + uint8_t hd_gpio_num = SPI_HD_GPIO_NUM; + uint8_t wp_gpio_num = SPI_WP_GPIO_NUM; + esp_rom_gpio_pad_set_drv(clk_gpio_num, drv); + esp_rom_gpio_pad_set_drv(q_gpio_num, drv); + esp_rom_gpio_pad_set_drv(d_gpio_num, drv); + esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv); + esp_rom_gpio_pad_set_drv(hd_gpio_num, drv); + esp_rom_gpio_pad_set_drv(wp_gpio_num, drv); +} + +static void update_flash_config(const esp_image_header_t *bootloader_hdr) +{ + uint32_t size; + switch (bootloader_hdr->spi_size) { + case ESP_IMAGE_FLASH_SIZE_1MB: + size = 1; + break; + case ESP_IMAGE_FLASH_SIZE_2MB: + size = 2; + break; + case ESP_IMAGE_FLASH_SIZE_4MB: + size = 4; + break; + case ESP_IMAGE_FLASH_SIZE_8MB: + size = 8; + break; + case ESP_IMAGE_FLASH_SIZE_16MB: + size = 16; + break; + default: + size = 2; + } + cache_hal_disable(CACHE_TYPE_ALL); + // Set flash chip size + esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff); // TODO: set mode + cache_hal_enable(CACHE_TYPE_ALL); +} + +static void print_flash_info(const esp_image_header_t *bootloader_hdr) +{ + ESP_EARLY_LOGD(TAG, "magic %02x", bootloader_hdr->magic); + ESP_EARLY_LOGD(TAG, "segments %02x", bootloader_hdr->segment_count); + ESP_EARLY_LOGD(TAG, "spi_mode %02x", bootloader_hdr->spi_mode); + ESP_EARLY_LOGD(TAG, "spi_speed %02x", bootloader_hdr->spi_speed); + ESP_EARLY_LOGD(TAG, "spi_size %02x", bootloader_hdr->spi_size); + + const char *str; + switch (bootloader_hdr->spi_speed) { + case ESP_IMAGE_SPI_SPEED_DIV_2: + str = "40MHz"; + break; + case ESP_IMAGE_SPI_SPEED_DIV_3: + str = "26.7MHz"; + break; + case ESP_IMAGE_SPI_SPEED_DIV_4: + str = "20MHz"; + break; + case ESP_IMAGE_SPI_SPEED_DIV_1: + str = "80MHz"; + break; + default: + str = "20MHz"; + break; + } + ESP_EARLY_LOGI(TAG, "SPI Speed : %s", str); + + /* SPI mode could have been set to QIO during boot already, + so test the SPI registers not the flash header */ + uint32_t spi_ctrl = REG_READ(SPI_MEM_CTRL_REG(0)); + if (spi_ctrl & SPI_MEM_FREAD_QIO) { + str = "QIO"; + } else if (spi_ctrl & SPI_MEM_FREAD_QUAD) { + str = "QOUT"; + } else if (spi_ctrl & SPI_MEM_FREAD_DIO) { + str = "DIO"; + } else if (spi_ctrl & SPI_MEM_FREAD_DUAL) { + str = "DOUT"; + } else if (spi_ctrl & SPI_MEM_FASTRD_MODE) { + str = "FAST READ"; + } else { + str = "SLOW READ"; + } + ESP_EARLY_LOGI(TAG, "SPI Mode : %s", str); + + switch (bootloader_hdr->spi_size) { + case ESP_IMAGE_FLASH_SIZE_1MB: + str = "1MB"; + break; + case ESP_IMAGE_FLASH_SIZE_2MB: + str = "2MB"; + break; + case ESP_IMAGE_FLASH_SIZE_4MB: + str = "4MB"; + break; + case ESP_IMAGE_FLASH_SIZE_8MB: + str = "8MB"; + break; + case ESP_IMAGE_FLASH_SIZE_16MB: + str = "16MB"; + break; + default: + str = "2MB"; + break; + } + ESP_EARLY_LOGI(TAG, "SPI Flash Size : %s", str); +} + +static void IRAM_ATTR bootloader_init_flash_configure(void) +{ + bootloader_configure_spi_pins(1); + bootloader_flash_cs_timing_config(); +} + +static void bootloader_spi_flash_resume(void) +{ + bootloader_execute_flash_command(CMD_RESUME, 0, 0, 0); + esp_rom_spiflash_wait_idle(&g_rom_flashchip); +} + +esp_err_t bootloader_init_spi_flash(void) +{ + bootloader_init_flash_configure(); + bootloader_spi_flash_resume(); + bootloader_flash_unlock(); + +#if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT + bootloader_enable_qio_mode(); +#endif + + print_flash_info(&bootloader_image_hdr); + update_flash_config(&bootloader_image_hdr); + //ensure the flash is write-protected + bootloader_enable_wp(); + return ESP_OK; +} diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h2.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h2.c index ae5e8a96cd..147be37990 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h2.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h2.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,6 +9,8 @@ #include "sdkconfig.h" #include "esp_err.h" #include "esp_log.h" +#include "esp_rom_gpio.h" +#include "esp_rom_efuse.h" #include "esp32h2/rom/gpio.h" #include "esp32h2/rom/spi_flash.h" #include "esp32h2/rom/efuse.h" @@ -20,6 +22,11 @@ #include "flash_qio_mode.h" #include "bootloader_flash_config.h" #include "bootloader_common.h" +#include "bootloader_flash_priv.h" +#include "bootloader_init.h" +#include "hal/mmu_hal.h" +#include "hal/cache_hal.h" +#include "hal/mmu_ll.h" void bootloader_flash_update_id() { @@ -55,3 +62,147 @@ void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr) } esp_rom_spiflash_config_clk(spi_clk_div, 0); } + +static const char *TAG = "boot.esp32h2"; + +void IRAM_ATTR bootloader_configure_spi_pins(int drv) +{ + uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM; + uint8_t q_gpio_num = SPI_Q_GPIO_NUM; + uint8_t d_gpio_num = SPI_D_GPIO_NUM; + uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM; + uint8_t hd_gpio_num = SPI_HD_GPIO_NUM; + uint8_t wp_gpio_num = SPI_WP_GPIO_NUM; + esp_rom_gpio_pad_set_drv(clk_gpio_num, drv); + esp_rom_gpio_pad_set_drv(q_gpio_num, drv); + esp_rom_gpio_pad_set_drv(d_gpio_num, drv); + esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv); + esp_rom_gpio_pad_set_drv(hd_gpio_num, drv); + esp_rom_gpio_pad_set_drv(wp_gpio_num, drv); +} + +static void update_flash_config(const esp_image_header_t *bootloader_hdr) +{ + uint32_t size; + switch (bootloader_hdr->spi_size) { + case ESP_IMAGE_FLASH_SIZE_1MB: + size = 1; + break; + case ESP_IMAGE_FLASH_SIZE_2MB: + size = 2; + break; + case ESP_IMAGE_FLASH_SIZE_4MB: + size = 4; + break; + case ESP_IMAGE_FLASH_SIZE_8MB: + size = 8; + break; + case ESP_IMAGE_FLASH_SIZE_16MB: + size = 16; + break; + default: + size = 2; + } + cache_hal_disable(CACHE_TYPE_ALL); + // Set flash chip size + esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff); // TODO: set mode + cache_hal_enable(CACHE_TYPE_ALL); +} + +static void print_flash_info(const esp_image_header_t *bootloader_hdr) +{ + ESP_EARLY_LOGD(TAG, "magic %02x", bootloader_hdr->magic); + ESP_EARLY_LOGD(TAG, "segments %02x", bootloader_hdr->segment_count); + ESP_EARLY_LOGD(TAG, "spi_mode %02x", bootloader_hdr->spi_mode); + ESP_EARLY_LOGD(TAG, "spi_speed %02x", bootloader_hdr->spi_speed); + ESP_EARLY_LOGD(TAG, "spi_size %02x", bootloader_hdr->spi_size); + + const char *str; + switch (bootloader_hdr->spi_speed) { + case ESP_IMAGE_SPI_SPEED_DIV_2: + str = "40MHz"; + break; + case ESP_IMAGE_SPI_SPEED_DIV_3: + str = "26.7MHz"; + break; + case ESP_IMAGE_SPI_SPEED_DIV_4: + str = "20MHz"; + break; + case ESP_IMAGE_SPI_SPEED_DIV_1: + str = "80MHz"; + break; + default: + str = "20MHz"; + break; + } + ESP_LOGI(TAG, "SPI Speed : %s", str); + + /* SPI mode could have been set to QIO during boot already, + so test the SPI registers not the flash header */ + uint32_t spi_ctrl = REG_READ(SPI_MEM_CTRL_REG(0)); + if (spi_ctrl & SPI_MEM_FREAD_QIO) { + str = "QIO"; + } else if (spi_ctrl & SPI_MEM_FREAD_QUAD) { + str = "QOUT"; + } else if (spi_ctrl & SPI_MEM_FREAD_DIO) { + str = "DIO"; + } else if (spi_ctrl & SPI_MEM_FREAD_DUAL) { + str = "DOUT"; + } else if (spi_ctrl & SPI_MEM_FASTRD_MODE) { + str = "FAST READ"; + } else { + str = "SLOW READ"; + } + ESP_LOGI(TAG, "SPI Mode : %s", str); + + switch (bootloader_hdr->spi_size) { + case ESP_IMAGE_FLASH_SIZE_1MB: + str = "1MB"; + break; + case ESP_IMAGE_FLASH_SIZE_2MB: + str = "2MB"; + break; + case ESP_IMAGE_FLASH_SIZE_4MB: + str = "4MB"; + break; + case ESP_IMAGE_FLASH_SIZE_8MB: + str = "8MB"; + break; + case ESP_IMAGE_FLASH_SIZE_16MB: + str = "16MB"; + break; + default: + str = "2MB"; + break; + } + ESP_LOGI(TAG, "SPI Flash Size : %s", str); +} + +static void IRAM_ATTR bootloader_init_flash_configure(void) +{ + bootloader_configure_spi_pins(1); + bootloader_flash_cs_timing_config(); +} + +static void bootloader_spi_flash_resume(void) +{ + bootloader_execute_flash_command(CMD_RESUME, 0, 0, 0); + esp_rom_spiflash_wait_idle(&g_rom_flashchip); +} + +esp_err_t bootloader_init_spi_flash(void) +{ + bootloader_init_flash_configure(); + bootloader_spi_flash_resume(); + bootloader_flash_unlock(); + +#if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT + bootloader_enable_qio_mode(); +#endif + + print_flash_info(&bootloader_image_hdr); + update_flash_config(&bootloader_image_hdr); + //ensure the flash is write-protected + bootloader_enable_wp(); + return ESP_OK; +} diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h4.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h4.c index 1beecfe2d9..8281f42682 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h4.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32h4.c @@ -9,6 +9,8 @@ #include "sdkconfig.h" #include "esp_err.h" #include "esp_log.h" +#include "esp_rom_gpio.h" +#include "esp_rom_efuse.h" #include "esp32h4/rom/gpio.h" #include "esp32h4/rom/spi_flash.h" #include "esp32h4/rom/efuse.h" @@ -20,6 +22,11 @@ #include "flash_qio_mode.h" #include "bootloader_flash_config.h" #include "bootloader_common.h" +#include "bootloader_flash_priv.h" +#include "bootloader_init.h" +#include "hal/mmu_hal.h" +#include "hal/cache_hal.h" +#include "hal/mmu_ll.h" #define FLASH_IO_MATRIX_DUMMY_40M 0 #define FLASH_IO_MATRIX_DUMMY_80M 0 @@ -73,3 +80,171 @@ void IRAM_ATTR bootloader_flash_dummy_config(const esp_image_header_t *pfhdr) bootloader_configure_spi_pins(1); bootloader_flash_set_dummy_out(); } + +static const char *TAG = "boot.esp32h4"; + +void IRAM_ATTR bootloader_configure_spi_pins(int drv) +{ + const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); + uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio(); + uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM; + uint8_t q_gpio_num = SPI_Q_GPIO_NUM; + uint8_t d_gpio_num = SPI_D_GPIO_NUM; + uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM; + uint8_t hd_gpio_num = SPI_HD_GPIO_NUM; + uint8_t wp_gpio_num = SPI_WP_GPIO_NUM; + if (spiconfig == 0) { + + } else { + clk_gpio_num = spiconfig & 0x3f; + q_gpio_num = (spiconfig >> 6) & 0x3f; + d_gpio_num = (spiconfig >> 12) & 0x3f; + cs0_gpio_num = (spiconfig >> 18) & 0x3f; + hd_gpio_num = (spiconfig >> 24) & 0x3f; + wp_gpio_num = wp_pin; + } + esp_rom_gpio_pad_set_drv(clk_gpio_num, drv); + esp_rom_gpio_pad_set_drv(q_gpio_num, drv); + esp_rom_gpio_pad_set_drv(d_gpio_num, drv); + esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv); + if (hd_gpio_num <= MAX_PAD_GPIO_NUM) { + esp_rom_gpio_pad_set_drv(hd_gpio_num, drv); + } + if (wp_gpio_num <= MAX_PAD_GPIO_NUM) { + esp_rom_gpio_pad_set_drv(wp_gpio_num, drv); + } +} + +static void update_flash_config(const esp_image_header_t *bootloader_hdr) +{ + uint32_t size; + switch (bootloader_hdr->spi_size) { + case ESP_IMAGE_FLASH_SIZE_1MB: + size = 1; + break; + case ESP_IMAGE_FLASH_SIZE_2MB: + size = 2; + break; + case ESP_IMAGE_FLASH_SIZE_4MB: + size = 4; + break; + case ESP_IMAGE_FLASH_SIZE_8MB: + size = 8; + break; + case ESP_IMAGE_FLASH_SIZE_16MB: + size = 16; + break; + default: + size = 2; + } + cache_hal_disable(CACHE_TYPE_ALL); + // Set flash chip size + esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff); // TODO: set mode + cache_hal_enable(CACHE_TYPE_ALL); +} + +static void print_flash_info(const esp_image_header_t *bootloader_hdr) +{ + ESP_EARLY_LOGD(TAG, "magic %02x", bootloader_hdr->magic); + ESP_EARLY_LOGD(TAG, "segments %02x", bootloader_hdr->segment_count); + ESP_EARLY_LOGD(TAG, "spi_mode %02x", bootloader_hdr->spi_mode); + ESP_EARLY_LOGD(TAG, "spi_speed %02x", bootloader_hdr->spi_speed); + ESP_EARLY_LOGD(TAG, "spi_size %02x", bootloader_hdr->spi_size); + + const char *str; + switch (bootloader_hdr->spi_speed) { + case ESP_IMAGE_SPI_SPEED_DIV_2: + str = "24MHz"; + break; + case ESP_IMAGE_SPI_SPEED_DIV_3: + str = "16MHz"; + break; + case ESP_IMAGE_SPI_SPEED_DIV_4: + str = "12MHz"; + break; + case ESP_IMAGE_SPI_SPEED_DIV_1: + str = "48MHz"; + break; + default: + str = "12MHz"; + break; + } + ESP_EARLY_LOGI(TAG, "SPI Speed : %s", str); + + /* SPI mode could have been set to QIO during boot already, + so test the SPI registers not the flash header */ + uint32_t spi_ctrl = REG_READ(SPI_MEM_CTRL_REG(0)); + if (spi_ctrl & SPI_MEM_FREAD_QIO) { + str = "QIO"; + } else if (spi_ctrl & SPI_MEM_FREAD_QUAD) { + str = "QOUT"; + } else if (spi_ctrl & SPI_MEM_FREAD_DIO) { + str = "DIO"; + } else if (spi_ctrl & SPI_MEM_FREAD_DUAL) { + str = "DOUT"; + } else if (spi_ctrl & SPI_MEM_FASTRD_MODE) { + str = "FAST READ"; + } else { + str = "SLOW READ"; + } + ESP_EARLY_LOGI(TAG, "SPI Mode : %s", str); + + switch (bootloader_hdr->spi_size) { + case ESP_IMAGE_FLASH_SIZE_1MB: + str = "1MB"; + break; + case ESP_IMAGE_FLASH_SIZE_2MB: + str = "2MB"; + break; + case ESP_IMAGE_FLASH_SIZE_4MB: + str = "4MB"; + break; + case ESP_IMAGE_FLASH_SIZE_8MB: + str = "8MB"; + break; + case ESP_IMAGE_FLASH_SIZE_16MB: + str = "16MB"; + break; + default: + str = "2MB"; + break; + } + ESP_EARLY_LOGI(TAG, "SPI Flash Size : %s", str); +} + +static void IRAM_ATTR bootloader_init_flash_configure(void) +{ + bootloader_flash_dummy_config(&bootloader_image_hdr); + bootloader_flash_cs_timing_config(); +} + +static void bootloader_spi_flash_resume(void) +{ + bootloader_execute_flash_command(CMD_RESUME, 0, 0, 0); + esp_rom_spiflash_wait_idle(&g_rom_flashchip); +} + +esp_err_t bootloader_init_spi_flash(void) +{ + bootloader_init_flash_configure(); +#ifndef CONFIG_SPI_FLASH_ROM_DRIVER_PATCH + const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); + if (spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_SPI && spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI) { + ESP_EARLY_LOGE(TAG, "SPI flash pins are overridden. Enable CONFIG_SPI_FLASH_ROM_DRIVER_PATCH in menuconfig"); + return ESP_FAIL; + } +#endif + + bootloader_spi_flash_resume(); + bootloader_flash_unlock(); + +#if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT + bootloader_enable_qio_mode(); +#endif + + print_flash_info(&bootloader_image_hdr); + update_flash_config(&bootloader_image_hdr); + //ensure the flash is write-protected + bootloader_enable_wp(); + return ESP_OK; +} diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s2.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s2.c index da0c4b1684..94d8a4fd88 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s2.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s2.c @@ -9,14 +9,21 @@ #include "sdkconfig.h" #include "esp_err.h" #include "esp_log.h" +#include "esp_rom_gpio.h" +#include "esp_rom_efuse.h" #include "esp32s2/rom/spi_flash.h" #include "soc/efuse_reg.h" +#include "soc/io_mux_reg.h" #include "soc/spi_reg.h" #include "soc/spi_mem_reg.h" #include "soc/soc_caps.h" #include "flash_qio_mode.h" #include "bootloader_flash_config.h" +#include "bootloader_flash_priv.h" #include "bootloader_common.h" +#include "bootloader_init.h" +#include "hal/mmu_hal.h" +#include "hal/cache_hal.h" #define FLASH_IO_MATRIX_DUMMY_40M 0 #define FLASH_IO_MATRIX_DUMMY_80M 0 @@ -77,3 +84,184 @@ void IRAM_ATTR bootloader_flash_dummy_config(const esp_image_header_t* pfhdr) bootloader_configure_spi_pins(1); bootloader_flash_set_dummy_out(); } + +static const char *TAG = "boot.esp32s2"; + +void IRAM_ATTR bootloader_configure_spi_pins(int drv) +{ + const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); + uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio(); + uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM; + uint8_t q_gpio_num = SPI_Q_GPIO_NUM; + uint8_t d_gpio_num = SPI_D_GPIO_NUM; + uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM; + uint8_t hd_gpio_num = SPI_HD_GPIO_NUM; + uint8_t wp_gpio_num = SPI_WP_GPIO_NUM; + if (spiconfig == 0) { + + } else { + clk_gpio_num = spiconfig & 0x3f; + q_gpio_num = (spiconfig >> 6) & 0x3f; + d_gpio_num = (spiconfig >> 12) & 0x3f; + cs0_gpio_num = (spiconfig >> 18) & 0x3f; + hd_gpio_num = (spiconfig >> 24) & 0x3f; + wp_gpio_num = wp_pin; + } + esp_rom_gpio_pad_set_drv(clk_gpio_num, drv); + esp_rom_gpio_pad_set_drv(q_gpio_num, drv); + esp_rom_gpio_pad_set_drv(d_gpio_num, drv); + esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv); + if (hd_gpio_num <= MAX_PAD_GPIO_NUM) { + esp_rom_gpio_pad_set_drv(hd_gpio_num, drv); + } + if (wp_gpio_num <= MAX_PAD_GPIO_NUM) { + esp_rom_gpio_pad_set_drv(wp_gpio_num, drv); + } +} + +static void update_flash_config(const esp_image_header_t *bootloader_hdr) +{ + uint32_t size; + switch (bootloader_hdr->spi_size) { + case ESP_IMAGE_FLASH_SIZE_1MB: + size = 1; + break; + case ESP_IMAGE_FLASH_SIZE_2MB: + size = 2; + break; + case ESP_IMAGE_FLASH_SIZE_4MB: + size = 4; + break; + case ESP_IMAGE_FLASH_SIZE_8MB: + size = 8; + break; + case ESP_IMAGE_FLASH_SIZE_16MB: + size = 16; + break; + case ESP_IMAGE_FLASH_SIZE_32MB: + size = 32; + break; + case ESP_IMAGE_FLASH_SIZE_64MB: + size = 64; + break; + case ESP_IMAGE_FLASH_SIZE_128MB: + size = 128; + break; + default: + size = 2; + } + cache_hal_disable(CACHE_TYPE_ALL); + // Set flash chip size + esp_rom_spiflash_config_param(g_rom_flashchip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff); + // TODO: set mode + // TODO: set frequency + cache_hal_enable(CACHE_TYPE_ALL); +} + +static void print_flash_info(const esp_image_header_t *bootloader_hdr) +{ + ESP_EARLY_LOGD(TAG, "magic %02x", bootloader_hdr->magic); + ESP_EARLY_LOGD(TAG, "segments %02x", bootloader_hdr->segment_count); + ESP_EARLY_LOGD(TAG, "spi_mode %02x", bootloader_hdr->spi_mode); + ESP_EARLY_LOGD(TAG, "spi_speed %02x", bootloader_hdr->spi_speed); + ESP_EARLY_LOGD(TAG, "spi_size %02x", bootloader_hdr->spi_size); + + const char *str; + switch (bootloader_hdr->spi_speed) { + case ESP_IMAGE_SPI_SPEED_DIV_2: + str = "40MHz"; + break; + case ESP_IMAGE_SPI_SPEED_DIV_3: + str = "26.7MHz"; + break; + case ESP_IMAGE_SPI_SPEED_DIV_4: + str = "20MHz"; + break; + case ESP_IMAGE_SPI_SPEED_DIV_1: + str = "80MHz"; + break; + default: + str = "20MHz"; + break; + } + ESP_EARLY_LOGI(TAG, "SPI Speed : %s", str); + + /* SPI mode could have been set to QIO during boot already, + so test the SPI registers not the flash header */ + uint32_t spi_ctrl = REG_READ(SPI_MEM_CTRL_REG(0)); + if (spi_ctrl & SPI_MEM_FREAD_QIO) { + str = "QIO"; + } else if (spi_ctrl & SPI_MEM_FREAD_QUAD) { + str = "QOUT"; + } else if (spi_ctrl & SPI_MEM_FREAD_DIO) { + str = "DIO"; + } else if (spi_ctrl & SPI_MEM_FREAD_DUAL) { + str = "DOUT"; + } else if (spi_ctrl & SPI_MEM_FASTRD_MODE) { + str = "FAST READ"; + } else { + str = "SLOW READ"; + } + ESP_EARLY_LOGI(TAG, "SPI Mode : %s", str); + + switch (bootloader_hdr->spi_size) { + case ESP_IMAGE_FLASH_SIZE_1MB: + str = "1MB"; + break; + case ESP_IMAGE_FLASH_SIZE_2MB: + str = "2MB"; + break; + case ESP_IMAGE_FLASH_SIZE_4MB: + str = "4MB"; + break; + case ESP_IMAGE_FLASH_SIZE_8MB: + str = "8MB"; + break; + case ESP_IMAGE_FLASH_SIZE_16MB: + str = "16MB"; + break; + case ESP_IMAGE_FLASH_SIZE_32MB: + str = "32MB"; + break; + case ESP_IMAGE_FLASH_SIZE_64MB: + str = "64MB"; + break; + case ESP_IMAGE_FLASH_SIZE_128MB: + str = "128MB"; + break; + default: + str = "2MB"; + break; + } + ESP_EARLY_LOGI(TAG, "SPI Flash Size : %s", str); +} + +static void IRAM_ATTR bootloader_init_flash_configure(void) +{ + bootloader_flash_dummy_config(&bootloader_image_hdr); + bootloader_flash_cs_timing_config(); +} + +esp_err_t bootloader_init_spi_flash(void) +{ + bootloader_init_flash_configure(); +#ifndef CONFIG_SPI_FLASH_ROM_DRIVER_PATCH + const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); + if (spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_SPI && spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI) { + ESP_EARLY_LOGE(TAG, "SPI flash pins are overridden. Enable CONFIG_SPI_FLASH_ROM_DRIVER_PATCH in menuconfig"); + return ESP_FAIL; + } +#endif + + bootloader_flash_unlock(); + +#if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT + bootloader_enable_qio_mode(); +#endif + + print_flash_info(&bootloader_image_hdr); + update_flash_config(&bootloader_image_hdr); + //ensure the flash is write-protected + bootloader_enable_wp(); + return ESP_OK; +} diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s3.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s3.c index 9146ef5431..151e469f3b 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s3.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s3.c @@ -9,15 +9,22 @@ #include "sdkconfig.h" #include "esp_err.h" #include "esp_log.h" +#include "esp_rom_gpio.h" +#include "esp_rom_efuse.h" #include "esp32s3/rom/spi_flash.h" #include "soc/efuse_reg.h" +#include "soc/io_mux_reg.h" #include "soc/spi_reg.h" #include "soc/spi_mem_reg.h" #include "soc/soc_caps.h" #include "flash_qio_mode.h" #include "bootloader_flash_config.h" +#include "bootloader_flash_priv.h" #include "bootloader_common.h" #include "bootloader_flash.h" +#include "bootloader_init.h" +#include "hal/mmu_hal.h" +#include "hal/cache_hal.h" #define FLASH_IO_MATRIX_DUMMY_40M 0 #define FLASH_IO_MATRIX_DUMMY_80M 0 @@ -83,3 +90,192 @@ void IRAM_ATTR bootloader_flash_dummy_config(const esp_image_header_t *pfhdr) bootloader_configure_spi_pins(1); bootloader_flash_set_dummy_out(); } + +static const char *TAG = "boot.esp32s3"; + +void IRAM_ATTR bootloader_configure_spi_pins(int drv) +{ + const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); + uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio(); + uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM; + uint8_t q_gpio_num = SPI_Q_GPIO_NUM; + uint8_t d_gpio_num = SPI_D_GPIO_NUM; + uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM; + uint8_t hd_gpio_num = SPI_HD_GPIO_NUM; + uint8_t wp_gpio_num = SPI_WP_GPIO_NUM; + if (spiconfig == 0) { + + } else { + clk_gpio_num = spiconfig & 0x3f; + q_gpio_num = (spiconfig >> 6) & 0x3f; + d_gpio_num = (spiconfig >> 12) & 0x3f; + cs0_gpio_num = (spiconfig >> 18) & 0x3f; + hd_gpio_num = (spiconfig >> 24) & 0x3f; + wp_gpio_num = wp_pin; + } + esp_rom_gpio_pad_set_drv(clk_gpio_num, drv); + esp_rom_gpio_pad_set_drv(q_gpio_num, drv); + esp_rom_gpio_pad_set_drv(d_gpio_num, drv); + esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv); + if (hd_gpio_num <= MAX_PAD_GPIO_NUM) { + esp_rom_gpio_pad_set_drv(hd_gpio_num, drv); + } + if (wp_gpio_num <= MAX_PAD_GPIO_NUM) { + esp_rom_gpio_pad_set_drv(wp_gpio_num, drv); + } +} + +static void update_flash_config(const esp_image_header_t *bootloader_hdr) +{ + uint32_t size; + switch (bootloader_hdr->spi_size) { + case ESP_IMAGE_FLASH_SIZE_1MB: + size = 1; + break; + case ESP_IMAGE_FLASH_SIZE_2MB: + size = 2; + break; + case ESP_IMAGE_FLASH_SIZE_4MB: + size = 4; + break; + case ESP_IMAGE_FLASH_SIZE_8MB: + size = 8; + break; + case ESP_IMAGE_FLASH_SIZE_16MB: + size = 16; + break; + case ESP_IMAGE_FLASH_SIZE_32MB: + size = 32; + break; + case ESP_IMAGE_FLASH_SIZE_64MB: + size = 64; + break; + case ESP_IMAGE_FLASH_SIZE_128MB: + size = 128; + break; + default: + size = 2; + } + + cache_hal_disable(CACHE_TYPE_ALL); + // Set flash chip size + esp_rom_spiflash_config_param(g_rom_flashchip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff); + // TODO: set mode + // TODO: set frequency + cache_hal_enable(CACHE_TYPE_ALL); +} + +static void print_flash_info(const esp_image_header_t *bootloader_hdr) +{ + ESP_EARLY_LOGD(TAG, "magic %02x", bootloader_hdr->magic); + ESP_EARLY_LOGD(TAG, "segments %02x", bootloader_hdr->segment_count); + ESP_EARLY_LOGD(TAG, "spi_mode %02x", bootloader_hdr->spi_mode); + ESP_EARLY_LOGD(TAG, "spi_speed %02x", bootloader_hdr->spi_speed); + ESP_EARLY_LOGD(TAG, "spi_size %02x", bootloader_hdr->spi_size); + + const char *str; + switch (bootloader_hdr->spi_speed) { + case ESP_IMAGE_SPI_SPEED_DIV_2: + str = "40MHz"; + break; + case ESP_IMAGE_SPI_SPEED_DIV_3: + str = "26.7MHz"; + break; + case ESP_IMAGE_SPI_SPEED_DIV_4: + str = "20MHz"; + break; + case ESP_IMAGE_SPI_SPEED_DIV_1: + str = "80MHz"; + break; + default: + str = "20MHz"; + break; + } + ESP_EARLY_LOGI(TAG, "Boot SPI Speed : %s", str); + + /* SPI mode could have been set to QIO during boot already, + so test the SPI registers not the flash header */ + uint32_t spi_ctrl = REG_READ(SPI_MEM_CTRL_REG(0)); + if (spi_ctrl & SPI_MEM_FREAD_QIO) { + str = "QIO"; + } else if (spi_ctrl & SPI_MEM_FREAD_QUAD) { + str = "QOUT"; + } else if (spi_ctrl & SPI_MEM_FREAD_DIO) { + str = "DIO"; + } else if (spi_ctrl & SPI_MEM_FREAD_DUAL) { + str = "DOUT"; + } else if (spi_ctrl & SPI_MEM_FASTRD_MODE) { + str = "FAST READ"; + } else { + str = "SLOW READ"; + } + ESP_EARLY_LOGI(TAG, "SPI Mode : %s", str); + + switch (bootloader_hdr->spi_size) { + case ESP_IMAGE_FLASH_SIZE_1MB: + str = "1MB"; + break; + case ESP_IMAGE_FLASH_SIZE_2MB: + str = "2MB"; + break; + case ESP_IMAGE_FLASH_SIZE_4MB: + str = "4MB"; + break; + case ESP_IMAGE_FLASH_SIZE_8MB: + str = "8MB"; + break; + case ESP_IMAGE_FLASH_SIZE_16MB: + str = "16MB"; + break; + case ESP_IMAGE_FLASH_SIZE_32MB: + str = "32MB"; + break; + case ESP_IMAGE_FLASH_SIZE_64MB: + str = "64MB"; + break; + case ESP_IMAGE_FLASH_SIZE_128MB: + str = "128MB"; + break; + default: + str = "2MB"; + break; + } + ESP_EARLY_LOGI(TAG, "SPI Flash Size : %s", str); +} + +static void IRAM_ATTR bootloader_init_flash_configure(void) +{ + bootloader_flash_dummy_config(&bootloader_image_hdr); + bootloader_flash_cs_timing_config(); +} + +esp_err_t bootloader_init_spi_flash(void) +{ + bootloader_init_flash_configure(); +#ifndef CONFIG_SPI_FLASH_ROM_DRIVER_PATCH + const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); + if (spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_SPI && spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI) { + ESP_EARLY_LOGE(TAG, "SPI flash pins are overridden. Enable CONFIG_SPI_FLASH_ROM_DRIVER_PATCH in menuconfig"); + return ESP_FAIL; + } +#endif + +#if CONFIG_SPI_FLASH_HPM_ENABLE + // Reset flash, clear volatile bits DC[0:1]. Make it work under default mode to boot. + bootloader_spi_flash_reset(); +#endif + + bootloader_flash_unlock(); + +#if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT + if (!bootloader_flash_is_octal_mode_enabled()) { + bootloader_enable_qio_mode(); + } +#endif + + print_flash_info(&bootloader_image_hdr); + update_flash_config(&bootloader_image_hdr); + //ensure the flash is write-protected + bootloader_enable_wp(); + return ESP_OK; +} diff --git a/components/bootloader_support/src/esp32/bootloader_esp32.c b/components/bootloader_support/src/esp32/bootloader_esp32.c index e869b9b6e7..c2313b9f6e 100644 --- a/components/bootloader_support/src/esp32/bootloader_esp32.c +++ b/components/bootloader_support/src/esp32/bootloader_esp32.c @@ -17,7 +17,7 @@ #include "bootloader_mem.h" #include "bootloader_console.h" #include "bootloader_flash_priv.h" - +#include "esp_private/bootloader_flash_internal.h" #include "esp_cpu.h" #include "soc/dport_reg.h" #include "soc/efuse_reg.h" @@ -39,64 +39,7 @@ static const char *TAG = "boot.esp32"; -#define FLASH_CLK_IO SPI_CLK_GPIO_NUM -#define FLASH_CS_IO SPI_CS0_GPIO_NUM -#define FLASH_SPIQ_IO SPI_Q_GPIO_NUM -#define FLASH_SPID_IO SPI_D_GPIO_NUM -#define FLASH_SPIWP_IO SPI_WP_GPIO_NUM -#define FLASH_SPIHD_IO SPI_HD_GPIO_NUM - -void bootloader_configure_spi_pins(int drv) -{ - uint32_t pkg_ver = bootloader_common_get_chip_ver_pkg(); - - if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 || - pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 || - pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 || - pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302) { - // For ESP32D2WD or ESP32-PICO series,the SPI pins are already configured - // flash clock signal should come from IO MUX. - gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK); - SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S); - } else { - const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); - if (spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI) { - esp_rom_gpio_connect_out_signal(FLASH_CS_IO, SPICS0_OUT_IDX, 0, 0); - esp_rom_gpio_connect_out_signal(FLASH_SPIQ_IO, SPIQ_OUT_IDX, 0, 0); - esp_rom_gpio_connect_in_signal(FLASH_SPIQ_IO, SPIQ_IN_IDX, 0); - esp_rom_gpio_connect_out_signal(FLASH_SPID_IO, SPID_OUT_IDX, 0, 0); - esp_rom_gpio_connect_in_signal(FLASH_SPID_IO, SPID_IN_IDX, 0); - esp_rom_gpio_connect_out_signal(FLASH_SPIWP_IO, SPIWP_OUT_IDX, 0, 0); - esp_rom_gpio_connect_in_signal(FLASH_SPIWP_IO, SPIWP_IN_IDX, 0); - esp_rom_gpio_connect_out_signal(FLASH_SPIHD_IO, SPIHD_OUT_IDX, 0, 0); - esp_rom_gpio_connect_in_signal(FLASH_SPIHD_IO, SPIHD_IN_IDX, 0); - //select pin function gpio - gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA0_U, PIN_FUNC_GPIO); - gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA1_U, PIN_FUNC_GPIO); - gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA2_U, PIN_FUNC_GPIO); - gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_DATA3_U, PIN_FUNC_GPIO); - gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CMD_U, PIN_FUNC_GPIO); - // flash clock signal should come from IO MUX. - // set drive ability for clock - gpio_hal_iomux_func_sel(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK); - SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S); - -#if CONFIG_SPIRAM_TYPE_ESPPSRAM32 || CONFIG_SPIRAM_TYPE_ESPPSRAM64 - uint32_t flash_id = g_rom_flashchip.device_id; - if (flash_id == FLASH_ID_GD25LQ32C) { - // Set drive ability for 1.8v flash in 80Mhz. - SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_DATA0_U, FUN_DRV, 3, FUN_DRV_S); - SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_DATA1_U, FUN_DRV, 3, FUN_DRV_S); - SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_DATA2_U, FUN_DRV, 3, FUN_DRV_S); - SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_DATA3_U, FUN_DRV, 3, FUN_DRV_S); - SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CMD_U, FUN_DRV, 3, FUN_DRV_S); - SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, 3, FUN_DRV_S); - } -#endif - } - } -} - +#if !CONFIG_APP_BUILD_TYPE_RAM static void bootloader_reset_mmu(void) { /* completely reset MMU in case serial bootloader was running */ @@ -124,6 +67,7 @@ static void bootloader_reset_mmu(void) DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DROM0); #endif } +#endif //!CONFIG_APP_BUILD_TYPE_RAM static esp_err_t bootloader_check_rated_cpu_clock(void) { @@ -136,137 +80,6 @@ static esp_err_t bootloader_check_rated_cpu_clock(void) return ESP_OK; } -static void update_flash_config(const esp_image_header_t *bootloader_hdr) -{ - uint32_t size; - switch (bootloader_hdr->spi_size) { - case ESP_IMAGE_FLASH_SIZE_1MB: - size = 1; - break; - case ESP_IMAGE_FLASH_SIZE_2MB: - size = 2; - break; - case ESP_IMAGE_FLASH_SIZE_4MB: - size = 4; - break; - case ESP_IMAGE_FLASH_SIZE_8MB: - size = 8; - break; - case ESP_IMAGE_FLASH_SIZE_16MB: - size = 16; - break; - default: - size = 2; - } - Cache_Read_Disable(0); - // Set flash chip size - esp_rom_spiflash_config_param(g_rom_flashchip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff); - // TODO: set mode - // TODO: set frequency - Cache_Flush(0); - Cache_Read_Enable(0); -} - -static void print_flash_info(const esp_image_header_t *bootloader_hdr) -{ - ESP_LOGD(TAG, "magic %02x", bootloader_hdr->magic); - ESP_LOGD(TAG, "segments %02x", bootloader_hdr->segment_count); - ESP_LOGD(TAG, "spi_mode %02x", bootloader_hdr->spi_mode); - ESP_LOGD(TAG, "spi_speed %02x", bootloader_hdr->spi_speed); - ESP_LOGD(TAG, "spi_size %02x", bootloader_hdr->spi_size); - - const char *str; - switch (bootloader_hdr->spi_speed) { - case ESP_IMAGE_SPI_SPEED_DIV_2: - str = "40MHz"; - break; - case ESP_IMAGE_SPI_SPEED_DIV_3: - str = "26.7MHz"; - break; - case ESP_IMAGE_SPI_SPEED_DIV_4: - str = "20MHz"; - break; - case ESP_IMAGE_SPI_SPEED_DIV_1: - str = "80MHz"; - break; - default: - str = "20MHz"; - break; - } - ESP_LOGI(TAG, "SPI Speed : %s", str); - - /* SPI mode could have been set to QIO during boot already, - so test the SPI registers not the flash header */ - uint32_t spi_ctrl = REG_READ(SPI_CTRL_REG(0)); - if (spi_ctrl & SPI_FREAD_QIO) { - str = "QIO"; - } else if (spi_ctrl & SPI_FREAD_QUAD) { - str = "QOUT"; - } else if (spi_ctrl & SPI_FREAD_DIO) { - str = "DIO"; - } else if (spi_ctrl & SPI_FREAD_DUAL) { - str = "DOUT"; - } else if (spi_ctrl & SPI_FASTRD_MODE) { - str = "FAST READ"; - } else { - str = "SLOW READ"; - } - ESP_LOGI(TAG, "SPI Mode : %s", str); - - switch (bootloader_hdr->spi_size) { - case ESP_IMAGE_FLASH_SIZE_1MB: - str = "1MB"; - break; - case ESP_IMAGE_FLASH_SIZE_2MB: - str = "2MB"; - break; - case ESP_IMAGE_FLASH_SIZE_4MB: - str = "4MB"; - break; - case ESP_IMAGE_FLASH_SIZE_8MB: - str = "8MB"; - break; - case ESP_IMAGE_FLASH_SIZE_16MB: - str = "16MB"; - break; - default: - str = "2MB"; - break; - } - ESP_LOGI(TAG, "SPI Flash Size : %s", str); -} - -static void IRAM_ATTR bootloader_init_flash_configure(void) -{ - bootloader_flash_gpio_config(&bootloader_image_hdr); - bootloader_flash_dummy_config(&bootloader_image_hdr); - bootloader_flash_cs_timing_config(); -} - -static esp_err_t bootloader_init_spi_flash(void) -{ - bootloader_init_flash_configure(); -#ifndef CONFIG_SPI_FLASH_ROM_DRIVER_PATCH - const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); - if (spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_SPI && spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI) { - ESP_LOGE(TAG, "SPI flash pins are overridden. Enable CONFIG_SPI_FLASH_ROM_DRIVER_PATCH in menuconfig"); - return ESP_FAIL; - } -#endif - - bootloader_flash_unlock(); - -#if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT - bootloader_enable_qio_mode(); -#endif - - print_flash_info(&bootloader_image_hdr); - update_flash_config(&bootloader_image_hdr); - //ensure the flash is write-protected - bootloader_enable_wp(); - return ESP_OK; -} - static void wdt_reset_cpu0_info_enable(void) { //We do not reset core1 info here because it didn't work before cpu1 was up. So we put it into call_start_cpu1. diff --git a/components/bootloader_support/src/esp32c2/bootloader_esp32c2.c b/components/bootloader_support/src/esp32c2/bootloader_esp32c2.c index 9da25dce2a..bac2b8bc10 100644 --- a/components/bootloader_support/src/esp32c2/bootloader_esp32c2.c +++ b/components/bootloader_support/src/esp32c2/bootloader_esp32c2.c @@ -34,6 +34,7 @@ #include "bootloader_mem.h" #include "bootloader_console.h" #include "bootloader_flash_priv.h" +#include "esp_private/bootloader_flash_internal.h" #include "esp_efuse.h" #include "hal/mmu_hal.h" #include "hal/cache_hal.h" @@ -41,168 +42,6 @@ static const char *TAG = "boot.esp32c2"; -void IRAM_ATTR bootloader_configure_spi_pins(int drv) -{ - // IDF-4066 - const uint32_t spiconfig = 0; - uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM; - uint8_t q_gpio_num = SPI_Q_GPIO_NUM; - uint8_t d_gpio_num = SPI_D_GPIO_NUM; - uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM; - uint8_t hd_gpio_num = SPI_HD_GPIO_NUM; - uint8_t wp_gpio_num = SPI_WP_GPIO_NUM; - if (spiconfig == 0) { - - } - esp_rom_gpio_pad_set_drv(clk_gpio_num, drv); - esp_rom_gpio_pad_set_drv(q_gpio_num, drv); - esp_rom_gpio_pad_set_drv(d_gpio_num, drv); - esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv); - if (hd_gpio_num <= MAX_PAD_GPIO_NUM) { - esp_rom_gpio_pad_set_drv(hd_gpio_num, drv); - } - if (wp_gpio_num <= MAX_PAD_GPIO_NUM) { - esp_rom_gpio_pad_set_drv(wp_gpio_num, drv); - } -} - -static void update_flash_config(const esp_image_header_t *bootloader_hdr) -{ - uint32_t size; - switch (bootloader_hdr->spi_size) { - case ESP_IMAGE_FLASH_SIZE_1MB: - size = 1; - break; - case ESP_IMAGE_FLASH_SIZE_2MB: - size = 2; - break; - case ESP_IMAGE_FLASH_SIZE_4MB: - size = 4; - break; - case ESP_IMAGE_FLASH_SIZE_8MB: - size = 8; - break; - case ESP_IMAGE_FLASH_SIZE_16MB: - size = 16; - break; - default: - size = 2; - } - cache_hal_disable(CACHE_TYPE_ALL); - // Set flash chip size - esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff); // TODO: set mode - cache_hal_enable(CACHE_TYPE_ALL); -} - -static void print_flash_info(const esp_image_header_t *bootloader_hdr) -{ - ESP_LOGD(TAG, "magic %02x", bootloader_hdr->magic); - ESP_LOGD(TAG, "segments %02x", bootloader_hdr->segment_count); - ESP_LOGD(TAG, "spi_mode %02x", bootloader_hdr->spi_mode); - ESP_LOGD(TAG, "spi_speed %02x", bootloader_hdr->spi_speed); - ESP_LOGD(TAG, "spi_size %02x", bootloader_hdr->spi_size); - - const char *str; - switch (bootloader_hdr->spi_speed) { - case ESP_IMAGE_SPI_SPEED_DIV_2: - str = "30MHz"; - break; - case ESP_IMAGE_SPI_SPEED_DIV_3: - str = "20MHz"; - break; - case ESP_IMAGE_SPI_SPEED_DIV_4: - str = "15MHz"; - break; - case ESP_IMAGE_SPI_SPEED_DIV_1: - str = "60MHz"; - break; - default: - str = "15MHz"; - break; - } - ESP_LOGI(TAG, "SPI Speed : %s", str); - - /* SPI mode could have been set to QIO during boot already, - so test the SPI registers not the flash header */ - uint32_t spi_ctrl = REG_READ(SPI_MEM_CTRL_REG(0)); - if (spi_ctrl & SPI_MEM_FREAD_QIO) { - str = "QIO"; - } else if (spi_ctrl & SPI_MEM_FREAD_QUAD) { - str = "QOUT"; - } else if (spi_ctrl & SPI_MEM_FREAD_DIO) { - str = "DIO"; - } else if (spi_ctrl & SPI_MEM_FREAD_DUAL) { - str = "DOUT"; - } else if (spi_ctrl & SPI_MEM_FASTRD_MODE) { - str = "FAST READ"; - } else { - str = "SLOW READ"; - } - ESP_LOGI(TAG, "SPI Mode : %s", str); - - switch (bootloader_hdr->spi_size) { - case ESP_IMAGE_FLASH_SIZE_1MB: - str = "1MB"; - break; - case ESP_IMAGE_FLASH_SIZE_2MB: - str = "2MB"; - break; - case ESP_IMAGE_FLASH_SIZE_4MB: - str = "4MB"; - break; - case ESP_IMAGE_FLASH_SIZE_8MB: - str = "8MB"; - break; - case ESP_IMAGE_FLASH_SIZE_16MB: - str = "16MB"; - break; - default: - str = "2MB"; - break; - } - ESP_LOGI(TAG, "SPI Flash Size : %s", str); -} - -static void bootloader_print_mmu_page_size(void) -{ - mmu_page_size_t page_size = mmu_ll_get_page_size(0); - int size = (page_size == MMU_PAGE_16KB ? 16 : - page_size == MMU_PAGE_32KB ? 32 : - page_size == MMU_PAGE_64KB ? 64 : 0); - ESP_LOGI(TAG, "MMU Page Size : %dK", size); -} - -static void IRAM_ATTR bootloader_init_flash_configure(void) -{ - bootloader_flash_dummy_config(&bootloader_image_hdr); - bootloader_flash_cs_timing_config(); -} - -static void bootloader_spi_flash_resume(void) -{ - bootloader_execute_flash_command(CMD_RESUME, 0, 0, 0); - esp_rom_spiflash_wait_idle(&g_rom_flashchip); -} - -static esp_err_t bootloader_init_spi_flash(void) -{ - bootloader_init_flash_configure(); - - bootloader_spi_flash_resume(); - bootloader_flash_unlock(); - -#if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT - bootloader_enable_qio_mode(); -#endif - - bootloader_print_mmu_page_size(); - print_flash_info(&bootloader_image_hdr); - update_flash_config(&bootloader_image_hdr); - //ensure the flash is write-protected - bootloader_enable_wp(); - return ESP_OK; -} - static void wdt_reset_cpu0_info_enable(void) { REG_SET_BIT(SYSTEM_CPU_PERI_CLK_EN_REG, SYSTEM_CLK_EN_ASSIST_DEBUG); diff --git a/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c b/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c index 8cb6bbe3a3..1a7a8097b1 100644 --- a/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c +++ b/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c @@ -38,6 +38,7 @@ #include "soc/regi2c_bias.h" #include "bootloader_console.h" #include "bootloader_flash_priv.h" +#include "esp_private/bootloader_flash_internal.h" #include "bootloader_soc.h" #include "esp_efuse.h" #include "hal/mmu_hal.h" @@ -46,172 +47,6 @@ static const char *TAG = "boot.esp32c3"; -void IRAM_ATTR bootloader_configure_spi_pins(int drv) -{ - const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); - uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio(); - uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM; - uint8_t q_gpio_num = SPI_Q_GPIO_NUM; - uint8_t d_gpio_num = SPI_D_GPIO_NUM; - uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM; - uint8_t hd_gpio_num = SPI_HD_GPIO_NUM; - uint8_t wp_gpio_num = SPI_WP_GPIO_NUM; - if (spiconfig == 0) { - - } else { - clk_gpio_num = spiconfig & 0x3f; - q_gpio_num = (spiconfig >> 6) & 0x3f; - d_gpio_num = (spiconfig >> 12) & 0x3f; - cs0_gpio_num = (spiconfig >> 18) & 0x3f; - hd_gpio_num = (spiconfig >> 24) & 0x3f; - wp_gpio_num = wp_pin; - } - esp_rom_gpio_pad_set_drv(clk_gpio_num, drv); - esp_rom_gpio_pad_set_drv(q_gpio_num, drv); - esp_rom_gpio_pad_set_drv(d_gpio_num, drv); - esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv); - if (hd_gpio_num <= MAX_PAD_GPIO_NUM) { - esp_rom_gpio_pad_set_drv(hd_gpio_num, drv); - } - if (wp_gpio_num <= MAX_PAD_GPIO_NUM) { - esp_rom_gpio_pad_set_drv(wp_gpio_num, drv); - } -} - -static void update_flash_config(const esp_image_header_t *bootloader_hdr) -{ - uint32_t size; - switch (bootloader_hdr->spi_size) { - case ESP_IMAGE_FLASH_SIZE_1MB: - size = 1; - break; - case ESP_IMAGE_FLASH_SIZE_2MB: - size = 2; - break; - case ESP_IMAGE_FLASH_SIZE_4MB: - size = 4; - break; - case ESP_IMAGE_FLASH_SIZE_8MB: - size = 8; - break; - case ESP_IMAGE_FLASH_SIZE_16MB: - size = 16; - break; - default: - size = 2; - } - cache_hal_disable(CACHE_TYPE_ALL); - // Set flash chip size - esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff); // TODO: set mode - cache_hal_enable(CACHE_TYPE_ALL); -} - -static void print_flash_info(const esp_image_header_t *bootloader_hdr) -{ - ESP_LOGD(TAG, "magic %02x", bootloader_hdr->magic); - ESP_LOGD(TAG, "segments %02x", bootloader_hdr->segment_count); - ESP_LOGD(TAG, "spi_mode %02x", bootloader_hdr->spi_mode); - ESP_LOGD(TAG, "spi_speed %02x", bootloader_hdr->spi_speed); - ESP_LOGD(TAG, "spi_size %02x", bootloader_hdr->spi_size); - - const char *str; - switch (bootloader_hdr->spi_speed) { - case ESP_IMAGE_SPI_SPEED_DIV_2: - str = "40MHz"; - break; - case ESP_IMAGE_SPI_SPEED_DIV_3: - str = "26.7MHz"; - break; - case ESP_IMAGE_SPI_SPEED_DIV_4: - str = "20MHz"; - break; - case ESP_IMAGE_SPI_SPEED_DIV_1: - str = "80MHz"; - break; - default: - str = "20MHz"; - break; - } - ESP_LOGI(TAG, "SPI Speed : %s", str); - - /* SPI mode could have been set to QIO during boot already, - so test the SPI registers not the flash header */ - uint32_t spi_ctrl = REG_READ(SPI_MEM_CTRL_REG(0)); - if (spi_ctrl & SPI_MEM_FREAD_QIO) { - str = "QIO"; - } else if (spi_ctrl & SPI_MEM_FREAD_QUAD) { - str = "QOUT"; - } else if (spi_ctrl & SPI_MEM_FREAD_DIO) { - str = "DIO"; - } else if (spi_ctrl & SPI_MEM_FREAD_DUAL) { - str = "DOUT"; - } else if (spi_ctrl & SPI_MEM_FASTRD_MODE) { - str = "FAST READ"; - } else { - str = "SLOW READ"; - } - ESP_LOGI(TAG, "SPI Mode : %s", str); - - switch (bootloader_hdr->spi_size) { - case ESP_IMAGE_FLASH_SIZE_1MB: - str = "1MB"; - break; - case ESP_IMAGE_FLASH_SIZE_2MB: - str = "2MB"; - break; - case ESP_IMAGE_FLASH_SIZE_4MB: - str = "4MB"; - break; - case ESP_IMAGE_FLASH_SIZE_8MB: - str = "8MB"; - break; - case ESP_IMAGE_FLASH_SIZE_16MB: - str = "16MB"; - break; - default: - str = "2MB"; - break; - } - ESP_LOGI(TAG, "SPI Flash Size : %s", str); -} - -static void IRAM_ATTR bootloader_init_flash_configure(void) -{ - bootloader_flash_dummy_config(&bootloader_image_hdr); - bootloader_flash_cs_timing_config(); -} - -static void bootloader_spi_flash_resume(void) -{ - bootloader_execute_flash_command(CMD_RESUME, 0, 0, 0); - esp_rom_spiflash_wait_idle(&g_rom_flashchip); -} - -static esp_err_t bootloader_init_spi_flash(void) -{ - bootloader_init_flash_configure(); -#ifndef CONFIG_SPI_FLASH_ROM_DRIVER_PATCH - const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); - if (spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_SPI && spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI) { - ESP_LOGE(TAG, "SPI flash pins are overridden. Enable CONFIG_SPI_FLASH_ROM_DRIVER_PATCH in menuconfig"); - return ESP_FAIL; - } -#endif - - bootloader_spi_flash_resume(); - bootloader_flash_unlock(); - -#if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT - bootloader_enable_qio_mode(); -#endif - - print_flash_info(&bootloader_image_hdr); - update_flash_config(&bootloader_image_hdr); - //ensure the flash is write-protected - bootloader_enable_wp(); - return ESP_OK; -} - static void wdt_reset_cpu0_info_enable(void) { REG_SET_BIT(SYSTEM_CPU_PERI_CLK_EN_REG, SYSTEM_CLK_EN_ASSIST_DEBUG); diff --git a/components/bootloader_support/src/esp32c6/bootloader_esp32c6.c b/components/bootloader_support/src/esp32c6/bootloader_esp32c6.c index f3eeb64a0a..6db0df6a6f 100644 --- a/components/bootloader_support/src/esp32c6/bootloader_esp32c6.c +++ b/components/bootloader_support/src/esp32c6/bootloader_esp32c6.c @@ -37,6 +37,7 @@ #include "bootloader_console.h" #include "bootloader_flash_priv.h" #include "bootloader_soc.h" +#include "esp_private/bootloader_flash_internal.h" #include "esp_efuse.h" #include "hal/mmu_hal.h" #include "hal/cache_hal.h" @@ -47,148 +48,6 @@ static const char *TAG = "boot.esp32c6"; -void IRAM_ATTR bootloader_configure_spi_pins(int drv) -{ - uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM; - uint8_t q_gpio_num = SPI_Q_GPIO_NUM; - uint8_t d_gpio_num = SPI_D_GPIO_NUM; - uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM; - uint8_t hd_gpio_num = SPI_HD_GPIO_NUM; - uint8_t wp_gpio_num = SPI_WP_GPIO_NUM; - esp_rom_gpio_pad_set_drv(clk_gpio_num, drv); - esp_rom_gpio_pad_set_drv(q_gpio_num, drv); - esp_rom_gpio_pad_set_drv(d_gpio_num, drv); - esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv); - esp_rom_gpio_pad_set_drv(hd_gpio_num, drv); - esp_rom_gpio_pad_set_drv(wp_gpio_num, drv); -} - -static void update_flash_config(const esp_image_header_t *bootloader_hdr) -{ - uint32_t size; - switch (bootloader_hdr->spi_size) { - case ESP_IMAGE_FLASH_SIZE_1MB: - size = 1; - break; - case ESP_IMAGE_FLASH_SIZE_2MB: - size = 2; - break; - case ESP_IMAGE_FLASH_SIZE_4MB: - size = 4; - break; - case ESP_IMAGE_FLASH_SIZE_8MB: - size = 8; - break; - case ESP_IMAGE_FLASH_SIZE_16MB: - size = 16; - break; - default: - size = 2; - } - cache_hal_disable(CACHE_TYPE_ALL); - // Set flash chip size - esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff); // TODO: set mode - cache_hal_enable(CACHE_TYPE_ALL); -} - -static void print_flash_info(const esp_image_header_t *bootloader_hdr) -{ - ESP_LOGD(TAG, "magic %02x", bootloader_hdr->magic); - ESP_LOGD(TAG, "segments %02x", bootloader_hdr->segment_count); - ESP_LOGD(TAG, "spi_mode %02x", bootloader_hdr->spi_mode); - ESP_LOGD(TAG, "spi_speed %02x", bootloader_hdr->spi_speed); - ESP_LOGD(TAG, "spi_size %02x", bootloader_hdr->spi_size); - - const char *str; - switch (bootloader_hdr->spi_speed) { - case ESP_IMAGE_SPI_SPEED_DIV_2: - str = "40MHz"; - break; - case ESP_IMAGE_SPI_SPEED_DIV_3: - str = "26.7MHz"; - break; - case ESP_IMAGE_SPI_SPEED_DIV_4: - str = "20MHz"; - break; - case ESP_IMAGE_SPI_SPEED_DIV_1: - str = "80MHz"; - break; - default: - str = "20MHz"; - break; - } - ESP_LOGI(TAG, "SPI Speed : %s", str); - - /* SPI mode could have been set to QIO during boot already, - so test the SPI registers not the flash header */ - uint32_t spi_ctrl = REG_READ(SPI_MEM_CTRL_REG(0)); - if (spi_ctrl & SPI_MEM_FREAD_QIO) { - str = "QIO"; - } else if (spi_ctrl & SPI_MEM_FREAD_QUAD) { - str = "QOUT"; - } else if (spi_ctrl & SPI_MEM_FREAD_DIO) { - str = "DIO"; - } else if (spi_ctrl & SPI_MEM_FREAD_DUAL) { - str = "DOUT"; - } else if (spi_ctrl & SPI_MEM_FASTRD_MODE) { - str = "FAST READ"; - } else { - str = "SLOW READ"; - } - ESP_LOGI(TAG, "SPI Mode : %s", str); - - switch (bootloader_hdr->spi_size) { - case ESP_IMAGE_FLASH_SIZE_1MB: - str = "1MB"; - break; - case ESP_IMAGE_FLASH_SIZE_2MB: - str = "2MB"; - break; - case ESP_IMAGE_FLASH_SIZE_4MB: - str = "4MB"; - break; - case ESP_IMAGE_FLASH_SIZE_8MB: - str = "8MB"; - break; - case ESP_IMAGE_FLASH_SIZE_16MB: - str = "16MB"; - break; - default: - str = "2MB"; - break; - } - ESP_LOGI(TAG, "SPI Flash Size : %s", str); -} - -static void IRAM_ATTR bootloader_init_flash_configure(void) -{ - bootloader_configure_spi_pins(1); - bootloader_flash_cs_timing_config(); -} - -static void bootloader_spi_flash_resume(void) -{ - bootloader_execute_flash_command(CMD_RESUME, 0, 0, 0); - esp_rom_spiflash_wait_idle(&g_rom_flashchip); -} - -static esp_err_t bootloader_init_spi_flash(void) -{ - bootloader_init_flash_configure(); - bootloader_spi_flash_resume(); - bootloader_flash_unlock(); - -#if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT - bootloader_enable_qio_mode(); -#endif - - print_flash_info(&bootloader_image_hdr); - update_flash_config(&bootloader_image_hdr); - //ensure the flash is write-protected - bootloader_enable_wp(); - return ESP_OK; -} - static void wdt_reset_cpu0_info_enable(void) { REG_SET_BIT(PCR_ASSIST_CONF_REG, PCR_ASSIST_CLK_EN); diff --git a/components/bootloader_support/src/esp32h2/bootloader_esp32h2.c b/components/bootloader_support/src/esp32h2/bootloader_esp32h2.c index a2c9245e30..ba06e9609e 100644 --- a/components/bootloader_support/src/esp32h2/bootloader_esp32h2.c +++ b/components/bootloader_support/src/esp32h2/bootloader_esp32h2.c @@ -36,6 +36,7 @@ #include "bootloader_console.h" #include "bootloader_flash_priv.h" #include "bootloader_soc.h" +#include "esp_private/bootloader_flash_internal.h" #include "esp_efuse.h" #include "hal/mmu_hal.h" #include "hal/cache_hal.h" @@ -45,148 +46,6 @@ static const char *TAG = "boot.esp32h2"; -void IRAM_ATTR bootloader_configure_spi_pins(int drv) -{ - uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM; - uint8_t q_gpio_num = SPI_Q_GPIO_NUM; - uint8_t d_gpio_num = SPI_D_GPIO_NUM; - uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM; - uint8_t hd_gpio_num = SPI_HD_GPIO_NUM; - uint8_t wp_gpio_num = SPI_WP_GPIO_NUM; - esp_rom_gpio_pad_set_drv(clk_gpio_num, drv); - esp_rom_gpio_pad_set_drv(q_gpio_num, drv); - esp_rom_gpio_pad_set_drv(d_gpio_num, drv); - esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv); - esp_rom_gpio_pad_set_drv(hd_gpio_num, drv); - esp_rom_gpio_pad_set_drv(wp_gpio_num, drv); -} - -static void update_flash_config(const esp_image_header_t *bootloader_hdr) -{ - uint32_t size; - switch (bootloader_hdr->spi_size) { - case ESP_IMAGE_FLASH_SIZE_1MB: - size = 1; - break; - case ESP_IMAGE_FLASH_SIZE_2MB: - size = 2; - break; - case ESP_IMAGE_FLASH_SIZE_4MB: - size = 4; - break; - case ESP_IMAGE_FLASH_SIZE_8MB: - size = 8; - break; - case ESP_IMAGE_FLASH_SIZE_16MB: - size = 16; - break; - default: - size = 2; - } - cache_hal_disable(CACHE_TYPE_ALL); - // Set flash chip size - esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff); // TODO: set mode - cache_hal_enable(CACHE_TYPE_ALL); -} - -static void print_flash_info(const esp_image_header_t *bootloader_hdr) -{ - ESP_EARLY_LOGD(TAG, "magic %02x", bootloader_hdr->magic); - ESP_EARLY_LOGD(TAG, "segments %02x", bootloader_hdr->segment_count); - ESP_EARLY_LOGD(TAG, "spi_mode %02x", bootloader_hdr->spi_mode); - ESP_EARLY_LOGD(TAG, "spi_speed %02x", bootloader_hdr->spi_speed); - ESP_EARLY_LOGD(TAG, "spi_size %02x", bootloader_hdr->spi_size); - - const char *str; - switch (bootloader_hdr->spi_speed) { - case ESP_IMAGE_SPI_SPEED_DIV_2: - str = "40MHz"; - break; - case ESP_IMAGE_SPI_SPEED_DIV_3: - str = "26.7MHz"; - break; - case ESP_IMAGE_SPI_SPEED_DIV_4: - str = "20MHz"; - break; - case ESP_IMAGE_SPI_SPEED_DIV_1: - str = "80MHz"; - break; - default: - str = "20MHz"; - break; - } - ESP_LOGI(TAG, "SPI Speed : %s", str); - - /* SPI mode could have been set to QIO during boot already, - so test the SPI registers not the flash header */ - uint32_t spi_ctrl = REG_READ(SPI_MEM_CTRL_REG(0)); - if (spi_ctrl & SPI_MEM_FREAD_QIO) { - str = "QIO"; - } else if (spi_ctrl & SPI_MEM_FREAD_QUAD) { - str = "QOUT"; - } else if (spi_ctrl & SPI_MEM_FREAD_DIO) { - str = "DIO"; - } else if (spi_ctrl & SPI_MEM_FREAD_DUAL) { - str = "DOUT"; - } else if (spi_ctrl & SPI_MEM_FASTRD_MODE) { - str = "FAST READ"; - } else { - str = "SLOW READ"; - } - ESP_LOGI(TAG, "SPI Mode : %s", str); - - switch (bootloader_hdr->spi_size) { - case ESP_IMAGE_FLASH_SIZE_1MB: - str = "1MB"; - break; - case ESP_IMAGE_FLASH_SIZE_2MB: - str = "2MB"; - break; - case ESP_IMAGE_FLASH_SIZE_4MB: - str = "4MB"; - break; - case ESP_IMAGE_FLASH_SIZE_8MB: - str = "8MB"; - break; - case ESP_IMAGE_FLASH_SIZE_16MB: - str = "16MB"; - break; - default: - str = "2MB"; - break; - } - ESP_LOGI(TAG, "SPI Flash Size : %s", str); -} - -static void IRAM_ATTR bootloader_init_flash_configure(void) -{ - bootloader_configure_spi_pins(1); - bootloader_flash_cs_timing_config(); -} - -static void bootloader_spi_flash_resume(void) -{ - bootloader_execute_flash_command(CMD_RESUME, 0, 0, 0); - esp_rom_spiflash_wait_idle(&g_rom_flashchip); -} - -static esp_err_t bootloader_init_spi_flash(void) -{ - bootloader_init_flash_configure(); - bootloader_spi_flash_resume(); - bootloader_flash_unlock(); - -#if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT - bootloader_enable_qio_mode(); -#endif - - print_flash_info(&bootloader_image_hdr); - update_flash_config(&bootloader_image_hdr); - //ensure the flash is write-protected - bootloader_enable_wp(); - return ESP_OK; -} - static void wdt_reset_cpu0_info_enable(void) { REG_SET_BIT(PCR_ASSIST_CONF_REG, PCR_ASSIST_CLK_EN); diff --git a/components/bootloader_support/src/esp32h4/bootloader_esp32h4.c b/components/bootloader_support/src/esp32h4/bootloader_esp32h4.c index 8d75accd18..ef7cf34687 100644 --- a/components/bootloader_support/src/esp32h4/bootloader_esp32h4.c +++ b/components/bootloader_support/src/esp32h4/bootloader_esp32h4.c @@ -35,177 +35,12 @@ #include "bootloader_console.h" #include "bootloader_flash_priv.h" #include "bootloader_soc.h" +#include "esp_private/bootloader_flash_internal.h" #include "hal/mmu_hal.h" #include "hal/cache_hal.h" static const char *TAG = "boot.esp32h4"; -void IRAM_ATTR bootloader_configure_spi_pins(int drv) -{ - const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); - uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio(); - uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM; - uint8_t q_gpio_num = SPI_Q_GPIO_NUM; - uint8_t d_gpio_num = SPI_D_GPIO_NUM; - uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM; - uint8_t hd_gpio_num = SPI_HD_GPIO_NUM; - uint8_t wp_gpio_num = SPI_WP_GPIO_NUM; - if (spiconfig == 0) { - - } else { - clk_gpio_num = spiconfig & 0x3f; - q_gpio_num = (spiconfig >> 6) & 0x3f; - d_gpio_num = (spiconfig >> 12) & 0x3f; - cs0_gpio_num = (spiconfig >> 18) & 0x3f; - hd_gpio_num = (spiconfig >> 24) & 0x3f; - wp_gpio_num = wp_pin; - } - esp_rom_gpio_pad_set_drv(clk_gpio_num, drv); - esp_rom_gpio_pad_set_drv(q_gpio_num, drv); - esp_rom_gpio_pad_set_drv(d_gpio_num, drv); - esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv); - if (hd_gpio_num <= MAX_PAD_GPIO_NUM) { - esp_rom_gpio_pad_set_drv(hd_gpio_num, drv); - } - if (wp_gpio_num <= MAX_PAD_GPIO_NUM) { - esp_rom_gpio_pad_set_drv(wp_gpio_num, drv); - } -} - -static void update_flash_config(const esp_image_header_t *bootloader_hdr) -{ - uint32_t size; - switch (bootloader_hdr->spi_size) { - case ESP_IMAGE_FLASH_SIZE_1MB: - size = 1; - break; - case ESP_IMAGE_FLASH_SIZE_2MB: - size = 2; - break; - case ESP_IMAGE_FLASH_SIZE_4MB: - size = 4; - break; - case ESP_IMAGE_FLASH_SIZE_8MB: - size = 8; - break; - case ESP_IMAGE_FLASH_SIZE_16MB: - size = 16; - break; - default: - size = 2; - } - cache_hal_disable(CACHE_TYPE_ALL); - // Set flash chip size - esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff); // TODO: set mode - cache_hal_enable(CACHE_TYPE_ALL); -} - -static void print_flash_info(const esp_image_header_t *bootloader_hdr) -{ - ESP_LOGD(TAG, "magic %02x", bootloader_hdr->magic); - ESP_LOGD(TAG, "segments %02x", bootloader_hdr->segment_count); - ESP_LOGD(TAG, "spi_mode %02x", bootloader_hdr->spi_mode); - ESP_LOGD(TAG, "spi_speed %02x", bootloader_hdr->spi_speed); - ESP_LOGD(TAG, "spi_size %02x", bootloader_hdr->spi_size); - - const char *str; - switch (bootloader_hdr->spi_speed) { - case ESP_IMAGE_SPI_SPEED_DIV_2: - str = "24MHz"; - break; - case ESP_IMAGE_SPI_SPEED_DIV_3: - str = "16MHz"; - break; - case ESP_IMAGE_SPI_SPEED_DIV_4: - str = "12MHz"; - break; - case ESP_IMAGE_SPI_SPEED_DIV_1: - str = "48MHz"; - break; - default: - str = "12MHz"; - break; - } - ESP_LOGI(TAG, "SPI Speed : %s", str); - - /* SPI mode could have been set to QIO during boot already, - so test the SPI registers not the flash header */ - uint32_t spi_ctrl = REG_READ(SPI_MEM_CTRL_REG(0)); - if (spi_ctrl & SPI_MEM_FREAD_QIO) { - str = "QIO"; - } else if (spi_ctrl & SPI_MEM_FREAD_QUAD) { - str = "QOUT"; - } else if (spi_ctrl & SPI_MEM_FREAD_DIO) { - str = "DIO"; - } else if (spi_ctrl & SPI_MEM_FREAD_DUAL) { - str = "DOUT"; - } else if (spi_ctrl & SPI_MEM_FASTRD_MODE) { - str = "FAST READ"; - } else { - str = "SLOW READ"; - } - ESP_LOGI(TAG, "SPI Mode : %s", str); - - switch (bootloader_hdr->spi_size) { - case ESP_IMAGE_FLASH_SIZE_1MB: - str = "1MB"; - break; - case ESP_IMAGE_FLASH_SIZE_2MB: - str = "2MB"; - break; - case ESP_IMAGE_FLASH_SIZE_4MB: - str = "4MB"; - break; - case ESP_IMAGE_FLASH_SIZE_8MB: - str = "8MB"; - break; - case ESP_IMAGE_FLASH_SIZE_16MB: - str = "16MB"; - break; - default: - str = "2MB"; - break; - } - ESP_LOGI(TAG, "SPI Flash Size : %s", str); -} - -static void IRAM_ATTR bootloader_init_flash_configure(void) -{ - bootloader_flash_dummy_config(&bootloader_image_hdr); - bootloader_flash_cs_timing_config(); -} - -static void bootloader_spi_flash_resume(void) -{ - bootloader_execute_flash_command(CMD_RESUME, 0, 0, 0); - esp_rom_spiflash_wait_idle(&g_rom_flashchip); -} - -static esp_err_t bootloader_init_spi_flash(void) -{ - bootloader_init_flash_configure(); -#ifndef CONFIG_SPI_FLASH_ROM_DRIVER_PATCH - const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); - if (spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_SPI && spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI) { - ESP_LOGE(TAG, "SPI flash pins are overridden. Enable CONFIG_SPI_FLASH_ROM_DRIVER_PATCH in menuconfig"); - return ESP_FAIL; - } -#endif - - bootloader_spi_flash_resume(); - bootloader_flash_unlock(); - -#if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT - bootloader_enable_qio_mode(); -#endif - - print_flash_info(&bootloader_image_hdr); - update_flash_config(&bootloader_image_hdr); - //ensure the flash is write-protected - bootloader_enable_wp(); - return ESP_OK; -} - static void wdt_reset_cpu0_info_enable(void) { REG_SET_BIT(SYSTEM_CPU_PERI_CLK_EN_REG, SYSTEM_CLK_EN_ASSIST_DEBUG); diff --git a/components/bootloader_support/src/esp32s2/bootloader_esp32s2.c b/components/bootloader_support/src/esp32s2/bootloader_esp32s2.c index 8250bd63f1..c3a25ef54e 100644 --- a/components/bootloader_support/src/esp32s2/bootloader_esp32s2.c +++ b/components/bootloader_support/src/esp32s2/bootloader_esp32s2.c @@ -18,7 +18,7 @@ #include "bootloader_mem.h" #include "bootloader_console.h" #include "bootloader_flash_priv.h" - +#include "esp_private/bootloader_flash_internal.h" #include "esp_rom_gpio.h" #include "esp_rom_efuse.h" #include "esp_rom_sys.h" @@ -40,184 +40,6 @@ #include "hal/cache_hal.h" static const char *TAG = "boot.esp32s2"; -void IRAM_ATTR bootloader_configure_spi_pins(int drv) -{ - const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); - uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio(); - uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM; - uint8_t q_gpio_num = SPI_Q_GPIO_NUM; - uint8_t d_gpio_num = SPI_D_GPIO_NUM; - uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM; - uint8_t hd_gpio_num = SPI_HD_GPIO_NUM; - uint8_t wp_gpio_num = SPI_WP_GPIO_NUM; - if (spiconfig == 0) { - - } else { - clk_gpio_num = spiconfig & 0x3f; - q_gpio_num = (spiconfig >> 6) & 0x3f; - d_gpio_num = (spiconfig >> 12) & 0x3f; - cs0_gpio_num = (spiconfig >> 18) & 0x3f; - hd_gpio_num = (spiconfig >> 24) & 0x3f; - wp_gpio_num = wp_pin; - } - esp_rom_gpio_pad_set_drv(clk_gpio_num, drv); - esp_rom_gpio_pad_set_drv(q_gpio_num, drv); - esp_rom_gpio_pad_set_drv(d_gpio_num, drv); - esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv); - if (hd_gpio_num <= MAX_PAD_GPIO_NUM) { - esp_rom_gpio_pad_set_drv(hd_gpio_num, drv); - } - if (wp_gpio_num <= MAX_PAD_GPIO_NUM) { - esp_rom_gpio_pad_set_drv(wp_gpio_num, drv); - } -} - -static void update_flash_config(const esp_image_header_t *bootloader_hdr) -{ - uint32_t size; - switch (bootloader_hdr->spi_size) { - case ESP_IMAGE_FLASH_SIZE_1MB: - size = 1; - break; - case ESP_IMAGE_FLASH_SIZE_2MB: - size = 2; - break; - case ESP_IMAGE_FLASH_SIZE_4MB: - size = 4; - break; - case ESP_IMAGE_FLASH_SIZE_8MB: - size = 8; - break; - case ESP_IMAGE_FLASH_SIZE_16MB: - size = 16; - break; - case ESP_IMAGE_FLASH_SIZE_32MB: - size = 32; - break; - case ESP_IMAGE_FLASH_SIZE_64MB: - size = 64; - break; - case ESP_IMAGE_FLASH_SIZE_128MB: - size = 128; - break; - default: - size = 2; - } - cache_hal_disable(CACHE_TYPE_ALL); - // Set flash chip size - esp_rom_spiflash_config_param(g_rom_flashchip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff); - // TODO: set mode - // TODO: set frequency - cache_hal_enable(CACHE_TYPE_ALL); -} - -static void print_flash_info(const esp_image_header_t *bootloader_hdr) -{ - ESP_LOGD(TAG, "magic %02x", bootloader_hdr->magic); - ESP_LOGD(TAG, "segments %02x", bootloader_hdr->segment_count); - ESP_LOGD(TAG, "spi_mode %02x", bootloader_hdr->spi_mode); - ESP_LOGD(TAG, "spi_speed %02x", bootloader_hdr->spi_speed); - ESP_LOGD(TAG, "spi_size %02x", bootloader_hdr->spi_size); - - const char *str; - switch (bootloader_hdr->spi_speed) { - case ESP_IMAGE_SPI_SPEED_DIV_2: - str = "40MHz"; - break; - case ESP_IMAGE_SPI_SPEED_DIV_3: - str = "26.7MHz"; - break; - case ESP_IMAGE_SPI_SPEED_DIV_4: - str = "20MHz"; - break; - case ESP_IMAGE_SPI_SPEED_DIV_1: - str = "80MHz"; - break; - default: - str = "20MHz"; - break; - } - ESP_LOGI(TAG, "SPI Speed : %s", str); - - /* SPI mode could have been set to QIO during boot already, - so test the SPI registers not the flash header */ - uint32_t spi_ctrl = REG_READ(SPI_MEM_CTRL_REG(0)); - if (spi_ctrl & SPI_MEM_FREAD_QIO) { - str = "QIO"; - } else if (spi_ctrl & SPI_MEM_FREAD_QUAD) { - str = "QOUT"; - } else if (spi_ctrl & SPI_MEM_FREAD_DIO) { - str = "DIO"; - } else if (spi_ctrl & SPI_MEM_FREAD_DUAL) { - str = "DOUT"; - } else if (spi_ctrl & SPI_MEM_FASTRD_MODE) { - str = "FAST READ"; - } else { - str = "SLOW READ"; - } - ESP_LOGI(TAG, "SPI Mode : %s", str); - - switch (bootloader_hdr->spi_size) { - case ESP_IMAGE_FLASH_SIZE_1MB: - str = "1MB"; - break; - case ESP_IMAGE_FLASH_SIZE_2MB: - str = "2MB"; - break; - case ESP_IMAGE_FLASH_SIZE_4MB: - str = "4MB"; - break; - case ESP_IMAGE_FLASH_SIZE_8MB: - str = "8MB"; - break; - case ESP_IMAGE_FLASH_SIZE_16MB: - str = "16MB"; - break; - case ESP_IMAGE_FLASH_SIZE_32MB: - str = "32MB"; - break; - case ESP_IMAGE_FLASH_SIZE_64MB: - str = "64MB"; - break; - case ESP_IMAGE_FLASH_SIZE_128MB: - str = "128MB"; - break; - default: - str = "2MB"; - break; - } - ESP_LOGI(TAG, "SPI Flash Size : %s", str); -} - -static void IRAM_ATTR bootloader_init_flash_configure(void) -{ - bootloader_flash_dummy_config(&bootloader_image_hdr); - bootloader_flash_cs_timing_config(); -} - -static esp_err_t bootloader_init_spi_flash(void) -{ - bootloader_init_flash_configure(); -#ifndef CONFIG_SPI_FLASH_ROM_DRIVER_PATCH - const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); - if (spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_SPI && spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI) { - ESP_LOGE(TAG, "SPI flash pins are overridden. Enable CONFIG_SPI_FLASH_ROM_DRIVER_PATCH in menuconfig"); - return ESP_FAIL; - } -#endif - - bootloader_flash_unlock(); - -#if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT - bootloader_enable_qio_mode(); -#endif - - print_flash_info(&bootloader_image_hdr); - update_flash_config(&bootloader_image_hdr); - //ensure the flash is write-protected - bootloader_enable_wp(); - return ESP_OK; -} static void wdt_reset_cpu0_info_enable(void) { diff --git a/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c b/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c index e28ddcf384..31a36b8098 100644 --- a/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c +++ b/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c @@ -34,6 +34,7 @@ #include "bootloader_console.h" #include "bootloader_flash_priv.h" #include "bootloader_soc.h" +#include "esp_private/bootloader_flash_internal.h" #include "esp_efuse.h" #include "hal/mmu_hal.h" #include "hal/cache_hal.h" @@ -43,193 +44,6 @@ static const char *TAG = "boot.esp32s3"; -void IRAM_ATTR bootloader_configure_spi_pins(int drv) -{ - const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); - uint8_t wp_pin = esp_rom_efuse_get_flash_wp_gpio(); - uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM; - uint8_t q_gpio_num = SPI_Q_GPIO_NUM; - uint8_t d_gpio_num = SPI_D_GPIO_NUM; - uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM; - uint8_t hd_gpio_num = SPI_HD_GPIO_NUM; - uint8_t wp_gpio_num = SPI_WP_GPIO_NUM; - if (spiconfig == 0) { - - } else { - clk_gpio_num = spiconfig & 0x3f; - q_gpio_num = (spiconfig >> 6) & 0x3f; - d_gpio_num = (spiconfig >> 12) & 0x3f; - cs0_gpio_num = (spiconfig >> 18) & 0x3f; - hd_gpio_num = (spiconfig >> 24) & 0x3f; - wp_gpio_num = wp_pin; - } - esp_rom_gpio_pad_set_drv(clk_gpio_num, drv); - esp_rom_gpio_pad_set_drv(q_gpio_num, drv); - esp_rom_gpio_pad_set_drv(d_gpio_num, drv); - esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv); - if (hd_gpio_num <= MAX_PAD_GPIO_NUM) { - esp_rom_gpio_pad_set_drv(hd_gpio_num, drv); - } - if (wp_gpio_num <= MAX_PAD_GPIO_NUM) { - esp_rom_gpio_pad_set_drv(wp_gpio_num, drv); - } -} - -static void update_flash_config(const esp_image_header_t *bootloader_hdr) -{ - uint32_t size; - switch (bootloader_hdr->spi_size) { - case ESP_IMAGE_FLASH_SIZE_1MB: - size = 1; - break; - case ESP_IMAGE_FLASH_SIZE_2MB: - size = 2; - break; - case ESP_IMAGE_FLASH_SIZE_4MB: - size = 4; - break; - case ESP_IMAGE_FLASH_SIZE_8MB: - size = 8; - break; - case ESP_IMAGE_FLASH_SIZE_16MB: - size = 16; - break; - case ESP_IMAGE_FLASH_SIZE_32MB: - size = 32; - break; - case ESP_IMAGE_FLASH_SIZE_64MB: - size = 64; - break; - case ESP_IMAGE_FLASH_SIZE_128MB: - size = 128; - break; - default: - size = 2; - } - - cache_hal_disable(CACHE_TYPE_ALL); - // Set flash chip size - esp_rom_spiflash_config_param(g_rom_flashchip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff); - // TODO: set mode - // TODO: set frequency - cache_hal_enable(CACHE_TYPE_ALL); -} - -static void print_flash_info(const esp_image_header_t *bootloader_hdr) -{ - ESP_LOGD(TAG, "magic %02x", bootloader_hdr->magic); - ESP_LOGD(TAG, "segments %02x", bootloader_hdr->segment_count); - ESP_LOGD(TAG, "spi_mode %02x", bootloader_hdr->spi_mode); - ESP_LOGD(TAG, "spi_speed %02x", bootloader_hdr->spi_speed); - ESP_LOGD(TAG, "spi_size %02x", bootloader_hdr->spi_size); - - const char *str; - switch (bootloader_hdr->spi_speed) { - case ESP_IMAGE_SPI_SPEED_DIV_2: - str = "40MHz"; - break; - case ESP_IMAGE_SPI_SPEED_DIV_3: - str = "26.7MHz"; - break; - case ESP_IMAGE_SPI_SPEED_DIV_4: - str = "20MHz"; - break; - case ESP_IMAGE_SPI_SPEED_DIV_1: - str = "80MHz"; - break; - default: - str = "20MHz"; - break; - } - ESP_LOGI(TAG, "Boot SPI Speed : %s", str); - - /* SPI mode could have been set to QIO during boot already, - so test the SPI registers not the flash header */ - uint32_t spi_ctrl = REG_READ(SPI_MEM_CTRL_REG(0)); - if (spi_ctrl & SPI_MEM_FREAD_QIO) { - str = "QIO"; - } else if (spi_ctrl & SPI_MEM_FREAD_QUAD) { - str = "QOUT"; - } else if (spi_ctrl & SPI_MEM_FREAD_DIO) { - str = "DIO"; - } else if (spi_ctrl & SPI_MEM_FREAD_DUAL) { - str = "DOUT"; - } else if (spi_ctrl & SPI_MEM_FASTRD_MODE) { - str = "FAST READ"; - } else { - str = "SLOW READ"; - } - ESP_LOGI(TAG, "SPI Mode : %s", str); - - switch (bootloader_hdr->spi_size) { - case ESP_IMAGE_FLASH_SIZE_1MB: - str = "1MB"; - break; - case ESP_IMAGE_FLASH_SIZE_2MB: - str = "2MB"; - break; - case ESP_IMAGE_FLASH_SIZE_4MB: - str = "4MB"; - break; - case ESP_IMAGE_FLASH_SIZE_8MB: - str = "8MB"; - break; - case ESP_IMAGE_FLASH_SIZE_16MB: - str = "16MB"; - break; - case ESP_IMAGE_FLASH_SIZE_32MB: - str = "32MB"; - break; - case ESP_IMAGE_FLASH_SIZE_64MB: - str = "64MB"; - break; - case ESP_IMAGE_FLASH_SIZE_128MB: - str = "128MB"; - break; - default: - str = "2MB"; - break; - } - ESP_LOGI(TAG, "SPI Flash Size : %s", str); -} - -static void IRAM_ATTR bootloader_init_flash_configure(void) -{ - bootloader_flash_dummy_config(&bootloader_image_hdr); - bootloader_flash_cs_timing_config(); -} - -static esp_err_t bootloader_init_spi_flash(void) -{ - bootloader_init_flash_configure(); -#ifndef CONFIG_SPI_FLASH_ROM_DRIVER_PATCH - const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info(); - if (spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_SPI && spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI) { - ESP_LOGE(TAG, "SPI flash pins are overridden. Enable CONFIG_SPI_FLASH_ROM_DRIVER_PATCH in menuconfig"); - return ESP_FAIL; - } -#endif - -#if CONFIG_SPI_FLASH_HPM_ENABLE - // Reset flash, clear volatile bits DC[0:1]. Make it work under default mode to boot. - bootloader_spi_flash_reset(); -#endif - - bootloader_flash_unlock(); - -#if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT - if (!bootloader_flash_is_octal_mode_enabled()) { - bootloader_enable_qio_mode(); - } -#endif - - print_flash_info(&bootloader_image_hdr); - update_flash_config(&bootloader_image_hdr); - //ensure the flash is write-protected - bootloader_enable_wp(); - return ESP_OK; -} - static void wdt_reset_cpu0_info_enable(void) { REG_SET_BIT(SYSTEM_CPU_PERI_CLK_EN_REG, SYSTEM_CLK_EN_ASSIST_DEBUG);