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fix c3 hardware bug before ECO3 and optimizate bbpll config:

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1. deepsleep poweron reset bug in high temperature before ECO3;
2. brownout reset bug before ECO2;
3. bbpll voltage low bug before ECO3;
4. need xpd iph for xtal before ECO3;
This commit is contained in:
chaijie
2021-03-26 17:24:46 +08:00
committed by bot
parent ada4a8274f
commit c101fc3e3d
4 changed files with 28 additions and 14 deletions
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4
components/soc/esp32c3/include/soc/rtc_cntl_reg.h
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@@ -2362,6 +2362,10 @@ extern "C" {
#define RTC_CNTL_FIB_SEL_V 0x7
#define RTC_CNTL_FIB_SEL_S 0
#define RTC_CNTL_FIB_GLITCH_RST BIT(0)
#define RTC_CNTL_FIB_BOR_RST BIT(1)
#define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2)
#define RTC_CNTL_GPIO_WAKEUP_REG (DR_REG_RTCCNTL_BASE + 0x0110)
/* RTC_CNTL_GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */
/*description: */