alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2025-08-14 06:04:19 +00:00
Code Issues Packages Projects Releases Wiki Activity

Fix http client read return value

Browse Source 
1.esp_tls: fail connection if esp_tls_conn_new() timeouts
https://gitlab.espressif.cn:6688/espressif/esp-idf/merge_requests/7397

2.esp32:panic: avoid access cache in panichandler

3.Sync https://gitlab.espressif.cn:6688/espressif/esp-idf/merge_requests/7152
Even if frame->exccause != PANIC_RSN_CACHEERR, it is possible that the cache error interrupt status is set. For example, this may happen due to an invalid cache access in the panic$
Check cache error interrupt status instead of frame->exccause to decide whether to do CPU reset or digital reset.
Also remove unnecessary esp_dport_access_int_pause from esp_cache_err_get_cpuid, since the panic handler already calls
esp_dport_access_int_abort on entry.
This commit is contained in:
maojianxin
2020-01-09 16:16:38 +08:00
parent d396624a60
commit c1374ff769
4 changed files with 19 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
components/esp32/cache_err_int.c
View File

@@ -13,9 +13,9 @@
// limitations under the License.
/*
The cache has an interrupt that can be raised as soon as an access to a cached
region (flash, psram) is done without the cache being enabled. We use that here
to panic the CPU, which from a debugging perspective is better than grabbing bad
The cache has an interrupt that can be raised as soon as an access to a cached
region (flash, psram) is done without the cache being enabled. We use that here
to panic the CPU, which from a debugging perspective is better than grabbing bad
data from the bus.
*/
@@ -73,7 +73,6 @@ void esp_cache_err_int_init()
int IRAM_ATTR esp_cache_err_get_cpuid()
{
esp_dport_access_int_pause();
const uint32_t pro_mask =
DPORT_PRO_CPU_DISABLED_CACHE_IA_DRAM1 |
DPORT_PRO_CPU_DISABLED_CACHE_IA_DROM0 |