cache/mmu: implememnt cache and mmu hal APIs in bootloader

components/soc/esp32/include/soc/Kconfig.soc_caps.in

@@ -139,6 +139,10 @@ config SOC_ADC_MAX_BITWIDTH
     int
     default 12
 
+config SOC_SHARED_IDCACHE_SUPPORTED
+    bool
+    default y
+
 config SOC_CPU_BREAKPOINTS_NUM
     int
     default 2

components/soc/esp32/include/soc/ext_mem_defs.h

@@ -0,0 +1,45 @@
+/*
+ * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _CACHE_MEMORY_H_
+#define _CACHE_MEMORY_H_
+
+#include "esp_bit_defs.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#define IRAM0_CACHE_ADDRESS_LOW     0x400D0000
+#define IRAM0_CACHE_ADDRESS_HIGH    0x40400000
+
+#define IRAM1_CACHE_ADDRESS_LOW     0x40400000
+#define IRAM1_CACHE_ADDRESS_HIGH    0x40800000
+
+#define IROM0_CACHE_ADDRESS_LOW     0x40800000
+#define IROM0_CACHE_ADDRESS_HIGH    0x40C00000
+
+#define DRAM1_CACHE_ADDRESS_LOW     0x3F800000
+#define DRAM1_CACHE_ADDRESS_HIGH    0x3FC00000
+
+#define DROM0_CACHE_ADDRESS_LOW     0x3F400000
+#define DROM0_CACHE_ADDRESS_HIGH    0x3F800000
+
+
+#define ADDRESS_IN_BUS(bus_name, vaddr)    ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
+#define ADDRESS_IN_IRAM0_CACHE(vaddr)      ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
+#define ADDRESS_IN_IRAM1_CACHE(vaddr)      ADDRESS_IN_BUS(IRAM1_CACHE, vaddr)
+#define ADDRESS_IN_IROM0_CACHE(vaddr)      ADDRESS_IN_BUS(IROM0_CACHE, vaddr)
+#define ADDRESS_IN_DRAM1_CACHE(vaddr)      ADDRESS_IN_BUS(DRAM1_CACHE, vaddr)
+#define ADDRESS_IN_DROM0_CACHE(vaddr)      ADDRESS_IN_BUS(DROM0_CACHE, vaddr)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*_CACHE_MEMORY_H_ */

components/soc/esp32/include/soc/soc_caps.h

@@ -120,6 +120,9 @@
 #define SOC_BROWNOUT_RESET_SUPPORTED 1
 #endif
 
+/*-------------------------- CACHE CAPS --------------------------------------*/
+#define SOC_SHARED_IDCACHE_SUPPORTED            1   //Shared Cache for both instructions and data
+
 /*-------------------------- CPU CAPS ----------------------------------------*/
 #define SOC_CPU_BREAKPOINTS_NUM         2
 #define SOC_CPU_WATCHPOINTS_NUM         2