cache/mmu: implememnt cache and mmu hal APIs in bootloader

components/soc/esp32h2/include/soc/Kconfig.soc_caps.in

@@ -55,10 +55,6 @@ config SOC_EFUSE_KEY_PURPOSE_FIELD
     bool
     default y
 
-config SOC_ICACHE_ACCESS_RODATA_SUPPORTED
-    bool
-    default y
-
 config SOC_TEMP_SENSOR_SUPPORTED
     bool
     default y
@@ -167,6 +163,10 @@ config SOC_BROWNOUT_RESET_SUPPORTED
     bool
     default y
 
+config SOC_SHARED_IDCACHE_SUPPORTED
+    bool
+    default y
+
 config SOC_CPU_BREAKPOINTS_NUM
     int
     default 8

components/soc/esp32h2/include/soc/ext_mem_defs.h

@@ -6,6 +6,8 @@
 #ifndef _CACHE_MEMORY_H_
 #define _CACHE_MEMORY_H_
 
+#include "esp_bit_defs.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -35,6 +37,7 @@ extern "C" {
 #define BUS_IRAM0_CACHE_SIZE              BUS_SIZE(IRAM0_CACHE)
 #define BUS_DRAM0_CACHE_SIZE              BUS_SIZE(DRAM0_CACHE)
 
+//TODO, remove these cache function dependencies
 #define CACHE_IBUS                      0
 #define CACHE_IBUS_MMU_START            0
 #define CACHE_IBUS_MMU_END              0x200
@@ -60,6 +63,7 @@ extern "C" {
 #define MMU_BUS_SIZE(i)                 0x200
 
 #define MMU_INVALID                     BIT(8)
+#define MMU_VALID                       0
 #define MMU_TYPE                        0
 #define MMU_ACCESS_FLASH                0
 
@@ -71,12 +75,27 @@ extern "C" {
 
 #define MMU_TABLE_INVALID_VAL 0x100
 #define FLASH_MMU_TABLE_INVALID_VAL DPORT_MMU_TABLE_INVALID_VAL
-#define MMU_ADDRESS_MASK 0xff
-#define MMU_PAGE_SIZE 0x10000
+/**
+ * MMU entry valid bit mask for mapping value. For an entry:
+ * valid bit + value bits
+ * valid bit is BIT(8), so value bits are 0xff
+ */
+#define MMU_VALID_VAL_MASK 0xff
+/**
+ * Helper macro to make a MMU entry invalid
+ */
 #define INVALID_PHY_PAGE 0xffff
-
-#define BUS_ADDR_SIZE 0x800000
-#define BUS_ADDR_MASK (BUS_ADDR_SIZE - 1)
+/**
+ * Max MMU entry num.
+ * `MMU_MAX_ENTRY_NUM * MMU_PAGE_SIZE` means the max paddr and vaddr region supported by the MMU. e.g.:
+ * 256 * 64KB, means MMU can map 16MB at most
+ */
+#define MMU_MAX_ENTRY_NUM    256
+/**
+ * This is the mask used for mapping. e.g.:
+ * 0x4200_0000 & MMU_VADDR_MASK
+ */
+#define MMU_VADDR_MASK    0x7fffff
 
 #define CACHE_ICACHE_LOW_SHIFT         0
 #define CACHE_ICACHE_HIGH_SHIFT        2

components/soc/esp32h2/include/soc/mmu.h

@@ -1,20 +1,12 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #pragma once
 
 #include <stdint.h>
-#include "soc/cache_memory.h"
+#include "soc/ext_mem_defs.h"
 #include "soc/soc.h"
 
 #ifdef __cplusplus
@@ -29,7 +21,7 @@ extern "C" {
 #define SOC_MMU_DROM0_PAGES_START               (CACHE_DROM_MMU_START / sizeof(uint32_t))
 #define SOC_MMU_DROM0_PAGES_END                 (CACHE_DROM_MMU_END / sizeof(uint32_t))
 #define SOC_MMU_INVALID_ENTRY_VAL               MMU_TABLE_INVALID_VAL
-#define SOC_MMU_ADDR_MASK                       MMU_ADDRESS_MASK
+#define SOC_MMU_ADDR_MASK                       MMU_VALID_VAL_MASK
 #define SOC_MMU_PAGE_IN_FLASH(page)             (page) //Always in Flash
 #define SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE       FLASH_MMU_TABLE
 #define SOC_MMU_VADDR1_START_ADDR               IRAM0_CACHE_ADDRESS_LOW

components/soc/esp32h2/include/soc/soc_caps.h

@@ -46,7 +46,6 @@
 #define SOC_SUPPORTS_SECURE_DL_MODE         1
 #define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS   3
 #define SOC_EFUSE_KEY_PURPOSE_FIELD         1
-#define SOC_ICACHE_ACCESS_RODATA_SUPPORTED  1
 #define SOC_TEMP_SENSOR_SUPPORTED           1
 #define SOC_RTC_FAST_MEM_SUPPORTED          1
 #define SOC_RTC_SLOW_MEM_SUPPORTED          0
@@ -95,6 +94,9 @@
 /*-------------------------- BROWNOUT CAPS -----------------------------------*/
 #define SOC_BROWNOUT_RESET_SUPPORTED 1
 
+/*-------------------------- CACHE CAPS --------------------------------------*/
+#define SOC_SHARED_IDCACHE_SUPPORTED            1   //Shared Cache for both instructions and data
+
 /*-------------------------- CPU CAPS ----------------------------------------*/
 #define SOC_CPU_BREAKPOINTS_NUM         8
 #define SOC_CPU_WATCHPOINTS_NUM         8