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fix(dma): feat(adc): support ADC oneshot mod on ESP32P4

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This commit is contained in:
gaoxu
2024-03-28 15:16:12 +08:00
committed by Gao Xu
parent f36d034f7f
commit c1edeca849
32 changed files with 970 additions and 54 deletions
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18
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
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@@ -3,6 +3,10 @@
# using gen_soc_caps_kconfig.py, do not edit manually
#####################################################
config SOC_ADC_SUPPORTED
bool
default y
config SOC_ANA_CMPR_SUPPORTED
bool
default y
@@ -303,13 +307,21 @@ config SOC_AES_SUPPORT_AES_256
bool
default y
config SOC_ADC_RTC_CTRL_SUPPORTED
bool
default y
config SOC_ADC_DIG_CTRL_SUPPORTED
bool
default y
config SOC_ADC_PERIPH_NUM
int
default 1
default 2
config SOC_ADC_MAX_CHANNEL_NUM
int
default 7
default 8
config SOC_ADC_ATTEN_NUM
int
@@ -317,7 +329,7 @@ config SOC_ADC_ATTEN_NUM
config SOC_ADC_DIGI_CONTROLLER_NUM
int
default 1
default 2
config SOC_ADC_PATT_LEN_MAX
int

44
components/soc/esp32p4/include/soc/adc_channel.h
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@@ -1,7 +1,49 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#define ADC1_GPIO16_CHANNEL 0
#define ADC1_CHANNEL_0_GPIO_NUM 16
#define ADC1_GPIO17_CHANNEL 1
#define ADC1_CHANNEL_1_GPIO_NUM 17
#define ADC1_GPIO18_CHANNEL 2
#define ADC1_CHANNEL_2_GPIO_NUM 18
#define ADC1_GPIO19_CHANNEL 3
#define ADC1_CHANNEL_3_GPIO_NUM 19
#define ADC1_GPIO20_CHANNEL 4
#define ADC1_CHANNEL_4_GPIO_NUM 20
#define ADC1_GPIO21_CHANNEL 5
#define ADC1_CHANNEL_5_GPIO_NUM 21
#define ADC1_GPIO22_CHANNEL 6
#define ADC1_CHANNEL_6_GPIO_NUM 22
#define ADC1_GPIO23_CHANNEL 7
#define ADC1_CHANNEL_7_GPIO_NUM 23
#define ADC2_GPIO49_CHANNEL 0
#define ADC2_CHANNEL_0_GPIO_NUM 49
#define ADC2_GPIO50_CHANNEL 1
#define ADC2_CHANNEL_1_GPIO_NUM 50
#define ADC2_GPIO51_CHANNEL 2
#define ADC2_CHANNEL_2_GPIO_NUM 51
#define ADC2_GPIO52_CHANNEL 3
#define ADC2_CHANNEL_3_GPIO_NUM 52
#define ADC2_GPIO53_CHANNEL 4
#define ADC2_CHANNEL_4_GPIO_NUM 53
#define ADC2_GPIO54_CHANNEL 5
#define ADC2_CHANNEL_5_GPIO_NUM 54

1
components/soc/esp32p4/include/soc/adc_struct.h
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@@ -684,6 +684,7 @@ typedef struct {
volatile adc_ctrl_date_reg_t ctrl_date;
} adc_dev_t;
extern adc_dev_t ADC;
#ifndef __cplusplus
_Static_assert(sizeof(adc_dev_t) == 0x400, "Invalid size of adc_dev_t structure");

30
components/soc/esp32p4/include/soc/clk_tree_defs.h
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@@ -589,6 +589,36 @@ typedef enum {
//////////////////////////////////////////////////ADC///////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of ADC digital controller
*/
#define SOC_ADC_DIGI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST}
/**
* @brief ADC digital controller clock source
*/
typedef enum {
ADC_DIGI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
ADC_DIGI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
ADC_DIGI_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */
ADC_DIGI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default clock choice */
} soc_periph_adc_digi_clk_src_t;
/**
* @brief Array initializer for all supported clock sources of ADC RTC controller
*/
#define SOC_ADC_RTC_CLKS {SOC_MOD_CLK_RC_FAST}
/**
* @brief ADC RTC controller clock source
*/
typedef enum {
ADC_RTC_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
ADC_RTC_CLK_SRC_DEFAULT = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the default clock choice */
} soc_periph_adc_rtc_clk_src_t;
//////////////////////////////////////////////////MWDT/////////////////////////////////////////////////////////////////
/**

0
components/soc/esp32p4/include/soc/rtcadc_reg.h → components/soc/esp32p4/include/soc/lp_adc_reg.h
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25
components/soc/esp32p4/include/soc/rtcadc_struct.h → components/soc/esp32p4/include/soc/lp_adc_struct.h
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@@ -259,11 +259,11 @@ typedef union {
*/
uint32_t cocpu_saradc2_int_raw:1;
/** cocpu_saradc1_error_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
* An errro occurs from ADC1, int raw.
* An error occurs from ADC1, int raw.
*/
uint32_t cocpu_saradc1_error_int_raw:1;
/** cocpu_saradc2_error_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
* An errro occurs from ADC2, int raw.
* An error occurs from ADC2, int raw.
*/
uint32_t cocpu_saradc2_error_int_raw:1;
/** cocpu_saradc1_wake_int_raw : R/WTC/SS; bitpos: [4]; default: 0;
@@ -293,11 +293,11 @@ typedef union {
*/
uint32_t cocpu_saradc2_int_ena:1;
/** cocpu_saradc1_error_int_ena : R/WTC; bitpos: [2]; default: 0;
* An errro occurs from ADC1, int enable.
* An error occurs from ADC1, int enable.
*/
uint32_t cocpu_saradc1_error_int_ena:1;
/** cocpu_saradc2_error_int_ena : R/WTC; bitpos: [3]; default: 0;
* An errro occurs from ADC2, int enable.
* An error occurs from ADC2, int enable.
*/
uint32_t cocpu_saradc2_error_int_ena:1;
/** cocpu_saradc1_wake_int_ena : R/WTC; bitpos: [4]; default: 0;
@@ -327,11 +327,11 @@ typedef union {
*/
uint32_t cocpu_saradc2_int_st:1;
/** cocpu_saradc1_error_int_st : RO; bitpos: [2]; default: 0;
* An errro occurs from ADC1, int status.
* An error occurs from ADC1, int status.
*/
uint32_t cocpu_saradc1_error_int_st:1;
/** cocpu_saradc2_error_int_st : RO; bitpos: [3]; default: 0;
* An errro occurs from ADC2, int status.
* An error occurs from ADC2, int status.
*/
uint32_t cocpu_saradc2_error_int_st:1;
/** cocpu_saradc1_wake_int_st : RO; bitpos: [4]; default: 0;
@@ -361,11 +361,11 @@ typedef union {
*/
uint32_t cocpu_saradc2_int_clr:1;
/** cocpu_saradc1_error_int_clr : WT; bitpos: [2]; default: 0;
* An errro occurs from ADC1, int clear.
* An error occurs from ADC1, int clear.
*/
uint32_t cocpu_saradc1_error_int_clr:1;
/** cocpu_saradc2_error_int_clr : WT; bitpos: [3]; default: 0;
* An errro occurs from ADC2, int clear.
* An error occurs from ADC2, int clear.
*/
uint32_t cocpu_saradc2_error_int_clr:1;
/** cocpu_saradc1_wake_int_clr : WT; bitpos: [4]; default: 0;
@@ -395,11 +395,11 @@ typedef union {
*/
uint32_t cocpu_saradc2_int_ena_w1ts:1;
/** cocpu_saradc1_error_int_ena_w1ts : WT; bitpos: [2]; default: 0;
* An errro occurs from ADC1, write 1 to assert int enable.
* An error occurs from ADC1, write 1 to assert int enable.
*/
uint32_t cocpu_saradc1_error_int_ena_w1ts:1;
/** cocpu_saradc2_error_int_ena_w1ts : WT; bitpos: [3]; default: 0;
* An errro occurs from ADC2, write 1 to assert int enable.
* An error occurs from ADC2, write 1 to assert int enable.
*/
uint32_t cocpu_saradc2_error_int_ena_w1ts:1;
/** cocpu_saradc1_wake_int_ena_w1ts : WT; bitpos: [4]; default: 0;
@@ -429,11 +429,11 @@ typedef union {
*/
uint32_t cocpu_saradc2_int_ena_w1tc:1;
/** cocpu_saradc1_error_int_ena_w1tc : WT; bitpos: [2]; default: 0;
* An errro occurs from ADC1, write 1 to deassert int enable.
* An error occurs from ADC1, write 1 to deassert int enable.
*/
uint32_t cocpu_saradc1_error_int_ena_w1tc:1;
/** cocpu_saradc2_error_int_ena_w1tc : WT; bitpos: [3]; default: 0;
* An errro occurs from ADC2, write 1 to deassert int enable.
* An error occurs from ADC2, write 1 to deassert int enable.
*/
uint32_t cocpu_saradc2_error_int_ena_w1tc:1;
/** cocpu_saradc1_wake_int_ena_w1tc : WT; bitpos: [4]; default: 0;
@@ -592,6 +592,7 @@ typedef struct {
volatile rtcadc_sar2_hw_wakeup_reg_t sar2_hw_wakeup;
} rtcadc_dev_t;
extern rtcadc_dev_t LP_ADC;
#ifndef __cplusplus
_Static_assert(sizeof(rtcadc_dev_t) == 0x74, "Invalid size of rtcadc_dev_t structure");

41
components/soc/esp32p4/include/soc/regi2c_saradc.h
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@@ -37,3 +37,44 @@
#define I2C_SAR_ADC_DTEST_VDD_GRP1 9
#define I2C_SAR_ADC_DTEST_VDD_GRP1_MSB 3
#define I2C_SAR_ADC_DTEST_VDD_GRP1_LSB 0
#define ADC_SAR1_SAMPLE_CYCLE_ADDR 0x2
#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2
#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0
#define ADC_SAR1_DREF_ADDR 0x2
#define ADC_SAR1_DREF_ADDR_MSB 0x6
#define ADC_SAR1_DREF_ADDR_LSB 0x4
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR 0x3
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB 0x7
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB 0x0
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR 0x4
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0
#define ADC_SAR2_SAMPLE_CYCLE_ADDR 0x5
#define ADC_SAR2_SAMPLE_CYCLE_ADDR_MSB 0x2
#define ADC_SAR2_SAMPLE_CYCLE_ADDR_LSB 0x0
#define ADC_SAR2_DREF_ADDR 0x5
#define ADC_SAR2_DREF_ADDR_MSB 0x6
#define ADC_SAR2_DREF_ADDR_LSB 0x4
#define ADC_SAR1_ENCAL_REF_ADDR 0x7
#define ADC_SAR1_ENCAL_REF_ADDR_MSB 4
#define ADC_SAR1_ENCAL_REF_ADDR_LSB 4
#define ADC_SAR1_ENCAL_GND_ADDR 0x7
#define ADC_SAR1_ENCAL_GND_ADDR_MSB 5
#define ADC_SAR1_ENCAL_GND_ADDR_LSB 5
#define ADC_SAR2_ENCAL_REF_ADDR 0x7
#define ADC_SAR2_ENCAL_REF_ADDR_MSB 6
#define ADC_SAR2_ENCAL_REF_ADDR_LSB 6
#define ADC_SAR2_ENCAL_GND_ADDR 0x7
#define ADC_SAR2_ENCAL_GND_ADDR_MSB 7
#define ADC_SAR2_ENCAL_GND_ADDR_LSB 7

14
components/soc/esp32p4/include/soc/soc_caps.h
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@@ -17,7 +17,7 @@
#pragma once
/*-------------------------- COMMON CAPS ---------------------------------------*/
// #define SOC_ADC_SUPPORTED 1 //TODO: IDF-6496
#define SOC_ADC_SUPPORTED 1
#define SOC_ANA_CMPR_SUPPORTED 1
#define SOC_DEDICATED_GPIO_SUPPORTED 1
#define SOC_UART_SUPPORTED 1
@@ -108,18 +108,20 @@
/*-------------------------- ADC CAPS -------------------------------*/
/*!< SAR ADC Module*/
// #define SOC_ADC_DIG_CTRL_SUPPORTED 1 //TODO: IDF-6496, TODO: IDF-6497
#define SOC_ADC_RTC_CTRL_SUPPORTED 1
#define SOC_ADC_DIG_CTRL_SUPPORTED 1
// #define SOC_ADC_ARBITER_SUPPORTED 1
// #define SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1
// #define SOC_ADC_MONITOR_SUPPORTED 1
#define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit
// #define SOC_ADC_DMA_SUPPORTED 1
#define SOC_ADC_PERIPH_NUM (1U)
#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (7)
#define SOC_ADC_MAX_CHANNEL_NUM (7)
#define SOC_ADC_PERIPH_NUM (2)
#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (14)
#define SOC_ADC_MAX_CHANNEL_NUM (8)
#define SOC_ADC_ATTEN_NUM (4)
/*!< Digital */
#define SOC_ADC_DIGI_CONTROLLER_NUM (1U)
#define SOC_ADC_DIGI_CONTROLLER_NUM (2)
#define SOC_ADC_PATT_LEN_MAX (8) /*!< Two pattern tables, each contains 4 items. Each item takes 1 byte */
#define SOC_ADC_DIGI_MAX_BITWIDTH (12)
#define SOC_ADC_DIGI_MIN_BITWIDTH (12)