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i2s: fix incorrect sclk in legacy driver

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laokaiyao
2023-01-11 10:23:57 +08:00
parent 3df87a91a3
commit c25fc7d242
8 changed files with 12 additions and 6 deletions
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components/hal/esp32h4/include/hal/i2s_ll.h
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@@ -34,6 +34,7 @@ extern "C" {
#define I2S_LL_MCLK_DIVIDER_MAX ((1 << I2S_LL_MCLK_DIVIDER_BIT_WIDTH) - 1)
#define I2S_LL_PLL_F96M_CLK_FREQ (96 * 1000000) // PLL_F96M_CLK: 96MHz
#define I2S_LL_DEFAULT_PLL_CLK_FREQ I2S_LL_PLL_F96M_CLK_FREQ // The default PLL clock frequency while using I2S_CLK_SRC_DEFAULT
/* I2S clock configuration structure */
typedef struct {