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i2s: fix incorrect sclk in legacy driver
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@@ -43,6 +43,7 @@ extern "C" {
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#define I2S_LL_RX_EVENT_MASK I2S_LL_EVENT_RX_EOF
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#define I2S_LL_PLL_F160M_CLK_FREQ (160 * 1000000) // PLL_F160M_CLK: 160MHz
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#define I2S_LL_DEFAULT_PLL_CLK_FREQ I2S_LL_PLL_F160M_CLK_FREQ // The default PLL clock frequency while using I2S_CLK_SRC_DEFAULT
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/* I2S clock configuration structure */
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typedef struct {
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