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mspi: make cpu clock source switch safe

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For some of the MSPI high frequency setting (e.g. 80M DDR mode Flash or PSRAM), timing tuning is required.
Certain delays will be added to the MSPI RX direction. When system clock switches down, the delays should be
cleared. When system clock switches up, the delays should be restored.
This commit is contained in:
Armando
2021-10-19 12:25:08 +08:00
parent 7c3a37977f
commit c331c85318
8 changed files with 81 additions and 70 deletions
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21
components/spi_flash/esp32s3/spi_timing_config.c
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@@ -359,25 +359,20 @@ void spi_timing_config_psram_tune_dummy(uint8_t extra_dummy)
#endif //#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING
static bool spi_timing_config_cs_setup_enable(void)
/*-------------------------------------------------------------------------------------------------
* To let upper lay (spi_flash_timing_tuning.c) to know the necessary timing registers
*-------------------------------------------------------------------------------------------------*/
static bool s_get_cs_setup_enable(void)
{
return REG_GET_BIT(SPI_MEM_USER_REG(0), SPI_MEM_CS_SETUP);
}
static bool spi_timing_config_cs_hold_enable(void)
static bool s_get_cs_hold_enable(void)
{
return REG_GET_BIT(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD);
}
bool spi_timine_config_flash_is_tuned(void)
{
#if SPI_TIMING_FLASH_NEEDS_TUNING || SPI_TIMING_PSRAM_NEEDS_TUNING
return true;
#else
return false;
#endif
}
/**
* Get the SPI1 Flash CS timing setting. The setup time and hold time are both realistic cycles.
* @note On ESP32-S3, SPI0/1 share the Flash CS timing registers. Therefore, we should not change these values.
@@ -392,12 +387,12 @@ void spi_timing_config_get_cs_timing(uint8_t *setup_time, uint32_t *hold_time)
* The logic here is, if setup_en / hold_en is false, then we return the realistic cycle number,
* which is 0. If true, then the realistic cycle number is (reg_value + 1)
*/
if (spi_timing_config_cs_setup_enable()) {
if (s_get_cs_setup_enable()) {
*setup_time += 1;
} else {
*setup_time = 0;
}
if (spi_timing_config_cs_hold_enable()) {
if (s_get_cs_hold_enable()) {
*hold_time += 1;
} else {
*hold_time = 0;