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mspi: make cpu clock source switch safe

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For some of the MSPI high frequency setting (e.g. 80M DDR mode Flash or PSRAM), timing tuning is required.
Certain delays will be added to the MSPI RX direction. When system clock switches down, the delays should be
cleared. When system clock switches up, the delays should be restored.
This commit is contained in:
Armando
2021-10-19 12:25:08 +08:00
parent 7c3a37977f
commit c331c85318
8 changed files with 81 additions and 70 deletions
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2
components/spi_flash/esp_flash_spi_init.c
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@@ -296,7 +296,7 @@ esp_err_t esp_flash_init_default_chip(void)
// For chips need time tuning, get value directely from system here.
#if SOC_SPI_MEM_SUPPORT_TIME_TUNING
if (spi_timine_config_flash_is_tuned()) {
if (spi_timing_is_tuned()) {
cfg.using_timing_tuning = 1;
spi_timing_get_flash_timing_param(&cfg.timing_reg);
}