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core: fix cases where riscv SP were not 16 byte aligned

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RISC-V stack pointer should always be 16 byte aligned, but for some cases where
we were doing manual SP manipulation this was not always the case.
This commit is contained in:
Marius Vikhammer
2021-02-19 11:26:21 +08:00
parent 9830fcaff9
commit c36dd7834f
5 changed files with 19 additions and 9 deletions
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3
components/riscv/expression_with_stack_riscv.c
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@@ -38,8 +38,7 @@ static StackType_t *esp_switch_stack_setup(StackType_t *stack, size_t stack_size
//Align stack to a 16byte boundary, as required by CPU specific:
top_of_stack = (StackType_t *)(((UBaseType_t)(top_of_stack - 16) & ~0xf));
RvExcFrame *adjusted_top_of_stack = (RvExcFrame *) top_of_stack;
adjusted_top_of_stack--;
StackType_t *adjusted_top_of_stack = top_of_stack - RV_STK_FRMSZ;
#if CONFIG_FREERTOS_WATCHPOINT_END_OF_STACK
vPortSetStackWatchpoint(stack);