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core: fix cases where riscv SP were not 16 byte aligned

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RISC-V stack pointer should always be 16 byte aligned, but for some cases where
we were doing manual SP manipulation this was not always the case.
This commit is contained in:
Marius Vikhammer
2021-02-19 11:26:21 +08:00
parent 9830fcaff9
commit c36dd7834f
5 changed files with 19 additions and 9 deletions
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7
components/riscv/expression_with_stack_riscv_asm.S
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@@ -24,8 +24,9 @@ esp_shared_stack_invoke_function:
/* Set shared stack as new stack pointer */
mv sp, a1
/* store the ra and previous stack pointer in a safe place */
addi sp,sp,-4
/* store the ra and previous stack pointer in a safe place
stack pointer for riscv should always be 16 byte aligned */
addi sp,sp,-16
sw t0, 0(sp)
sw t1, 4(sp)
@@ -35,7 +36,7 @@ esp_shared_stack_invoke_function:
/* gets the ra and stack pointer saved previously */
lw t0, 0(sp)
lw t1, 4(sp)
addi sp, sp, 4
addi sp, sp, 16
/* restore both ra and real stack pointer of current task */
mv ra, t1