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rename clock enable and reset bits for SPI modules

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1.The names of clock enable and reset bits do not match with TRM, just rename them.
This commit is contained in:
jack
2018-04-24 16:38:46 +08:00
parent d4276efed7
commit c384fa2492
6 changed files with 27 additions and 21 deletions
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8
components/esp32/clk.c
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@@ -221,7 +221,7 @@ void esp_perip_clk_init(void)
#if CONFIG_CONSOLE_UART_NUM != 2
DPORT_UART2_CLK_EN |
#endif
DPORT_SPI_CLK_EN |
DPORT_SPI2_CLK_EN |
DPORT_I2C_EXT0_CLK_EN |
DPORT_UHCI0_CLK_EN |
DPORT_RMT_CLK_EN |
@@ -229,7 +229,7 @@ void esp_perip_clk_init(void)
DPORT_LEDC_CLK_EN |
DPORT_UHCI1_CLK_EN |
DPORT_TIMERGROUP1_CLK_EN |
DPORT_SPI_CLK_EN_2 |
DPORT_SPI3_CLK_EN |
DPORT_PWM0_CLK_EN |
DPORT_I2C_EXT1_CLK_EN |
DPORT_CAN_CLK_EN |
@@ -253,11 +253,11 @@ void esp_perip_clk_init(void)
#if CONFIG_SPIRAM_SPEED_80M
//80MHz SPIRAM uses SPI2 as well; it's initialized before this is called. Because it is used in
//80MHz SPIRAM uses SPI3 as well; it's initialized before this is called. Because it is used in
//a weird mode where clock to the peripheral is disabled but reset is also disabled, it 'hangs'
//in a state where it outputs a continuous 80MHz signal. Mask its bit here because we should
//not modify that state, regardless of what we calculated earlier.
common_perip_clk &= ~DPORT_SPI_CLK_EN_2;
common_perip_clk &= ~DPORT_SPI3_CLK_EN;
#endif
/* Change I2S clock to audio PLL first. Because if I2S uses 160MHz clock,

2
components/esp32/spiram_psram.c
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@@ -543,7 +543,7 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vad
while (1) {
spi_status = READ_PERI_REG(SPI_EXT2_REG(PSRAM_SPI_3));
if (spi_status != 0 && spi_status != 1) {
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI_CLK_EN_2);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI3_CLK_EN);
break;
}
}

2
components/esp32/system_api.c
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@@ -327,7 +327,7 @@ void IRAM_ATTR esp_restart_noos()
// Reset timer/spi/uart
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,
DPORT_TIMERS_RST | DPORT_SPI_RST_1 | DPORT_UART_RST);
DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_UART_RST);
DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0);
// Set CPU back to XTAL source, no PLL, same as hard reset

6
components/esp32/test/test_intr_alloc.c
View File

@@ -16,6 +16,7 @@
#include "soc/dport_reg.h"
#include "soc/io_mux_reg.h"
#include "esp_intr_alloc.h"
#include "driver/periph_ctrl.h"
#include "driver/timer.h"
@@ -266,9 +267,8 @@ TEST_CASE("allocate 2 handlers for a same source and remove the later one","[esp
intr_alloc_test_ctx_t ctx = {false, false, false, false };
intr_handle_t handle1, handle2;
//enable spi
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI_CLK_EN );
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_RST);
//enable HSPI(spi2)
periph_module_enable(PERIPH_HSPI_MODULE);
esp_err_t r;
r=esp_intr_alloc(ETS_SPI2_INTR_SOURCE, ESP_INTR_FLAG_SHARED, int_handler1, &ctx, &handle1);