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rename clock enable and reset bits for SPI modules

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1.The names of clock enable and reset bits do not match with TRM, just rename them.
This commit is contained in:
jack
2018-04-24 16:38:46 +08:00
parent d4276efed7
commit c384fa2492
6 changed files with 27 additions and 21 deletions
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18
components/soc/esp32/include/soc/dport_reg.h
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@@ -958,7 +958,8 @@
#define DPORT_CAN_CLK_EN (BIT(19))
#define DPORT_I2C_EXT1_CLK_EN (BIT(18))
#define DPORT_PWM0_CLK_EN (BIT(17))
#define DPORT_SPI_CLK_EN_2 (BIT(16))
#define DPORT_SPI_CLK_EN_2 (BIT(16)) /** Deprecated, please use DPORT_SPI3_CLK_EN **/
#define DPORT_SPI3_CLK_EN (BIT(16))
#define DPORT_TIMERGROUP1_CLK_EN (BIT(15))
#define DPORT_EFUSE_CLK_EN (BIT(14))
#define DPORT_TIMERGROUP_CLK_EN (BIT(13))
@@ -968,12 +969,14 @@
#define DPORT_RMT_CLK_EN (BIT(9))
#define DPORT_UHCI0_CLK_EN (BIT(8))
#define DPORT_I2C_EXT0_CLK_EN (BIT(7))
#define DPORT_SPI_CLK_EN (BIT(6))
#define DPORT_SPI_CLK_EN (BIT(6)) /** Deprecated, please use DPORT_SPI2_CLK_EN **/
#define DPORT_SPI2_CLK_EN (BIT(6))
#define DPORT_UART1_CLK_EN (BIT(5))
#define DPORT_I2S0_CLK_EN (BIT(4))
#define DPORT_WDG_CLK_EN (BIT(3))
#define DPORT_UART_CLK_EN (BIT(2))
#define DPORT_SPI_CLK_EN_1 (BIT(1))
#define DPORT_SPI_CLK_EN_1 (BIT(1)) /** Deprecated, please use DPORT_SPI01_CLK_EN **/
#define DPORT_SPI01_CLK_EN (BIT(1))
#define DPORT_TIMERS_CLK_EN (BIT(0))
#define DPORT_PERIP_RST_EN_REG (DR_REG_DPORT_BASE + 0x0C4)
/* DPORT_PERIP_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
@@ -992,7 +995,8 @@
#define DPORT_CAN_RST (BIT(19))
#define DPORT_I2C_EXT1_RST (BIT(18))
#define DPORT_PWM0_RST (BIT(17))
#define DPORT_SPI_RST_2 (BIT(16))
#define DPORT_SPI_RST_2 (BIT(16)) /** Deprecated, please use DPORT_SPI3_RST **/
#define DPORT_SPI3_RST (BIT(16))
#define DPORT_TIMERGROUP1_RST (BIT(15))
#define DPORT_EFUSE_RST (BIT(14))
#define DPORT_TIMERGROUP_RST (BIT(13))
@@ -1002,12 +1006,14 @@
#define DPORT_RMT_RST (BIT(9))
#define DPORT_UHCI0_RST (BIT(8))
#define DPORT_I2C_EXT0_RST (BIT(7))
#define DPORT_SPI_RST (BIT(6))
#define DPORT_SPI_RST (BIT(6)) /** Deprecated, please use DPORT_SPI2_RST **/
#define DPORT_SPI2_RST (BIT(6))
#define DPORT_UART1_RST (BIT(5))
#define DPORT_I2S0_RST (BIT(4))
#define DPORT_WDG_RST (BIT(3))
#define DPORT_UART_RST (BIT(2))
#define DPORT_SPI_RST_1 (BIT(1))
#define DPORT_SPI_RST_1 (BIT(1)) /** Deprecated, please use DPORT_SPI01_RST **/
#define DPORT_SPI01_RST (BIT(1))
#define DPORT_TIMERS_RST (BIT(0))
#define DPORT_SLAVE_SPI_CONFIG_REG (DR_REG_DPORT_BASE + 0x0C8)
/* DPORT_SPI_DECRYPT_ENABLE : R/W ;bitpos:[12] ;default: 1'b0 ; */