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Merge branch 'fix/flash_noos_issues_v5.1' into 'release/v5.1'

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flash: fixed some no_os API issues (v5.1)

See merge request espressif/esp-idf!35795
This commit is contained in:
morris
2024-12-23 17:34:21 +08:00
parent 81a34cbbc7 218947014c
commit c3b7a31f28
3 changed files with 23 additions and 61 deletions
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7
components/esp_system/port/cpu_start.c
View File

@@ -45,7 +45,6 @@
#include "soc/assist_debug_reg.h" #include "soc/assist_debug_reg.h"
#include "soc/system_reg.h" #include "soc/system_reg.h"
#include "esp32s3/rom/opi_flash.h" #include "esp32s3/rom/opi_flash.h"
#include "hal/cache_hal.h"
#elif CONFIG_IDF_TARGET_ESP32C3 #elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rtc.h" #include "esp32c3/rtc.h"
#include "esp32c3/rom/cache.h" #include "esp32c3/rom/cache.h"
@@ -83,6 +82,7 @@
#include "esp_private/sleep_gpio.h" #include "esp_private/sleep_gpio.h"
#include "hal/wdt_hal.h" #include "hal/wdt_hal.h"
#include "soc/rtc.h" #include "soc/rtc.h"
#include "hal/cache_hal.h"
#include "hal/cache_ll.h" #include "hal/cache_ll.h"
#include "hal/efuse_ll.h" #include "hal/efuse_ll.h"
#include "soc/periph_defs.h" #include "soc/periph_defs.h"
@@ -374,6 +374,11 @@ void IRAM_ATTR call_start_cpu0(void)
#endif #endif
#endif // !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP #endif // !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
//cache hal ctx needs to be initialised
cache_hal_init();
#endif
// When the APP is loaded into ram for execution, some hardware initialization behaviors // When the APP is loaded into ram for execution, some hardware initialization behaviors
// in the bootloader are still necessary // in the bootloader are still necessary
#if CONFIG_APP_BUILD_TYPE_RAM #if CONFIG_APP_BUILD_TYPE_RAM

7
components/hal/esp32/cache_hal_esp32.c
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -8,6 +8,11 @@
static uint32_t s_cache_status[2]; static uint32_t s_cache_status[2];
void cache_hal_init(void)
{
//for compatibility
}
void cache_hal_suspend(cache_type_t type) void cache_hal_suspend(cache_type_t type)
{ {
s_cache_status[0] = cache_ll_l1_get_enabled_bus(0); s_cache_status[0] = cache_ll_l1_get_enabled_bus(0);

70
components/spi_flash/spi_flash_os_func_noos.c
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -8,59 +8,21 @@
#include "sdkconfig.h" #include "sdkconfig.h"
#include "esp_flash.h" #include "esp_flash.h"
#include "esp_attr.h" #include "esp_attr.h"
#include "esp_rom_sys.h" #include "esp_rom_sys.h"
#if CONFIG_IDF_TARGET_ESP32 #include "rom/cache.h"
#include "esp32/rom/cache.h" #include "hal/cache_hal.h"
#elif CONFIG_IDF_TARGET_ESP32S2 #include "hal/cache_ll.h"
#include "esp32s2/rom/cache.h" #include "soc/soc_caps.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/ets_sys.h"
#include "esp32s3/rom/cache.h"
#elif CONFIG_IDF_TARGET_ESP32C3
#include "esp32c3/rom/ets_sys.h"
#include "esp32c3/rom/cache.h"
#elif CONFIG_IDF_TARGET_ESP32C2
#include "esp32c2/rom/ets_sys.h"
#include "esp32c2/rom/cache.h"
#elif CONFIG_IDF_TARGET_ESP32C6
#include "esp32c6/rom/ets_sys.h"
#include "esp32c6/rom/cache.h"
#elif CONFIG_IDF_TARGET_ESP32H2
#include "esp32h2/rom/ets_sys.h"
#include "esp32h2/rom/cache.h"
#endif
#include "esp_attr.h"
#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
typedef struct {
uint32_t icache_autoload;
uint32_t dcache_autoload;
} spi_noos_arg_t;
static DRAM_ATTR spi_noos_arg_t spi_arg = { 0 };
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
typedef struct {
uint32_t icache_autoload;
} spi_noos_arg_t;
static DRAM_ATTR spi_noos_arg_t spi_arg = { 0 };
#endif
static IRAM_ATTR esp_err_t start(void *arg) static IRAM_ATTR esp_err_t start(void *arg)
{ {
#if CONFIG_IDF_TARGET_ESP32 #if CONFIG_IDF_TARGET_ESP32
Cache_Read_Disable(0); Cache_Read_Disable(0);
Cache_Read_Disable(1); Cache_Read_Disable(1);
#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 #else
spi_noos_arg_t *spi_arg = arg; cache_hal_suspend(CACHE_TYPE_ALL);
spi_arg->icache_autoload = Cache_Suspend_ICache();
spi_arg->dcache_autoload = Cache_Suspend_DCache();
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
spi_noos_arg_t *spi_arg = arg;
spi_arg->icache_autoload = Cache_Suspend_ICache();
#endif #endif
return ESP_OK; return ESP_OK;
} }
@@ -69,16 +31,10 @@ static IRAM_ATTR esp_err_t end(void *arg)
#if CONFIG_IDF_TARGET_ESP32 #if CONFIG_IDF_TARGET_ESP32
Cache_Read_Enable(0); Cache_Read_Enable(0);
Cache_Read_Enable(1); Cache_Read_Enable(1);
#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 #else
spi_noos_arg_t *spi_arg = arg; cache_hal_resume(CACHE_TYPE_ALL);
Cache_Invalidate_ICache_All();
Cache_Resume_ICache(spi_arg->icache_autoload);
Cache_Resume_DCache(spi_arg->dcache_autoload);
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2
spi_noos_arg_t *spi_arg = arg;
Cache_Invalidate_ICache_All();
Cache_Resume_ICache(spi_arg->icache_autoload);
#endif #endif
return ESP_OK; return ESP_OK;
} }
@@ -110,9 +66,5 @@ esp_err_t IRAM_ATTR esp_flash_app_disable_os_functions(esp_flash_t* chip)
{ {
chip->os_func = &esp_flash_noos_functions; chip->os_func = &esp_flash_noos_functions;
#if !CONFIG_IDF_TARGET_ESP32
chip->os_func_data = &spi_arg;
#endif
return ESP_OK; return ESP_OK;
} }