mirror of
https://github.com/espressif/esp-idf.git
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refactor(soc): sort esp32s3 soc headers
This commit is contained in:
laokaiyao
committed by
Kevin (Lao Kaiyao)
Kevin (Lao Kaiyao)
parent
6a29351bd0
commit
c3e0dd610a
@@ -1,656 +0,0 @@
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/*
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* SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _SOC_APB_CTRL_REG_H_
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#define _SOC_APB_CTRL_REG_H_
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#warning "apb_ctrl_reg is deprecated due to duplicated with syscon_reg, please use syscon_reg instead, they are same"
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#include "soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define APB_CTRL_SYSCLK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x0)
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/* APB_CTRL_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */
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/*description: .*/
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#define APB_CTRL_RST_TICK_CNT (BIT(12))
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#define APB_CTRL_RST_TICK_CNT_M (BIT(12))
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#define APB_CTRL_RST_TICK_CNT_V 0x1
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#define APB_CTRL_RST_TICK_CNT_S 12
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/* APB_CTRL_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
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/*description: .*/
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#define APB_CTRL_CLK_EN (BIT(11))
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#define APB_CTRL_CLK_EN_M (BIT(11))
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#define APB_CTRL_CLK_EN_V 0x1
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#define APB_CTRL_CLK_EN_S 11
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/* APB_CTRL_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
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/*description: .*/
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#define APB_CTRL_CLK_320M_EN (BIT(10))
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#define APB_CTRL_CLK_320M_EN_M (BIT(10))
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#define APB_CTRL_CLK_320M_EN_V 0x1
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#define APB_CTRL_CLK_320M_EN_S 10
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/* APB_CTRL_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */
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/*description: .*/
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#define APB_CTRL_PRE_DIV_CNT 0x000003FF
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#define APB_CTRL_PRE_DIV_CNT_M ((APB_CTRL_PRE_DIV_CNT_V)<<(APB_CTRL_PRE_DIV_CNT_S))
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#define APB_CTRL_PRE_DIV_CNT_V 0x3FF
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#define APB_CTRL_PRE_DIV_CNT_S 0
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#define APB_CTRL_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x4)
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/* APB_CTRL_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */
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/*description: .*/
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#define APB_CTRL_TICK_ENABLE (BIT(16))
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#define APB_CTRL_TICK_ENABLE_M (BIT(16))
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#define APB_CTRL_TICK_ENABLE_V 0x1
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#define APB_CTRL_TICK_ENABLE_S 16
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/* APB_CTRL_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */
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/*description: .*/
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#define APB_CTRL_CK8M_TICK_NUM 0x000000FF
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#define APB_CTRL_CK8M_TICK_NUM_M ((APB_CTRL_CK8M_TICK_NUM_V)<<(APB_CTRL_CK8M_TICK_NUM_S))
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#define APB_CTRL_CK8M_TICK_NUM_V 0xFF
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#define APB_CTRL_CK8M_TICK_NUM_S 8
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/* APB_CTRL_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */
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/*description: .*/
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#define APB_CTRL_XTAL_TICK_NUM 0x000000FF
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#define APB_CTRL_XTAL_TICK_NUM_M ((APB_CTRL_XTAL_TICK_NUM_V)<<(APB_CTRL_XTAL_TICK_NUM_S))
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#define APB_CTRL_XTAL_TICK_NUM_V 0xFF
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#define APB_CTRL_XTAL_TICK_NUM_S 0
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#define APB_CTRL_CLK_OUT_EN_REG (DR_REG_APB_CTRL_BASE + 0x8)
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/* APB_CTRL_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */
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/*description: .*/
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#define APB_CTRL_CLK_XTAL_OEN (BIT(10))
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#define APB_CTRL_CLK_XTAL_OEN_M (BIT(10))
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#define APB_CTRL_CLK_XTAL_OEN_V 0x1
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#define APB_CTRL_CLK_XTAL_OEN_S 10
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/* APB_CTRL_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */
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/*description: .*/
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#define APB_CTRL_CLK40X_BB_OEN (BIT(9))
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#define APB_CTRL_CLK40X_BB_OEN_M (BIT(9))
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#define APB_CTRL_CLK40X_BB_OEN_V 0x1
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#define APB_CTRL_CLK40X_BB_OEN_S 9
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/* APB_CTRL_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */
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/*description: .*/
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#define APB_CTRL_CLK_DAC_CPU_OEN (BIT(8))
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#define APB_CTRL_CLK_DAC_CPU_OEN_M (BIT(8))
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#define APB_CTRL_CLK_DAC_CPU_OEN_V 0x1
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#define APB_CTRL_CLK_DAC_CPU_OEN_S 8
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/* APB_CTRL_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */
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/*description: .*/
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#define APB_CTRL_CLK_ADC_INF_OEN (BIT(7))
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#define APB_CTRL_CLK_ADC_INF_OEN_M (BIT(7))
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#define APB_CTRL_CLK_ADC_INF_OEN_V 0x1
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#define APB_CTRL_CLK_ADC_INF_OEN_S 7
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/* APB_CTRL_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */
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/*description: .*/
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#define APB_CTRL_CLK_320M_OEN (BIT(6))
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#define APB_CTRL_CLK_320M_OEN_M (BIT(6))
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#define APB_CTRL_CLK_320M_OEN_V 0x1
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#define APB_CTRL_CLK_320M_OEN_S 6
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/* APB_CTRL_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */
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/*description: .*/
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#define APB_CTRL_CLK160_OEN (BIT(5))
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#define APB_CTRL_CLK160_OEN_M (BIT(5))
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#define APB_CTRL_CLK160_OEN_V 0x1
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#define APB_CTRL_CLK160_OEN_S 5
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/* APB_CTRL_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */
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/*description: .*/
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#define APB_CTRL_CLK80_OEN (BIT(4))
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#define APB_CTRL_CLK80_OEN_M (BIT(4))
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#define APB_CTRL_CLK80_OEN_V 0x1
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#define APB_CTRL_CLK80_OEN_S 4
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/* APB_CTRL_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */
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/*description: .*/
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#define APB_CTRL_CLK_BB_OEN (BIT(3))
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#define APB_CTRL_CLK_BB_OEN_M (BIT(3))
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#define APB_CTRL_CLK_BB_OEN_V 0x1
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#define APB_CTRL_CLK_BB_OEN_S 3
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/* APB_CTRL_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */
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/*description: .*/
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#define APB_CTRL_CLK44_OEN (BIT(2))
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#define APB_CTRL_CLK44_OEN_M (BIT(2))
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#define APB_CTRL_CLK44_OEN_V 0x1
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#define APB_CTRL_CLK44_OEN_S 2
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/* APB_CTRL_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */
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/*description: .*/
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#define APB_CTRL_CLK22_OEN (BIT(1))
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#define APB_CTRL_CLK22_OEN_M (BIT(1))
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#define APB_CTRL_CLK22_OEN_V 0x1
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#define APB_CTRL_CLK22_OEN_S 1
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/* APB_CTRL_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */
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/*description: .*/
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#define APB_CTRL_CLK20_OEN (BIT(0))
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#define APB_CTRL_CLK20_OEN_M (BIT(0))
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#define APB_CTRL_CLK20_OEN_V 0x1
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#define APB_CTRL_CLK20_OEN_S 0
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#define APB_CTRL_WIFI_BB_CFG_REG (DR_REG_APB_CTRL_BASE + 0xC)
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/* APB_CTRL_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
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/*description: .*/
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#define APB_CTRL_WIFI_BB_CFG 0xFFFFFFFF
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#define APB_CTRL_WIFI_BB_CFG_M ((APB_CTRL_WIFI_BB_CFG_V)<<(APB_CTRL_WIFI_BB_CFG_S))
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#define APB_CTRL_WIFI_BB_CFG_V 0xFFFFFFFF
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#define APB_CTRL_WIFI_BB_CFG_S 0
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#define APB_CTRL_WIFI_BB_CFG_2_REG (DR_REG_APB_CTRL_BASE + 0x10)
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/* APB_CTRL_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
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/*description: .*/
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#define APB_CTRL_WIFI_BB_CFG_2 0xFFFFFFFF
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#define APB_CTRL_WIFI_BB_CFG_2_M ((APB_CTRL_WIFI_BB_CFG_2_V)<<(APB_CTRL_WIFI_BB_CFG_2_S))
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#define APB_CTRL_WIFI_BB_CFG_2_V 0xFFFFFFFF
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#define APB_CTRL_WIFI_BB_CFG_2_S 0
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#define APB_CTRL_WIFI_CLK_EN_REG (DR_REG_APB_CTRL_BASE + 0x14)
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/* APB_CTRL_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
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/*description: .*/
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#define APB_CTRL_WIFI_CLK_EN 0xFFFFFFFF
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#define APB_CTRL_WIFI_CLK_EN_M ((APB_CTRL_WIFI_CLK_EN_V)<<(APB_CTRL_WIFI_CLK_EN_S))
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#define APB_CTRL_WIFI_CLK_EN_V 0xFFFFFFFF
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#define APB_CTRL_WIFI_CLK_EN_S 0
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#define APB_CTRL_WIFI_RST_EN_REG (DR_REG_APB_CTRL_BASE + 0x18)
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/* APB_CTRL_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
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/*description: .*/
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#define APB_CTRL_WIFI_RST 0xFFFFFFFF
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#define APB_CTRL_WIFI_RST_M ((APB_CTRL_WIFI_RST_V)<<(APB_CTRL_WIFI_RST_S))
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#define APB_CTRL_WIFI_RST_V 0xFFFFFFFF
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#define APB_CTRL_WIFI_RST_S 0
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#define APB_CTRL_HOST_INF_SEL_REG (DR_REG_APB_CTRL_BASE + 0x1C)
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/* APB_CTRL_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
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/*description: .*/
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#define APB_CTRL_PERI_IO_SWAP 0x000000FF
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#define APB_CTRL_PERI_IO_SWAP_M ((APB_CTRL_PERI_IO_SWAP_V)<<(APB_CTRL_PERI_IO_SWAP_S))
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#define APB_CTRL_PERI_IO_SWAP_V 0xFF
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#define APB_CTRL_PERI_IO_SWAP_S 0
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#define APB_CTRL_EXT_MEM_PMS_LOCK_REG (DR_REG_APB_CTRL_BASE + 0x20)
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/* APB_CTRL_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
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/*description: .*/
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#define APB_CTRL_EXT_MEM_PMS_LOCK (BIT(0))
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#define APB_CTRL_EXT_MEM_PMS_LOCK_M (BIT(0))
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#define APB_CTRL_EXT_MEM_PMS_LOCK_V 0x1
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#define APB_CTRL_EXT_MEM_PMS_LOCK_S 0
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#define APB_CTRL_EXT_MEM_WRITEBACK_BYPASS_REG (DR_REG_APB_CTRL_BASE + 0x24)
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/* APB_CTRL_WRITEBACK_BYPASS : R/W ;bitpos:[0] ;default: 1'b0 ; */
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/*description: Set 1 to bypass cache writeback request to external memory so that spi will not
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check its attribute..*/
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#define APB_CTRL_WRITEBACK_BYPASS (BIT(0))
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#define APB_CTRL_WRITEBACK_BYPASS_M (BIT(0))
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#define APB_CTRL_WRITEBACK_BYPASS_V 0x1
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#define APB_CTRL_WRITEBACK_BYPASS_S 0
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#define APB_CTRL_FLASH_ACE0_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x28)
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/* APB_CTRL_FLASH_ACE0_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
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/*description: .*/
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#define APB_CTRL_FLASH_ACE0_ATTR 0x000001FF
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#define APB_CTRL_FLASH_ACE0_ATTR_M ((APB_CTRL_FLASH_ACE0_ATTR_V)<<(APB_CTRL_FLASH_ACE0_ATTR_S))
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#define APB_CTRL_FLASH_ACE0_ATTR_V 0x1FF
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#define APB_CTRL_FLASH_ACE0_ATTR_S 0
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#define APB_CTRL_FLASH_ACE1_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x2C)
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/* APB_CTRL_FLASH_ACE1_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
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/*description: .*/
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#define APB_CTRL_FLASH_ACE1_ATTR 0x000001FF
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#define APB_CTRL_FLASH_ACE1_ATTR_M ((APB_CTRL_FLASH_ACE1_ATTR_V)<<(APB_CTRL_FLASH_ACE1_ATTR_S))
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#define APB_CTRL_FLASH_ACE1_ATTR_V 0x1FF
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#define APB_CTRL_FLASH_ACE1_ATTR_S 0
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#define APB_CTRL_FLASH_ACE2_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x30)
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/* APB_CTRL_FLASH_ACE2_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
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/*description: .*/
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#define APB_CTRL_FLASH_ACE2_ATTR 0x000001FF
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#define APB_CTRL_FLASH_ACE2_ATTR_M ((APB_CTRL_FLASH_ACE2_ATTR_V)<<(APB_CTRL_FLASH_ACE2_ATTR_S))
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#define APB_CTRL_FLASH_ACE2_ATTR_V 0x1FF
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#define APB_CTRL_FLASH_ACE2_ATTR_S 0
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#define APB_CTRL_FLASH_ACE3_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x34)
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/* APB_CTRL_FLASH_ACE3_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
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/*description: .*/
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#define APB_CTRL_FLASH_ACE3_ATTR 0x000001FF
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#define APB_CTRL_FLASH_ACE3_ATTR_M ((APB_CTRL_FLASH_ACE3_ATTR_V)<<(APB_CTRL_FLASH_ACE3_ATTR_S))
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#define APB_CTRL_FLASH_ACE3_ATTR_V 0x1FF
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#define APB_CTRL_FLASH_ACE3_ATTR_S 0
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#define APB_CTRL_FLASH_ACE0_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x38)
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/* APB_CTRL_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
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/*description: .*/
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#define APB_CTRL_FLASH_ACE0_ADDR_S 0xFFFFFFFF
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#define APB_CTRL_FLASH_ACE0_ADDR_S_M ((APB_CTRL_FLASH_ACE0_ADDR_S_V)<<(APB_CTRL_FLASH_ACE0_ADDR_S_S))
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#define APB_CTRL_FLASH_ACE0_ADDR_S_V 0xFFFFFFFF
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#define APB_CTRL_FLASH_ACE0_ADDR_S_S 0
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#define APB_CTRL_FLASH_ACE1_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x3C)
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/* APB_CTRL_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */
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/*description: .*/
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#define APB_CTRL_FLASH_ACE1_ADDR_S 0xFFFFFFFF
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#define APB_CTRL_FLASH_ACE1_ADDR_S_M ((APB_CTRL_FLASH_ACE1_ADDR_S_V)<<(APB_CTRL_FLASH_ACE1_ADDR_S_S))
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#define APB_CTRL_FLASH_ACE1_ADDR_S_V 0xFFFFFFFF
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#define APB_CTRL_FLASH_ACE1_ADDR_S_S 0
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#define APB_CTRL_FLASH_ACE2_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x40)
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/* APB_CTRL_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */
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/*description: .*/
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#define APB_CTRL_FLASH_ACE2_ADDR_S 0xFFFFFFFF
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#define APB_CTRL_FLASH_ACE2_ADDR_S_M ((APB_CTRL_FLASH_ACE2_ADDR_S_V)<<(APB_CTRL_FLASH_ACE2_ADDR_S_S))
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#define APB_CTRL_FLASH_ACE2_ADDR_S_V 0xFFFFFFFF
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#define APB_CTRL_FLASH_ACE2_ADDR_S_S 0
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#define APB_CTRL_FLASH_ACE3_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x44)
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/* APB_CTRL_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */
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/*description: .*/
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#define APB_CTRL_FLASH_ACE3_ADDR_S 0xFFFFFFFF
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#define APB_CTRL_FLASH_ACE3_ADDR_S_M ((APB_CTRL_FLASH_ACE3_ADDR_S_V)<<(APB_CTRL_FLASH_ACE3_ADDR_S_S))
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#define APB_CTRL_FLASH_ACE3_ADDR_S_V 0xFFFFFFFF
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#define APB_CTRL_FLASH_ACE3_ADDR_S_S 0
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#define APB_CTRL_FLASH_ACE0_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x48)
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/* APB_CTRL_FLASH_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
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/*description: .*/
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#define APB_CTRL_FLASH_ACE0_SIZE 0x0000FFFF
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#define APB_CTRL_FLASH_ACE0_SIZE_M ((APB_CTRL_FLASH_ACE0_SIZE_V)<<(APB_CTRL_FLASH_ACE0_SIZE_S))
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#define APB_CTRL_FLASH_ACE0_SIZE_V 0xFFFF
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#define APB_CTRL_FLASH_ACE0_SIZE_S 0
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#define APB_CTRL_FLASH_ACE1_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x4C)
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/* APB_CTRL_FLASH_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
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/*description: .*/
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#define APB_CTRL_FLASH_ACE1_SIZE 0x0000FFFF
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#define APB_CTRL_FLASH_ACE1_SIZE_M ((APB_CTRL_FLASH_ACE1_SIZE_V)<<(APB_CTRL_FLASH_ACE1_SIZE_S))
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#define APB_CTRL_FLASH_ACE1_SIZE_V 0xFFFF
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#define APB_CTRL_FLASH_ACE1_SIZE_S 0
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#define APB_CTRL_FLASH_ACE2_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x50)
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/* APB_CTRL_FLASH_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
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/*description: .*/
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#define APB_CTRL_FLASH_ACE2_SIZE 0x0000FFFF
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#define APB_CTRL_FLASH_ACE2_SIZE_M ((APB_CTRL_FLASH_ACE2_SIZE_V)<<(APB_CTRL_FLASH_ACE2_SIZE_S))
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#define APB_CTRL_FLASH_ACE2_SIZE_V 0xFFFF
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#define APB_CTRL_FLASH_ACE2_SIZE_S 0
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#define APB_CTRL_FLASH_ACE3_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x54)
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/* APB_CTRL_FLASH_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
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/*description: .*/
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#define APB_CTRL_FLASH_ACE3_SIZE 0x0000FFFF
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#define APB_CTRL_FLASH_ACE3_SIZE_M ((APB_CTRL_FLASH_ACE3_SIZE_V)<<(APB_CTRL_FLASH_ACE3_SIZE_S))
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#define APB_CTRL_FLASH_ACE3_SIZE_V 0xFFFF
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#define APB_CTRL_FLASH_ACE3_SIZE_S 0
|
||||
|
||||
#define APB_CTRL_SRAM_ACE0_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x58)
|
||||
/* APB_CTRL_SRAM_ACE0_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_SRAM_ACE0_ATTR 0x000001FF
|
||||
#define APB_CTRL_SRAM_ACE0_ATTR_M ((APB_CTRL_SRAM_ACE0_ATTR_V)<<(APB_CTRL_SRAM_ACE0_ATTR_S))
|
||||
#define APB_CTRL_SRAM_ACE0_ATTR_V 0x1FF
|
||||
#define APB_CTRL_SRAM_ACE0_ATTR_S 0
|
||||
|
||||
#define APB_CTRL_SRAM_ACE1_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x5C)
|
||||
/* APB_CTRL_SRAM_ACE1_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_SRAM_ACE1_ATTR 0x000001FF
|
||||
#define APB_CTRL_SRAM_ACE1_ATTR_M ((APB_CTRL_SRAM_ACE1_ATTR_V)<<(APB_CTRL_SRAM_ACE1_ATTR_S))
|
||||
#define APB_CTRL_SRAM_ACE1_ATTR_V 0x1FF
|
||||
#define APB_CTRL_SRAM_ACE1_ATTR_S 0
|
||||
|
||||
#define APB_CTRL_SRAM_ACE2_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x60)
|
||||
/* APB_CTRL_SRAM_ACE2_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_SRAM_ACE2_ATTR 0x000001FF
|
||||
#define APB_CTRL_SRAM_ACE2_ATTR_M ((APB_CTRL_SRAM_ACE2_ATTR_V)<<(APB_CTRL_SRAM_ACE2_ATTR_S))
|
||||
#define APB_CTRL_SRAM_ACE2_ATTR_V 0x1FF
|
||||
#define APB_CTRL_SRAM_ACE2_ATTR_S 0
|
||||
|
||||
#define APB_CTRL_SRAM_ACE3_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x64)
|
||||
/* APB_CTRL_SRAM_ACE3_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_SRAM_ACE3_ATTR 0x000001FF
|
||||
#define APB_CTRL_SRAM_ACE3_ATTR_M ((APB_CTRL_SRAM_ACE3_ATTR_V)<<(APB_CTRL_SRAM_ACE3_ATTR_S))
|
||||
#define APB_CTRL_SRAM_ACE3_ATTR_V 0x1FF
|
||||
#define APB_CTRL_SRAM_ACE3_ATTR_S 0
|
||||
|
||||
#define APB_CTRL_SRAM_ACE0_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x68)
|
||||
/* APB_CTRL_SRAM_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_SRAM_ACE0_ADDR_S 0xFFFFFFFF
|
||||
#define APB_CTRL_SRAM_ACE0_ADDR_S_M ((APB_CTRL_SRAM_ACE0_ADDR_S_V)<<(APB_CTRL_SRAM_ACE0_ADDR_S_S))
|
||||
#define APB_CTRL_SRAM_ACE0_ADDR_S_V 0xFFFFFFFF
|
||||
#define APB_CTRL_SRAM_ACE0_ADDR_S_S 0
|
||||
|
||||
#define APB_CTRL_SRAM_ACE1_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x6C)
|
||||
/* APB_CTRL_SRAM_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_SRAM_ACE1_ADDR_S 0xFFFFFFFF
|
||||
#define APB_CTRL_SRAM_ACE1_ADDR_S_M ((APB_CTRL_SRAM_ACE1_ADDR_S_V)<<(APB_CTRL_SRAM_ACE1_ADDR_S_S))
|
||||
#define APB_CTRL_SRAM_ACE1_ADDR_S_V 0xFFFFFFFF
|
||||
#define APB_CTRL_SRAM_ACE1_ADDR_S_S 0
|
||||
|
||||
#define APB_CTRL_SRAM_ACE2_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x70)
|
||||
/* APB_CTRL_SRAM_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_SRAM_ACE2_ADDR_S 0xFFFFFFFF
|
||||
#define APB_CTRL_SRAM_ACE2_ADDR_S_M ((APB_CTRL_SRAM_ACE2_ADDR_S_V)<<(APB_CTRL_SRAM_ACE2_ADDR_S_S))
|
||||
#define APB_CTRL_SRAM_ACE2_ADDR_S_V 0xFFFFFFFF
|
||||
#define APB_CTRL_SRAM_ACE2_ADDR_S_S 0
|
||||
|
||||
#define APB_CTRL_SRAM_ACE3_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x74)
|
||||
/* APB_CTRL_SRAM_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_SRAM_ACE3_ADDR_S 0xFFFFFFFF
|
||||
#define APB_CTRL_SRAM_ACE3_ADDR_S_M ((APB_CTRL_SRAM_ACE3_ADDR_S_V)<<(APB_CTRL_SRAM_ACE3_ADDR_S_S))
|
||||
#define APB_CTRL_SRAM_ACE3_ADDR_S_V 0xFFFFFFFF
|
||||
#define APB_CTRL_SRAM_ACE3_ADDR_S_S 0
|
||||
|
||||
#define APB_CTRL_SRAM_ACE0_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x78)
|
||||
/* APB_CTRL_SRAM_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_SRAM_ACE0_SIZE 0x0000FFFF
|
||||
#define APB_CTRL_SRAM_ACE0_SIZE_M ((APB_CTRL_SRAM_ACE0_SIZE_V)<<(APB_CTRL_SRAM_ACE0_SIZE_S))
|
||||
#define APB_CTRL_SRAM_ACE0_SIZE_V 0xFFFF
|
||||
#define APB_CTRL_SRAM_ACE0_SIZE_S 0
|
||||
|
||||
#define APB_CTRL_SRAM_ACE1_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x7C)
|
||||
/* APB_CTRL_SRAM_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_SRAM_ACE1_SIZE 0x0000FFFF
|
||||
#define APB_CTRL_SRAM_ACE1_SIZE_M ((APB_CTRL_SRAM_ACE1_SIZE_V)<<(APB_CTRL_SRAM_ACE1_SIZE_S))
|
||||
#define APB_CTRL_SRAM_ACE1_SIZE_V 0xFFFF
|
||||
#define APB_CTRL_SRAM_ACE1_SIZE_S 0
|
||||
|
||||
#define APB_CTRL_SRAM_ACE2_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x80)
|
||||
/* APB_CTRL_SRAM_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_SRAM_ACE2_SIZE 0x0000FFFF
|
||||
#define APB_CTRL_SRAM_ACE2_SIZE_M ((APB_CTRL_SRAM_ACE2_SIZE_V)<<(APB_CTRL_SRAM_ACE2_SIZE_S))
|
||||
#define APB_CTRL_SRAM_ACE2_SIZE_V 0xFFFF
|
||||
#define APB_CTRL_SRAM_ACE2_SIZE_S 0
|
||||
|
||||
#define APB_CTRL_SRAM_ACE3_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x84)
|
||||
/* APB_CTRL_SRAM_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_SRAM_ACE3_SIZE 0x0000FFFF
|
||||
#define APB_CTRL_SRAM_ACE3_SIZE_M ((APB_CTRL_SRAM_ACE3_SIZE_V)<<(APB_CTRL_SRAM_ACE3_SIZE_S))
|
||||
#define APB_CTRL_SRAM_ACE3_SIZE_V 0xFFFF
|
||||
#define APB_CTRL_SRAM_ACE3_SIZE_S 0
|
||||
|
||||
#define APB_CTRL_SPI_MEM_PMS_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x88)
|
||||
/* APB_CTRL_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_SPI_MEM_REJECT_CDE 0x0000001F
|
||||
#define APB_CTRL_SPI_MEM_REJECT_CDE_M ((APB_CTRL_SPI_MEM_REJECT_CDE_V)<<(APB_CTRL_SPI_MEM_REJECT_CDE_S))
|
||||
#define APB_CTRL_SPI_MEM_REJECT_CDE_V 0x1F
|
||||
#define APB_CTRL_SPI_MEM_REJECT_CDE_S 2
|
||||
/* APB_CTRL_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_SPI_MEM_REJECT_CLR (BIT(1))
|
||||
#define APB_CTRL_SPI_MEM_REJECT_CLR_M (BIT(1))
|
||||
#define APB_CTRL_SPI_MEM_REJECT_CLR_V 0x1
|
||||
#define APB_CTRL_SPI_MEM_REJECT_CLR_S 1
|
||||
/* APB_CTRL_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_SPI_MEM_REJECT_INT (BIT(0))
|
||||
#define APB_CTRL_SPI_MEM_REJECT_INT_M (BIT(0))
|
||||
#define APB_CTRL_SPI_MEM_REJECT_INT_V 0x1
|
||||
#define APB_CTRL_SPI_MEM_REJECT_INT_S 0
|
||||
|
||||
#define APB_CTRL_SPI_MEM_REJECT_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x8C)
|
||||
/* APB_CTRL_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_SPI_MEM_REJECT_ADDR 0xFFFFFFFF
|
||||
#define APB_CTRL_SPI_MEM_REJECT_ADDR_M ((APB_CTRL_SPI_MEM_REJECT_ADDR_V)<<(APB_CTRL_SPI_MEM_REJECT_ADDR_S))
|
||||
#define APB_CTRL_SPI_MEM_REJECT_ADDR_V 0xFFFFFFFF
|
||||
#define APB_CTRL_SPI_MEM_REJECT_ADDR_S 0
|
||||
|
||||
#define APB_CTRL_SDIO_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x90)
|
||||
/* APB_CTRL_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_SDIO_WIN_ACCESS_EN (BIT(0))
|
||||
#define APB_CTRL_SDIO_WIN_ACCESS_EN_M (BIT(0))
|
||||
#define APB_CTRL_SDIO_WIN_ACCESS_EN_V 0x1
|
||||
#define APB_CTRL_SDIO_WIN_ACCESS_EN_S 0
|
||||
|
||||
#define APB_CTRL_REDCY_SIG0_REG (DR_REG_APB_CTRL_BASE + 0x94)
|
||||
/* APB_CTRL_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_REDCY_ANDOR (BIT(31))
|
||||
#define APB_CTRL_REDCY_ANDOR_M (BIT(31))
|
||||
#define APB_CTRL_REDCY_ANDOR_V 0x1
|
||||
#define APB_CTRL_REDCY_ANDOR_S 31
|
||||
/* APB_CTRL_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_REDCY_SIG0 0x7FFFFFFF
|
||||
#define APB_CTRL_REDCY_SIG0_M ((APB_CTRL_REDCY_SIG0_V)<<(APB_CTRL_REDCY_SIG0_S))
|
||||
#define APB_CTRL_REDCY_SIG0_V 0x7FFFFFFF
|
||||
#define APB_CTRL_REDCY_SIG0_S 0
|
||||
|
||||
#define APB_CTRL_REDCY_SIG1_REG (DR_REG_APB_CTRL_BASE + 0x98)
|
||||
/* APB_CTRL_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_REDCY_NANDOR (BIT(31))
|
||||
#define APB_CTRL_REDCY_NANDOR_M (BIT(31))
|
||||
#define APB_CTRL_REDCY_NANDOR_V 0x1
|
||||
#define APB_CTRL_REDCY_NANDOR_S 31
|
||||
/* APB_CTRL_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_REDCY_SIG1 0x7FFFFFFF
|
||||
#define APB_CTRL_REDCY_SIG1_M ((APB_CTRL_REDCY_SIG1_V)<<(APB_CTRL_REDCY_SIG1_S))
|
||||
#define APB_CTRL_REDCY_SIG1_V 0x7FFFFFFF
|
||||
#define APB_CTRL_REDCY_SIG1_S 0
|
||||
|
||||
#define APB_CTRL_FRONT_END_MEM_PD_REG (DR_REG_APB_CTRL_BASE + 0x9C)
|
||||
/* APB_CTRL_FREQ_MEM_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_FREQ_MEM_FORCE_PD (BIT(7))
|
||||
#define APB_CTRL_FREQ_MEM_FORCE_PD_M (BIT(7))
|
||||
#define APB_CTRL_FREQ_MEM_FORCE_PD_V 0x1
|
||||
#define APB_CTRL_FREQ_MEM_FORCE_PD_S 7
|
||||
/* APB_CTRL_FREQ_MEM_FORCE_PU : R/W ;bitpos:[6] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_FREQ_MEM_FORCE_PU (BIT(6))
|
||||
#define APB_CTRL_FREQ_MEM_FORCE_PU_M (BIT(6))
|
||||
#define APB_CTRL_FREQ_MEM_FORCE_PU_V 0x1
|
||||
#define APB_CTRL_FREQ_MEM_FORCE_PU_S 6
|
||||
/* APB_CTRL_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_DC_MEM_FORCE_PD (BIT(5))
|
||||
#define APB_CTRL_DC_MEM_FORCE_PD_M (BIT(5))
|
||||
#define APB_CTRL_DC_MEM_FORCE_PD_V 0x1
|
||||
#define APB_CTRL_DC_MEM_FORCE_PD_S 5
|
||||
/* APB_CTRL_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_DC_MEM_FORCE_PU (BIT(4))
|
||||
#define APB_CTRL_DC_MEM_FORCE_PU_M (BIT(4))
|
||||
#define APB_CTRL_DC_MEM_FORCE_PU_V 0x1
|
||||
#define APB_CTRL_DC_MEM_FORCE_PU_S 4
|
||||
/* APB_CTRL_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_PBUS_MEM_FORCE_PD (BIT(3))
|
||||
#define APB_CTRL_PBUS_MEM_FORCE_PD_M (BIT(3))
|
||||
#define APB_CTRL_PBUS_MEM_FORCE_PD_V 0x1
|
||||
#define APB_CTRL_PBUS_MEM_FORCE_PD_S 3
|
||||
/* APB_CTRL_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_PBUS_MEM_FORCE_PU (BIT(2))
|
||||
#define APB_CTRL_PBUS_MEM_FORCE_PU_M (BIT(2))
|
||||
#define APB_CTRL_PBUS_MEM_FORCE_PU_V 0x1
|
||||
#define APB_CTRL_PBUS_MEM_FORCE_PU_S 2
|
||||
/* APB_CTRL_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_AGC_MEM_FORCE_PD (BIT(1))
|
||||
#define APB_CTRL_AGC_MEM_FORCE_PD_M (BIT(1))
|
||||
#define APB_CTRL_AGC_MEM_FORCE_PD_V 0x1
|
||||
#define APB_CTRL_AGC_MEM_FORCE_PD_S 1
|
||||
/* APB_CTRL_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_AGC_MEM_FORCE_PU (BIT(0))
|
||||
#define APB_CTRL_AGC_MEM_FORCE_PU_M (BIT(0))
|
||||
#define APB_CTRL_AGC_MEM_FORCE_PU_V 0x1
|
||||
#define APB_CTRL_AGC_MEM_FORCE_PU_S 0
|
||||
|
||||
#define APB_CTRL_SPI_MEM_ECC_CTRL_REG (DR_REG_APB_CTRL_BASE + 0xA0)
|
||||
/* APB_CTRL_SRAM_PAGE_SIZE : R/W ;bitpos:[21:20] ;default: 2'd2 ; */
|
||||
/*description: Set the page size of the used MSPI external RAM. 0: 256 bytes. 1: 512 bytes. 2:
|
||||
1024 bytes. 3: 2048 bytes..*/
|
||||
#define APB_CTRL_SRAM_PAGE_SIZE 0x00000003
|
||||
#define APB_CTRL_SRAM_PAGE_SIZE_M ((APB_CTRL_SRAM_PAGE_SIZE_V)<<(APB_CTRL_SRAM_PAGE_SIZE_S))
|
||||
#define APB_CTRL_SRAM_PAGE_SIZE_V 0x3
|
||||
#define APB_CTRL_SRAM_PAGE_SIZE_S 20
|
||||
/* APB_CTRL_FLASH_PAGE_SIZE : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
|
||||
/*description: Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512 bytes. 2: 1024 by
|
||||
tes. 3: 2048 bytes..*/
|
||||
#define APB_CTRL_FLASH_PAGE_SIZE 0x00000003
|
||||
#define APB_CTRL_FLASH_PAGE_SIZE_M ((APB_CTRL_FLASH_PAGE_SIZE_V)<<(APB_CTRL_FLASH_PAGE_SIZE_S))
|
||||
#define APB_CTRL_FLASH_PAGE_SIZE_V 0x3
|
||||
#define APB_CTRL_FLASH_PAGE_SIZE_S 18
|
||||
|
||||
#define APB_CTRL_CLKGATE_FORCE_ON_REG (DR_REG_APB_CTRL_BASE + 0xA8)
|
||||
/* APB_CTRL_SRAM_CLKGATE_FORCE_ON : R/W ;bitpos:[13:3] ;default: ~11'b0 ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_SRAM_CLKGATE_FORCE_ON 0x000007FF
|
||||
#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_M ((APB_CTRL_SRAM_CLKGATE_FORCE_ON_V)<<(APB_CTRL_SRAM_CLKGATE_FORCE_ON_S))
|
||||
#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_V 0x7FF
|
||||
#define APB_CTRL_SRAM_CLKGATE_FORCE_ON_S 3
|
||||
/* APB_CTRL_ROM_CLKGATE_FORCE_ON : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_ROM_CLKGATE_FORCE_ON 0x00000007
|
||||
#define APB_CTRL_ROM_CLKGATE_FORCE_ON_M ((APB_CTRL_ROM_CLKGATE_FORCE_ON_V)<<(APB_CTRL_ROM_CLKGATE_FORCE_ON_S))
|
||||
#define APB_CTRL_ROM_CLKGATE_FORCE_ON_V 0x7
|
||||
#define APB_CTRL_ROM_CLKGATE_FORCE_ON_S 0
|
||||
|
||||
#define APB_CTRL_MEM_POWER_DOWN_REG (DR_REG_APB_CTRL_BASE + 0xAC)
|
||||
/* APB_CTRL_SRAM_POWER_DOWN : R/W ;bitpos:[13:3] ;default: 11'b0 ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_SRAM_POWER_DOWN 0x000007FF
|
||||
#define APB_CTRL_SRAM_POWER_DOWN_M ((APB_CTRL_SRAM_POWER_DOWN_V)<<(APB_CTRL_SRAM_POWER_DOWN_S))
|
||||
#define APB_CTRL_SRAM_POWER_DOWN_V 0x7FF
|
||||
#define APB_CTRL_SRAM_POWER_DOWN_S 3
|
||||
/* APB_CTRL_ROM_POWER_DOWN : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_ROM_POWER_DOWN 0x00000007
|
||||
#define APB_CTRL_ROM_POWER_DOWN_M ((APB_CTRL_ROM_POWER_DOWN_V)<<(APB_CTRL_ROM_POWER_DOWN_S))
|
||||
#define APB_CTRL_ROM_POWER_DOWN_V 0x7
|
||||
#define APB_CTRL_ROM_POWER_DOWN_S 0
|
||||
|
||||
#define APB_CTRL_MEM_POWER_UP_REG (DR_REG_APB_CTRL_BASE + 0xB0)
|
||||
/* APB_CTRL_SRAM_POWER_UP : R/W ;bitpos:[13:3] ;default: ~11'b0 ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_SRAM_POWER_UP 0x000007FF
|
||||
#define APB_CTRL_SRAM_POWER_UP_M ((APB_CTRL_SRAM_POWER_UP_V)<<(APB_CTRL_SRAM_POWER_UP_S))
|
||||
#define APB_CTRL_SRAM_POWER_UP_V 0x7FF
|
||||
#define APB_CTRL_SRAM_POWER_UP_S 3
|
||||
/* APB_CTRL_ROM_POWER_UP : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_ROM_POWER_UP 0x00000007
|
||||
#define APB_CTRL_ROM_POWER_UP_M ((APB_CTRL_ROM_POWER_UP_V)<<(APB_CTRL_ROM_POWER_UP_S))
|
||||
#define APB_CTRL_ROM_POWER_UP_V 0x7
|
||||
#define APB_CTRL_ROM_POWER_UP_S 0
|
||||
|
||||
#define APB_CTRL_RETENTION_CTRL_REG (DR_REG_APB_CTRL_BASE + 0xB4)
|
||||
/* APB_CTRL_NOBYPASS_CPU_ISO_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_NOBYPASS_CPU_ISO_RST (BIT(27))
|
||||
#define APB_CTRL_NOBYPASS_CPU_ISO_RST_M (BIT(27))
|
||||
#define APB_CTRL_NOBYPASS_CPU_ISO_RST_V 0x1
|
||||
#define APB_CTRL_NOBYPASS_CPU_ISO_RST_S 27
|
||||
/* APB_CTRL_RETENTION_CPU_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_RETENTION_CPU_LINK_ADDR 0x07FFFFFF
|
||||
#define APB_CTRL_RETENTION_CPU_LINK_ADDR_M ((APB_CTRL_RETENTION_CPU_LINK_ADDR_V)<<(APB_CTRL_RETENTION_CPU_LINK_ADDR_S))
|
||||
#define APB_CTRL_RETENTION_CPU_LINK_ADDR_V 0x7FFFFFF
|
||||
#define APB_CTRL_RETENTION_CPU_LINK_ADDR_S 0
|
||||
|
||||
#define APB_CTRL_RETENTION_CTRL1_REG (DR_REG_APB_CTRL_BASE + 0xB8)
|
||||
/* APB_CTRL_RETENTION_TAG_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_RETENTION_TAG_LINK_ADDR 0x07FFFFFF
|
||||
#define APB_CTRL_RETENTION_TAG_LINK_ADDR_M ((APB_CTRL_RETENTION_TAG_LINK_ADDR_V)<<(APB_CTRL_RETENTION_TAG_LINK_ADDR_S))
|
||||
#define APB_CTRL_RETENTION_TAG_LINK_ADDR_V 0x7FFFFFF
|
||||
#define APB_CTRL_RETENTION_TAG_LINK_ADDR_S 0
|
||||
|
||||
#define APB_CTRL_RETENTION_CTRL2_REG (DR_REG_APB_CTRL_BASE + 0xBC)
|
||||
/* APB_CTRL_RET_ICACHE_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_RET_ICACHE_ENABLE (BIT(31))
|
||||
#define APB_CTRL_RET_ICACHE_ENABLE_M (BIT(31))
|
||||
#define APB_CTRL_RET_ICACHE_ENABLE_V 0x1
|
||||
#define APB_CTRL_RET_ICACHE_ENABLE_S 31
|
||||
/* APB_CTRL_RET_ICACHE_START_POINT : R/W ;bitpos:[29:22] ;default: 8'd0 ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_RET_ICACHE_START_POINT 0x000000FF
|
||||
#define APB_CTRL_RET_ICACHE_START_POINT_M ((APB_CTRL_RET_ICACHE_START_POINT_V)<<(APB_CTRL_RET_ICACHE_START_POINT_S))
|
||||
#define APB_CTRL_RET_ICACHE_START_POINT_V 0xFF
|
||||
#define APB_CTRL_RET_ICACHE_START_POINT_S 22
|
||||
/* APB_CTRL_RET_ICACHE_VLD_SIZE : R/W ;bitpos:[20:13] ;default: 8'hff ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_RET_ICACHE_VLD_SIZE 0x000000FF
|
||||
#define APB_CTRL_RET_ICACHE_VLD_SIZE_M ((APB_CTRL_RET_ICACHE_VLD_SIZE_V)<<(APB_CTRL_RET_ICACHE_VLD_SIZE_S))
|
||||
#define APB_CTRL_RET_ICACHE_VLD_SIZE_V 0xFF
|
||||
#define APB_CTRL_RET_ICACHE_VLD_SIZE_S 13
|
||||
/* APB_CTRL_RET_ICACHE_SIZE : R/W ;bitpos:[11:4] ;default: 8'hff ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_RET_ICACHE_SIZE 0x000000FF
|
||||
#define APB_CTRL_RET_ICACHE_SIZE_M ((APB_CTRL_RET_ICACHE_SIZE_V)<<(APB_CTRL_RET_ICACHE_SIZE_S))
|
||||
#define APB_CTRL_RET_ICACHE_SIZE_V 0xFF
|
||||
#define APB_CTRL_RET_ICACHE_SIZE_S 4
|
||||
|
||||
#define APB_CTRL_RETENTION_CTRL3_REG (DR_REG_APB_CTRL_BASE + 0xC0)
|
||||
/* APB_CTRL_RET_DCACHE_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_RET_DCACHE_ENABLE (BIT(31))
|
||||
#define APB_CTRL_RET_DCACHE_ENABLE_M (BIT(31))
|
||||
#define APB_CTRL_RET_DCACHE_ENABLE_V 0x1
|
||||
#define APB_CTRL_RET_DCACHE_ENABLE_S 31
|
||||
/* APB_CTRL_RET_DCACHE_START_POINT : R/W ;bitpos:[30:22] ;default: 9'd0 ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_RET_DCACHE_START_POINT 0x000001FF
|
||||
#define APB_CTRL_RET_DCACHE_START_POINT_M ((APB_CTRL_RET_DCACHE_START_POINT_V)<<(APB_CTRL_RET_DCACHE_START_POINT_S))
|
||||
#define APB_CTRL_RET_DCACHE_START_POINT_V 0x1FF
|
||||
#define APB_CTRL_RET_DCACHE_START_POINT_S 22
|
||||
/* APB_CTRL_RET_DCACHE_VLD_SIZE : R/W ;bitpos:[21:13] ;default: 9'h1ff ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_RET_DCACHE_VLD_SIZE 0x000001FF
|
||||
#define APB_CTRL_RET_DCACHE_VLD_SIZE_M ((APB_CTRL_RET_DCACHE_VLD_SIZE_V)<<(APB_CTRL_RET_DCACHE_VLD_SIZE_S))
|
||||
#define APB_CTRL_RET_DCACHE_VLD_SIZE_V 0x1FF
|
||||
#define APB_CTRL_RET_DCACHE_VLD_SIZE_S 13
|
||||
/* APB_CTRL_RET_DCACHE_SIZE : R/W ;bitpos:[12:4] ;default: 9'h1ff ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_RET_DCACHE_SIZE 0x000001FF
|
||||
#define APB_CTRL_RET_DCACHE_SIZE_M ((APB_CTRL_RET_DCACHE_SIZE_V)<<(APB_CTRL_RET_DCACHE_SIZE_S))
|
||||
#define APB_CTRL_RET_DCACHE_SIZE_V 0x1FF
|
||||
#define APB_CTRL_RET_DCACHE_SIZE_S 4
|
||||
|
||||
#define APB_CTRL_RETENTION_CTRL4_REG (DR_REG_APB_CTRL_BASE + 0xC4)
|
||||
/* APB_CTRL_RETENTION_INV_CFG : R/W ;bitpos:[31:0] ;default: ~32'h0 ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_RETENTION_INV_CFG 0xFFFFFFFF
|
||||
#define APB_CTRL_RETENTION_INV_CFG_M ((APB_CTRL_RETENTION_INV_CFG_V)<<(APB_CTRL_RETENTION_INV_CFG_S))
|
||||
#define APB_CTRL_RETENTION_INV_CFG_V 0xFFFFFFFF
|
||||
#define APB_CTRL_RETENTION_INV_CFG_S 0
|
||||
|
||||
#define APB_CTRL_RETENTION_CTRL5_REG (DR_REG_APB_CTRL_BASE + 0xC8)
|
||||
/* APB_CTRL_RETENTION_DISABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define APB_CTRL_RETENTION_DISABLE (BIT(0))
|
||||
#define APB_CTRL_RETENTION_DISABLE_M (BIT(0))
|
||||
#define APB_CTRL_RETENTION_DISABLE_V 0x1
|
||||
#define APB_CTRL_RETENTION_DISABLE_S 0
|
||||
|
||||
#define APB_CTRL_DATE_REG (DR_REG_APB_CTRL_BASE + 0x3FC)
|
||||
/* APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h2101150 ; */
|
||||
/*description: Version control.*/
|
||||
#define APB_CTRL_DATE 0xFFFFFFFF
|
||||
#define APB_CTRL_DATE_M ((APB_CTRL_DATE_V)<<(APB_CTRL_DATE_S))
|
||||
#define APB_CTRL_DATE_V 0xFFFFFFFF
|
||||
#define APB_CTRL_DATE_S 0
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /*_SOC_APB_CTRL_REG_H_ */
|
||||
@@ -1,536 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#ifndef _SOC_APB_CTRL_STRUCT_H_
|
||||
#define _SOC_APB_CTRL_STRUCT_H_
|
||||
|
||||
#warning "apb_ctrl_struct is deprecated due to duplicated with syscon_struct, please use syscon_struct instead, they are same"
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct apb_ctrl_dev_s {
|
||||
union {
|
||||
struct {
|
||||
uint32_t pre_div : 10;
|
||||
uint32_t clk_320m_en : 1;
|
||||
uint32_t clk_en : 1;
|
||||
uint32_t rst_tick : 1;
|
||||
uint32_t reserved13 : 19;
|
||||
};
|
||||
uint32_t val;
|
||||
} clk_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t xtal_tick : 8;
|
||||
uint32_t ck8m_tick : 8;
|
||||
uint32_t tick_enable : 1;
|
||||
uint32_t reserved17 : 15;
|
||||
};
|
||||
uint32_t val;
|
||||
} tick_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk20_oen : 1;
|
||||
uint32_t clk22_oen : 1;
|
||||
uint32_t clk44_oen : 1;
|
||||
uint32_t clk_bb_oen : 1;
|
||||
uint32_t clk80_oen : 1;
|
||||
uint32_t clk160_oen : 1;
|
||||
uint32_t clk_320m_oen : 1;
|
||||
uint32_t clk_adc_inf_oen : 1;
|
||||
uint32_t clk_dac_cpu_oen : 1;
|
||||
uint32_t clk40x_bb_oen : 1;
|
||||
uint32_t clk_xtal_oen : 1;
|
||||
uint32_t reserved11 : 21;
|
||||
};
|
||||
uint32_t val;
|
||||
} clk_out_en;
|
||||
uint32_t wifi_bb_cfg;
|
||||
uint32_t wifi_bb_cfg_2;
|
||||
uint32_t wifi_clk_en;
|
||||
uint32_t wifi_rst_en;
|
||||
union {
|
||||
struct {
|
||||
uint32_t peri_io_swap : 8;
|
||||
uint32_t reserved8 : 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} host_inf_sel;
|
||||
union {
|
||||
struct {
|
||||
uint32_t ext_mem_pms_lock : 1;
|
||||
uint32_t reserved1 : 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} ext_mem_pms_lock;
|
||||
union {
|
||||
struct {
|
||||
uint32_t writeback_bypass : 1; /*Set 1 to bypass cache writeback request to external memory so that spi will not check its attribute.*/
|
||||
uint32_t reserved1 : 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} ext_mem_writeback_bypass;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace0_attr : 9;
|
||||
uint32_t reserved9 : 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace0_attr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace1_attr : 9;
|
||||
uint32_t reserved9 : 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace1_attr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace2_attr : 9;
|
||||
uint32_t reserved9 : 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace2_attr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace3_attr : 9;
|
||||
uint32_t reserved9 : 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace3_attr;
|
||||
uint32_t flash_ace0_addr;
|
||||
uint32_t flash_ace1_addr;
|
||||
uint32_t flash_ace2_addr;
|
||||
uint32_t flash_ace3_addr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace0_size : 16;
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace0_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace1_size : 16;
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace1_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace2_size : 16;
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace2_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace3_size : 16;
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace3_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sram_ace0_attr : 9;
|
||||
uint32_t reserved9 : 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} sram_ace0_attr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sram_ace1_attr : 9;
|
||||
uint32_t reserved9 : 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} sram_ace1_attr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sram_ace2_attr : 9;
|
||||
uint32_t reserved9 : 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} sram_ace2_attr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sram_ace3_attr : 9;
|
||||
uint32_t reserved9 : 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} sram_ace3_attr;
|
||||
uint32_t sram_ace0_addr;
|
||||
uint32_t sram_ace1_addr;
|
||||
uint32_t sram_ace2_addr;
|
||||
uint32_t sram_ace3_addr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sram_ace0_size : 16;
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} sram_ace0_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sram_ace1_size : 16;
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} sram_ace1_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sram_ace2_size : 16;
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} sram_ace2_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sram_ace3_size : 16;
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} sram_ace3_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t spi_mem_reject_int : 1;
|
||||
uint32_t spi_mem_reject_clr : 1;
|
||||
uint32_t spi_mem_reject_cde : 5;
|
||||
uint32_t reserved7 : 25;
|
||||
};
|
||||
uint32_t val;
|
||||
} spi_mem_pms_ctrl;
|
||||
uint32_t spi_mem_reject_addr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sdio_win_access_en : 1;
|
||||
uint32_t reserved1 : 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} sdio_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t redcy_sig0 : 31;
|
||||
uint32_t redcy_andor : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} redcy_sig0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t redcy_sig1 : 31;
|
||||
uint32_t redcy_nandor : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} redcy_sig1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t agc_mem_force_pu : 1;
|
||||
uint32_t agc_mem_force_pd : 1;
|
||||
uint32_t pbus_mem_force_pu : 1;
|
||||
uint32_t pbus_mem_force_pd : 1;
|
||||
uint32_t dc_mem_force_pu : 1;
|
||||
uint32_t dc_mem_force_pd : 1;
|
||||
uint32_t freq_mem_force_pu : 1;
|
||||
uint32_t freq_mem_force_pd : 1;
|
||||
uint32_t reserved8 : 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} front_end_mem_pd;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 18; /*reserved*/
|
||||
uint32_t flash_page_size : 2; /*Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
|
||||
uint32_t sram_page_size : 2; /*Set the page size of the used MSPI external RAM. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
|
||||
uint32_t reserved22 : 10; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} spi_mem_ecc_ctrl;
|
||||
uint32_t reserved_a4;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rom_clkgate_force_on : 3;
|
||||
uint32_t sram_clkgate_force_on : 11;
|
||||
uint32_t reserved14 : 18;
|
||||
};
|
||||
uint32_t val;
|
||||
} clkgate_force_on;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rom_power_down : 3;
|
||||
uint32_t sram_power_down : 11;
|
||||
uint32_t reserved14 : 18;
|
||||
};
|
||||
uint32_t val;
|
||||
} mem_power_down;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rom_power_up : 3;
|
||||
uint32_t sram_power_up : 11;
|
||||
uint32_t reserved14 : 18;
|
||||
};
|
||||
uint32_t val;
|
||||
} mem_power_up;
|
||||
union {
|
||||
struct {
|
||||
uint32_t retention_cpu_link_addr : 27;
|
||||
uint32_t nobypass_cpu_iso_rst : 1;
|
||||
uint32_t reserved28 : 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} retention_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t retention_tag_link_addr : 27;
|
||||
uint32_t reserved27 : 5;
|
||||
};
|
||||
uint32_t val;
|
||||
} retention_ctrl1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 4;
|
||||
uint32_t ret_icache_size : 8;
|
||||
uint32_t reserved12 : 1;
|
||||
uint32_t ret_icache_vld_size : 8;
|
||||
uint32_t reserved21 : 1;
|
||||
uint32_t ret_icache_start_point : 8;
|
||||
uint32_t reserved30 : 1;
|
||||
uint32_t ret_icache_enable : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} retention_ctrl2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 4;
|
||||
uint32_t ret_dcache_size : 9;
|
||||
uint32_t ret_dcache_vld_size : 9;
|
||||
uint32_t ret_dcache_start_point : 9;
|
||||
uint32_t ret_dcache_enable : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} retention_ctrl3;
|
||||
uint32_t retention_ctrl4;
|
||||
union {
|
||||
struct {
|
||||
uint32_t retention_disable : 1;
|
||||
uint32_t reserved1 : 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} retention_ctrl5;
|
||||
uint32_t reserved_cc;
|
||||
uint32_t reserved_d0;
|
||||
uint32_t reserved_d4;
|
||||
uint32_t reserved_d8;
|
||||
uint32_t reserved_dc;
|
||||
uint32_t reserved_e0;
|
||||
uint32_t reserved_e4;
|
||||
uint32_t reserved_e8;
|
||||
uint32_t reserved_ec;
|
||||
uint32_t reserved_f0;
|
||||
uint32_t reserved_f4;
|
||||
uint32_t reserved_f8;
|
||||
uint32_t reserved_fc;
|
||||
uint32_t reserved_100;
|
||||
uint32_t reserved_104;
|
||||
uint32_t reserved_108;
|
||||
uint32_t reserved_10c;
|
||||
uint32_t reserved_110;
|
||||
uint32_t reserved_114;
|
||||
uint32_t reserved_118;
|
||||
uint32_t reserved_11c;
|
||||
uint32_t reserved_120;
|
||||
uint32_t reserved_124;
|
||||
uint32_t reserved_128;
|
||||
uint32_t reserved_12c;
|
||||
uint32_t reserved_130;
|
||||
uint32_t reserved_134;
|
||||
uint32_t reserved_138;
|
||||
uint32_t reserved_13c;
|
||||
uint32_t reserved_140;
|
||||
uint32_t reserved_144;
|
||||
uint32_t reserved_148;
|
||||
uint32_t reserved_14c;
|
||||
uint32_t reserved_150;
|
||||
uint32_t reserved_154;
|
||||
uint32_t reserved_158;
|
||||
uint32_t reserved_15c;
|
||||
uint32_t reserved_160;
|
||||
uint32_t reserved_164;
|
||||
uint32_t reserved_168;
|
||||
uint32_t reserved_16c;
|
||||
uint32_t reserved_170;
|
||||
uint32_t reserved_174;
|
||||
uint32_t reserved_178;
|
||||
uint32_t reserved_17c;
|
||||
uint32_t reserved_180;
|
||||
uint32_t reserved_184;
|
||||
uint32_t reserved_188;
|
||||
uint32_t reserved_18c;
|
||||
uint32_t reserved_190;
|
||||
uint32_t reserved_194;
|
||||
uint32_t reserved_198;
|
||||
uint32_t reserved_19c;
|
||||
uint32_t reserved_1a0;
|
||||
uint32_t reserved_1a4;
|
||||
uint32_t reserved_1a8;
|
||||
uint32_t reserved_1ac;
|
||||
uint32_t reserved_1b0;
|
||||
uint32_t reserved_1b4;
|
||||
uint32_t reserved_1b8;
|
||||
uint32_t reserved_1bc;
|
||||
uint32_t reserved_1c0;
|
||||
uint32_t reserved_1c4;
|
||||
uint32_t reserved_1c8;
|
||||
uint32_t reserved_1cc;
|
||||
uint32_t reserved_1d0;
|
||||
uint32_t reserved_1d4;
|
||||
uint32_t reserved_1d8;
|
||||
uint32_t reserved_1dc;
|
||||
uint32_t reserved_1e0;
|
||||
uint32_t reserved_1e4;
|
||||
uint32_t reserved_1e8;
|
||||
uint32_t reserved_1ec;
|
||||
uint32_t reserved_1f0;
|
||||
uint32_t reserved_1f4;
|
||||
uint32_t reserved_1f8;
|
||||
uint32_t reserved_1fc;
|
||||
uint32_t reserved_200;
|
||||
uint32_t reserved_204;
|
||||
uint32_t reserved_208;
|
||||
uint32_t reserved_20c;
|
||||
uint32_t reserved_210;
|
||||
uint32_t reserved_214;
|
||||
uint32_t reserved_218;
|
||||
uint32_t reserved_21c;
|
||||
uint32_t reserved_220;
|
||||
uint32_t reserved_224;
|
||||
uint32_t reserved_228;
|
||||
uint32_t reserved_22c;
|
||||
uint32_t reserved_230;
|
||||
uint32_t reserved_234;
|
||||
uint32_t reserved_238;
|
||||
uint32_t reserved_23c;
|
||||
uint32_t reserved_240;
|
||||
uint32_t reserved_244;
|
||||
uint32_t reserved_248;
|
||||
uint32_t reserved_24c;
|
||||
uint32_t reserved_250;
|
||||
uint32_t reserved_254;
|
||||
uint32_t reserved_258;
|
||||
uint32_t reserved_25c;
|
||||
uint32_t reserved_260;
|
||||
uint32_t reserved_264;
|
||||
uint32_t reserved_268;
|
||||
uint32_t reserved_26c;
|
||||
uint32_t reserved_270;
|
||||
uint32_t reserved_274;
|
||||
uint32_t reserved_278;
|
||||
uint32_t reserved_27c;
|
||||
uint32_t reserved_280;
|
||||
uint32_t reserved_284;
|
||||
uint32_t reserved_288;
|
||||
uint32_t reserved_28c;
|
||||
uint32_t reserved_290;
|
||||
uint32_t reserved_294;
|
||||
uint32_t reserved_298;
|
||||
uint32_t reserved_29c;
|
||||
uint32_t reserved_2a0;
|
||||
uint32_t reserved_2a4;
|
||||
uint32_t reserved_2a8;
|
||||
uint32_t reserved_2ac;
|
||||
uint32_t reserved_2b0;
|
||||
uint32_t reserved_2b4;
|
||||
uint32_t reserved_2b8;
|
||||
uint32_t reserved_2bc;
|
||||
uint32_t reserved_2c0;
|
||||
uint32_t reserved_2c4;
|
||||
uint32_t reserved_2c8;
|
||||
uint32_t reserved_2cc;
|
||||
uint32_t reserved_2d0;
|
||||
uint32_t reserved_2d4;
|
||||
uint32_t reserved_2d8;
|
||||
uint32_t reserved_2dc;
|
||||
uint32_t reserved_2e0;
|
||||
uint32_t reserved_2e4;
|
||||
uint32_t reserved_2e8;
|
||||
uint32_t reserved_2ec;
|
||||
uint32_t reserved_2f0;
|
||||
uint32_t reserved_2f4;
|
||||
uint32_t reserved_2f8;
|
||||
uint32_t reserved_2fc;
|
||||
uint32_t reserved_300;
|
||||
uint32_t reserved_304;
|
||||
uint32_t reserved_308;
|
||||
uint32_t reserved_30c;
|
||||
uint32_t reserved_310;
|
||||
uint32_t reserved_314;
|
||||
uint32_t reserved_318;
|
||||
uint32_t reserved_31c;
|
||||
uint32_t reserved_320;
|
||||
uint32_t reserved_324;
|
||||
uint32_t reserved_328;
|
||||
uint32_t reserved_32c;
|
||||
uint32_t reserved_330;
|
||||
uint32_t reserved_334;
|
||||
uint32_t reserved_338;
|
||||
uint32_t reserved_33c;
|
||||
uint32_t reserved_340;
|
||||
uint32_t reserved_344;
|
||||
uint32_t reserved_348;
|
||||
uint32_t reserved_34c;
|
||||
uint32_t reserved_350;
|
||||
uint32_t reserved_354;
|
||||
uint32_t reserved_358;
|
||||
uint32_t reserved_35c;
|
||||
uint32_t reserved_360;
|
||||
uint32_t reserved_364;
|
||||
uint32_t reserved_368;
|
||||
uint32_t reserved_36c;
|
||||
uint32_t reserved_370;
|
||||
uint32_t reserved_374;
|
||||
uint32_t reserved_378;
|
||||
uint32_t reserved_37c;
|
||||
uint32_t reserved_380;
|
||||
uint32_t reserved_384;
|
||||
uint32_t reserved_388;
|
||||
uint32_t reserved_38c;
|
||||
uint32_t reserved_390;
|
||||
uint32_t reserved_394;
|
||||
uint32_t reserved_398;
|
||||
uint32_t reserved_39c;
|
||||
uint32_t reserved_3a0;
|
||||
uint32_t reserved_3a4;
|
||||
uint32_t reserved_3a8;
|
||||
uint32_t reserved_3ac;
|
||||
uint32_t reserved_3b0;
|
||||
uint32_t reserved_3b4;
|
||||
uint32_t reserved_3b8;
|
||||
uint32_t reserved_3bc;
|
||||
uint32_t reserved_3c0;
|
||||
uint32_t reserved_3c4;
|
||||
uint32_t reserved_3c8;
|
||||
uint32_t reserved_3cc;
|
||||
uint32_t reserved_3d0;
|
||||
uint32_t reserved_3d4;
|
||||
uint32_t reserved_3d8;
|
||||
uint32_t reserved_3dc;
|
||||
uint32_t reserved_3e0;
|
||||
uint32_t reserved_3e4;
|
||||
uint32_t reserved_3e8;
|
||||
uint32_t reserved_3ec;
|
||||
uint32_t reserved_3f0;
|
||||
uint32_t reserved_3f4;
|
||||
uint32_t reserved_3f8;
|
||||
uint32_t date;
|
||||
} apb_ctrl_dev_t;
|
||||
extern apb_ctrl_dev_t APB_CTRL;
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /*_SOC_APB_CTRL_STRUCT_H_ */
|
||||
@@ -1,646 +0,0 @@
|
||||
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_APB_SARADC_REG_H_
|
||||
#define _SOC_APB_SARADC_REG_H_
|
||||
|
||||
|
||||
#include "soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x0)
|
||||
/* APB_SARADC_WAIT_ARB_CYCLE : R/W ;bitpos:[31:30] ;default: 2'd1 ; */
|
||||
/*description: wait arbit signal stable after sar_done.*/
|
||||
#define APB_SARADC_WAIT_ARB_CYCLE 0x00000003
|
||||
#define APB_SARADC_WAIT_ARB_CYCLE_M ((APB_SARADC_WAIT_ARB_CYCLE_V)<<(APB_SARADC_WAIT_ARB_CYCLE_S))
|
||||
#define APB_SARADC_WAIT_ARB_CYCLE_V 0x3
|
||||
#define APB_SARADC_WAIT_ARB_CYCLE_S 30
|
||||
/* APB_SARADC_XPD_SAR_FORCE : R/W ;bitpos:[28:27] ;default: 2'd0 ; */
|
||||
/*description: force option to xpd sar blocks.*/
|
||||
#define APB_SARADC_XPD_SAR_FORCE 0x00000003
|
||||
#define APB_SARADC_XPD_SAR_FORCE_M ((APB_SARADC_XPD_SAR_FORCE_V)<<(APB_SARADC_XPD_SAR_FORCE_S))
|
||||
#define APB_SARADC_XPD_SAR_FORCE_V 0x3
|
||||
#define APB_SARADC_XPD_SAR_FORCE_S 27
|
||||
/* APB_SARADC_DATA_TO_I2S : R/W ;bitpos:[26] ;default: 1'b0 ; */
|
||||
/*description: 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matr
|
||||
ix.*/
|
||||
#define APB_SARADC_DATA_TO_I2S (BIT(26))
|
||||
#define APB_SARADC_DATA_TO_I2S_M (BIT(26))
|
||||
#define APB_SARADC_DATA_TO_I2S_V 0x1
|
||||
#define APB_SARADC_DATA_TO_I2S_S 26
|
||||
/* APB_SARADC_DATA_SAR_SEL : R/W ;bitpos:[25] ;default: 1'b0 ; */
|
||||
/*description: 1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the
|
||||
resolution should not be larger than 11 bits..*/
|
||||
#define APB_SARADC_DATA_SAR_SEL (BIT(25))
|
||||
#define APB_SARADC_DATA_SAR_SEL_M (BIT(25))
|
||||
#define APB_SARADC_DATA_SAR_SEL_V 0x1
|
||||
#define APB_SARADC_DATA_SAR_SEL_S 25
|
||||
/* APB_SARADC_SAR2_PATT_P_CLEAR : R/W ;bitpos:[24] ;default: 1'd0 ; */
|
||||
/*description: clear the pointer of pattern table for DIG ADC2 CTRL.*/
|
||||
#define APB_SARADC_SAR2_PATT_P_CLEAR (BIT(24))
|
||||
#define APB_SARADC_SAR2_PATT_P_CLEAR_M (BIT(24))
|
||||
#define APB_SARADC_SAR2_PATT_P_CLEAR_V 0x1
|
||||
#define APB_SARADC_SAR2_PATT_P_CLEAR_S 24
|
||||
/* APB_SARADC_SAR1_PATT_P_CLEAR : R/W ;bitpos:[23] ;default: 1'd0 ; */
|
||||
/*description: clear the pointer of pattern table for DIG ADC1 CTRL.*/
|
||||
#define APB_SARADC_SAR1_PATT_P_CLEAR (BIT(23))
|
||||
#define APB_SARADC_SAR1_PATT_P_CLEAR_M (BIT(23))
|
||||
#define APB_SARADC_SAR1_PATT_P_CLEAR_V 0x1
|
||||
#define APB_SARADC_SAR1_PATT_P_CLEAR_S 23
|
||||
/* APB_SARADC_SAR2_PATT_LEN : R/W ;bitpos:[22:19] ;default: 4'd15 ; */
|
||||
/*description: 0 ~ 15 means length 1 ~ 16.*/
|
||||
#define APB_SARADC_SAR2_PATT_LEN 0x0000000F
|
||||
#define APB_SARADC_SAR2_PATT_LEN_M ((APB_SARADC_SAR2_PATT_LEN_V)<<(APB_SARADC_SAR2_PATT_LEN_S))
|
||||
#define APB_SARADC_SAR2_PATT_LEN_V 0xF
|
||||
#define APB_SARADC_SAR2_PATT_LEN_S 19
|
||||
/* APB_SARADC_SAR1_PATT_LEN : R/W ;bitpos:[18:15] ;default: 4'd15 ; */
|
||||
/*description: 0 ~ 15 means length 1 ~ 16.*/
|
||||
#define APB_SARADC_SAR1_PATT_LEN 0x0000000F
|
||||
#define APB_SARADC_SAR1_PATT_LEN_M ((APB_SARADC_SAR1_PATT_LEN_V)<<(APB_SARADC_SAR1_PATT_LEN_S))
|
||||
#define APB_SARADC_SAR1_PATT_LEN_V 0xF
|
||||
#define APB_SARADC_SAR1_PATT_LEN_S 15
|
||||
/* APB_SARADC_SAR_CLK_DIV : R/W ;bitpos:[14:7] ;default: 8'd4 ; */
|
||||
/*description: SAR clock divider.*/
|
||||
#define APB_SARADC_SAR_CLK_DIV 0x000000FF
|
||||
#define APB_SARADC_SAR_CLK_DIV_M ((APB_SARADC_SAR_CLK_DIV_V)<<(APB_SARADC_SAR_CLK_DIV_S))
|
||||
#define APB_SARADC_SAR_CLK_DIV_V 0xFF
|
||||
#define APB_SARADC_SAR_CLK_DIV_S 7
|
||||
/* APB_SARADC_SAR_CLK_GATED : R/W ;bitpos:[6] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_SAR_CLK_GATED (BIT(6))
|
||||
#define APB_SARADC_SAR_CLK_GATED_M (BIT(6))
|
||||
#define APB_SARADC_SAR_CLK_GATED_V 0x1
|
||||
#define APB_SARADC_SAR_CLK_GATED_S 6
|
||||
/* APB_SARADC_SAR_SEL : R/W ;bitpos:[5] ;default: 1'd0 ; */
|
||||
/*description: 0: SAR1, 1: SAR2, only work for single SAR mode.*/
|
||||
#define APB_SARADC_SAR_SEL (BIT(5))
|
||||
#define APB_SARADC_SAR_SEL_M (BIT(5))
|
||||
#define APB_SARADC_SAR_SEL_V 0x1
|
||||
#define APB_SARADC_SAR_SEL_S 5
|
||||
/* APB_SARADC_WORK_MODE : R/W ;bitpos:[4:3] ;default: 2'd0 ; */
|
||||
/*description: 0: single mode, 1: double mode, 2: alternate mode.*/
|
||||
#define APB_SARADC_WORK_MODE 0x00000003
|
||||
#define APB_SARADC_WORK_MODE_M ((APB_SARADC_WORK_MODE_V)<<(APB_SARADC_WORK_MODE_S))
|
||||
#define APB_SARADC_WORK_MODE_V 0x3
|
||||
#define APB_SARADC_WORK_MODE_S 3
|
||||
/* APB_SARADC_START : R/W ;bitpos:[1] ;default: 1'd0 ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_START (BIT(1))
|
||||
#define APB_SARADC_START_M (BIT(1))
|
||||
#define APB_SARADC_START_V 0x1
|
||||
#define APB_SARADC_START_S 1
|
||||
/* APB_SARADC_START_FORCE : R/W ;bitpos:[0] ;default: 1'd0 ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_START_FORCE (BIT(0))
|
||||
#define APB_SARADC_START_FORCE_M (BIT(0))
|
||||
#define APB_SARADC_START_FORCE_V 0x1
|
||||
#define APB_SARADC_START_FORCE_S 0
|
||||
|
||||
#define APB_SARADC_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x4)
|
||||
/* APB_SARADC_TIMER_EN : R/W ;bitpos:[24] ;default: 1'd0 ; */
|
||||
/*description: to enable saradc timer trigger.*/
|
||||
#define APB_SARADC_TIMER_EN (BIT(24))
|
||||
#define APB_SARADC_TIMER_EN_M (BIT(24))
|
||||
#define APB_SARADC_TIMER_EN_V 0x1
|
||||
#define APB_SARADC_TIMER_EN_S 24
|
||||
/* APB_SARADC_TIMER_TARGET : R/W ;bitpos:[23:12] ;default: 12'd10 ; */
|
||||
/*description: to set saradc timer target.*/
|
||||
#define APB_SARADC_TIMER_TARGET 0x00000FFF
|
||||
#define APB_SARADC_TIMER_TARGET_M ((APB_SARADC_TIMER_TARGET_V)<<(APB_SARADC_TIMER_TARGET_S))
|
||||
#define APB_SARADC_TIMER_TARGET_V 0xFFF
|
||||
#define APB_SARADC_TIMER_TARGET_S 12
|
||||
/* APB_SARADC_TIMER_SEL : R/W ;bitpos:[11] ;default: 1'd0 ; */
|
||||
/*description: 1: select saradc timer 0: i2s_ws trigger.*/
|
||||
#define APB_SARADC_TIMER_SEL (BIT(11))
|
||||
#define APB_SARADC_TIMER_SEL_M (BIT(11))
|
||||
#define APB_SARADC_TIMER_SEL_V 0x1
|
||||
#define APB_SARADC_TIMER_SEL_S 11
|
||||
/* APB_SARADC_SAR2_INV : R/W ;bitpos:[10] ;default: 1'd0 ; */
|
||||
/*description: 1: data to DIG ADC2 CTRL is inverted, otherwise not.*/
|
||||
#define APB_SARADC_SAR2_INV (BIT(10))
|
||||
#define APB_SARADC_SAR2_INV_M (BIT(10))
|
||||
#define APB_SARADC_SAR2_INV_V 0x1
|
||||
#define APB_SARADC_SAR2_INV_S 10
|
||||
/* APB_SARADC_SAR1_INV : R/W ;bitpos:[9] ;default: 1'd0 ; */
|
||||
/*description: 1: data to DIG ADC1 CTRL is inverted, otherwise not.*/
|
||||
#define APB_SARADC_SAR1_INV (BIT(9))
|
||||
#define APB_SARADC_SAR1_INV_M (BIT(9))
|
||||
#define APB_SARADC_SAR1_INV_V 0x1
|
||||
#define APB_SARADC_SAR1_INV_S 9
|
||||
/* APB_SARADC_MAX_MEAS_NUM : R/W ;bitpos:[8:1] ;default: 8'd255 ; */
|
||||
/*description: max conversion number.*/
|
||||
#define APB_SARADC_MAX_MEAS_NUM 0x000000FF
|
||||
#define APB_SARADC_MAX_MEAS_NUM_M ((APB_SARADC_MAX_MEAS_NUM_V)<<(APB_SARADC_MAX_MEAS_NUM_S))
|
||||
#define APB_SARADC_MAX_MEAS_NUM_V 0xFF
|
||||
#define APB_SARADC_MAX_MEAS_NUM_S 1
|
||||
/* APB_SARADC_MEAS_NUM_LIMIT : R/W ;bitpos:[0] ;default: 1'd0 ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_MEAS_NUM_LIMIT (BIT(0))
|
||||
#define APB_SARADC_MEAS_NUM_LIMIT_M (BIT(0))
|
||||
#define APB_SARADC_MEAS_NUM_LIMIT_V 0x1
|
||||
#define APB_SARADC_MEAS_NUM_LIMIT_S 0
|
||||
|
||||
#define APB_SARADC_FILTER_CTRL1_REG (DR_REG_APB_SARADC_BASE + 0x8)
|
||||
/* APB_SARADC_FILTER_FACTOR0 : R/W ;bitpos:[31:29] ;default: 3'd0 ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_FILTER_FACTOR0 0x00000007
|
||||
#define APB_SARADC_FILTER_FACTOR0_M ((APB_SARADC_FILTER_FACTOR0_V)<<(APB_SARADC_FILTER_FACTOR0_S))
|
||||
#define APB_SARADC_FILTER_FACTOR0_V 0x7
|
||||
#define APB_SARADC_FILTER_FACTOR0_S 29
|
||||
/* APB_SARADC_FILTER_FACTOR1 : R/W ;bitpos:[28:26] ;default: 3'd0 ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_FILTER_FACTOR1 0x00000007
|
||||
#define APB_SARADC_FILTER_FACTOR1_M ((APB_SARADC_FILTER_FACTOR1_V)<<(APB_SARADC_FILTER_FACTOR1_S))
|
||||
#define APB_SARADC_FILTER_FACTOR1_V 0x7
|
||||
#define APB_SARADC_FILTER_FACTOR1_S 26
|
||||
|
||||
#define APB_SARADC_FSM_WAIT_REG (DR_REG_APB_SARADC_BASE + 0xC)
|
||||
/* APB_SARADC_STANDBY_WAIT : R/W ;bitpos:[23:16] ;default: 8'd255 ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_STANDBY_WAIT 0x000000FF
|
||||
#define APB_SARADC_STANDBY_WAIT_M ((APB_SARADC_STANDBY_WAIT_V)<<(APB_SARADC_STANDBY_WAIT_S))
|
||||
#define APB_SARADC_STANDBY_WAIT_V 0xFF
|
||||
#define APB_SARADC_STANDBY_WAIT_S 16
|
||||
/* APB_SARADC_RSTB_WAIT : R/W ;bitpos:[15:8] ;default: 8'd8 ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_RSTB_WAIT 0x000000FF
|
||||
#define APB_SARADC_RSTB_WAIT_M ((APB_SARADC_RSTB_WAIT_V)<<(APB_SARADC_RSTB_WAIT_S))
|
||||
#define APB_SARADC_RSTB_WAIT_V 0xFF
|
||||
#define APB_SARADC_RSTB_WAIT_S 8
|
||||
/* APB_SARADC_XPD_WAIT : R/W ;bitpos:[7:0] ;default: 8'd8 ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_XPD_WAIT 0x000000FF
|
||||
#define APB_SARADC_XPD_WAIT_M ((APB_SARADC_XPD_WAIT_V)<<(APB_SARADC_XPD_WAIT_S))
|
||||
#define APB_SARADC_XPD_WAIT_V 0xFF
|
||||
#define APB_SARADC_XPD_WAIT_S 0
|
||||
|
||||
#define APB_SARADC_SAR1_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x10)
|
||||
/* APB_SARADC_SAR1_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_SAR1_STATUS 0xFFFFFFFF
|
||||
#define APB_SARADC_SAR1_STATUS_M ((APB_SARADC_SAR1_STATUS_V)<<(APB_SARADC_SAR1_STATUS_S))
|
||||
#define APB_SARADC_SAR1_STATUS_V 0xFFFFFFFF
|
||||
#define APB_SARADC_SAR1_STATUS_S 0
|
||||
|
||||
#define APB_SARADC_SAR2_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x14)
|
||||
/* APB_SARADC_SAR2_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_SAR2_STATUS 0xFFFFFFFF
|
||||
#define APB_SARADC_SAR2_STATUS_M ((APB_SARADC_SAR2_STATUS_V)<<(APB_SARADC_SAR2_STATUS_S))
|
||||
#define APB_SARADC_SAR2_STATUS_V 0xFFFFFFFF
|
||||
#define APB_SARADC_SAR2_STATUS_S 0
|
||||
|
||||
#define APB_SARADC_SAR1_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x18)
|
||||
/* APB_SARADC_SAR1_PATT_TAB1 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
|
||||
/*description: item 0 ~ 3 for pattern table 1 (each item one byte).*/
|
||||
#define APB_SARADC_SAR1_PATT_TAB1 0x00FFFFFF
|
||||
#define APB_SARADC_SAR1_PATT_TAB1_M ((APB_SARADC_SAR1_PATT_TAB1_V)<<(APB_SARADC_SAR1_PATT_TAB1_S))
|
||||
#define APB_SARADC_SAR1_PATT_TAB1_V 0xFFFFFF
|
||||
#define APB_SARADC_SAR1_PATT_TAB1_S 0
|
||||
|
||||
#define APB_SARADC_SAR1_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x1C)
|
||||
/* APB_SARADC_SAR1_PATT_TAB2 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
|
||||
/*description: Item 4 ~ 7 for pattern table 1 (each item one byte).*/
|
||||
#define APB_SARADC_SAR1_PATT_TAB2 0x00FFFFFF
|
||||
#define APB_SARADC_SAR1_PATT_TAB2_M ((APB_SARADC_SAR1_PATT_TAB2_V)<<(APB_SARADC_SAR1_PATT_TAB2_S))
|
||||
#define APB_SARADC_SAR1_PATT_TAB2_V 0xFFFFFF
|
||||
#define APB_SARADC_SAR1_PATT_TAB2_S 0
|
||||
|
||||
#define APB_SARADC_SAR1_PATT_TAB3_REG (DR_REG_APB_SARADC_BASE + 0x20)
|
||||
/* APB_SARADC_SAR1_PATT_TAB3 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
|
||||
/*description: Item 8 ~ 11 for pattern table 1 (each item one byte).*/
|
||||
#define APB_SARADC_SAR1_PATT_TAB3 0x00FFFFFF
|
||||
#define APB_SARADC_SAR1_PATT_TAB3_M ((APB_SARADC_SAR1_PATT_TAB3_V)<<(APB_SARADC_SAR1_PATT_TAB3_S))
|
||||
#define APB_SARADC_SAR1_PATT_TAB3_V 0xFFFFFF
|
||||
#define APB_SARADC_SAR1_PATT_TAB3_S 0
|
||||
|
||||
#define APB_SARADC_SAR1_PATT_TAB4_REG (DR_REG_APB_SARADC_BASE + 0x24)
|
||||
/* APB_SARADC_SAR1_PATT_TAB4 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
|
||||
/*description: Item 12 ~ 15 for pattern table 1 (each item one byte).*/
|
||||
#define APB_SARADC_SAR1_PATT_TAB4 0x00FFFFFF
|
||||
#define APB_SARADC_SAR1_PATT_TAB4_M ((APB_SARADC_SAR1_PATT_TAB4_V)<<(APB_SARADC_SAR1_PATT_TAB4_S))
|
||||
#define APB_SARADC_SAR1_PATT_TAB4_V 0xFFFFFF
|
||||
#define APB_SARADC_SAR1_PATT_TAB4_S 0
|
||||
|
||||
#define APB_SARADC_SAR2_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x28)
|
||||
/* APB_SARADC_SAR2_PATT_TAB1 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
|
||||
/*description: item 0 ~ 3 for pattern table 2 (each item one byte).*/
|
||||
#define APB_SARADC_SAR2_PATT_TAB1 0x00FFFFFF
|
||||
#define APB_SARADC_SAR2_PATT_TAB1_M ((APB_SARADC_SAR2_PATT_TAB1_V)<<(APB_SARADC_SAR2_PATT_TAB1_S))
|
||||
#define APB_SARADC_SAR2_PATT_TAB1_V 0xFFFFFF
|
||||
#define APB_SARADC_SAR2_PATT_TAB1_S 0
|
||||
|
||||
#define APB_SARADC_SAR2_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x2C)
|
||||
/* APB_SARADC_SAR2_PATT_TAB2 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
|
||||
/*description: Item 4 ~ 7 for pattern table 2 (each item one byte).*/
|
||||
#define APB_SARADC_SAR2_PATT_TAB2 0x00FFFFFF
|
||||
#define APB_SARADC_SAR2_PATT_TAB2_M ((APB_SARADC_SAR2_PATT_TAB2_V)<<(APB_SARADC_SAR2_PATT_TAB2_S))
|
||||
#define APB_SARADC_SAR2_PATT_TAB2_V 0xFFFFFF
|
||||
#define APB_SARADC_SAR2_PATT_TAB2_S 0
|
||||
|
||||
#define APB_SARADC_SAR2_PATT_TAB3_REG (DR_REG_APB_SARADC_BASE + 0x30)
|
||||
/* APB_SARADC_SAR2_PATT_TAB3 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
|
||||
/*description: Item 8 ~ 11 for pattern table 2 (each item one byte).*/
|
||||
#define APB_SARADC_SAR2_PATT_TAB3 0x00FFFFFF
|
||||
#define APB_SARADC_SAR2_PATT_TAB3_M ((APB_SARADC_SAR2_PATT_TAB3_V)<<(APB_SARADC_SAR2_PATT_TAB3_S))
|
||||
#define APB_SARADC_SAR2_PATT_TAB3_V 0xFFFFFF
|
||||
#define APB_SARADC_SAR2_PATT_TAB3_S 0
|
||||
|
||||
#define APB_SARADC_SAR2_PATT_TAB4_REG (DR_REG_APB_SARADC_BASE + 0x34)
|
||||
/* APB_SARADC_SAR2_PATT_TAB4 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
|
||||
/*description: Item 12 ~ 15 for pattern table 2 (each item one byte).*/
|
||||
#define APB_SARADC_SAR2_PATT_TAB4 0x00FFFFFF
|
||||
#define APB_SARADC_SAR2_PATT_TAB4_M ((APB_SARADC_SAR2_PATT_TAB4_V)<<(APB_SARADC_SAR2_PATT_TAB4_S))
|
||||
#define APB_SARADC_SAR2_PATT_TAB4_V 0xFFFFFF
|
||||
#define APB_SARADC_SAR2_PATT_TAB4_S 0
|
||||
|
||||
#define APB_SARADC_APB_ADC_ARB_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x38)
|
||||
/* APB_SARADC_ADC_ARB_FIX_PRIORITY : R/W ;bitpos:[12] ;default: 1'b0 ; */
|
||||
/*description: adc2 arbiter uses fixed priority.*/
|
||||
#define APB_SARADC_ADC_ARB_FIX_PRIORITY (BIT(12))
|
||||
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_M (BIT(12))
|
||||
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_V 0x1
|
||||
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_S 12
|
||||
/* APB_SARADC_ADC_ARB_WIFI_PRIORITY : R/W ;bitpos:[11:10] ;default: 2'd2 ; */
|
||||
/*description: Set adc2 arbiter wifi priority.*/
|
||||
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY 0x00000003
|
||||
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_M ((APB_SARADC_ADC_ARB_WIFI_PRIORITY_V)<<(APB_SARADC_ADC_ARB_WIFI_PRIORITY_S))
|
||||
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_V 0x3
|
||||
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_S 10
|
||||
/* APB_SARADC_ADC_ARB_RTC_PRIORITY : R/W ;bitpos:[9:8] ;default: 2'd1 ; */
|
||||
/*description: Set adc2 arbiter rtc priority.*/
|
||||
#define APB_SARADC_ADC_ARB_RTC_PRIORITY 0x00000003
|
||||
#define APB_SARADC_ADC_ARB_RTC_PRIORITY_M ((APB_SARADC_ADC_ARB_RTC_PRIORITY_V)<<(APB_SARADC_ADC_ARB_RTC_PRIORITY_S))
|
||||
#define APB_SARADC_ADC_ARB_RTC_PRIORITY_V 0x3
|
||||
#define APB_SARADC_ADC_ARB_RTC_PRIORITY_S 8
|
||||
/* APB_SARADC_ADC_ARB_APB_PRIORITY : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
|
||||
/*description: Set adc2 arbiterapb priority.*/
|
||||
#define APB_SARADC_ADC_ARB_APB_PRIORITY 0x00000003
|
||||
#define APB_SARADC_ADC_ARB_APB_PRIORITY_M ((APB_SARADC_ADC_ARB_APB_PRIORITY_V)<<(APB_SARADC_ADC_ARB_APB_PRIORITY_S))
|
||||
#define APB_SARADC_ADC_ARB_APB_PRIORITY_V 0x3
|
||||
#define APB_SARADC_ADC_ARB_APB_PRIORITY_S 6
|
||||
/* APB_SARADC_ADC_ARB_GRANT_FORCE : R/W ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: adc2 arbiter force grant.*/
|
||||
#define APB_SARADC_ADC_ARB_GRANT_FORCE (BIT(5))
|
||||
#define APB_SARADC_ADC_ARB_GRANT_FORCE_M (BIT(5))
|
||||
#define APB_SARADC_ADC_ARB_GRANT_FORCE_V 0x1
|
||||
#define APB_SARADC_ADC_ARB_GRANT_FORCE_S 5
|
||||
/* APB_SARADC_ADC_ARB_WIFI_FORCE : R/W ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: adc2 arbiter force to enable wifi controller.*/
|
||||
#define APB_SARADC_ADC_ARB_WIFI_FORCE (BIT(4))
|
||||
#define APB_SARADC_ADC_ARB_WIFI_FORCE_M (BIT(4))
|
||||
#define APB_SARADC_ADC_ARB_WIFI_FORCE_V 0x1
|
||||
#define APB_SARADC_ADC_ARB_WIFI_FORCE_S 4
|
||||
/* APB_SARADC_ADC_ARB_RTC_FORCE : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: adc2 arbiter force to enable rtc controller.*/
|
||||
#define APB_SARADC_ADC_ARB_RTC_FORCE (BIT(3))
|
||||
#define APB_SARADC_ADC_ARB_RTC_FORCE_M (BIT(3))
|
||||
#define APB_SARADC_ADC_ARB_RTC_FORCE_V 0x1
|
||||
#define APB_SARADC_ADC_ARB_RTC_FORCE_S 3
|
||||
/* APB_SARADC_ADC_ARB_APB_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: adc2 arbiter force to enableapb controller.*/
|
||||
#define APB_SARADC_ADC_ARB_APB_FORCE (BIT(2))
|
||||
#define APB_SARADC_ADC_ARB_APB_FORCE_M (BIT(2))
|
||||
#define APB_SARADC_ADC_ARB_APB_FORCE_V 0x1
|
||||
#define APB_SARADC_ADC_ARB_APB_FORCE_S 2
|
||||
|
||||
#define APB_SARADC_FILTER_CTRL0_REG (DR_REG_APB_SARADC_BASE + 0x3C)
|
||||
/* APB_SARADC_FILTER_RESET : R/W ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: enable apb_adc1_filter.*/
|
||||
#define APB_SARADC_FILTER_RESET (BIT(31))
|
||||
#define APB_SARADC_FILTER_RESET_M (BIT(31))
|
||||
#define APB_SARADC_FILTER_RESET_V 0x1
|
||||
#define APB_SARADC_FILTER_RESET_S 31
|
||||
/* APB_SARADC_FILTER_CHANNEL0 : R/W ;bitpos:[23:19] ;default: 5'hd ; */
|
||||
/*description: apb_adc1_filter_factor.*/
|
||||
#define APB_SARADC_FILTER_CHANNEL0 0x0000001F
|
||||
#define APB_SARADC_FILTER_CHANNEL0_M ((APB_SARADC_FILTER_CHANNEL0_V)<<(APB_SARADC_FILTER_CHANNEL0_S))
|
||||
#define APB_SARADC_FILTER_CHANNEL0_V 0x1F
|
||||
#define APB_SARADC_FILTER_CHANNEL0_S 19
|
||||
/* APB_SARADC_FILTER_CHANNEL1 : R/W ;bitpos:[18:14] ;default: 5'hd ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_FILTER_CHANNEL1 0x0000001F
|
||||
#define APB_SARADC_FILTER_CHANNEL1_M ((APB_SARADC_FILTER_CHANNEL1_V)<<(APB_SARADC_FILTER_CHANNEL1_S))
|
||||
#define APB_SARADC_FILTER_CHANNEL1_V 0x1F
|
||||
#define APB_SARADC_FILTER_CHANNEL1_S 14
|
||||
|
||||
#define APB_SARADC_APB_SARADC1_DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x40)
|
||||
/* APB_SARADC_ADC1_DATA : RO ;bitpos:[16:0] ;default: 17'd0 ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_ADC1_DATA 0x0001FFFF
|
||||
#define APB_SARADC_ADC1_DATA_M ((APB_SARADC_ADC1_DATA_V)<<(APB_SARADC_ADC1_DATA_S))
|
||||
#define APB_SARADC_ADC1_DATA_V 0x1FFFF
|
||||
#define APB_SARADC_ADC1_DATA_S 0
|
||||
|
||||
#define APB_SARADC_THRES0_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x44)
|
||||
/* APB_SARADC_THRES0_LOW : R/W ;bitpos:[30:18] ;default: 13'd0 ; */
|
||||
/*description: saradc1's thres0 monitor thres.*/
|
||||
#define APB_SARADC_THRES0_LOW 0x00001FFF
|
||||
#define APB_SARADC_THRES0_LOW_M ((APB_SARADC_THRES0_LOW_V)<<(APB_SARADC_THRES0_LOW_S))
|
||||
#define APB_SARADC_THRES0_LOW_V 0x1FFF
|
||||
#define APB_SARADC_THRES0_LOW_S 18
|
||||
/* APB_SARADC_THRES0_HIGH : R/W ;bitpos:[17:5] ;default: 13'h1fff ; */
|
||||
/*description: saradc1's thres0 monitor thres.*/
|
||||
#define APB_SARADC_THRES0_HIGH 0x00001FFF
|
||||
#define APB_SARADC_THRES0_HIGH_M ((APB_SARADC_THRES0_HIGH_V)<<(APB_SARADC_THRES0_HIGH_S))
|
||||
#define APB_SARADC_THRES0_HIGH_V 0x1FFF
|
||||
#define APB_SARADC_THRES0_HIGH_S 5
|
||||
/* APB_SARADC_THRES0_CHANNEL : R/W ;bitpos:[4:0] ;default: 5'd13 ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_THRES0_CHANNEL 0x0000001F
|
||||
#define APB_SARADC_THRES0_CHANNEL_M ((APB_SARADC_THRES0_CHANNEL_V)<<(APB_SARADC_THRES0_CHANNEL_S))
|
||||
#define APB_SARADC_THRES0_CHANNEL_V 0x1F
|
||||
#define APB_SARADC_THRES0_CHANNEL_S 0
|
||||
|
||||
#define APB_SARADC_THRES1_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x48)
|
||||
/* APB_SARADC_THRES1_LOW : R/W ;bitpos:[30:18] ;default: 13'd0 ; */
|
||||
/*description: saradc1's thres0 monitor thres.*/
|
||||
#define APB_SARADC_THRES1_LOW 0x00001FFF
|
||||
#define APB_SARADC_THRES1_LOW_M ((APB_SARADC_THRES1_LOW_V)<<(APB_SARADC_THRES1_LOW_S))
|
||||
#define APB_SARADC_THRES1_LOW_V 0x1FFF
|
||||
#define APB_SARADC_THRES1_LOW_S 18
|
||||
/* APB_SARADC_THRES1_HIGH : R/W ;bitpos:[17:5] ;default: 13'h1fff ; */
|
||||
/*description: saradc1's thres0 monitor thres.*/
|
||||
#define APB_SARADC_THRES1_HIGH 0x00001FFF
|
||||
#define APB_SARADC_THRES1_HIGH_M ((APB_SARADC_THRES1_HIGH_V)<<(APB_SARADC_THRES1_HIGH_S))
|
||||
#define APB_SARADC_THRES1_HIGH_V 0x1FFF
|
||||
#define APB_SARADC_THRES1_HIGH_S 5
|
||||
/* APB_SARADC_THRES1_CHANNEL : R/W ;bitpos:[4:0] ;default: 5'd13 ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_THRES1_CHANNEL 0x0000001F
|
||||
#define APB_SARADC_THRES1_CHANNEL_M ((APB_SARADC_THRES1_CHANNEL_V)<<(APB_SARADC_THRES1_CHANNEL_S))
|
||||
#define APB_SARADC_THRES1_CHANNEL_V 0x1F
|
||||
#define APB_SARADC_THRES1_CHANNEL_S 0
|
||||
|
||||
#define APB_SARADC_THRES_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x58)
|
||||
/* APB_SARADC_THRES0_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_THRES0_EN (BIT(31))
|
||||
#define APB_SARADC_THRES0_EN_M (BIT(31))
|
||||
#define APB_SARADC_THRES0_EN_V 0x1
|
||||
#define APB_SARADC_THRES0_EN_S 31
|
||||
/* APB_SARADC_THRES1_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_THRES1_EN (BIT(30))
|
||||
#define APB_SARADC_THRES1_EN_M (BIT(30))
|
||||
#define APB_SARADC_THRES1_EN_V 0x1
|
||||
#define APB_SARADC_THRES1_EN_S 30
|
||||
/* APB_SARADC_THRES2_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_THRES2_EN (BIT(29))
|
||||
#define APB_SARADC_THRES2_EN_M (BIT(29))
|
||||
#define APB_SARADC_THRES2_EN_V 0x1
|
||||
#define APB_SARADC_THRES2_EN_S 29
|
||||
/* APB_SARADC_THRES3_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_THRES3_EN (BIT(28))
|
||||
#define APB_SARADC_THRES3_EN_M (BIT(28))
|
||||
#define APB_SARADC_THRES3_EN_V 0x1
|
||||
#define APB_SARADC_THRES3_EN_S 28
|
||||
/* APB_SARADC_THRES_ALL_EN : R/W ;bitpos:[27] ;default: 1'd0 ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_THRES_ALL_EN (BIT(27))
|
||||
#define APB_SARADC_THRES_ALL_EN_M (BIT(27))
|
||||
#define APB_SARADC_THRES_ALL_EN_V 0x1
|
||||
#define APB_SARADC_THRES_ALL_EN_S 27
|
||||
|
||||
#define APB_SARADC_INT_ENA_REG (DR_REG_APB_SARADC_BASE + 0x5C)
|
||||
/* APB_SARADC_ADC1_DONE_INT_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_ADC1_DONE_INT_ENA (BIT(31))
|
||||
#define APB_SARADC_ADC1_DONE_INT_ENA_M (BIT(31))
|
||||
#define APB_SARADC_ADC1_DONE_INT_ENA_V 0x1
|
||||
#define APB_SARADC_ADC1_DONE_INT_ENA_S 31
|
||||
/* APB_SARADC_ADC2_DONE_INT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_ADC2_DONE_INT_ENA (BIT(30))
|
||||
#define APB_SARADC_ADC2_DONE_INT_ENA_M (BIT(30))
|
||||
#define APB_SARADC_ADC2_DONE_INT_ENA_V 0x1
|
||||
#define APB_SARADC_ADC2_DONE_INT_ENA_S 30
|
||||
/* APB_SARADC_THRES0_HIGH_INT_ENA : R/W ;bitpos:[29] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_THRES0_HIGH_INT_ENA (BIT(29))
|
||||
#define APB_SARADC_THRES0_HIGH_INT_ENA_M (BIT(29))
|
||||
#define APB_SARADC_THRES0_HIGH_INT_ENA_V 0x1
|
||||
#define APB_SARADC_THRES0_HIGH_INT_ENA_S 29
|
||||
/* APB_SARADC_THRES1_HIGH_INT_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_THRES1_HIGH_INT_ENA (BIT(28))
|
||||
#define APB_SARADC_THRES1_HIGH_INT_ENA_M (BIT(28))
|
||||
#define APB_SARADC_THRES1_HIGH_INT_ENA_V 0x1
|
||||
#define APB_SARADC_THRES1_HIGH_INT_ENA_S 28
|
||||
/* APB_SARADC_THRES0_LOW_INT_ENA : R/W ;bitpos:[27] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_THRES0_LOW_INT_ENA (BIT(27))
|
||||
#define APB_SARADC_THRES0_LOW_INT_ENA_M (BIT(27))
|
||||
#define APB_SARADC_THRES0_LOW_INT_ENA_V 0x1
|
||||
#define APB_SARADC_THRES0_LOW_INT_ENA_S 27
|
||||
/* APB_SARADC_THRES1_LOW_INT_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_THRES1_LOW_INT_ENA (BIT(26))
|
||||
#define APB_SARADC_THRES1_LOW_INT_ENA_M (BIT(26))
|
||||
#define APB_SARADC_THRES1_LOW_INT_ENA_V 0x1
|
||||
#define APB_SARADC_THRES1_LOW_INT_ENA_S 26
|
||||
|
||||
#define APB_SARADC_INT_RAW_REG (DR_REG_APB_SARADC_BASE + 0x60)
|
||||
/* APB_SARADC_ADC1_DONE_INT_RAW : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_ADC1_DONE_INT_RAW (BIT(31))
|
||||
#define APB_SARADC_ADC1_DONE_INT_RAW_M (BIT(31))
|
||||
#define APB_SARADC_ADC1_DONE_INT_RAW_V 0x1
|
||||
#define APB_SARADC_ADC1_DONE_INT_RAW_S 31
|
||||
/* APB_SARADC_ADC2_DONE_INT_RAW : RO ;bitpos:[30] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_ADC2_DONE_INT_RAW (BIT(30))
|
||||
#define APB_SARADC_ADC2_DONE_INT_RAW_M (BIT(30))
|
||||
#define APB_SARADC_ADC2_DONE_INT_RAW_V 0x1
|
||||
#define APB_SARADC_ADC2_DONE_INT_RAW_S 30
|
||||
/* APB_SARADC_THRES0_HIGH_INT_RAW : RO ;bitpos:[29] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_THRES0_HIGH_INT_RAW (BIT(29))
|
||||
#define APB_SARADC_THRES0_HIGH_INT_RAW_M (BIT(29))
|
||||
#define APB_SARADC_THRES0_HIGH_INT_RAW_V 0x1
|
||||
#define APB_SARADC_THRES0_HIGH_INT_RAW_S 29
|
||||
/* APB_SARADC_THRES1_HIGH_INT_RAW : RO ;bitpos:[28] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_THRES1_HIGH_INT_RAW (BIT(28))
|
||||
#define APB_SARADC_THRES1_HIGH_INT_RAW_M (BIT(28))
|
||||
#define APB_SARADC_THRES1_HIGH_INT_RAW_V 0x1
|
||||
#define APB_SARADC_THRES1_HIGH_INT_RAW_S 28
|
||||
/* APB_SARADC_THRES0_LOW_INT_RAW : RO ;bitpos:[27] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_THRES0_LOW_INT_RAW (BIT(27))
|
||||
#define APB_SARADC_THRES0_LOW_INT_RAW_M (BIT(27))
|
||||
#define APB_SARADC_THRES0_LOW_INT_RAW_V 0x1
|
||||
#define APB_SARADC_THRES0_LOW_INT_RAW_S 27
|
||||
/* APB_SARADC_THRES1_LOW_INT_RAW : RO ;bitpos:[26] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_THRES1_LOW_INT_RAW (BIT(26))
|
||||
#define APB_SARADC_THRES1_LOW_INT_RAW_M (BIT(26))
|
||||
#define APB_SARADC_THRES1_LOW_INT_RAW_V 0x1
|
||||
#define APB_SARADC_THRES1_LOW_INT_RAW_S 26
|
||||
|
||||
#define APB_SARADC_INT_ST_REG (DR_REG_APB_SARADC_BASE + 0x64)
|
||||
/* APB_SARADC_ADC1_DONE_INT_ST : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_ADC1_DONE_INT_ST (BIT(31))
|
||||
#define APB_SARADC_ADC1_DONE_INT_ST_M (BIT(31))
|
||||
#define APB_SARADC_ADC1_DONE_INT_ST_V 0x1
|
||||
#define APB_SARADC_ADC1_DONE_INT_ST_S 31
|
||||
/* APB_SARADC_ADC2_DONE_INT_ST : RO ;bitpos:[30] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_ADC2_DONE_INT_ST (BIT(30))
|
||||
#define APB_SARADC_ADC2_DONE_INT_ST_M (BIT(30))
|
||||
#define APB_SARADC_ADC2_DONE_INT_ST_V 0x1
|
||||
#define APB_SARADC_ADC2_DONE_INT_ST_S 30
|
||||
/* APB_SARADC_THRES0_HIGH_INT_ST : RO ;bitpos:[29] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_THRES0_HIGH_INT_ST (BIT(29))
|
||||
#define APB_SARADC_THRES0_HIGH_INT_ST_M (BIT(29))
|
||||
#define APB_SARADC_THRES0_HIGH_INT_ST_V 0x1
|
||||
#define APB_SARADC_THRES0_HIGH_INT_ST_S 29
|
||||
/* APB_SARADC_THRES1_HIGH_INT_ST : RO ;bitpos:[28] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_THRES1_HIGH_INT_ST (BIT(28))
|
||||
#define APB_SARADC_THRES1_HIGH_INT_ST_M (BIT(28))
|
||||
#define APB_SARADC_THRES1_HIGH_INT_ST_V 0x1
|
||||
#define APB_SARADC_THRES1_HIGH_INT_ST_S 28
|
||||
/* APB_SARADC_THRES0_LOW_INT_ST : RO ;bitpos:[27] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_THRES0_LOW_INT_ST (BIT(27))
|
||||
#define APB_SARADC_THRES0_LOW_INT_ST_M (BIT(27))
|
||||
#define APB_SARADC_THRES0_LOW_INT_ST_V 0x1
|
||||
#define APB_SARADC_THRES0_LOW_INT_ST_S 27
|
||||
/* APB_SARADC_THRES1_LOW_INT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_THRES1_LOW_INT_ST (BIT(26))
|
||||
#define APB_SARADC_THRES1_LOW_INT_ST_M (BIT(26))
|
||||
#define APB_SARADC_THRES1_LOW_INT_ST_V 0x1
|
||||
#define APB_SARADC_THRES1_LOW_INT_ST_S 26
|
||||
|
||||
#define APB_SARADC_INT_CLR_REG (DR_REG_APB_SARADC_BASE + 0x68)
|
||||
/* APB_SARADC_ADC1_DONE_INT_CLR : WO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_ADC1_DONE_INT_CLR (BIT(31))
|
||||
#define APB_SARADC_ADC1_DONE_INT_CLR_M (BIT(31))
|
||||
#define APB_SARADC_ADC1_DONE_INT_CLR_V 0x1
|
||||
#define APB_SARADC_ADC1_DONE_INT_CLR_S 31
|
||||
/* APB_SARADC_ADC2_DONE_INT_CLR : WO ;bitpos:[30] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_ADC2_DONE_INT_CLR (BIT(30))
|
||||
#define APB_SARADC_ADC2_DONE_INT_CLR_M (BIT(30))
|
||||
#define APB_SARADC_ADC2_DONE_INT_CLR_V 0x1
|
||||
#define APB_SARADC_ADC2_DONE_INT_CLR_S 30
|
||||
/* APB_SARADC_THRES0_HIGH_INT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_THRES0_HIGH_INT_CLR (BIT(29))
|
||||
#define APB_SARADC_THRES0_HIGH_INT_CLR_M (BIT(29))
|
||||
#define APB_SARADC_THRES0_HIGH_INT_CLR_V 0x1
|
||||
#define APB_SARADC_THRES0_HIGH_INT_CLR_S 29
|
||||
/* APB_SARADC_THRES1_HIGH_INT_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_THRES1_HIGH_INT_CLR (BIT(28))
|
||||
#define APB_SARADC_THRES1_HIGH_INT_CLR_M (BIT(28))
|
||||
#define APB_SARADC_THRES1_HIGH_INT_CLR_V 0x1
|
||||
#define APB_SARADC_THRES1_HIGH_INT_CLR_S 28
|
||||
/* APB_SARADC_THRES0_LOW_INT_CLR : WO ;bitpos:[27] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_THRES0_LOW_INT_CLR (BIT(27))
|
||||
#define APB_SARADC_THRES0_LOW_INT_CLR_M (BIT(27))
|
||||
#define APB_SARADC_THRES0_LOW_INT_CLR_V 0x1
|
||||
#define APB_SARADC_THRES0_LOW_INT_CLR_S 27
|
||||
/* APB_SARADC_THRES1_LOW_INT_CLR : WO ;bitpos:[26] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_THRES1_LOW_INT_CLR (BIT(26))
|
||||
#define APB_SARADC_THRES1_LOW_INT_CLR_M (BIT(26))
|
||||
#define APB_SARADC_THRES1_LOW_INT_CLR_V 0x1
|
||||
#define APB_SARADC_THRES1_LOW_INT_CLR_S 26
|
||||
|
||||
#define APB_SARADC_DMA_CONF_REG (DR_REG_APB_SARADC_BASE + 0x6C)
|
||||
/* APB_SARADC_APB_ADC_TRANS : R/W ;bitpos:[31] ;default: 1'd0 ; */
|
||||
/*description: enable apb_adc use spi_dma.*/
|
||||
#define APB_SARADC_APB_ADC_TRANS (BIT(31))
|
||||
#define APB_SARADC_APB_ADC_TRANS_M (BIT(31))
|
||||
#define APB_SARADC_APB_ADC_TRANS_V 0x1
|
||||
#define APB_SARADC_APB_ADC_TRANS_S 31
|
||||
/* APB_SARADC_APB_ADC_RESET_FSM : R/W ;bitpos:[30] ;default: 1'b0 ; */
|
||||
/*description: reset_apb_adc_state.*/
|
||||
#define APB_SARADC_APB_ADC_RESET_FSM (BIT(30))
|
||||
#define APB_SARADC_APB_ADC_RESET_FSM_M (BIT(30))
|
||||
#define APB_SARADC_APB_ADC_RESET_FSM_V 0x1
|
||||
#define APB_SARADC_APB_ADC_RESET_FSM_S 30
|
||||
/* APB_SARADC_APB_ADC_EOF_NUM : R/W ;bitpos:[15:0] ;default: 16'd255 ; */
|
||||
/*description: the dma_in_suc_eof gen when sample cnt = spi_eof_num.*/
|
||||
#define APB_SARADC_APB_ADC_EOF_NUM 0x0000FFFF
|
||||
#define APB_SARADC_APB_ADC_EOF_NUM_M ((APB_SARADC_APB_ADC_EOF_NUM_V)<<(APB_SARADC_APB_ADC_EOF_NUM_S))
|
||||
#define APB_SARADC_APB_ADC_EOF_NUM_V 0xFFFF
|
||||
#define APB_SARADC_APB_ADC_EOF_NUM_S 0
|
||||
|
||||
#define APB_SARADC_APB_ADC_CLKM_CONF_REG (DR_REG_APB_SARADC_BASE + 0x70)
|
||||
/* APB_SARADC_CLK_SEL : R/W ;bitpos:[22:21] ;default: 2'b0 ; */
|
||||
/*description: Set this bit to enable clk_apll.*/
|
||||
#define APB_SARADC_CLK_SEL 0x00000003
|
||||
#define APB_SARADC_CLK_SEL_M ((APB_SARADC_CLK_SEL_V)<<(APB_SARADC_CLK_SEL_S))
|
||||
#define APB_SARADC_CLK_SEL_V 0x3
|
||||
#define APB_SARADC_CLK_SEL_S 21
|
||||
/* APB_SARADC_CLK_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_CLK_EN (BIT(20))
|
||||
#define APB_SARADC_CLK_EN_M (BIT(20))
|
||||
#define APB_SARADC_CLK_EN_V 0x1
|
||||
#define APB_SARADC_CLK_EN_S 20
|
||||
/* APB_SARADC_CLKM_DIV_A : R/W ;bitpos:[19:14] ;default: 6'h0 ; */
|
||||
/*description: Fractional clock divider denominator value.*/
|
||||
#define APB_SARADC_CLKM_DIV_A 0x0000003F
|
||||
#define APB_SARADC_CLKM_DIV_A_M ((APB_SARADC_CLKM_DIV_A_V)<<(APB_SARADC_CLKM_DIV_A_S))
|
||||
#define APB_SARADC_CLKM_DIV_A_V 0x3F
|
||||
#define APB_SARADC_CLKM_DIV_A_S 14
|
||||
/* APB_SARADC_CLKM_DIV_B : R/W ;bitpos:[13:8] ;default: 6'h0 ; */
|
||||
/*description: Fractional clock divider numerator value.*/
|
||||
#define APB_SARADC_CLKM_DIV_B 0x0000003F
|
||||
#define APB_SARADC_CLKM_DIV_B_M ((APB_SARADC_CLKM_DIV_B_V)<<(APB_SARADC_CLKM_DIV_B_S))
|
||||
#define APB_SARADC_CLKM_DIV_B_V 0x3F
|
||||
#define APB_SARADC_CLKM_DIV_B_S 8
|
||||
/* APB_SARADC_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd4 ; */
|
||||
/*description: Integral I2S clock divider value.*/
|
||||
#define APB_SARADC_CLKM_DIV_NUM 0x000000FF
|
||||
#define APB_SARADC_CLKM_DIV_NUM_M ((APB_SARADC_CLKM_DIV_NUM_V)<<(APB_SARADC_CLKM_DIV_NUM_S))
|
||||
#define APB_SARADC_CLKM_DIV_NUM_V 0xFF
|
||||
#define APB_SARADC_CLKM_DIV_NUM_S 0
|
||||
|
||||
#define APB_SARADC_APB_SARADC2_DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x78)
|
||||
/* APB_SARADC_ADC2_DATA : RO ;bitpos:[16:0] ;default: 17'd0 ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_ADC2_DATA 0x0001FFFF
|
||||
#define APB_SARADC_ADC2_DATA_M ((APB_SARADC_ADC2_DATA_V)<<(APB_SARADC_ADC2_DATA_S))
|
||||
#define APB_SARADC_ADC2_DATA_V 0x1FFFF
|
||||
#define APB_SARADC_ADC2_DATA_S 0
|
||||
|
||||
#define APB_SARADC_APB_CTRL_DATE_REG (DR_REG_APB_SARADC_BASE + 0x3FC)
|
||||
/* APB_SARADC_APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h02101180 ; */
|
||||
/*description: .*/
|
||||
#define APB_SARADC_APB_CTRL_DATE 0xFFFFFFFF
|
||||
#define APB_SARADC_APB_CTRL_DATE_M ((APB_SARADC_APB_CTRL_DATE_V)<<(APB_SARADC_APB_CTRL_DATE_S))
|
||||
#define APB_SARADC_APB_CTRL_DATE_V 0xFFFFFFFF
|
||||
#define APB_SARADC_APB_CTRL_DATE_S 0
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /*_SOC_APB_SARADC_REG_H_ */
|
||||
@@ -1,456 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#ifndef _SOC_APB_SARADC_STRUCT_H_
|
||||
#define _SOC_APB_SARADC_STRUCT_H_
|
||||
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct apb_saradc_dev_s {
|
||||
union {
|
||||
struct {
|
||||
uint32_t start_force : 1;
|
||||
uint32_t start : 1;
|
||||
uint32_t reserved2 : 1;
|
||||
uint32_t work_mode : 2; /* 0: single mode, 1: double mode, 2: alternate mode*/
|
||||
uint32_t sar_sel : 1; /* 0: SAR1, 1: SAR2, only work for single SAR mode*/
|
||||
uint32_t sar_clk_gated : 1;
|
||||
uint32_t sar_clk_div : 8; /*SAR clock divider*/
|
||||
uint32_t sar1_patt_len : 4; /* 0 ~ 15 means length 1 ~ 16*/
|
||||
uint32_t sar2_patt_len : 4; /* 0 ~ 15 means length 1 ~ 16*/
|
||||
uint32_t sar1_patt_p_clear : 1; /*clear the pointer of pattern table for DIG ADC1 CTRL*/
|
||||
uint32_t sar2_patt_p_clear : 1; /*clear the pointer of pattern table for DIG ADC2 CTRL*/
|
||||
uint32_t data_sar_sel : 1; /*1: sar_sel will be coded by the MSB of the 16-bit output data, in this case the resolution should not be larger than 11 bits.*/
|
||||
uint32_t data_to_i2s : 1; /*1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is from GPIO matrix*/
|
||||
uint32_t xpd_sar_force : 2; /*force option to xpd sar blocks*/
|
||||
uint32_t reserved29 : 1;
|
||||
uint32_t wait_arb_cycle : 2; /*wait arbit signal stable after sar_done*/
|
||||
};
|
||||
uint32_t val;
|
||||
} ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t meas_num_limit : 1;
|
||||
uint32_t max_meas_num : 8; /*max conversion number*/
|
||||
uint32_t sar1_inv : 1; /*1: data to DIG ADC1 CTRL is inverted, otherwise not*/
|
||||
uint32_t sar2_inv : 1; /*1: data to DIG ADC2 CTRL is inverted, otherwise not*/
|
||||
uint32_t timer_sel : 1; /*1: select saradc timer 0: i2s_ws trigger*/
|
||||
uint32_t timer_target : 12; /*to set saradc timer target*/
|
||||
uint32_t timer_en : 1; /*to enable saradc timer trigger*/
|
||||
uint32_t reserved25 : 7;
|
||||
};
|
||||
uint32_t val;
|
||||
} ctrl2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 26;
|
||||
uint32_t filter_factor1 : 3;
|
||||
uint32_t filter_factor0 : 3;
|
||||
};
|
||||
uint32_t val;
|
||||
} filter_ctrl1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t xpd_wait : 8;
|
||||
uint32_t rstb_wait : 8;
|
||||
uint32_t standby_wait : 8;
|
||||
uint32_t reserved24 : 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} fsm_wait;
|
||||
uint32_t sar1_status;
|
||||
uint32_t sar2_status;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar1_patt_tab : 24; /*item 0 ~ 3 for pattern table 1 (each item one byte)*/
|
||||
uint32_t reserved24 : 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar1_patt_tab[4];
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar2_patt_tab : 24; /*item 0 ~ 3 for pattern table 2 (each item one byte)*/
|
||||
uint32_t reserved24 : 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar2_patt_tab[4];
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 2;
|
||||
uint32_t adc_arb_apb_force : 1; /*adc2 arbiter force to enableapb controller*/
|
||||
uint32_t adc_arb_rtc_force : 1; /*adc2 arbiter force to enable rtc controller*/
|
||||
uint32_t adc_arb_wifi_force : 1; /*adc2 arbiter force to enable wifi controller*/
|
||||
uint32_t adc_arb_grant_force : 1; /*adc2 arbiter force grant*/
|
||||
uint32_t adc_arb_apb_priority : 2; /*Set adc2 arbiterapb priority*/
|
||||
uint32_t adc_arb_rtc_priority : 2; /*Set adc2 arbiter rtc priority*/
|
||||
uint32_t adc_arb_wifi_priority : 2; /*Set adc2 arbiter wifi priority*/
|
||||
uint32_t adc_arb_fix_priority : 1; /*adc2 arbiter uses fixed priority*/
|
||||
uint32_t reserved13 : 19;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_adc_arb_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 14;
|
||||
uint32_t filter_channel1 : 5;
|
||||
uint32_t filter_channel0 : 5; /*apb_adc1_filter_factor*/
|
||||
uint32_t reserved24 : 7;
|
||||
uint32_t filter_reset : 1; /*enable apb_adc1_filter*/
|
||||
};
|
||||
uint32_t val;
|
||||
} filter_ctrl0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t adc1_data : 17;
|
||||
uint32_t reserved17 : 15;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_saradc1_data_status;
|
||||
union {
|
||||
struct {
|
||||
uint32_t thres0_channel : 5;
|
||||
uint32_t thres0_high : 13; /*saradc1's thres0 monitor thres*/
|
||||
uint32_t thres0_low : 13; /*saradc1's thres0 monitor thres*/
|
||||
uint32_t reserved31 : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} thres0_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t thres1_channel : 5;
|
||||
uint32_t thres1_high : 13; /*saradc1's thres0 monitor thres*/
|
||||
uint32_t thres1_low : 13; /*saradc1's thres0 monitor thres*/
|
||||
uint32_t reserved31 : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} thres1_ctrl;
|
||||
uint32_t reserved_4c;
|
||||
uint32_t reserved_50;
|
||||
uint32_t reserved_54;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 27;
|
||||
uint32_t thres_all_en : 1;
|
||||
uint32_t thres3_en : 1;
|
||||
uint32_t thres2_en : 1;
|
||||
uint32_t thres1_en : 1;
|
||||
uint32_t thres0_en : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} thres_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 26;
|
||||
uint32_t thres1_low : 1;
|
||||
uint32_t thres0_low : 1;
|
||||
uint32_t thres1_high : 1;
|
||||
uint32_t thres0_high : 1;
|
||||
uint32_t adc2_done : 1;
|
||||
uint32_t adc1_done : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 26;
|
||||
uint32_t thres1_low : 1;
|
||||
uint32_t thres0_low : 1;
|
||||
uint32_t thres1_high : 1;
|
||||
uint32_t thres0_high : 1;
|
||||
uint32_t adc2_done : 1;
|
||||
uint32_t adc1_done : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 26;
|
||||
uint32_t thres1_low : 1;
|
||||
uint32_t thres0_low : 1;
|
||||
uint32_t thres1_high : 1;
|
||||
uint32_t thres0_high : 1;
|
||||
uint32_t adc2_done : 1;
|
||||
uint32_t adc1_done : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 26;
|
||||
uint32_t thres1_low : 1;
|
||||
uint32_t thres0_low : 1;
|
||||
uint32_t thres1_high : 1;
|
||||
uint32_t thres0_high : 1;
|
||||
uint32_t adc2_done : 1;
|
||||
uint32_t adc1_done : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t apb_adc_eof_num : 16; /*the dma_in_suc_eof gen when sample cnt = spi_eof_num*/
|
||||
uint32_t reserved16 : 14;
|
||||
uint32_t apb_adc_reset_fsm : 1; /*reset_apb_adc_state*/
|
||||
uint32_t apb_adc_trans : 1; /*enable apb_adc use spi_dma*/
|
||||
};
|
||||
uint32_t val;
|
||||
} dma_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clkm_div_num : 8; /*Integral I2S clock divider value*/
|
||||
uint32_t clkm_div_b : 6; /*Fractional clock divider numerator value*/
|
||||
uint32_t clkm_div_a : 6; /*Fractional clock divider denominator value*/
|
||||
uint32_t clk_en : 1;
|
||||
uint32_t clk_sel : 2; /*Set this bit to enable clk_apll*/
|
||||
uint32_t reserved23 : 9;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_adc_clkm_conf;
|
||||
uint32_t reserved_74;
|
||||
union {
|
||||
struct {
|
||||
uint32_t adc2_data : 17;
|
||||
uint32_t reserved17 : 15;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_saradc2_data_status;
|
||||
uint32_t reserved_7c;
|
||||
uint32_t reserved_80;
|
||||
uint32_t reserved_84;
|
||||
uint32_t reserved_88;
|
||||
uint32_t reserved_8c;
|
||||
uint32_t reserved_90;
|
||||
uint32_t reserved_94;
|
||||
uint32_t reserved_98;
|
||||
uint32_t reserved_9c;
|
||||
uint32_t reserved_a0;
|
||||
uint32_t reserved_a4;
|
||||
uint32_t reserved_a8;
|
||||
uint32_t reserved_ac;
|
||||
uint32_t reserved_b0;
|
||||
uint32_t reserved_b4;
|
||||
uint32_t reserved_b8;
|
||||
uint32_t reserved_bc;
|
||||
uint32_t reserved_c0;
|
||||
uint32_t reserved_c4;
|
||||
uint32_t reserved_c8;
|
||||
uint32_t reserved_cc;
|
||||
uint32_t reserved_d0;
|
||||
uint32_t reserved_d4;
|
||||
uint32_t reserved_d8;
|
||||
uint32_t reserved_dc;
|
||||
uint32_t reserved_e0;
|
||||
uint32_t reserved_e4;
|
||||
uint32_t reserved_e8;
|
||||
uint32_t reserved_ec;
|
||||
uint32_t reserved_f0;
|
||||
uint32_t reserved_f4;
|
||||
uint32_t reserved_f8;
|
||||
uint32_t reserved_fc;
|
||||
uint32_t reserved_100;
|
||||
uint32_t reserved_104;
|
||||
uint32_t reserved_108;
|
||||
uint32_t reserved_10c;
|
||||
uint32_t reserved_110;
|
||||
uint32_t reserved_114;
|
||||
uint32_t reserved_118;
|
||||
uint32_t reserved_11c;
|
||||
uint32_t reserved_120;
|
||||
uint32_t reserved_124;
|
||||
uint32_t reserved_128;
|
||||
uint32_t reserved_12c;
|
||||
uint32_t reserved_130;
|
||||
uint32_t reserved_134;
|
||||
uint32_t reserved_138;
|
||||
uint32_t reserved_13c;
|
||||
uint32_t reserved_140;
|
||||
uint32_t reserved_144;
|
||||
uint32_t reserved_148;
|
||||
uint32_t reserved_14c;
|
||||
uint32_t reserved_150;
|
||||
uint32_t reserved_154;
|
||||
uint32_t reserved_158;
|
||||
uint32_t reserved_15c;
|
||||
uint32_t reserved_160;
|
||||
uint32_t reserved_164;
|
||||
uint32_t reserved_168;
|
||||
uint32_t reserved_16c;
|
||||
uint32_t reserved_170;
|
||||
uint32_t reserved_174;
|
||||
uint32_t reserved_178;
|
||||
uint32_t reserved_17c;
|
||||
uint32_t reserved_180;
|
||||
uint32_t reserved_184;
|
||||
uint32_t reserved_188;
|
||||
uint32_t reserved_18c;
|
||||
uint32_t reserved_190;
|
||||
uint32_t reserved_194;
|
||||
uint32_t reserved_198;
|
||||
uint32_t reserved_19c;
|
||||
uint32_t reserved_1a0;
|
||||
uint32_t reserved_1a4;
|
||||
uint32_t reserved_1a8;
|
||||
uint32_t reserved_1ac;
|
||||
uint32_t reserved_1b0;
|
||||
uint32_t reserved_1b4;
|
||||
uint32_t reserved_1b8;
|
||||
uint32_t reserved_1bc;
|
||||
uint32_t reserved_1c0;
|
||||
uint32_t reserved_1c4;
|
||||
uint32_t reserved_1c8;
|
||||
uint32_t reserved_1cc;
|
||||
uint32_t reserved_1d0;
|
||||
uint32_t reserved_1d4;
|
||||
uint32_t reserved_1d8;
|
||||
uint32_t reserved_1dc;
|
||||
uint32_t reserved_1e0;
|
||||
uint32_t reserved_1e4;
|
||||
uint32_t reserved_1e8;
|
||||
uint32_t reserved_1ec;
|
||||
uint32_t reserved_1f0;
|
||||
uint32_t reserved_1f4;
|
||||
uint32_t reserved_1f8;
|
||||
uint32_t reserved_1fc;
|
||||
uint32_t reserved_200;
|
||||
uint32_t reserved_204;
|
||||
uint32_t reserved_208;
|
||||
uint32_t reserved_20c;
|
||||
uint32_t reserved_210;
|
||||
uint32_t reserved_214;
|
||||
uint32_t reserved_218;
|
||||
uint32_t reserved_21c;
|
||||
uint32_t reserved_220;
|
||||
uint32_t reserved_224;
|
||||
uint32_t reserved_228;
|
||||
uint32_t reserved_22c;
|
||||
uint32_t reserved_230;
|
||||
uint32_t reserved_234;
|
||||
uint32_t reserved_238;
|
||||
uint32_t reserved_23c;
|
||||
uint32_t reserved_240;
|
||||
uint32_t reserved_244;
|
||||
uint32_t reserved_248;
|
||||
uint32_t reserved_24c;
|
||||
uint32_t reserved_250;
|
||||
uint32_t reserved_254;
|
||||
uint32_t reserved_258;
|
||||
uint32_t reserved_25c;
|
||||
uint32_t reserved_260;
|
||||
uint32_t reserved_264;
|
||||
uint32_t reserved_268;
|
||||
uint32_t reserved_26c;
|
||||
uint32_t reserved_270;
|
||||
uint32_t reserved_274;
|
||||
uint32_t reserved_278;
|
||||
uint32_t reserved_27c;
|
||||
uint32_t reserved_280;
|
||||
uint32_t reserved_284;
|
||||
uint32_t reserved_288;
|
||||
uint32_t reserved_28c;
|
||||
uint32_t reserved_290;
|
||||
uint32_t reserved_294;
|
||||
uint32_t reserved_298;
|
||||
uint32_t reserved_29c;
|
||||
uint32_t reserved_2a0;
|
||||
uint32_t reserved_2a4;
|
||||
uint32_t reserved_2a8;
|
||||
uint32_t reserved_2ac;
|
||||
uint32_t reserved_2b0;
|
||||
uint32_t reserved_2b4;
|
||||
uint32_t reserved_2b8;
|
||||
uint32_t reserved_2bc;
|
||||
uint32_t reserved_2c0;
|
||||
uint32_t reserved_2c4;
|
||||
uint32_t reserved_2c8;
|
||||
uint32_t reserved_2cc;
|
||||
uint32_t reserved_2d0;
|
||||
uint32_t reserved_2d4;
|
||||
uint32_t reserved_2d8;
|
||||
uint32_t reserved_2dc;
|
||||
uint32_t reserved_2e0;
|
||||
uint32_t reserved_2e4;
|
||||
uint32_t reserved_2e8;
|
||||
uint32_t reserved_2ec;
|
||||
uint32_t reserved_2f0;
|
||||
uint32_t reserved_2f4;
|
||||
uint32_t reserved_2f8;
|
||||
uint32_t reserved_2fc;
|
||||
uint32_t reserved_300;
|
||||
uint32_t reserved_304;
|
||||
uint32_t reserved_308;
|
||||
uint32_t reserved_30c;
|
||||
uint32_t reserved_310;
|
||||
uint32_t reserved_314;
|
||||
uint32_t reserved_318;
|
||||
uint32_t reserved_31c;
|
||||
uint32_t reserved_320;
|
||||
uint32_t reserved_324;
|
||||
uint32_t reserved_328;
|
||||
uint32_t reserved_32c;
|
||||
uint32_t reserved_330;
|
||||
uint32_t reserved_334;
|
||||
uint32_t reserved_338;
|
||||
uint32_t reserved_33c;
|
||||
uint32_t reserved_340;
|
||||
uint32_t reserved_344;
|
||||
uint32_t reserved_348;
|
||||
uint32_t reserved_34c;
|
||||
uint32_t reserved_350;
|
||||
uint32_t reserved_354;
|
||||
uint32_t reserved_358;
|
||||
uint32_t reserved_35c;
|
||||
uint32_t reserved_360;
|
||||
uint32_t reserved_364;
|
||||
uint32_t reserved_368;
|
||||
uint32_t reserved_36c;
|
||||
uint32_t reserved_370;
|
||||
uint32_t reserved_374;
|
||||
uint32_t reserved_378;
|
||||
uint32_t reserved_37c;
|
||||
uint32_t reserved_380;
|
||||
uint32_t reserved_384;
|
||||
uint32_t reserved_388;
|
||||
uint32_t reserved_38c;
|
||||
uint32_t reserved_390;
|
||||
uint32_t reserved_394;
|
||||
uint32_t reserved_398;
|
||||
uint32_t reserved_39c;
|
||||
uint32_t reserved_3a0;
|
||||
uint32_t reserved_3a4;
|
||||
uint32_t reserved_3a8;
|
||||
uint32_t reserved_3ac;
|
||||
uint32_t reserved_3b0;
|
||||
uint32_t reserved_3b4;
|
||||
uint32_t reserved_3b8;
|
||||
uint32_t reserved_3bc;
|
||||
uint32_t reserved_3c0;
|
||||
uint32_t reserved_3c4;
|
||||
uint32_t reserved_3c8;
|
||||
uint32_t reserved_3cc;
|
||||
uint32_t reserved_3d0;
|
||||
uint32_t reserved_3d4;
|
||||
uint32_t reserved_3d8;
|
||||
uint32_t reserved_3dc;
|
||||
uint32_t reserved_3e0;
|
||||
uint32_t reserved_3e4;
|
||||
uint32_t reserved_3e8;
|
||||
uint32_t reserved_3ec;
|
||||
uint32_t reserved_3f0;
|
||||
uint32_t reserved_3f4;
|
||||
uint32_t reserved_3f8;
|
||||
uint32_t apb_ctrl_date;
|
||||
} apb_saradc_dev_t;
|
||||
extern apb_saradc_dev_t APB_SARADC;
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /*_SOC_APB_SARADC_STRUCT_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,466 +0,0 @@
|
||||
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_ASSIST_DEBUG_STRUCT_H_
|
||||
#define _SOC_ASSIST_DEBUG_STRUCT_H_
|
||||
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct assist_debug_dev_s {
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_0_area_dram0_0_rd : 1;
|
||||
uint32_t core_0_area_dram0_0_wr : 1;
|
||||
uint32_t core_0_area_dram0_1_rd : 1;
|
||||
uint32_t core_0_area_dram0_1_wr : 1;
|
||||
uint32_t core_0_area_pif_0_rd : 1;
|
||||
uint32_t core_0_area_pif_0_wr : 1;
|
||||
uint32_t core_0_area_pif_1_rd : 1;
|
||||
uint32_t core_0_area_pif_1_wr : 1;
|
||||
uint32_t core_0_sp_spill_min : 1;
|
||||
uint32_t core_0_sp_spill_max : 1;
|
||||
uint32_t core_0_iram0_exception_monitor: 1;
|
||||
uint32_t core_0_dram0_exception_monitor: 1;
|
||||
uint32_t reserved12 : 20;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_0_interrupt_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_0_area_dram0_0_rd : 1;
|
||||
uint32_t core_0_area_dram0_0_wr : 1;
|
||||
uint32_t core_0_area_dram0_1_rd : 1;
|
||||
uint32_t core_0_area_dram0_1_wr : 1;
|
||||
uint32_t core_0_area_pif_0_rd : 1;
|
||||
uint32_t core_0_area_pif_0_wr : 1;
|
||||
uint32_t core_0_area_pif_1_rd : 1;
|
||||
uint32_t core_0_area_pif_1_wr : 1;
|
||||
uint32_t core_0_sp_spill_min : 1;
|
||||
uint32_t core_0_sp_spill_max : 1;
|
||||
uint32_t core_0_iram0_exception_monitor: 1;
|
||||
uint32_t core_0_dram0_exception_monitor: 1;
|
||||
uint32_t reserved12 : 20;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_0_interrupt_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_0_area_dram0_0_rd : 1;
|
||||
uint32_t core_0_area_dram0_0_wr : 1;
|
||||
uint32_t core_0_area_dram0_1_rd : 1;
|
||||
uint32_t core_0_area_dram0_1_wr : 1;
|
||||
uint32_t core_0_area_pif_0_rd : 1;
|
||||
uint32_t core_0_area_pif_0_wr : 1;
|
||||
uint32_t core_0_area_pif_1_rd : 1;
|
||||
uint32_t core_0_area_pif_1_wr : 1;
|
||||
uint32_t core_0_sp_spill_min : 1;
|
||||
uint32_t core_0_sp_spill_max : 1;
|
||||
uint32_t core_0_iram0_exception_monitor: 1;
|
||||
uint32_t core_0_dram0_exception_monitor: 1;
|
||||
uint32_t reserved12 : 20;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_0_interrupt_rls;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_0_area_dram0_0_rd : 1;
|
||||
uint32_t core_0_area_dram0_0_wr : 1;
|
||||
uint32_t core_0_area_dram0_1_rd : 1;
|
||||
uint32_t core_0_area_dram0_1_wr : 1;
|
||||
uint32_t core_0_area_pif_0_rd : 1;
|
||||
uint32_t core_0_area_pif_0_wr : 1;
|
||||
uint32_t core_0_area_pif_1_rd : 1;
|
||||
uint32_t core_0_area_pif_1_wr : 1;
|
||||
uint32_t core_0_sp_spill_min : 1;
|
||||
uint32_t core_0_sp_spill_max : 1;
|
||||
uint32_t core_0_iram0_exception_monitor: 1;
|
||||
uint32_t core_0_dram0_exception_monitor: 1;
|
||||
uint32_t reserved12 : 20;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_0_interrupt_clr;
|
||||
uint32_t core_0_area_dram0_0_min;
|
||||
uint32_t core_0_area_dram0_0_max;
|
||||
uint32_t core_0_area_dram0_1_min;
|
||||
uint32_t core_0_area_dram0_1_max;
|
||||
uint32_t core_0_area_pif_0_min;
|
||||
uint32_t core_0_area_pif_0_max;
|
||||
uint32_t core_0_area_pif_1_min;
|
||||
uint32_t core_0_area_pif_1_max;
|
||||
uint32_t core_0_area_sp;
|
||||
uint32_t core_0_area_pc;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_0_sp_unstable : 8;
|
||||
uint32_t reserved8 : 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_0_sp_unstable;
|
||||
uint32_t core_0_sp_min;
|
||||
uint32_t core_0_sp_max;
|
||||
uint32_t core_0_sp_pc;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_0_rcd_pdebugenable : 1;
|
||||
uint32_t reserved1 : 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_0_rcd_pdebugenable;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_0_rcd_recording : 1;
|
||||
uint32_t reserved1 : 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_0_rcd_recording;
|
||||
uint32_t core_0_rcd_pdebuginst;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_0_rcd_pdebugstatus : 8;
|
||||
uint32_t reserved8 : 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_0_rcd_pdebugstatus;
|
||||
uint32_t core_0_rcd_pdebugdata;
|
||||
uint32_t core_0_rcd_pdebugpc;
|
||||
uint32_t core_0_rcd_pdebugls0stat;
|
||||
uint32_t core_0_rcd_pdebugls0addr;
|
||||
uint32_t core_0_rcd_pdebugls0data;
|
||||
uint32_t core_0_rcd_sp;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_0_iram0_recording_addr_0 : 24;
|
||||
uint32_t core_0_iram0_recording_wr_0 : 1;
|
||||
uint32_t core_0_iram0_recording_loadstore_0: 1;
|
||||
uint32_t reserved26 : 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_0_iram0_exception_monitor_0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_0_iram0_recording_addr_1 : 24;
|
||||
uint32_t core_0_iram0_recording_wr_1 : 1;
|
||||
uint32_t core_0_iram0_recording_loadstore_1: 1;
|
||||
uint32_t reserved26 : 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_0_iram0_exception_monitor_1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_0_dram0_recording_addr_0 : 22;
|
||||
uint32_t core_0_dram0_recording_wr_0 : 1;
|
||||
uint32_t reserved23 : 9;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_0_dram0_exception_monitor_0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_0_dram0_recording_byteen_0: 16;
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_0_dram0_exception_monitor_1;
|
||||
uint32_t core_0_dram0_exception_monitor_2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_0_dram0_recording_addr_1 : 22;
|
||||
uint32_t core_0_dram0_recording_wr_1 : 1;
|
||||
uint32_t reserved23 : 9;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_0_dram0_exception_monitor_3;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_0_dram0_recording_byteen_1: 16;
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_0_dram0_exception_monitor_4;
|
||||
uint32_t core_0_dram0_exception_monitor_5;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_1_area_dram0_0_rd : 1;
|
||||
uint32_t core_1_area_dram0_0_wr : 1;
|
||||
uint32_t core_1_area_dram0_1_rd : 1;
|
||||
uint32_t core_1_area_dram0_1_wr : 1;
|
||||
uint32_t core_1_area_pif_0_rd : 1;
|
||||
uint32_t core_1_area_pif_0_wr : 1;
|
||||
uint32_t core_1_area_pif_1_rd : 1;
|
||||
uint32_t core_1_area_pif_1_wr : 1;
|
||||
uint32_t core_1_sp_spill_min : 1;
|
||||
uint32_t core_1_sp_spill_max : 1;
|
||||
uint32_t core_1_iram0_exception_monitor: 1;
|
||||
uint32_t core_1_dram0_exception_monitor: 1;
|
||||
uint32_t reserved12 : 20;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_1_interrupt_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_1_area_dram0_0_rd : 1;
|
||||
uint32_t core_1_area_dram0_0_wr : 1;
|
||||
uint32_t core_1_area_dram0_1_rd : 1;
|
||||
uint32_t core_1_area_dram0_1_wr : 1;
|
||||
uint32_t core_1_area_pif_0_rd : 1;
|
||||
uint32_t core_1_area_pif_0_wr : 1;
|
||||
uint32_t core_1_area_pif_1_rd : 1;
|
||||
uint32_t core_1_area_pif_1_wr : 1;
|
||||
uint32_t core_1_sp_spill_min : 1;
|
||||
uint32_t core_1_sp_spill_max : 1;
|
||||
uint32_t core_1_iram0_exception_monitor: 1;
|
||||
uint32_t core_1_dram0_exception_monitor: 1;
|
||||
uint32_t reserved12 : 20;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_1_interrupt_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_1_area_dram0_0_rd : 1;
|
||||
uint32_t core_1_area_dram0_0_wr : 1;
|
||||
uint32_t core_1_area_dram0_1_rd : 1;
|
||||
uint32_t core_1_area_dram0_1_wr : 1;
|
||||
uint32_t core_1_area_pif_0_rd : 1;
|
||||
uint32_t core_1_area_pif_0_wr : 1;
|
||||
uint32_t core_1_area_pif_1_rd : 1;
|
||||
uint32_t core_1_area_pif_1_wr : 1;
|
||||
uint32_t core_1_sp_spill_min : 1;
|
||||
uint32_t core_1_sp_spill_max : 1;
|
||||
uint32_t core_1_iram0_exception_monitor: 1;
|
||||
uint32_t core_1_dram0_exception_monitor: 1;
|
||||
uint32_t reserved12 : 20;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_1_interrupt_rls;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_1_area_dram0_0_rd : 1;
|
||||
uint32_t core_1_area_dram0_0_wr : 1;
|
||||
uint32_t core_1_area_dram0_1_rd : 1;
|
||||
uint32_t core_1_area_dram0_1_wr : 1;
|
||||
uint32_t core_1_area_pif_0_rd : 1;
|
||||
uint32_t core_1_area_pif_0_wr : 1;
|
||||
uint32_t core_1_area_pif_1_rd : 1;
|
||||
uint32_t core_1_area_pif_1_wr : 1;
|
||||
uint32_t core_1_sp_spill_min : 1;
|
||||
uint32_t core_1_sp_spill_max : 1;
|
||||
uint32_t core_1_iram0_exception_monitor: 1;
|
||||
uint32_t core_1_dram0_exception_monitor: 1;
|
||||
uint32_t reserved12 : 20;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_1_interrupt_clr;
|
||||
uint32_t core_1_area_dram0_0_min;
|
||||
uint32_t core_1_area_dram0_0_max;
|
||||
uint32_t core_1_area_dram0_1_min;
|
||||
uint32_t core_1_area_dram0_1_max;
|
||||
uint32_t core_1_area_pif_0_min;
|
||||
uint32_t core_1_area_pif_0_max;
|
||||
uint32_t core_1_area_pif_1_min;
|
||||
uint32_t core_1_area_pif_1_max;
|
||||
uint32_t core_1_area_pc;
|
||||
uint32_t core_1_area_sp;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_1_sp_unstable : 8;
|
||||
uint32_t reserved8 : 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_1_sp_unstable;
|
||||
uint32_t core_1_sp_min;
|
||||
uint32_t core_1_sp_max;
|
||||
uint32_t core_1_sp_pc;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_1_rcd_pdebugenable : 1;
|
||||
uint32_t reserved1 : 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_1_rcd_pdebugenable;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_1_rcd_recording : 1;
|
||||
uint32_t reserved1 : 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_1_rcd_recording;
|
||||
uint32_t core_1_rcd_pdebuginst;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_1_rcd_pdebugstatus : 8;
|
||||
uint32_t reserved8 : 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_1_rcd_pdebugstatus;
|
||||
uint32_t core_1_rcd_pdebugdata;
|
||||
uint32_t core_1_rcd_pdebugpc;
|
||||
uint32_t core_1_rcd_pdebugls0stat;
|
||||
uint32_t core_1_rcd_pdebugls0addr;
|
||||
uint32_t core_1_rcd_pdebugls0data;
|
||||
uint32_t core_1_rcd_sp;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_1_iram0_recording_addr_0 : 24;
|
||||
uint32_t core_1_iram0_recording_wr_0 : 1;
|
||||
uint32_t core_1_iram0_recording_loadstore_0: 1;
|
||||
uint32_t reserved26 : 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_1_iram0_exception_monitor_0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_1_iram0_recording_addr_1 : 24;
|
||||
uint32_t core_1_iram0_recording_wr_1 : 1;
|
||||
uint32_t core_1_iram0_recording_loadstore_1: 1;
|
||||
uint32_t reserved26 : 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_1_iram0_exception_monitor_1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_1_dram0_recording_addr_0 : 22;
|
||||
uint32_t core_1_dram0_recording_wr_0 : 1;
|
||||
uint32_t reserved23 : 9;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_1_dram0_exception_monitor_0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_1_dram0_recording_byteen_0: 16;
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_1_dram0_exception_monitor_1;
|
||||
uint32_t core_1_dram0_exception_monitor_2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_1_dram0_recording_addr_1 : 22;
|
||||
uint32_t core_1_dram0_recording_wr_1 : 1;
|
||||
uint32_t reserved23 : 9;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_1_dram0_exception_monitor_3;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_1_dram0_recording_byteen_1: 16;
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_1_dram0_exception_monitor_4;
|
||||
uint32_t core_1_dram0_exception_monitor_5;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_x_iram0_dram0_limit_cycle_0: 20;
|
||||
uint32_t reserved20 : 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_x_iram0_dram0_exception_monitor_0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_x_iram0_dram0_limit_cycle_1: 20;
|
||||
uint32_t reserved20 : 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_x_iram0_dram0_exception_monitor_1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t log : 3;
|
||||
uint32_t log_mode : 3;
|
||||
uint32_t log_mem_loopble : 1;
|
||||
uint32_t reserved7 : 25;
|
||||
};
|
||||
uint32_t val;
|
||||
} log_setting;
|
||||
uint32_t log_data_0;
|
||||
uint32_t log_data_1;
|
||||
uint32_t log_data_2;
|
||||
uint32_t log_data_3;
|
||||
union {
|
||||
struct {
|
||||
uint32_t log_data_size : 16;
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} log_data_mask;
|
||||
uint32_t log_min;
|
||||
uint32_t log_max;
|
||||
uint32_t log_mem_start;
|
||||
uint32_t log_mem_end;
|
||||
uint32_t log_mem_writing_addr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t log_mem_full_flag : 1;
|
||||
uint32_t reserved1 : 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} log_mem_full_flag;
|
||||
uint32_t reserved_158;
|
||||
uint32_t reserved_15c;
|
||||
uint32_t reserved_160;
|
||||
uint32_t reserved_164;
|
||||
uint32_t reserved_168;
|
||||
uint32_t reserved_16c;
|
||||
uint32_t reserved_170;
|
||||
uint32_t reserved_174;
|
||||
uint32_t reserved_178;
|
||||
uint32_t reserved_17c;
|
||||
uint32_t reserved_180;
|
||||
uint32_t reserved_184;
|
||||
uint32_t reserved_188;
|
||||
uint32_t reserved_18c;
|
||||
uint32_t reserved_190;
|
||||
uint32_t reserved_194;
|
||||
uint32_t reserved_198;
|
||||
uint32_t reserved_19c;
|
||||
uint32_t reserved_1a0;
|
||||
uint32_t reserved_1a4;
|
||||
uint32_t reserved_1a8;
|
||||
uint32_t reserved_1ac;
|
||||
uint32_t reserved_1b0;
|
||||
uint32_t reserved_1b4;
|
||||
uint32_t reserved_1b8;
|
||||
uint32_t reserved_1bc;
|
||||
uint32_t reserved_1c0;
|
||||
uint32_t reserved_1c4;
|
||||
uint32_t reserved_1c8;
|
||||
uint32_t reserved_1cc;
|
||||
uint32_t reserved_1d0;
|
||||
uint32_t reserved_1d4;
|
||||
uint32_t reserved_1d8;
|
||||
uint32_t reserved_1dc;
|
||||
uint32_t reserved_1e0;
|
||||
uint32_t reserved_1e4;
|
||||
uint32_t reserved_1e8;
|
||||
uint32_t reserved_1ec;
|
||||
uint32_t reserved_1f0;
|
||||
uint32_t reserved_1f4;
|
||||
uint32_t reserved_1f8;
|
||||
union {
|
||||
struct {
|
||||
uint32_t assist_debug_reg_date : 28;
|
||||
uint32_t reserved28 : 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} reg_date;
|
||||
} assist_debug_dev_t;
|
||||
extern assist_debug_dev_t ASSIST_DEBUG;
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /*_SOC_ASSIST_DEBUG_STRUCT_H_ */
|
||||
@@ -5,20 +5,19 @@
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include "soc.h"
|
||||
#include "soc/interrupt_reg.h"
|
||||
#include "soc/system_reg.h"
|
||||
#include "soc/sensitive_reg.h"
|
||||
#include "soc/soc.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "interrupt_reg.h"
|
||||
#include "system_reg.h"
|
||||
#include "sensitive_reg.h"
|
||||
#include "soc.h"
|
||||
|
||||
#define DPORT_DATE_REG SYSTEM_DATE_REG
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
#include "dport_access.h"
|
||||
#include "soc/dport_access.h"
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,798 +0,0 @@
|
||||
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_EXTMEM_STRUCT_H_
|
||||
#define _SOC_EXTMEM_STRUCT_H_
|
||||
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct extmem_dev_s {
|
||||
union {
|
||||
struct {
|
||||
uint32_t dcache_enable : 1; /*The bit is used to activate the data cache. 0: disable, 1: enable*/
|
||||
uint32_t reserved1 : 1; /*Reserved*/
|
||||
uint32_t dcache_size_mode : 1; /*The bit is used to configure cache memory size.0: 32KB, 1: 64KB*/
|
||||
uint32_t dcache_blocksize_mode : 2; /*The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes,2: 64 bytes*/
|
||||
uint32_t reserved5 : 27;
|
||||
};
|
||||
uint32_t val;
|
||||
} dcache_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dcache_shut_core0_bus : 1; /*The bit is used to disable core0 dbus, 0: enable, 1: disable*/
|
||||
uint32_t dcache_shut_core1_bus : 1; /*The bit is used to disable core1 dbus, 0: enable, 1: disable*/
|
||||
uint32_t reserved2 : 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} dcache_ctrl1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dcache_tag_mem_force_on : 1; /*The bit is used to close clock gating of dcache tag memory. 1: close gating, 0: open clock gating.*/
|
||||
uint32_t dcache_tag_mem_force_pd : 1; /*The bit is used to power dcache tag memory down, 0: follow rtc_lslp_pd, 1: power down*/
|
||||
uint32_t dcache_tag_mem_force_pu : 1; /*The bit is used to power dcache tag memory up, 0: follow rtc_lslp_pd, 1: power up*/
|
||||
uint32_t reserved3 : 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} dcache_tag_power_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dcache_prelock_sct0_en : 1; /*The bit is used to enable the first section of prelock function.*/
|
||||
uint32_t dcache_prelock_sct1_en : 1; /*The bit is used to enable the second section of prelock function.*/
|
||||
uint32_t reserved2 : 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} dcache_prelock_ctrl;
|
||||
uint32_t dcache_prelock_sct0_addr;
|
||||
uint32_t dcache_prelock_sct1_addr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dcache_prelock_sct1_size : 16; /*The bits are used to configure the second length of data locking, which is combined with DCACHE_PRELOCK_SCT1_ADDR_REG*/
|
||||
uint32_t dcache_prelock_sct0_size : 16; /*The bits are used to configure the first length of data locking, which is combined with DCACHE_PRELOCK_SCT0_ADDR_REG*/
|
||||
};
|
||||
uint32_t val;
|
||||
} dcache_prelock_sct_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dcache_lock_ena : 1; /*The bit is used to enable lock operation. It will be cleared by hardware after lock operation done.*/
|
||||
uint32_t dcache_unlock_ena : 1; /*The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done.*/
|
||||
uint32_t dcache_lock_done : 1; /*The bit is used to indicate unlock/lock operation is finished.*/
|
||||
uint32_t reserved3 : 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} dcache_lock_ctrl;
|
||||
uint32_t dcache_lock_addr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dcache_lock_size : 16; /*The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with DCACHE_LOCK_ADDR_REG.*/
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} dcache_lock_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dcache_invalidate_ena : 1; /*The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done.*/
|
||||
uint32_t dcache_writeback_ena : 1; /*The bit is used to enable writeback operation. It will be cleared by hardware after writeback operation done.*/
|
||||
uint32_t dcache_clean_ena : 1; /*The bit is used to enable clean operation. It will be cleared by hardware after clean operation done.*/
|
||||
uint32_t dcache_sync_done : 1; /*The bit is used to indicate clean/writeback/invalidate operation is finished.*/
|
||||
uint32_t reserved4 : 28;
|
||||
};
|
||||
uint32_t val;
|
||||
} dcache_sync_ctrl;
|
||||
uint32_t dcache_sync_addr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dcache_sync_size : 23; /*The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with DCACHE_SYNC_ADDR_REG.*/
|
||||
uint32_t reserved23 : 9;
|
||||
};
|
||||
uint32_t val;
|
||||
} dcache_sync_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dcache_occupy_ena : 1; /*The bit is used to enable occupy operation. It will be cleared by hardware after issuing Auot-Invalidate Operation.*/
|
||||
uint32_t dcache_occupy_done : 1; /*The bit is used to indicate occupy operation is finished.*/
|
||||
uint32_t reserved2 : 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} dcache_occupy_ctrl;
|
||||
uint32_t dcache_occupy_addr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dcache_occupy_size : 16; /*The bits are used to configure the length for occupy operation. The bits are the counts of cache block. It should be combined with DCACHE_OCCUPY_ADDR_REG.*/
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} dcache_occupy_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dcache_preload_ena : 1; /*The bit is used to enable preload operation. It will be cleared by hardware after preload operation done.*/
|
||||
uint32_t dcache_preload_done : 1; /*The bit is used to indicate preload operation is finished.*/
|
||||
uint32_t dcache_preload_order : 1; /*The bit is used to configure the direction of preload operation. 1: descending, 0: ascending.*/
|
||||
uint32_t reserved3 : 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} dcache_preload_ctrl;
|
||||
uint32_t dcache_preload_addr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dcache_preload_size : 16; /*The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with DCACHE_PRELOAD_ADDR_REG..*/
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} dcache_preload_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dcache_autoload_sct0_ena : 1; /*The bits are used to enable the first section for autoload operation.*/
|
||||
uint32_t dcache_autoload_sct1_ena : 1; /*The bits are used to enable the second section for autoload operation.*/
|
||||
uint32_t dcache_autoload_ena : 1; /*The bit is used to enable and disable autoload operation. It is combined with dcache_autoload_done. 1: enable, 0: disable. */
|
||||
uint32_t dcache_autoload_done : 1; /*The bit is used to indicate autoload operation is finished.*/
|
||||
uint32_t dcache_autoload_order : 1; /*The bits are used to configure the direction of autoload. 1: descending, 0: ascending.*/
|
||||
uint32_t dcache_autoload_rqst : 2; /*The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit.*/
|
||||
uint32_t dcache_autoload_size : 2; /*The bits are used to configure the numbers of the cache block for the issuing autoload operation.*/
|
||||
uint32_t dcache_autoload_buffer_clear : 1; /*The bit is used to clear autoload buffer in dcache.*/
|
||||
uint32_t reserved10 : 22;
|
||||
};
|
||||
uint32_t val;
|
||||
} dcache_autoload_ctrl;
|
||||
uint32_t dcache_autoload_sct0_addr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dcache_autoload_sct0_size : 27; /*The bits are used to configure the length of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena.*/
|
||||
uint32_t reserved27 : 5;
|
||||
};
|
||||
uint32_t val;
|
||||
} dcache_autoload_sct0_size;
|
||||
uint32_t dcache_autoload_sct1_addr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dcache_autoload_sct1_size : 27; /*The bits are used to configure the length of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena.*/
|
||||
uint32_t reserved27 : 5;
|
||||
};
|
||||
uint32_t val;
|
||||
} dcache_autoload_sct1_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t icache_enable : 1; /*The bit is used to activate the data cache. 0: disable, 1: enable*/
|
||||
uint32_t icache_way_mode : 1; /*The bit is used to configure cache way mode.0: 4-way, 1: 8-way*/
|
||||
uint32_t icache_size_mode : 1; /*The bit is used to configure cache memory size.0: 16KB, 1: 32KB*/
|
||||
uint32_t icache_blocksize_mode : 1; /*The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes*/
|
||||
uint32_t reserved4 : 28;
|
||||
};
|
||||
uint32_t val;
|
||||
} icache_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t icache_shut_core0_bus : 1; /*The bit is used to disable core0 ibus, 0: enable, 1: disable*/
|
||||
uint32_t icache_shut_core1_bus : 1; /*The bit is used to disable core1 ibus, 0: enable, 1: disable*/
|
||||
uint32_t reserved2 : 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} icache_ctrl1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t icache_tag_mem_force_on : 1; /*The bit is used to close clock gating of icache tag memory. 1: close gating, 0: open clock gating.*/
|
||||
uint32_t icache_tag_mem_force_pd : 1; /*The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1: power down*/
|
||||
uint32_t icache_tag_mem_force_pu : 1; /*The bit is used to power icache tag memory up, 0: follow rtc_lslp, 1: power up*/
|
||||
uint32_t reserved3 : 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} icache_tag_power_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t icache_prelock_sct0_en : 1; /*The bit is used to enable the first section of prelock function.*/
|
||||
uint32_t icache_prelock_sct1_en : 1; /*The bit is used to enable the second section of prelock function.*/
|
||||
uint32_t reserved2 : 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} icache_prelock_ctrl;
|
||||
uint32_t icache_prelock_sct0_addr;
|
||||
uint32_t icache_prelock_sct1_addr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t icache_prelock_sct1_size : 16; /*The bits are used to configure the second length of data locking, which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG*/
|
||||
uint32_t icache_prelock_sct0_size : 16; /*The bits are used to configure the first length of data locking, which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG*/
|
||||
};
|
||||
uint32_t val;
|
||||
} icache_prelock_sct_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t icache_lock_ena : 1; /*The bit is used to enable lock operation. It will be cleared by hardware after lock operation done.*/
|
||||
uint32_t icache_unlock_ena : 1; /*The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done.*/
|
||||
uint32_t icache_lock_done : 1; /*The bit is used to indicate unlock/lock operation is finished.*/
|
||||
uint32_t reserved3 : 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} icache_lock_ctrl;
|
||||
uint32_t icache_lock_addr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t icache_lock_size : 16; /*The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG.*/
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} icache_lock_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t icache_invalidate_ena : 1; /*The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done.*/
|
||||
uint32_t icache_sync_done : 1; /*The bit is used to indicate invalidate operation is finished.*/
|
||||
uint32_t reserved2 : 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} icache_sync_ctrl;
|
||||
uint32_t icache_sync_addr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t icache_sync_size : 23; /*The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG.*/
|
||||
uint32_t reserved23 : 9;
|
||||
};
|
||||
uint32_t val;
|
||||
} icache_sync_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t icache_preload_ena : 1; /*The bit is used to enable preload operation. It will be cleared by hardware after preload operation done.*/
|
||||
uint32_t icache_preload_done : 1; /*The bit is used to indicate preload operation is finished.*/
|
||||
uint32_t icache_preload_order : 1; /*The bit is used to configure the direction of preload operation. 1: descending, 0: ascending.*/
|
||||
uint32_t reserved3 : 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} icache_preload_ctrl;
|
||||
uint32_t icache_preload_addr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t icache_preload_size : 16; /*The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG..*/
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} icache_preload_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t icache_autoload_sct0_ena : 1; /*The bits are used to enable the first section for autoload operation.*/
|
||||
uint32_t icache_autoload_sct1_ena : 1; /*The bits are used to enable the second section for autoload operation.*/
|
||||
uint32_t icache_autoload_ena : 1; /*The bit is used to enable and disable autoload operation. It is combined with icache_autoload_done. 1: enable, 0: disable. */
|
||||
uint32_t icache_autoload_done : 1; /*The bit is used to indicate autoload operation is finished.*/
|
||||
uint32_t icache_autoload_order : 1; /*The bits are used to configure the direction of autoload. 1: descending, 0: ascending.*/
|
||||
uint32_t icache_autoload_rqst : 2; /*The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit.*/
|
||||
uint32_t icache_autoload_size : 2; /*The bits are used to configure the numbers of the cache block for the issuing autoload operation.*/
|
||||
uint32_t icache_autoload_buffer_clear : 1; /*The bit is used to clear autoload buffer in icache.*/
|
||||
uint32_t reserved10 : 22;
|
||||
};
|
||||
uint32_t val;
|
||||
} icache_autoload_ctrl;
|
||||
uint32_t icache_autoload_sct0_addr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t icache_autoload_sct0_size : 27; /*The bits are used to configure the length of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena.*/
|
||||
uint32_t reserved27 : 5;
|
||||
};
|
||||
uint32_t val;
|
||||
} icache_autoload_sct0_size;
|
||||
uint32_t icache_autoload_sct1_addr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t icache_autoload_sct1_size : 27; /*The bits are used to configure the length of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena.*/
|
||||
uint32_t reserved27 : 5;
|
||||
};
|
||||
uint32_t val;
|
||||
} icache_autoload_sct1_size;
|
||||
uint32_t ibus_to_flash_start_vaddr;
|
||||
uint32_t ibus_to_flash_end_vaddr;
|
||||
uint32_t dbus_to_flash_start_vaddr;
|
||||
uint32_t dbus_to_flash_end_vaddr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dcache_acs_cnt_clr : 1; /*The bit is used to clear dcache counter.*/
|
||||
uint32_t icache_acs_cnt_clr : 1; /*The bit is used to clear icache counter.*/
|
||||
uint32_t reserved2 : 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} cache_acs_cnt_clr;
|
||||
uint32_t ibus_acs_miss_cnt;
|
||||
uint32_t ibus_acs_cnt;
|
||||
uint32_t dbus_acs_flash_miss_cnt;
|
||||
uint32_t dbus_acs_spiram_miss_cnt;
|
||||
uint32_t dbus_acs_cnt;
|
||||
union {
|
||||
struct {
|
||||
uint32_t icache_sync_op_fault : 1; /*The bit is used to enable interrupt by sync configurations fault.*/
|
||||
uint32_t icache_preload_op_fault : 1; /*The bit is used to enable interrupt by preload configurations fault.*/
|
||||
uint32_t dcache_sync_op_fault : 1; /*The bit is used to enable interrupt by sync configurations fault.*/
|
||||
uint32_t dcache_preload_op_fault : 1; /*The bit is used to enable interrupt by preload configurations fault.*/
|
||||
uint32_t dcache_write_flash : 1; /*The bit is used to enable interrupt by dcache trying to write flash.*/
|
||||
uint32_t mmu_entry_fault : 1; /*The bit is used to enable interrupt by mmu entry fault.*/
|
||||
uint32_t dcache_occupy_exc : 1; /*The bit is used to enable interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode.*/
|
||||
uint32_t ibus_cnt_ovf : 1; /*The bit is used to enable interrupt by ibus counter overflow.*/
|
||||
uint32_t dbus_cnt_ovf : 1; /*The bit is used to enable interrupt by dbus counter overflow.*/
|
||||
uint32_t reserved9 : 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} cache_ilg_int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t icache_sync_op_fault : 1; /*The bit is used to clear interrupt by sync configurations fault.*/
|
||||
uint32_t icache_preload_op_fault : 1; /*The bit is used to clear interrupt by preload configurations fault.*/
|
||||
uint32_t dcache_sync_op_fault : 1; /*The bit is used to clear interrupt by sync configurations fault.*/
|
||||
uint32_t dcache_preload_op_fault : 1; /*The bit is used to clear interrupt by preload configurations fault.*/
|
||||
uint32_t dcache_write_flash : 1; /*The bit is used to clear interrupt by dcache trying to write flash.*/
|
||||
uint32_t mmu_entry_fault : 1; /*The bit is used to clear interrupt by mmu entry fault.*/
|
||||
uint32_t dcache_occupy_exc : 1; /*The bit is used to clear interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode.*/
|
||||
uint32_t ibus_cnt_ovf : 1; /*The bit is used to clear interrupt by ibus counter overflow.*/
|
||||
uint32_t dbus_cnt_ovf : 1; /*The bit is used to clear interrupt by dbus counter overflow.*/
|
||||
uint32_t reserved9 : 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} cache_ilg_int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t icache_sync_op_fault_st : 1; /*The bit is used to indicate interrupt by sync configurations fault.*/
|
||||
uint32_t icache_preload_op_fault_st : 1; /*The bit is used to indicate interrupt by preload configurations fault.*/
|
||||
uint32_t dcache_sync_op_fault_st : 1; /*The bit is used to indicate interrupt by sync configurations fault.*/
|
||||
uint32_t dcache_preload_op_fault_st : 1; /*The bit is used to indicate interrupt by preload configurations fault.*/
|
||||
uint32_t dcache_write_flash_st : 1; /*The bit is used to indicate interrupt by dcache trying to write flash.*/
|
||||
uint32_t mmu_entry_fault_st : 1; /*The bit is used to indicate interrupt by mmu entry fault.*/
|
||||
uint32_t dcache_occupy_exc_st : 1; /*The bit is used to indicate interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode.*/
|
||||
uint32_t ibus_acs_cnt_ovf_st : 1; /*The bit is used to indicate interrupt by ibus access flash/spiram counter overflow.*/
|
||||
uint32_t ibus_acs_miss_cnt_ovf_st : 1; /*The bit is used to indicate interrupt by ibus access flash/spiram miss counter overflow.*/
|
||||
uint32_t dbus_acs_cnt_ovf_st : 1; /*The bit is used to indicate interrupt by dbus access flash/spiram counter overflow.*/
|
||||
uint32_t dbus_acs_flash_miss_cnt_ovf_st: 1; /*The bit is used to indicate interrupt by dbus access flash miss counter overflow.*/
|
||||
uint32_t dbus_acs_spiram_miss_cnt_ovf_st: 1; /*The bit is used to indicate interrupt by dbus access spiram miss counter overflow.*/
|
||||
uint32_t reserved12 : 20;
|
||||
};
|
||||
uint32_t val;
|
||||
} cache_ilg_int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core0_ibus_acs_msk_ic : 1; /*The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access.*/
|
||||
uint32_t core0_ibus_wr_ic : 1; /*The bit is used to enable interrupt by ibus trying to write icache*/
|
||||
uint32_t core0_ibus_reject : 1; /*The bit is used to enable interrupt by authentication fail.*/
|
||||
uint32_t core0_dbus_acs_msk_dc : 1; /*The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access.*/
|
||||
uint32_t core0_dbus_reject : 1; /*The bit is used to enable interrupt by authentication fail.*/
|
||||
uint32_t reserved5 : 27;
|
||||
};
|
||||
uint32_t val;
|
||||
} core0_acs_cache_int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core0_ibus_acs_msk_ic : 1; /*The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access.*/
|
||||
uint32_t core0_ibus_wr_ic : 1; /*The bit is used to clear interrupt by ibus trying to write icache*/
|
||||
uint32_t core0_ibus_reject : 1; /*The bit is used to clear interrupt by authentication fail.*/
|
||||
uint32_t core0_dbus_acs_msk_dc : 1; /*The bit is used to clear interrupt by cpu access dcache while the corresponding dbus is disabled or dcache is disabled which include speculative access.*/
|
||||
uint32_t core0_dbus_reject : 1; /*The bit is used to clear interrupt by authentication fail.*/
|
||||
uint32_t reserved5 : 27;
|
||||
};
|
||||
uint32_t val;
|
||||
} core0_acs_cache_int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core0_ibus_acs_msk_icache_st : 1; /*The bit is used to indicate interrupt by cpu access icache while the core0_ibus is disabled or icache is disabled which include speculative access.*/
|
||||
uint32_t core0_ibus_wr_icache_st : 1; /*The bit is used to indicate interrupt by ibus trying to write icache*/
|
||||
uint32_t core0_ibus_reject_st : 1; /*The bit is used to indicate interrupt by authentication fail.*/
|
||||
uint32_t core0_dbus_acs_msk_dcache_st : 1; /*The bit is used to indicate interrupt by cpu access dcache while the core0_dbus is disabled or dcache is disabled which include speculative access.*/
|
||||
uint32_t core0_dbus_reject_st : 1; /*The bit is used to indicate interrupt by authentication fail.*/
|
||||
uint32_t reserved5 : 27;
|
||||
};
|
||||
uint32_t val;
|
||||
} core0_acs_cache_int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core1_ibus_acs_msk_ic : 1; /*The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access.*/
|
||||
uint32_t core1_ibus_wr_ic : 1; /*The bit is used to enable interrupt by ibus trying to write icache*/
|
||||
uint32_t core1_ibus_reject : 1; /*The bit is used to enable interrupt by authentication fail.*/
|
||||
uint32_t core1_dbus_acs_msk_dc : 1; /*The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access.*/
|
||||
uint32_t core1_dbus_reject : 1; /*The bit is used to enable interrupt by authentication fail.*/
|
||||
uint32_t reserved5 : 27;
|
||||
};
|
||||
uint32_t val;
|
||||
} core1_acs_cache_int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core1_ibus_acs_msk_ic : 1; /*The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access.*/
|
||||
uint32_t core1_ibus_wr_ic : 1; /*The bit is used to clear interrupt by ibus trying to write icache*/
|
||||
uint32_t core1_ibus_reject : 1; /*The bit is used to clear interrupt by authentication fail.*/
|
||||
uint32_t core1_dbus_acs_msk_dc : 1; /*The bit is used to clear interrupt by cpu access dcache while the corresponding dbus is disabled or dcache is disabled which include speculative access.*/
|
||||
uint32_t core1_dbus_reject : 1; /*The bit is used to clear interrupt by authentication fail.*/
|
||||
uint32_t reserved5 : 27;
|
||||
};
|
||||
uint32_t val;
|
||||
} core1_acs_cache_int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core1_ibus_acs_msk_icache_st : 1; /*The bit is used to indicate interrupt by cpu access icache while the core1_ibus is disabled or icache is disabled which include speculative access.*/
|
||||
uint32_t core1_ibus_wr_icache_st : 1; /*The bit is used to indicate interrupt by ibus trying to write icache*/
|
||||
uint32_t core1_ibus_reject_st : 1; /*The bit is used to indicate interrupt by authentication fail.*/
|
||||
uint32_t core1_dbus_acs_msk_dcache_st : 1; /*The bit is used to indicate interrupt by cpu access dcache while the core1_dbus is disabled or dcache is disabled which include speculative access.*/
|
||||
uint32_t core1_dbus_reject_st : 1; /*The bit is used to indicate interrupt by authentication fail.*/
|
||||
uint32_t reserved5 : 27;
|
||||
};
|
||||
uint32_t val;
|
||||
} core1_acs_cache_int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core0_dbus_tag_attr : 3; /*The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.*/
|
||||
uint32_t core0_dbus_attr : 3; /*The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.*/
|
||||
uint32_t core0_dbus_world : 1; /*The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0, 1: WORLD1*/
|
||||
uint32_t reserved7 : 25;
|
||||
};
|
||||
uint32_t val;
|
||||
} core0_dbus_reject_st;
|
||||
uint32_t core0_dbus_reject_vaddr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core0_ibus_tag_attr : 3; /*The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.*/
|
||||
uint32_t core0_ibus_attr : 3; /*The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able*/
|
||||
uint32_t core0_ibus_world : 1; /*The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0, 1: WORLD1*/
|
||||
uint32_t reserved7 : 25;
|
||||
};
|
||||
uint32_t val;
|
||||
} core0_ibus_reject_st;
|
||||
uint32_t core0_ibus_reject_vaddr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core1_dbus_tag_attr : 3; /*The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.*/
|
||||
uint32_t core1_dbus_attr : 3; /*The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.*/
|
||||
uint32_t core1_dbus_world : 1; /*The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0, 1: WORLD1*/
|
||||
uint32_t reserved7 : 25;
|
||||
};
|
||||
uint32_t val;
|
||||
} core1_dbus_reject_st;
|
||||
uint32_t core1_dbus_reject_vaddr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core1_ibus_tag_attr : 3; /*The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.*/
|
||||
uint32_t core1_ibus_attr : 3; /*The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able*/
|
||||
uint32_t core1_ibus_world : 1; /*The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0, 1: WORLD1*/
|
||||
uint32_t reserved7 : 25;
|
||||
};
|
||||
uint32_t val;
|
||||
} core1_ibus_reject_st;
|
||||
uint32_t core1_ibus_reject_vaddr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cache_mmu_fault_content : 16; /*The bits are used to indicate the content of mmu entry which cause mmu fault..*/
|
||||
uint32_t cache_mmu_fault_code : 4; /*The right-most 3 bits are used to indicate the operations which cause mmu fault occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: writeback, 4: cpu miss evict recovery address, 5: load miss evict recovery address, 6: external dma tx, 7: external dma rx. The most significant bit is used to indicate this operation occurs in which one icache. */
|
||||
uint32_t reserved20 : 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} cache_mmu_fault_content;
|
||||
uint32_t cache_mmu_fault_vaddr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cache_flash_wrap_around : 1; /*The bit is used to enable wrap around mode when read data from flash.*/
|
||||
uint32_t cache_sram_rd_wrap_around : 1; /*The bit is used to enable wrap around mode when read data from spiram.*/
|
||||
uint32_t reserved2 : 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} cache_wrap_around_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cache_mmu_mem_force_on : 1; /*The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable*/
|
||||
uint32_t cache_mmu_mem_force_pd : 1; /*The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down*/
|
||||
uint32_t cache_mmu_mem_force_pu : 1; /*The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up*/
|
||||
uint32_t reserved3 : 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} cache_mmu_power_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t icache_state : 12; /*The bit is used to indicate whether icache main fsm is in idle state or not. 1: in idle state, 0: not in idle state*/
|
||||
uint32_t dcache_state : 12; /*The bit is used to indicate whether dcache main fsm is in idle state or not. 1: in idle state, 0: not in idle state*/
|
||||
uint32_t reserved24 : 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} cache_state;
|
||||
union {
|
||||
struct {
|
||||
uint32_t record_disable_db_encrypt : 1; /*Reserved.*/
|
||||
uint32_t record_disable_g0cb_decrypt : 1; /*Reserved.*/
|
||||
uint32_t reserved2 : 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} cache_encrypt_decrypt_record_disable;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_force_on_manual_crypt : 1; /*The bit is used to close clock gating of manual crypt clock. 1: close gating, 0: open clock gating.*/
|
||||
uint32_t clk_force_on_auto_crypt : 1; /*The bit is used to close clock gating of automatic crypt clock. 1: close gating, 0: open clock gating.*/
|
||||
uint32_t clk_force_on_crypt : 1; /*The bit is used to close clock gating of external memory encrypt and decrypt clock. 1: close gating, 0: open clock gating.*/
|
||||
uint32_t reserved3 : 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} cache_encrypt_decrypt_clk_force_on;
|
||||
union {
|
||||
struct {
|
||||
uint32_t alloc_wb_hold_arbiter : 1; /*Reserved.*/
|
||||
uint32_t reserved1 : 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} cache_bridge_arbiter_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t icache_preload_ist : 1; /*The bit is used to indicate the interrupt by icache pre-load done.*/
|
||||
uint32_t icache_preload_iena : 1; /*The bit is used to enable the interrupt by icache pre-load done.*/
|
||||
uint32_t icache_preload_iclr : 1; /*The bit is used to clear the interrupt by icache pre-load done.*/
|
||||
uint32_t dcache_preload_ist : 1; /*The bit is used to indicate the interrupt by dcache pre-load done.*/
|
||||
uint32_t dcache_preload_iena : 1; /*The bit is used to enable the interrupt by dcache pre-load done.*/
|
||||
uint32_t dcache_preload_iclr : 1; /*The bit is used to clear the interrupt by dcache pre-load done.*/
|
||||
uint32_t reserved6 : 26;
|
||||
};
|
||||
uint32_t val;
|
||||
} cache_preload_int_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t icache_sync_ist : 1; /*The bit is used to indicate the interrupt by icache sync done.*/
|
||||
uint32_t icache_sync_iena : 1; /*The bit is used to enable the interrupt by icache sync done.*/
|
||||
uint32_t icache_sync_iclr : 1; /*The bit is used to clear the interrupt by icache sync done.*/
|
||||
uint32_t dcache_sync_ist : 1; /*The bit is used to indicate the interrupt by dcache sync done.*/
|
||||
uint32_t dcache_sync_iena : 1; /*The bit is used to enable the interrupt by dcache sync done.*/
|
||||
uint32_t dcache_sync_iclr : 1; /*The bit is used to clear the interrupt by dcache sync done.*/
|
||||
uint32_t reserved6 : 26;
|
||||
};
|
||||
uint32_t val;
|
||||
} cache_sync_int_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cache_mmu_owner : 24; /*The bits are used to specify the owner of MMU.bit0: icache, bit1: dcache, bit2: dma, bit3: reserved.*/
|
||||
uint32_t reserved24 : 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} cache_mmu_owner;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cache_ignore_preload_mmu_entry_fault: 1; /*The bit is used to disable checking mmu entry fault by preload operation.*/
|
||||
uint32_t cache_ignore_sync_mmu_entry_fault: 1; /*The bit is used to disable checking mmu entry fault by sync operation.*/
|
||||
uint32_t cache_trace_ena : 1; /*The bit is used to enable cache trace function.*/
|
||||
uint32_t reserved3 : 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} cache_conf_misc;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dcache_freeze_ena : 1; /*The bit is used to enable dcache freeze mode*/
|
||||
uint32_t dcache_freeze_mode : 1; /*The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert hit if CPU miss*/
|
||||
uint32_t dcache_freeze_done : 1; /*The bit is used to indicate dcache freeze success*/
|
||||
uint32_t reserved3 : 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} dcache_freeze;
|
||||
union {
|
||||
struct {
|
||||
uint32_t icache_freeze_ena : 1; /*The bit is used to enable icache freeze mode*/
|
||||
uint32_t icache_freeze_mode : 1; /*The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert hit if CPU miss*/
|
||||
uint32_t icache_freeze_done : 1; /*The bit is used to indicate icache freeze success*/
|
||||
uint32_t reserved3 : 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} icache_freeze;
|
||||
union {
|
||||
struct {
|
||||
uint32_t icache_atomic_operate_ena : 1; /*The bit is used to activate icache atomic operation protection. In this case, sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation.*/
|
||||
uint32_t reserved1 : 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} icache_atomic_operate_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dcache_atomic_operate_ena : 1; /*The bit is used to activate dcache atomic operation protection. In this case, sync/lock/occupy operation can not interrupt miss-work. This feature does not work during invalidateAll operation.*/
|
||||
uint32_t reserved1 : 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} dcache_atomic_operate_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cache_request_bypass : 1; /*The bit is used to disable request recording which could cause performance issue*/
|
||||
uint32_t reserved1 : 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} cache_request;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_en : 1; /*Reserved.*/
|
||||
uint32_t reserved1 : 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} clock_gate;
|
||||
uint32_t reserved_168;
|
||||
uint32_t reserved_16c;
|
||||
uint32_t reserved_170;
|
||||
uint32_t reserved_174;
|
||||
uint32_t reserved_178;
|
||||
uint32_t reserved_17c;
|
||||
union {
|
||||
struct {
|
||||
uint32_t icache_tag_object : 1; /*Set this bit to set icache tag memory as object. This bit should be onehot with the others fields inside this register.*/
|
||||
uint32_t dcache_tag_object : 1; /*Set this bit to set dcache tag memory as object. This bit should be onehot with the others fields inside this register.*/
|
||||
uint32_t reserved2 : 30; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} cache_tag_object_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cache_tag_way_object : 3; /*Set this bits to select which way of the tag-object will be accessed. 0: way0, 1: way1, 2: way2, 3: way3, .., 7: way7.*/
|
||||
uint32_t reserved3 : 29; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} cache_tag_way_object;
|
||||
uint32_t cache_vaddr;
|
||||
uint32_t cache_tag_content;
|
||||
uint32_t reserved_190;
|
||||
uint32_t reserved_194;
|
||||
uint32_t reserved_198;
|
||||
uint32_t reserved_19c;
|
||||
uint32_t reserved_1a0;
|
||||
uint32_t reserved_1a4;
|
||||
uint32_t reserved_1a8;
|
||||
uint32_t reserved_1ac;
|
||||
uint32_t reserved_1b0;
|
||||
uint32_t reserved_1b4;
|
||||
uint32_t reserved_1b8;
|
||||
uint32_t reserved_1bc;
|
||||
uint32_t reserved_1c0;
|
||||
uint32_t reserved_1c4;
|
||||
uint32_t reserved_1c8;
|
||||
uint32_t reserved_1cc;
|
||||
uint32_t reserved_1d0;
|
||||
uint32_t reserved_1d4;
|
||||
uint32_t reserved_1d8;
|
||||
uint32_t reserved_1dc;
|
||||
uint32_t reserved_1e0;
|
||||
uint32_t reserved_1e4;
|
||||
uint32_t reserved_1e8;
|
||||
uint32_t reserved_1ec;
|
||||
uint32_t reserved_1f0;
|
||||
uint32_t reserved_1f4;
|
||||
uint32_t reserved_1f8;
|
||||
uint32_t reserved_1fc;
|
||||
uint32_t reserved_200;
|
||||
uint32_t reserved_204;
|
||||
uint32_t reserved_208;
|
||||
uint32_t reserved_20c;
|
||||
uint32_t reserved_210;
|
||||
uint32_t reserved_214;
|
||||
uint32_t reserved_218;
|
||||
uint32_t reserved_21c;
|
||||
uint32_t reserved_220;
|
||||
uint32_t reserved_224;
|
||||
uint32_t reserved_228;
|
||||
uint32_t reserved_22c;
|
||||
uint32_t reserved_230;
|
||||
uint32_t reserved_234;
|
||||
uint32_t reserved_238;
|
||||
uint32_t reserved_23c;
|
||||
uint32_t reserved_240;
|
||||
uint32_t reserved_244;
|
||||
uint32_t reserved_248;
|
||||
uint32_t reserved_24c;
|
||||
uint32_t reserved_250;
|
||||
uint32_t reserved_254;
|
||||
uint32_t reserved_258;
|
||||
uint32_t reserved_25c;
|
||||
uint32_t reserved_260;
|
||||
uint32_t reserved_264;
|
||||
uint32_t reserved_268;
|
||||
uint32_t reserved_26c;
|
||||
uint32_t reserved_270;
|
||||
uint32_t reserved_274;
|
||||
uint32_t reserved_278;
|
||||
uint32_t reserved_27c;
|
||||
uint32_t reserved_280;
|
||||
uint32_t reserved_284;
|
||||
uint32_t reserved_288;
|
||||
uint32_t reserved_28c;
|
||||
uint32_t reserved_290;
|
||||
uint32_t reserved_294;
|
||||
uint32_t reserved_298;
|
||||
uint32_t reserved_29c;
|
||||
uint32_t reserved_2a0;
|
||||
uint32_t reserved_2a4;
|
||||
uint32_t reserved_2a8;
|
||||
uint32_t reserved_2ac;
|
||||
uint32_t reserved_2b0;
|
||||
uint32_t reserved_2b4;
|
||||
uint32_t reserved_2b8;
|
||||
uint32_t reserved_2bc;
|
||||
uint32_t reserved_2c0;
|
||||
uint32_t reserved_2c4;
|
||||
uint32_t reserved_2c8;
|
||||
uint32_t reserved_2cc;
|
||||
uint32_t reserved_2d0;
|
||||
uint32_t reserved_2d4;
|
||||
uint32_t reserved_2d8;
|
||||
uint32_t reserved_2dc;
|
||||
uint32_t reserved_2e0;
|
||||
uint32_t reserved_2e4;
|
||||
uint32_t reserved_2e8;
|
||||
uint32_t reserved_2ec;
|
||||
uint32_t reserved_2f0;
|
||||
uint32_t reserved_2f4;
|
||||
uint32_t reserved_2f8;
|
||||
uint32_t reserved_2fc;
|
||||
uint32_t reserved_300;
|
||||
uint32_t reserved_304;
|
||||
uint32_t reserved_308;
|
||||
uint32_t reserved_30c;
|
||||
uint32_t reserved_310;
|
||||
uint32_t reserved_314;
|
||||
uint32_t reserved_318;
|
||||
uint32_t reserved_31c;
|
||||
uint32_t reserved_320;
|
||||
uint32_t reserved_324;
|
||||
uint32_t reserved_328;
|
||||
uint32_t reserved_32c;
|
||||
uint32_t reserved_330;
|
||||
uint32_t reserved_334;
|
||||
uint32_t reserved_338;
|
||||
uint32_t reserved_33c;
|
||||
uint32_t reserved_340;
|
||||
uint32_t reserved_344;
|
||||
uint32_t reserved_348;
|
||||
uint32_t reserved_34c;
|
||||
uint32_t reserved_350;
|
||||
uint32_t reserved_354;
|
||||
uint32_t reserved_358;
|
||||
uint32_t reserved_35c;
|
||||
uint32_t reserved_360;
|
||||
uint32_t reserved_364;
|
||||
uint32_t reserved_368;
|
||||
uint32_t reserved_36c;
|
||||
uint32_t reserved_370;
|
||||
uint32_t reserved_374;
|
||||
uint32_t reserved_378;
|
||||
uint32_t reserved_37c;
|
||||
uint32_t reserved_380;
|
||||
uint32_t reserved_384;
|
||||
uint32_t reserved_388;
|
||||
uint32_t reserved_38c;
|
||||
uint32_t reserved_390;
|
||||
uint32_t reserved_394;
|
||||
uint32_t reserved_398;
|
||||
uint32_t reserved_39c;
|
||||
uint32_t reserved_3a0;
|
||||
uint32_t reserved_3a4;
|
||||
uint32_t reserved_3a8;
|
||||
uint32_t reserved_3ac;
|
||||
uint32_t reserved_3b0;
|
||||
uint32_t reserved_3b4;
|
||||
uint32_t reserved_3b8;
|
||||
uint32_t reserved_3bc;
|
||||
uint32_t reserved_3c0;
|
||||
uint32_t reserved_3c4;
|
||||
uint32_t reserved_3c8;
|
||||
uint32_t reserved_3cc;
|
||||
uint32_t reserved_3d0;
|
||||
uint32_t reserved_3d4;
|
||||
uint32_t reserved_3d8;
|
||||
uint32_t reserved_3dc;
|
||||
uint32_t reserved_3e0;
|
||||
uint32_t reserved_3e4;
|
||||
uint32_t reserved_3e8;
|
||||
uint32_t reserved_3ec;
|
||||
uint32_t reserved_3f0;
|
||||
uint32_t reserved_3f4;
|
||||
uint32_t reserved_3f8;
|
||||
union {
|
||||
struct {
|
||||
uint32_t extmem_reg_date : 28; /*version information.*/
|
||||
uint32_t reserved28 : 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} date;
|
||||
} extmem_dev_t;
|
||||
extern extmem_dev_t EXTMEM;
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /*_SOC_EXTMEM_STRUCT_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,440 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#ifndef _SOC_GDMA_STRUCT_H_
|
||||
#define _SOC_GDMA_STRUCT_H_
|
||||
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct gdma_dev_s {
|
||||
struct {
|
||||
struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t in_rst : 1; /*This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.*/
|
||||
uint32_t in_loop_test : 1; /*reserved*/
|
||||
uint32_t indscr_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. */
|
||||
uint32_t in_data_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM. */
|
||||
uint32_t mem_trans_en : 1; /*Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.*/
|
||||
uint32_t reserved5 : 1; /*reserved*/
|
||||
uint32_t reserved6 : 26; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} conf0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dma_infifo_full_thrs : 12; /*This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx channel 0 received byte number in Rx FIFO is up to the value of the register.*/
|
||||
uint32_t in_check_owner : 1; /*Set this bit to enable checking the owner attribute of the link descriptor.*/
|
||||
uint32_t in_ext_mem_bk_size : 2; /*Block size of Rx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved*/
|
||||
uint32_t reserved15 : 17; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} conf1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t in_done : 1; /*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0.*/
|
||||
uint32_t in_suc_eof : 1; /*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0.*/
|
||||
uint32_t in_err_eof : 1; /*The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved.*/
|
||||
uint32_t in_dscr_err : 1; /*The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0.*/
|
||||
uint32_t in_dscr_empty : 1; /*The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0.*/
|
||||
uint32_t infifo_full_wm : 1; /*The raw interrupt bit turns to high level when received data byte number is up to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 0.*/
|
||||
uint32_t infifo_ovf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. */
|
||||
uint32_t infifo_udf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. */
|
||||
uint32_t infifo_ovf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is overflow. */
|
||||
uint32_t infifo_udf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is underflow. */
|
||||
uint32_t reserved10 : 22; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t in_done : 1; /*The raw interrupt status bit for the IN_DONE_CH_INT interrupt.*/
|
||||
uint32_t in_suc_eof : 1; /*The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.*/
|
||||
uint32_t in_err_eof : 1; /*The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.*/
|
||||
uint32_t in_dscr_err : 1; /*The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.*/
|
||||
uint32_t in_dscr_empty : 1; /*The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/
|
||||
uint32_t infifo_full_wm : 1; /*The raw interrupt status bit for the INFIFO_FULL_WM_CH_INT interrupt.*/
|
||||
uint32_t infifo_ovf_l1 : 1; /*The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.*/
|
||||
uint32_t infifo_udf_l1 : 1; /*The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.*/
|
||||
uint32_t infifo_ovf_l3 : 1; /*The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.*/
|
||||
uint32_t infifo_udf_l3 : 1; /*The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.*/
|
||||
uint32_t reserved10 : 22; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t in_done : 1; /*The interrupt enable bit for the IN_DONE_CH_INT interrupt.*/
|
||||
uint32_t in_suc_eof : 1; /*The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.*/
|
||||
uint32_t in_err_eof : 1; /*The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.*/
|
||||
uint32_t in_dscr_err : 1; /*The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.*/
|
||||
uint32_t in_dscr_empty : 1; /*The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/
|
||||
uint32_t infifo_full_wm : 1; /*The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt.*/
|
||||
uint32_t infifo_ovf_l1 : 1; /*The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.*/
|
||||
uint32_t infifo_udf_l1 : 1; /*The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.*/
|
||||
uint32_t infifo_ovf_l3 : 1; /*The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.*/
|
||||
uint32_t infifo_udf_l3 : 1; /*The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.*/
|
||||
uint32_t reserved10 : 22; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t in_done : 1; /*Set this bit to clear the IN_DONE_CH_INT interrupt.*/
|
||||
uint32_t in_suc_eof : 1; /*Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.*/
|
||||
uint32_t in_err_eof : 1; /*Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.*/
|
||||
uint32_t in_dscr_err : 1; /*Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.*/
|
||||
uint32_t in_dscr_empty : 1; /*Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.*/
|
||||
uint32_t dma_infifo_full_wm : 1; /*Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt.*/
|
||||
uint32_t infifo_ovf_l1 : 1; /*Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.*/
|
||||
uint32_t infifo_udf_l1 : 1; /*Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.*/
|
||||
uint32_t infifo_ovf_l3 : 1; /*Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.*/
|
||||
uint32_t infifo_udf_l3 : 1; /*Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.*/
|
||||
uint32_t reserved10 : 22; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t infifo_full_l1 : 1; /*L1 Rx FIFO full signal for Rx channel 0.*/
|
||||
uint32_t infifo_empty_l1 : 1; /*L1 Rx FIFO empty signal for Rx channel 0.*/
|
||||
uint32_t infifo_full_l2 : 1; /*L2 Rx FIFO full signal for Rx channel 0.*/
|
||||
uint32_t infifo_empty_l2 : 1; /*L2 Rx FIFO empty signal for Rx channel 0.*/
|
||||
uint32_t infifo_full_l3 : 1; /*L3 Rx FIFO full signal for Rx channel 0.*/
|
||||
uint32_t infifo_empty_l3 : 1; /*L3 Rx FIFO empty signal for Rx channel 0.*/
|
||||
uint32_t infifo_cnt_l1 : 6; /*The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.*/
|
||||
uint32_t infifo_cnt_l2 : 7; /*The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0.*/
|
||||
uint32_t infifo_cnt_l3 : 5; /*The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0.*/
|
||||
uint32_t in_remain_under_1b_l3 : 1; /*reserved*/
|
||||
uint32_t in_remain_under_2b_l3 : 1; /*reserved*/
|
||||
uint32_t in_remain_under_3b_l3 : 1; /*reserved*/
|
||||
uint32_t in_remain_under_4b_l3 : 1; /*reserved*/
|
||||
uint32_t in_buf_hungry : 1; /*reserved*/
|
||||
uint32_t reserved29 : 3; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} infifo_status;
|
||||
union {
|
||||
struct {
|
||||
uint32_t infifo_rdata : 12; /*This register stores the data popping from DMA FIFO.*/
|
||||
uint32_t infifo_pop : 1; /*Set this bit to pop data from DMA FIFO.*/
|
||||
uint32_t reserved13 : 19; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} pop;
|
||||
union {
|
||||
struct {
|
||||
uint32_t addr : 20; /*This register stores the 20 least significant bits of the first inlink descriptor's address.*/
|
||||
uint32_t auto_ret : 1; /*Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.*/
|
||||
uint32_t stop : 1; /*Set this bit to stop dealing with the inlink descriptors.*/
|
||||
uint32_t start : 1; /*Set this bit to start dealing with the inlink descriptors.*/
|
||||
uint32_t restart : 1; /*Set this bit to mount a new inlink descriptor.*/
|
||||
uint32_t park : 1; /*1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working.*/
|
||||
uint32_t reserved25 : 7;
|
||||
};
|
||||
uint32_t val;
|
||||
} link;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dscr_addr : 18; /*This register stores the current inlink descriptor's address.*/
|
||||
uint32_t in_dscr_state : 2; /*reserved*/
|
||||
uint32_t in_state : 3; /*reserved*/
|
||||
uint32_t reserved23 : 9; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} state;
|
||||
uint32_t suc_eof_des_addr;
|
||||
uint32_t err_eof_des_addr;
|
||||
uint32_t dscr;
|
||||
uint32_t dscr_bf0;
|
||||
uint32_t dscr_bf1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 8;
|
||||
uint32_t rx_weight : 4; /*The weight of Rx channel 0. */
|
||||
uint32_t reserved12 : 20;
|
||||
};
|
||||
uint32_t val;
|
||||
} weight;
|
||||
uint32_t reserved_40;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_pri : 4; /*The priority of Rx channel 0. The larger of the value, the higher of the priority.*/
|
||||
uint32_t reserved4 : 28;
|
||||
};
|
||||
uint32_t val;
|
||||
} pri;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sel : 6; /*This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT.*/
|
||||
uint32_t reserved6 : 26;
|
||||
};
|
||||
uint32_t val;
|
||||
} peri_sel;
|
||||
uint32_t reserved_4c;
|
||||
uint32_t reserved_50;
|
||||
uint32_t reserved_54;
|
||||
uint32_t reserved_58;
|
||||
uint32_t reserved_5c;
|
||||
} in;
|
||||
struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t out_rst : 1; /*This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.*/
|
||||
uint32_t out_loop_test : 1; /*reserved*/
|
||||
uint32_t out_auto_wrback : 1; /*Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.*/
|
||||
uint32_t out_eof_mode : 1; /*EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA*/
|
||||
uint32_t outdscr_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. */
|
||||
uint32_t out_data_burst_en : 1; /*Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM. */
|
||||
uint32_t reserved6 : 1;
|
||||
uint32_t reserved7 : 25;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 12;
|
||||
uint32_t out_check_owner : 1; /*Set this bit to enable checking the owner attribute of the link descriptor.*/
|
||||
uint32_t out_ext_mem_bk_size : 2; /*Block size of Tx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved*/
|
||||
uint32_t reserved15 : 17; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} conf1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t out_done : 1; /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0.*/
|
||||
uint32_t out_eof : 1; /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. */
|
||||
uint32_t out_dscr_err : 1; /*The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0.*/
|
||||
uint32_t out_total_eof : 1; /*The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0.*/
|
||||
uint32_t outfifo_ovf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow. */
|
||||
uint32_t outfifo_udf_l1 : 1; /*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow. */
|
||||
uint32_t outfifo_ovf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is overflow. */
|
||||
uint32_t outfifo_udf_l3 : 1; /*This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is underflow. */
|
||||
uint32_t reserved8 : 24; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t out_done : 1; /*The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.*/
|
||||
uint32_t out_eof : 1; /*The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.*/
|
||||
uint32_t out_dscr_err : 1; /*The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.*/
|
||||
uint32_t out_total_eof : 1; /*The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/
|
||||
uint32_t outfifo_ovf_l1 : 1; /*The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/
|
||||
uint32_t outfifo_udf_l1 : 1; /*The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/
|
||||
uint32_t outfifo_ovf_l3 : 1; /*The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/
|
||||
uint32_t outfifo_udf_l3 : 1; /*The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/
|
||||
uint32_t reserved8 : 24; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t out_done : 1; /*The interrupt enable bit for the OUT_DONE_CH_INT interrupt.*/
|
||||
uint32_t out_eof : 1; /*The interrupt enable bit for the OUT_EOF_CH_INT interrupt.*/
|
||||
uint32_t out_dscr_err : 1; /*The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.*/
|
||||
uint32_t out_total_eof : 1; /*The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/
|
||||
uint32_t outfifo_ovf_l1 : 1; /*The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/
|
||||
uint32_t outfifo_udf_l1 : 1; /*The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/
|
||||
uint32_t outfifo_ovf_l3 : 1; /*The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/
|
||||
uint32_t outfifo_udf_l3 : 1; /*The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/
|
||||
uint32_t reserved8 : 24; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t out_done : 1; /*Set this bit to clear the OUT_DONE_CH_INT interrupt.*/
|
||||
uint32_t out_eof : 1; /*Set this bit to clear the OUT_EOF_CH_INT interrupt.*/
|
||||
uint32_t out_dscr_err : 1; /*Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.*/
|
||||
uint32_t out_total_eof : 1; /*Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.*/
|
||||
uint32_t outfifo_ovf_l1 : 1; /*Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.*/
|
||||
uint32_t outfifo_udf_l1 : 1; /*Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.*/
|
||||
uint32_t outfifo_ovf_l3 : 1; /*Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.*/
|
||||
uint32_t outfifo_udf_l3 : 1; /*Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.*/
|
||||
uint32_t reserved8 : 24; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t outfifo_full_l1 : 1; /*L1 Tx FIFO full signal for Tx channel 0.*/
|
||||
uint32_t outfifo_empty_l1 : 1; /*L1 Tx FIFO empty signal for Tx channel 0.*/
|
||||
uint32_t outfifo_full_l2 : 1; /*L2 Tx FIFO full signal for Tx channel 0.*/
|
||||
uint32_t outfifo_empty_l2 : 1; /*L2 Tx FIFO empty signal for Tx channel 0.*/
|
||||
uint32_t outfifo_full_l3 : 1; /*L3 Tx FIFO full signal for Tx channel 0.*/
|
||||
uint32_t outfifo_empty_l3 : 1; /*L3 Tx FIFO empty signal for Tx channel 0.*/
|
||||
uint32_t outfifo_cnt_l1 : 5; /*The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.*/
|
||||
uint32_t outfifo_cnt_l2 : 7; /*The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0.*/
|
||||
uint32_t outfifo_cnt_l3 : 5; /*The register stores the byte number of the data in L3 Tx FIFO for Tx channel 0.*/
|
||||
uint32_t out_remain_under_1b_l3 : 1; /*reserved*/
|
||||
uint32_t out_remain_under_2b_l3 : 1; /*reserved*/
|
||||
uint32_t out_remain_under_3b_l3 : 1; /*reserved*/
|
||||
uint32_t out_remain_under_4b_l3 : 1; /*reserved*/
|
||||
uint32_t reserved27 : 5; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} outfifo_status;
|
||||
union {
|
||||
struct {
|
||||
uint32_t outfifo_wdata : 9; /*This register stores the data that need to be pushed into DMA FIFO.*/
|
||||
uint32_t outfifo_push : 1; /*Set this bit to push data into DMA FIFO.*/
|
||||
uint32_t reserved10 : 22; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} push;
|
||||
union {
|
||||
struct {
|
||||
uint32_t addr : 20; /*This register stores the 20 least significant bits of the first outlink descriptor's address.*/
|
||||
uint32_t stop : 1; /*Set this bit to stop dealing with the outlink descriptors.*/
|
||||
uint32_t start : 1; /*Set this bit to start dealing with the outlink descriptors.*/
|
||||
uint32_t restart : 1; /*Set this bit to restart a new outlink from the last address. */
|
||||
uint32_t park : 1; /*1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working.*/
|
||||
uint32_t reserved24 : 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} link;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dscr_addr : 18; /*This register stores the current outlink descriptor's address.*/
|
||||
uint32_t out_dscr_state : 2; /*reserved*/
|
||||
uint32_t out_state : 3; /*reserved*/
|
||||
uint32_t reserved23 : 9; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} state;
|
||||
uint32_t eof_des_addr;
|
||||
uint32_t eof_bfr_des_addr;
|
||||
uint32_t dscr;
|
||||
uint32_t dscr_bf0;
|
||||
uint32_t dscr_bf1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 8;
|
||||
uint32_t tx_weight : 4; /*The weight of Tx channel 0. */
|
||||
uint32_t reserved12 : 20;
|
||||
};
|
||||
uint32_t val;
|
||||
} weight;
|
||||
uint32_t reserved_a0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tx_pri : 4; /*The priority of Tx channel 0. The larger of the value, the higher of the priority.*/
|
||||
uint32_t reserved4 : 28;
|
||||
};
|
||||
uint32_t val;
|
||||
} pri;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sel : 6; /*This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: SPI3. 2: UHCI0. 3: I2S0. 4: I2S1. 5: LCD_CAM. 6: AES. 7: SHA. 8: ADC_DAC. 9: RMT.; 7: AES. 8: SHA. 9: ADC_DAC.*/
|
||||
uint32_t reserved6 : 26;
|
||||
};
|
||||
uint32_t val;
|
||||
} peri_sel;
|
||||
uint32_t reserved_ac;
|
||||
uint32_t reserved_b0;
|
||||
uint32_t reserved_b4;
|
||||
uint32_t reserved_b8;
|
||||
uint32_t reserved_bc;
|
||||
} out;
|
||||
} channel[5];
|
||||
union {
|
||||
struct {
|
||||
uint32_t ahb_testmode : 3; /*reserved*/
|
||||
uint32_t reserved3 : 1; /*reserved*/
|
||||
uint32_t ahb_testaddr : 2; /*reserved*/
|
||||
uint32_t reserved6 : 26; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} ahb_test;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 4; /*reserved*/
|
||||
uint32_t dma_ram_force_pd : 1; /*power down*/
|
||||
uint32_t dma_ram_force_pu : 1;
|
||||
uint32_t dma_ram_clk_fo : 1; /*1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA.*/
|
||||
uint32_t reserved7 : 25;
|
||||
};
|
||||
uint32_t val;
|
||||
} pd_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t ahbm_rst_inter : 1; /*Set this bit, then clear this bit to reset the internal ahb FSM.*/
|
||||
uint32_t ahbm_rst_exter : 1; /*Set this bit, then clear this bit to reset the external ahb FSM.*/
|
||||
uint32_t arb_pri_dis : 1; /*Set this bit to disable priority arbitration function.*/
|
||||
uint32_t reserved3 : 1;
|
||||
uint32_t clk_en : 1;
|
||||
uint32_t reserved5 : 27;
|
||||
};
|
||||
uint32_t val;
|
||||
} misc_conf;
|
||||
struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t in_size : 7; /*This register is used to configure the size of L2 Tx FIFO for Rx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes.*/
|
||||
uint32_t reserved7 : 25;
|
||||
};
|
||||
uint32_t val;
|
||||
} in;
|
||||
union {
|
||||
struct {
|
||||
uint32_t out_size : 7; /*This register is used to configure the size of L2 Tx FIFO for Tx channel 0. 0:16 bytes. 1:24 bytes. 2:32 bytes. 3: 40 bytes. 4: 48 bytes. 5:56 bytes. 6: 64 bytes. 7: 72 bytes. 8: 80 bytes.*/
|
||||
uint32_t reserved7 : 25;
|
||||
};
|
||||
uint32_t val;
|
||||
} out;
|
||||
} sram_size[5];
|
||||
uint32_t extmem_reject_addr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t extmem_reject_attr : 2; /*The reject accessing. Bit 0: if this bit is 1, the rejected accessing is READ. Bit 1: if this bit is 1, the rejected accessing is WRITE.*/
|
||||
uint32_t extmem_reject_channel_num : 4; /*The register indicate the reject accessing from which channel.*/
|
||||
uint32_t extmem_reject_peri_num : 6; /*This register indicate reject accessing from which peripheral.*/
|
||||
uint32_t reserved12 : 20;
|
||||
};
|
||||
uint32_t val;
|
||||
} extmem_reject_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t extmem_reject : 1; /*The raw interrupt bit turns to high level when accessing external RAM is rejected by permission control.*/
|
||||
uint32_t reserved1 : 31; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} extmem_reject_int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t extmem_reject : 1; /*The raw interrupt status bit for the EXTMEM_REJECT_INT interrupt.*/
|
||||
uint32_t reserved1 : 31; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} extmem_reject_int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t extmem_reject : 1; /*The interrupt enable bit for the EXTMEM_REJECT_INT interrupt.*/
|
||||
uint32_t reserved1 : 31; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} extmem_reject_int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t extmem_reject : 1; /*Set this bit to clear the EXTMEM_REJECT_INT interrupt.*/
|
||||
uint32_t reserved1 : 31; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} extmem_reject_int_clr;
|
||||
uint32_t date;
|
||||
} gdma_dev_t;
|
||||
extern gdma_dev_t GDMA;
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /*_SOC_GDMA_STRUCT_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,159 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "soc.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define GPIO_SIGMADELTA0_REG (DR_REG_GPIO_SD_BASE + 0x0)
|
||||
/* GPIO_SD0_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
|
||||
/*description: .*/
|
||||
#define GPIO_SD0_PRESCALE 0x000000FF
|
||||
#define GPIO_SD0_PRESCALE_M ((GPIO_SD0_PRESCALE_V)<<(GPIO_SD0_PRESCALE_S))
|
||||
#define GPIO_SD0_PRESCALE_V 0xFF
|
||||
#define GPIO_SD0_PRESCALE_S 8
|
||||
/* GPIO_SD0_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
|
||||
/*description: .*/
|
||||
#define GPIO_SD0_IN 0x000000FF
|
||||
#define GPIO_SD0_IN_M ((GPIO_SD0_IN_V)<<(GPIO_SD0_IN_S))
|
||||
#define GPIO_SD0_IN_V 0xFF
|
||||
#define GPIO_SD0_IN_S 0
|
||||
|
||||
#define GPIO_SIGMADELTA1_REG (DR_REG_GPIO_SD_BASE + 0x4)
|
||||
/* GPIO_SD1_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
|
||||
/*description: .*/
|
||||
#define GPIO_SD1_PRESCALE 0x000000FF
|
||||
#define GPIO_SD1_PRESCALE_M ((GPIO_SD1_PRESCALE_V)<<(GPIO_SD1_PRESCALE_S))
|
||||
#define GPIO_SD1_PRESCALE_V 0xFF
|
||||
#define GPIO_SD1_PRESCALE_S 8
|
||||
/* GPIO_SD1_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
|
||||
/*description: .*/
|
||||
#define GPIO_SD1_IN 0x000000FF
|
||||
#define GPIO_SD1_IN_M ((GPIO_SD1_IN_V)<<(GPIO_SD1_IN_S))
|
||||
#define GPIO_SD1_IN_V 0xFF
|
||||
#define GPIO_SD1_IN_S 0
|
||||
|
||||
#define GPIO_SIGMADELTA2_REG (DR_REG_GPIO_SD_BASE + 0x8)
|
||||
/* GPIO_SD2_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
|
||||
/*description: .*/
|
||||
#define GPIO_SD2_PRESCALE 0x000000FF
|
||||
#define GPIO_SD2_PRESCALE_M ((GPIO_SD2_PRESCALE_V)<<(GPIO_SD2_PRESCALE_S))
|
||||
#define GPIO_SD2_PRESCALE_V 0xFF
|
||||
#define GPIO_SD2_PRESCALE_S 8
|
||||
/* GPIO_SD2_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
|
||||
/*description: .*/
|
||||
#define GPIO_SD2_IN 0x000000FF
|
||||
#define GPIO_SD2_IN_M ((GPIO_SD2_IN_V)<<(GPIO_SD2_IN_S))
|
||||
#define GPIO_SD2_IN_V 0xFF
|
||||
#define GPIO_SD2_IN_S 0
|
||||
|
||||
#define GPIO_SIGMADELTA3_REG (DR_REG_GPIO_SD_BASE + 0xC)
|
||||
/* GPIO_SD3_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
|
||||
/*description: .*/
|
||||
#define GPIO_SD3_PRESCALE 0x000000FF
|
||||
#define GPIO_SD3_PRESCALE_M ((GPIO_SD3_PRESCALE_V)<<(GPIO_SD3_PRESCALE_S))
|
||||
#define GPIO_SD3_PRESCALE_V 0xFF
|
||||
#define GPIO_SD3_PRESCALE_S 8
|
||||
/* GPIO_SD3_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
|
||||
/*description: .*/
|
||||
#define GPIO_SD3_IN 0x000000FF
|
||||
#define GPIO_SD3_IN_M ((GPIO_SD3_IN_V)<<(GPIO_SD3_IN_S))
|
||||
#define GPIO_SD3_IN_V 0xFF
|
||||
#define GPIO_SD3_IN_S 0
|
||||
|
||||
#define GPIO_SIGMADELTA4_REG (DR_REG_GPIO_SD_BASE + 0x10)
|
||||
/* GPIO_SD4_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
|
||||
/*description: .*/
|
||||
#define GPIO_SD4_PRESCALE 0x000000FF
|
||||
#define GPIO_SD4_PRESCALE_M ((GPIO_SD4_PRESCALE_V)<<(GPIO_SD4_PRESCALE_S))
|
||||
#define GPIO_SD4_PRESCALE_V 0xFF
|
||||
#define GPIO_SD4_PRESCALE_S 8
|
||||
/* GPIO_SD4_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
|
||||
/*description: .*/
|
||||
#define GPIO_SD4_IN 0x000000FF
|
||||
#define GPIO_SD4_IN_M ((GPIO_SD4_IN_V)<<(GPIO_SD4_IN_S))
|
||||
#define GPIO_SD4_IN_V 0xFF
|
||||
#define GPIO_SD4_IN_S 0
|
||||
|
||||
#define GPIO_SIGMADELTA5_REG (DR_REG_GPIO_SD_BASE + 0x14)
|
||||
/* GPIO_SD5_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
|
||||
/*description: .*/
|
||||
#define GPIO_SD5_PRESCALE 0x000000FF
|
||||
#define GPIO_SD5_PRESCALE_M ((GPIO_SD5_PRESCALE_V)<<(GPIO_SD5_PRESCALE_S))
|
||||
#define GPIO_SD5_PRESCALE_V 0xFF
|
||||
#define GPIO_SD5_PRESCALE_S 8
|
||||
/* GPIO_SD5_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
|
||||
/*description: .*/
|
||||
#define GPIO_SD5_IN 0x000000FF
|
||||
#define GPIO_SD5_IN_M ((GPIO_SD5_IN_V)<<(GPIO_SD5_IN_S))
|
||||
#define GPIO_SD5_IN_V 0xFF
|
||||
#define GPIO_SD5_IN_S 0
|
||||
|
||||
#define GPIO_SIGMADELTA6_REG (DR_REG_GPIO_SD_BASE + 0x18)
|
||||
/* GPIO_SD6_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
|
||||
/*description: .*/
|
||||
#define GPIO_SD6_PRESCALE 0x000000FF
|
||||
#define GPIO_SD6_PRESCALE_M ((GPIO_SD6_PRESCALE_V)<<(GPIO_SD6_PRESCALE_S))
|
||||
#define GPIO_SD6_PRESCALE_V 0xFF
|
||||
#define GPIO_SD6_PRESCALE_S 8
|
||||
/* GPIO_SD6_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
|
||||
/*description: .*/
|
||||
#define GPIO_SD6_IN 0x000000FF
|
||||
#define GPIO_SD6_IN_M ((GPIO_SD6_IN_V)<<(GPIO_SD6_IN_S))
|
||||
#define GPIO_SD6_IN_V 0xFF
|
||||
#define GPIO_SD6_IN_S 0
|
||||
|
||||
#define GPIO_SIGMADELTA7_REG (DR_REG_GPIO_SD_BASE + 0x1C)
|
||||
/* GPIO_SD7_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
|
||||
/*description: .*/
|
||||
#define GPIO_SD7_PRESCALE 0x000000FF
|
||||
#define GPIO_SD7_PRESCALE_M ((GPIO_SD7_PRESCALE_V)<<(GPIO_SD7_PRESCALE_S))
|
||||
#define GPIO_SD7_PRESCALE_V 0xFF
|
||||
#define GPIO_SD7_PRESCALE_S 8
|
||||
/* GPIO_SD7_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
|
||||
/*description: .*/
|
||||
#define GPIO_SD7_IN 0x000000FF
|
||||
#define GPIO_SD7_IN_M ((GPIO_SD7_IN_V)<<(GPIO_SD7_IN_S))
|
||||
#define GPIO_SD7_IN_V 0xFF
|
||||
#define GPIO_SD7_IN_S 0
|
||||
|
||||
#define GPIO_SIGMADELTA_CG_REG (DR_REG_GPIO_SD_BASE + 0x20)
|
||||
/* GPIO_SD_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
|
||||
/*description: .*/
|
||||
#define GPIO_SD_CLK_EN (BIT(31))
|
||||
#define GPIO_SD_CLK_EN_M (BIT(31))
|
||||
#define GPIO_SD_CLK_EN_V 0x1
|
||||
#define GPIO_SD_CLK_EN_S 31
|
||||
|
||||
#define GPIO_SIGMADELTA_MISC_REG (DR_REG_GPIO_SD_BASE + 0x24)
|
||||
/* GPIO_SPI_SWAP : R/W ;bitpos:[31] ;default: 1'h0 ; */
|
||||
/*description: .*/
|
||||
#define GPIO_SPI_SWAP (BIT(31))
|
||||
#define GPIO_SPI_SWAP_M (BIT(31))
|
||||
#define GPIO_SPI_SWAP_V 0x1
|
||||
#define GPIO_SPI_SWAP_S 31
|
||||
/* GPIO_FUNCTION_CLK_EN : R/W ;bitpos:[30] ;default: 1'd0 ; */
|
||||
/*description: .*/
|
||||
#define GPIO_FUNCTION_CLK_EN (BIT(30))
|
||||
#define GPIO_FUNCTION_CLK_EN_M (BIT(30))
|
||||
#define GPIO_FUNCTION_CLK_EN_V 0x1
|
||||
#define GPIO_FUNCTION_CLK_EN_S 30
|
||||
|
||||
#define GPIO_SIGMADELTA_VERSION_REG (DR_REG_GPIO_SD_BASE + 0x28)
|
||||
/* GPIO_SD_DATE : R/W ;bitpos:[27:0] ;default: 28'h1802260 ; */
|
||||
/*description: .*/
|
||||
#define GPIO_SD_DATE 0x0FFFFFFF
|
||||
#define GPIO_SD_DATE_M ((GPIO_SD_DATE_V)<<(GPIO_SD_DATE_S))
|
||||
#define GPIO_SD_DATE_V 0xFFFFFFF
|
||||
#define GPIO_SD_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,52 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef struct gpio_sd_dev_t {
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t duty : 8;
|
||||
uint32_t prescale : 8;
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} channel[8];
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t reserved0 : 31;
|
||||
uint32_t clk_en : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} cg;
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t reserved0 : 30;
|
||||
uint32_t function_clk_en : 1;
|
||||
uint32_t spi_swap : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} misc;
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t date : 28;
|
||||
uint32_t reserved28 : 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} version;
|
||||
} gpio_sd_dev_t;
|
||||
|
||||
extern gpio_sd_dev_t SDM;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,250 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _SOC_GPIO_STRUCT_H_
|
||||
#define _SOC_GPIO_STRUCT_H_
|
||||
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct gpio_dev_s {
|
||||
uint32_t bt_select;
|
||||
uint32_t out;
|
||||
uint32_t out_w1ts;
|
||||
uint32_t out_w1tc;
|
||||
union {
|
||||
struct {
|
||||
uint32_t data : 22;
|
||||
uint32_t reserved22 : 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} out1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t data : 22;
|
||||
uint32_t reserved22 : 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} out1_w1ts;
|
||||
union {
|
||||
struct {
|
||||
uint32_t data : 22;
|
||||
uint32_t reserved22 : 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} out1_w1tc;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sel : 8;
|
||||
uint32_t reserved8 : 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} sdio_select;
|
||||
uint32_t enable;
|
||||
uint32_t enable_w1ts;
|
||||
uint32_t enable_w1tc;
|
||||
union {
|
||||
struct {
|
||||
uint32_t data : 22;
|
||||
uint32_t reserved22 : 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} enable1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t data : 22;
|
||||
uint32_t reserved22 : 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} enable1_w1ts;
|
||||
union {
|
||||
struct {
|
||||
uint32_t data : 22;
|
||||
uint32_t reserved22 : 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} enable1_w1tc;
|
||||
union {
|
||||
struct {
|
||||
uint32_t strapping : 16;
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} strap;
|
||||
uint32_t in;
|
||||
union {
|
||||
struct {
|
||||
uint32_t data : 22;
|
||||
uint32_t reserved22 : 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} in1;
|
||||
uint32_t status;
|
||||
uint32_t status_w1ts;
|
||||
uint32_t status_w1tc;
|
||||
union {
|
||||
struct {
|
||||
uint32_t intr_st : 22;
|
||||
uint32_t reserved22 : 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} status1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t intr_st : 22;
|
||||
uint32_t reserved22 : 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} status1_w1ts;
|
||||
union {
|
||||
struct {
|
||||
uint32_t intr_st : 22;
|
||||
uint32_t reserved22 : 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} status1_w1tc;
|
||||
uint32_t pcpu_int; /*GPIO0~31 PRO & APP CPU interrupt status*/
|
||||
uint32_t pcpu_nmi_int; /*GPIO0~31 PRO & APP CPU non-maskable interrupt status*/
|
||||
uint32_t cpusdio_int;
|
||||
union {
|
||||
struct {
|
||||
uint32_t intr : 22; /*GPIO32-48 PRO & APP CPU interrupt status*/
|
||||
uint32_t reserved22 : 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} pcpu_int1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t intr : 22; /*GPIO32-48 PRO & APP CPU non-maskable interrupt status*/
|
||||
uint32_t reserved22 : 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} pcpu_nmi_int1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t intr : 22;
|
||||
uint32_t reserved22 : 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} cpusdio_int1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sync2_bypass : 2;
|
||||
uint32_t pad_driver : 1;
|
||||
uint32_t sync1_bypass : 2;
|
||||
uint32_t reserved5 : 2;
|
||||
uint32_t int_type : 3;
|
||||
uint32_t wakeup_enable : 1;
|
||||
uint32_t config : 2;
|
||||
uint32_t int_ena : 5;
|
||||
uint32_t reserved18 : 14;
|
||||
};
|
||||
uint32_t val;
|
||||
} pin[54];
|
||||
uint32_t status_next;
|
||||
union {
|
||||
struct {
|
||||
uint32_t intr_st_next : 22;
|
||||
uint32_t reserved22 : 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} status_next1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t func_sel : 6;
|
||||
uint32_t sig_in_inv : 1;
|
||||
uint32_t sig_in_sel : 1;
|
||||
uint32_t reserved8 : 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} func_in_sel_cfg[256];
|
||||
union {
|
||||
struct {
|
||||
uint32_t func_sel : 9;
|
||||
uint32_t inv_sel : 1;
|
||||
uint32_t oen_sel : 1;
|
||||
uint32_t oen_inv_sel : 1;
|
||||
uint32_t reserved12 : 20;
|
||||
};
|
||||
uint32_t val;
|
||||
} func_out_sel_cfg[54];
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_en : 1;
|
||||
uint32_t reserved1 : 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} clock_gate;
|
||||
uint32_t reserved_630;
|
||||
uint32_t reserved_634;
|
||||
uint32_t reserved_638;
|
||||
uint32_t reserved_63c;
|
||||
uint32_t reserved_640;
|
||||
uint32_t reserved_644;
|
||||
uint32_t reserved_648;
|
||||
uint32_t reserved_64c;
|
||||
uint32_t reserved_650;
|
||||
uint32_t reserved_654;
|
||||
uint32_t reserved_658;
|
||||
uint32_t reserved_65c;
|
||||
uint32_t reserved_660;
|
||||
uint32_t reserved_664;
|
||||
uint32_t reserved_668;
|
||||
uint32_t reserved_66c;
|
||||
uint32_t reserved_670;
|
||||
uint32_t reserved_674;
|
||||
uint32_t reserved_678;
|
||||
uint32_t reserved_67c;
|
||||
uint32_t reserved_680;
|
||||
uint32_t reserved_684;
|
||||
uint32_t reserved_688;
|
||||
uint32_t reserved_68c;
|
||||
uint32_t reserved_690;
|
||||
uint32_t reserved_694;
|
||||
uint32_t reserved_698;
|
||||
uint32_t reserved_69c;
|
||||
uint32_t reserved_6a0;
|
||||
uint32_t reserved_6a4;
|
||||
uint32_t reserved_6a8;
|
||||
uint32_t reserved_6ac;
|
||||
uint32_t reserved_6b0;
|
||||
uint32_t reserved_6b4;
|
||||
uint32_t reserved_6b8;
|
||||
uint32_t reserved_6bc;
|
||||
uint32_t reserved_6c0;
|
||||
uint32_t reserved_6c4;
|
||||
uint32_t reserved_6c8;
|
||||
uint32_t reserved_6cc;
|
||||
uint32_t reserved_6d0;
|
||||
uint32_t reserved_6d4;
|
||||
uint32_t reserved_6d8;
|
||||
uint32_t reserved_6dc;
|
||||
uint32_t reserved_6e0;
|
||||
uint32_t reserved_6e4;
|
||||
uint32_t reserved_6e8;
|
||||
uint32_t reserved_6ec;
|
||||
uint32_t reserved_6f0;
|
||||
uint32_t reserved_6f4;
|
||||
uint32_t reserved_6f8;
|
||||
union {
|
||||
struct {
|
||||
uint32_t date : 28;
|
||||
uint32_t reserved28 : 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} date;
|
||||
} gpio_dev_t;
|
||||
extern gpio_dev_t GPIO;
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /*_SOC_GPIO_STRUCT_H_ */
|
||||
@@ -1,240 +0,0 @@
|
||||
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#include "soc.h"
|
||||
|
||||
#define HINF_CFG_DATA0_REG (DR_REG_HINF_BASE + 0x0)
|
||||
/* HINF_DEVICE_ID_FN1 : R/W ;bitpos:[31:16] ;default: 16'h2222 ; */
|
||||
/*description: */
|
||||
#define HINF_DEVICE_ID_FN1 0x0000FFFF
|
||||
#define HINF_DEVICE_ID_FN1_M ((HINF_DEVICE_ID_FN1_V) << (HINF_DEVICE_ID_FN1_S))
|
||||
#define HINF_DEVICE_ID_FN1_V 0xFFFF
|
||||
#define HINF_DEVICE_ID_FN1_S 16
|
||||
/* HINF_USER_ID_FN1 : R/W ;bitpos:[15:0] ;default: 16'h6666 ; */
|
||||
/*description: */
|
||||
#define HINF_USER_ID_FN1 0x0000FFFF
|
||||
#define HINF_USER_ID_FN1_M ((HINF_USER_ID_FN1_V) << (HINF_USER_ID_FN1_S))
|
||||
#define HINF_USER_ID_FN1_V 0xFFFF
|
||||
#define HINF_USER_ID_FN1_S 0
|
||||
|
||||
#define HINF_CFG_DATA1_REG (DR_REG_HINF_BASE + 0x4)
|
||||
/* HINF_SDIO20_CONF1 : R/W ;bitpos:[31:29] ;default: 3'h0 ; */
|
||||
/*description: */
|
||||
#define HINF_SDIO20_CONF1 0x00000007
|
||||
#define HINF_SDIO20_CONF1_M ((HINF_SDIO20_CONF1_V) << (HINF_SDIO20_CONF1_S))
|
||||
#define HINF_SDIO20_CONF1_V 0x7
|
||||
#define HINF_SDIO20_CONF1_S 29
|
||||
/* HINF_FUNC2_EPS : RO ;bitpos:[28] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define HINF_FUNC2_EPS (BIT(28))
|
||||
#define HINF_FUNC2_EPS_M (BIT(28))
|
||||
#define HINF_FUNC2_EPS_V 0x1
|
||||
#define HINF_FUNC2_EPS_S 28
|
||||
/* HINF_SDIO_VER : R/W ;bitpos:[27:16] ;default: 12'h111 ; */
|
||||
/*description: */
|
||||
#define HINF_SDIO_VER 0x00000FFF
|
||||
#define HINF_SDIO_VER_M ((HINF_SDIO_VER_V) << (HINF_SDIO_VER_S))
|
||||
#define HINF_SDIO_VER_V 0xFFF
|
||||
#define HINF_SDIO_VER_S 16
|
||||
/* HINF_SDIO20_CONF0 : R/W ;bitpos:[15:12] ;default: 4'b0 ; */
|
||||
/*description: */
|
||||
#define HINF_SDIO20_CONF0 0x0000000F
|
||||
#define HINF_SDIO20_CONF0_M ((HINF_SDIO20_CONF0_V) << (HINF_SDIO20_CONF0_S))
|
||||
#define HINF_SDIO20_CONF0_V 0xF
|
||||
#define HINF_SDIO20_CONF0_S 12
|
||||
/* HINF_IOENABLE1 : RO ;bitpos:[11] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define HINF_IOENABLE1 (BIT(11))
|
||||
#define HINF_IOENABLE1_M (BIT(11))
|
||||
#define HINF_IOENABLE1_V 0x1
|
||||
#define HINF_IOENABLE1_S 11
|
||||
/* HINF_EMP : RO ;bitpos:[10] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define HINF_EMP (BIT(10))
|
||||
#define HINF_EMP_M (BIT(10))
|
||||
#define HINF_EMP_V 0x1
|
||||
#define HINF_EMP_S 10
|
||||
/* HINF_FUNC1_EPS : RO ;bitpos:[9] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define HINF_FUNC1_EPS (BIT(9))
|
||||
#define HINF_FUNC1_EPS_M (BIT(9))
|
||||
#define HINF_FUNC1_EPS_V 0x1
|
||||
#define HINF_FUNC1_EPS_S 9
|
||||
/* HINF_CD_DISABLE : RO ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define HINF_CD_DISABLE (BIT(8))
|
||||
#define HINF_CD_DISABLE_M (BIT(8))
|
||||
#define HINF_CD_DISABLE_V 0x1
|
||||
#define HINF_CD_DISABLE_S 8
|
||||
/* HINF_IOENABLE2 : RO ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define HINF_IOENABLE2 (BIT(7))
|
||||
#define HINF_IOENABLE2_M (BIT(7))
|
||||
#define HINF_IOENABLE2_V 0x1
|
||||
#define HINF_IOENABLE2_S 7
|
||||
/* HINF_SDIO_INT_MASK : R/W ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define HINF_SDIO_INT_MASK (BIT(6))
|
||||
#define HINF_SDIO_INT_MASK_M (BIT(6))
|
||||
#define HINF_SDIO_INT_MASK_V 0x1
|
||||
#define HINF_SDIO_INT_MASK_S 6
|
||||
/* HINF_SDIO_IOREADY2 : R/W ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define HINF_SDIO_IOREADY2 (BIT(5))
|
||||
#define HINF_SDIO_IOREADY2_M (BIT(5))
|
||||
#define HINF_SDIO_IOREADY2_V 0x1
|
||||
#define HINF_SDIO_IOREADY2_S 5
|
||||
/* HINF_SDIO_CD_ENABLE : R/W ;bitpos:[4] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define HINF_SDIO_CD_ENABLE (BIT(4))
|
||||
#define HINF_SDIO_CD_ENABLE_M (BIT(4))
|
||||
#define HINF_SDIO_CD_ENABLE_V 0x1
|
||||
#define HINF_SDIO_CD_ENABLE_S 4
|
||||
/* HINF_HIGHSPEED_MODE : RO ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define HINF_HIGHSPEED_MODE (BIT(3))
|
||||
#define HINF_HIGHSPEED_MODE_M (BIT(3))
|
||||
#define HINF_HIGHSPEED_MODE_V 0x1
|
||||
#define HINF_HIGHSPEED_MODE_S 3
|
||||
/* HINF_HIGHSPEED_ENABLE : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define HINF_HIGHSPEED_ENABLE (BIT(2))
|
||||
#define HINF_HIGHSPEED_ENABLE_M (BIT(2))
|
||||
#define HINF_HIGHSPEED_ENABLE_V 0x1
|
||||
#define HINF_HIGHSPEED_ENABLE_S 2
|
||||
/* HINF_SDIO_IOREADY1 : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define HINF_SDIO_IOREADY1 (BIT(1))
|
||||
#define HINF_SDIO_IOREADY1_M (BIT(1))
|
||||
#define HINF_SDIO_IOREADY1_V 0x1
|
||||
#define HINF_SDIO_IOREADY1_S 1
|
||||
/* HINF_SDIO_ENABLE : R/W ;bitpos:[0] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define HINF_SDIO_ENABLE (BIT(0))
|
||||
#define HINF_SDIO_ENABLE_M (BIT(0))
|
||||
#define HINF_SDIO_ENABLE_V 0x1
|
||||
#define HINF_SDIO_ENABLE_S 0
|
||||
|
||||
#define HINF_CFG_DATA7_REG (DR_REG_HINF_BASE + 0x1C)
|
||||
/* HINF_SDIO_IOREADY0 : R/W ;bitpos:[17] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define HINF_SDIO_IOREADY0 (BIT(17))
|
||||
#define HINF_SDIO_IOREADY0_M (BIT(17))
|
||||
#define HINF_SDIO_IOREADY0_V 0x1
|
||||
#define HINF_SDIO_IOREADY0_S 17
|
||||
/* HINF_SDIO_RST : R/W ;bitpos:[16] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define HINF_SDIO_RST (BIT(16))
|
||||
#define HINF_SDIO_RST_M (BIT(16))
|
||||
#define HINF_SDIO_RST_V 0x1
|
||||
#define HINF_SDIO_RST_S 16
|
||||
/* HINF_CHIP_STATE : R/W ;bitpos:[15:8] ;default: 8'b0 ; */
|
||||
/*description: */
|
||||
#define HINF_CHIP_STATE 0x000000FF
|
||||
#define HINF_CHIP_STATE_M ((HINF_CHIP_STATE_V) << (HINF_CHIP_STATE_S))
|
||||
#define HINF_CHIP_STATE_V 0xFF
|
||||
#define HINF_CHIP_STATE_S 8
|
||||
/* HINF_PIN_STATE : R/W ;bitpos:[7:0] ;default: 8'b0 ; */
|
||||
/*description: */
|
||||
#define HINF_PIN_STATE 0x000000FF
|
||||
#define HINF_PIN_STATE_M ((HINF_PIN_STATE_V) << (HINF_PIN_STATE_S))
|
||||
#define HINF_PIN_STATE_V 0xFF
|
||||
#define HINF_PIN_STATE_S 0
|
||||
|
||||
#define HINF_CIS_CONF0_REG (DR_REG_HINF_BASE + 0x20)
|
||||
/* HINF_CIS_CONF_W0 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
|
||||
/*description: */
|
||||
#define HINF_CIS_CONF_W0 0xFFFFFFFF
|
||||
#define HINF_CIS_CONF_W0_M ((HINF_CIS_CONF_W0_V) << (HINF_CIS_CONF_W0_S))
|
||||
#define HINF_CIS_CONF_W0_V 0xFFFFFFFF
|
||||
#define HINF_CIS_CONF_W0_S 0
|
||||
|
||||
#define HINF_CIS_CONF1_REG (DR_REG_HINF_BASE + 0x24)
|
||||
/* HINF_CIS_CONF_W1 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
|
||||
/*description: */
|
||||
#define HINF_CIS_CONF_W1 0xFFFFFFFF
|
||||
#define HINF_CIS_CONF_W1_M ((HINF_CIS_CONF_W1_V) << (HINF_CIS_CONF_W1_S))
|
||||
#define HINF_CIS_CONF_W1_V 0xFFFFFFFF
|
||||
#define HINF_CIS_CONF_W1_S 0
|
||||
|
||||
#define HINF_CIS_CONF2_REG (DR_REG_HINF_BASE + 0x28)
|
||||
/* HINF_CIS_CONF_W2 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
|
||||
/*description: */
|
||||
#define HINF_CIS_CONF_W2 0xFFFFFFFF
|
||||
#define HINF_CIS_CONF_W2_M ((HINF_CIS_CONF_W2_V) << (HINF_CIS_CONF_W2_S))
|
||||
#define HINF_CIS_CONF_W2_V 0xFFFFFFFF
|
||||
#define HINF_CIS_CONF_W2_S 0
|
||||
|
||||
#define HINF_CIS_CONF3_REG (DR_REG_HINF_BASE + 0x2C)
|
||||
/* HINF_CIS_CONF_W3 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
|
||||
/*description: */
|
||||
#define HINF_CIS_CONF_W3 0xFFFFFFFF
|
||||
#define HINF_CIS_CONF_W3_M ((HINF_CIS_CONF_W3_V) << (HINF_CIS_CONF_W3_S))
|
||||
#define HINF_CIS_CONF_W3_V 0xFFFFFFFF
|
||||
#define HINF_CIS_CONF_W3_S 0
|
||||
|
||||
#define HINF_CIS_CONF4_REG (DR_REG_HINF_BASE + 0x30)
|
||||
/* HINF_CIS_CONF_W4 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
|
||||
/*description: */
|
||||
#define HINF_CIS_CONF_W4 0xFFFFFFFF
|
||||
#define HINF_CIS_CONF_W4_M ((HINF_CIS_CONF_W4_V) << (HINF_CIS_CONF_W4_S))
|
||||
#define HINF_CIS_CONF_W4_V 0xFFFFFFFF
|
||||
#define HINF_CIS_CONF_W4_S 0
|
||||
|
||||
#define HINF_CIS_CONF5_REG (DR_REG_HINF_BASE + 0x34)
|
||||
/* HINF_CIS_CONF_W5 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
|
||||
/*description: */
|
||||
#define HINF_CIS_CONF_W5 0xFFFFFFFF
|
||||
#define HINF_CIS_CONF_W5_M ((HINF_CIS_CONF_W5_V) << (HINF_CIS_CONF_W5_S))
|
||||
#define HINF_CIS_CONF_W5_V 0xFFFFFFFF
|
||||
#define HINF_CIS_CONF_W5_S 0
|
||||
|
||||
#define HINF_CIS_CONF6_REG (DR_REG_HINF_BASE + 0x38)
|
||||
/* HINF_CIS_CONF_W6 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
|
||||
/*description: */
|
||||
#define HINF_CIS_CONF_W6 0xFFFFFFFF
|
||||
#define HINF_CIS_CONF_W6_M ((HINF_CIS_CONF_W6_V) << (HINF_CIS_CONF_W6_S))
|
||||
#define HINF_CIS_CONF_W6_V 0xFFFFFFFF
|
||||
#define HINF_CIS_CONF_W6_S 0
|
||||
|
||||
#define HINF_CIS_CONF7_REG (DR_REG_HINF_BASE + 0x3C)
|
||||
/* HINF_CIS_CONF_W7 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
|
||||
/*description: */
|
||||
#define HINF_CIS_CONF_W7 0xFFFFFFFF
|
||||
#define HINF_CIS_CONF_W7_M ((HINF_CIS_CONF_W7_V) << (HINF_CIS_CONF_W7_S))
|
||||
#define HINF_CIS_CONF_W7_V 0xFFFFFFFF
|
||||
#define HINF_CIS_CONF_W7_S 0
|
||||
|
||||
#define HINF_CFG_DATA16_REG (DR_REG_HINF_BASE + 0x40)
|
||||
/* HINF_DEVICE_ID_FN2 : R/W ;bitpos:[31:16] ;default: 16'h3333 ; */
|
||||
/*description: */
|
||||
#define HINF_DEVICE_ID_FN2 0x0000FFFF
|
||||
#define HINF_DEVICE_ID_FN2_M ((HINF_DEVICE_ID_FN2_V) << (HINF_DEVICE_ID_FN2_S))
|
||||
#define HINF_DEVICE_ID_FN2_V 0xFFFF
|
||||
#define HINF_DEVICE_ID_FN2_S 16
|
||||
/* HINF_USER_ID_FN2 : R/W ;bitpos:[15:0] ;default: 16'h6666 ; */
|
||||
/*description: */
|
||||
#define HINF_USER_ID_FN2 0x0000FFFF
|
||||
#define HINF_USER_ID_FN2_M ((HINF_USER_ID_FN2_V) << (HINF_USER_ID_FN2_S))
|
||||
#define HINF_USER_ID_FN2_V 0xFFFF
|
||||
#define HINF_USER_ID_FN2_S 0
|
||||
|
||||
#define HINF_DATE_REG (DR_REG_HINF_BASE + 0xFC)
|
||||
/* HINF_SDIO_DATE : R/W ;bitpos:[31:0] ;default: 32'h15030200 ; */
|
||||
/*description: */
|
||||
#define HINF_SDIO_DATE 0xFFFFFFFF
|
||||
#define HINF_SDIO_DATE_M ((HINF_SDIO_DATE_V) << (HINF_SDIO_DATE_S))
|
||||
#define HINF_SDIO_DATE_V 0xFFFFFFFF
|
||||
#define HINF_SDIO_DATE_S 0
|
||||
@@ -1,135 +0,0 @@
|
||||
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef volatile struct hinf_dev_s {
|
||||
union {
|
||||
struct {
|
||||
uint32_t user_id_fn1: 16;
|
||||
uint32_t device_id_fn1: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} cfg_data0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sdio_enable: 1;
|
||||
uint32_t sdio_ioready1: 1;
|
||||
uint32_t highspeed_enable: 1;
|
||||
uint32_t highspeed_mode: 1;
|
||||
uint32_t sdio_cd_enable: 1;
|
||||
uint32_t sdio_ioready2: 1;
|
||||
uint32_t sdio_int_mask: 1;
|
||||
uint32_t ioenable2: 1;
|
||||
uint32_t cd_disable: 1;
|
||||
uint32_t func1_eps: 1;
|
||||
uint32_t emp: 1;
|
||||
uint32_t ioenable1: 1;
|
||||
uint32_t sdio20_conf0: 4;
|
||||
uint32_t sdio_ver: 12;
|
||||
uint32_t func2_eps: 1;
|
||||
uint32_t sdio20_conf1: 3;
|
||||
};
|
||||
uint32_t val;
|
||||
} cfg_data1;
|
||||
uint32_t reserved_8;
|
||||
uint32_t reserved_c;
|
||||
uint32_t reserved_10;
|
||||
uint32_t reserved_14;
|
||||
uint32_t reserved_18;
|
||||
union {
|
||||
struct {
|
||||
uint32_t pin_state: 8;
|
||||
uint32_t chip_state: 8;
|
||||
uint32_t sdio_rst: 1;
|
||||
uint32_t sdio_ioready0: 1;
|
||||
uint32_t reserved18: 14;
|
||||
};
|
||||
uint32_t val;
|
||||
} cfg_data7;
|
||||
uint32_t cis_conf0; /**/
|
||||
uint32_t cis_conf1; /**/
|
||||
uint32_t cis_conf2; /**/
|
||||
uint32_t cis_conf3; /**/
|
||||
uint32_t cis_conf4; /**/
|
||||
uint32_t cis_conf5; /**/
|
||||
uint32_t cis_conf6; /**/
|
||||
uint32_t cis_conf7; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t user_id_fn2: 16;
|
||||
uint32_t device_id_fn2: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} cfg_data16;
|
||||
uint32_t reserved_44;
|
||||
uint32_t reserved_48;
|
||||
uint32_t reserved_4c;
|
||||
uint32_t reserved_50;
|
||||
uint32_t reserved_54;
|
||||
uint32_t reserved_58;
|
||||
uint32_t reserved_5c;
|
||||
uint32_t reserved_60;
|
||||
uint32_t reserved_64;
|
||||
uint32_t reserved_68;
|
||||
uint32_t reserved_6c;
|
||||
uint32_t reserved_70;
|
||||
uint32_t reserved_74;
|
||||
uint32_t reserved_78;
|
||||
uint32_t reserved_7c;
|
||||
uint32_t reserved_80;
|
||||
uint32_t reserved_84;
|
||||
uint32_t reserved_88;
|
||||
uint32_t reserved_8c;
|
||||
uint32_t reserved_90;
|
||||
uint32_t reserved_94;
|
||||
uint32_t reserved_98;
|
||||
uint32_t reserved_9c;
|
||||
uint32_t reserved_a0;
|
||||
uint32_t reserved_a4;
|
||||
uint32_t reserved_a8;
|
||||
uint32_t reserved_ac;
|
||||
uint32_t reserved_b0;
|
||||
uint32_t reserved_b4;
|
||||
uint32_t reserved_b8;
|
||||
uint32_t reserved_bc;
|
||||
uint32_t reserved_c0;
|
||||
uint32_t reserved_c4;
|
||||
uint32_t reserved_c8;
|
||||
uint32_t reserved_cc;
|
||||
uint32_t reserved_d0;
|
||||
uint32_t reserved_d4;
|
||||
uint32_t reserved_d8;
|
||||
uint32_t reserved_dc;
|
||||
uint32_t reserved_e0;
|
||||
uint32_t reserved_e4;
|
||||
uint32_t reserved_e8;
|
||||
uint32_t reserved_ec;
|
||||
uint32_t reserved_f0;
|
||||
uint32_t reserved_f4;
|
||||
uint32_t reserved_f8;
|
||||
uint32_t date; /**/
|
||||
} hinf_dev_t;
|
||||
|
||||
extern hinf_dev_t HINF;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,607 +0,0 @@
|
||||
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_HOST_STRUCT_H_
|
||||
#define _SOC_HOST_STRUCT_H_
|
||||
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct host_dev_s {
|
||||
uint32_t reserved_0;
|
||||
uint32_t reserved_4;
|
||||
uint32_t reserved_8;
|
||||
uint32_t reserved_c;
|
||||
uint32_t reserved_10;
|
||||
uint32_t reserved_14;
|
||||
uint32_t reserved_18;
|
||||
uint32_t reserved_1c;
|
||||
union {
|
||||
struct {
|
||||
uint32_t func1_mdstat : 1;
|
||||
uint32_t reserved1 : 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} func2_2;
|
||||
uint32_t reserved_24;
|
||||
uint32_t reserved_28;
|
||||
uint32_t reserved_2c;
|
||||
uint32_t reserved_30;
|
||||
uint32_t gpio_status0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sdio_int1 : 22;
|
||||
uint32_t reserved22 : 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} gpio_status1;
|
||||
uint32_t gpio_in0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sdio_in1 : 22;
|
||||
uint32_t reserved22 : 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} gpio_in1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t token0 : 12;
|
||||
uint32_t rx_pf_valid : 1;
|
||||
uint32_t reserved13 : 3;
|
||||
uint32_t reg_token1 : 12;
|
||||
uint32_t rx_pf_eof : 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_token_rdata;
|
||||
uint32_t slc0_pf;
|
||||
uint32_t reserved_4c;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tohost_bit0 : 1;
|
||||
uint32_t tohost_bit1 : 1;
|
||||
uint32_t tohost_bit2 : 1;
|
||||
uint32_t tohost_bit3 : 1;
|
||||
uint32_t tohost_bit4 : 1;
|
||||
uint32_t tohost_bit5 : 1;
|
||||
uint32_t tohost_bit6 : 1;
|
||||
uint32_t tohost_bit7 : 1;
|
||||
uint32_t token0_1to0 : 1;
|
||||
uint32_t token1_1to0 : 1;
|
||||
uint32_t token0_0to1 : 1;
|
||||
uint32_t token1_0to1 : 1;
|
||||
uint32_t rx_sof : 1;
|
||||
uint32_t rx_eof : 1;
|
||||
uint32_t rx_start : 1;
|
||||
uint32_t tx_start : 1;
|
||||
uint32_t rx_udf : 1;
|
||||
uint32_t tx_ovf : 1;
|
||||
uint32_t rx_pf_valid : 1;
|
||||
uint32_t ext_bit0 : 1;
|
||||
uint32_t ext_bit1 : 1;
|
||||
uint32_t ext_bit2 : 1;
|
||||
uint32_t ext_bit3 : 1;
|
||||
uint32_t rx_new_packet : 1;
|
||||
uint32_t rd_retry : 1;
|
||||
uint32_t gpio_sdio : 1;
|
||||
uint32_t reserved26 : 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_int_raw;
|
||||
uint32_t reserved_54;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tohost_bit0 : 1;
|
||||
uint32_t tohost_bit1 : 1;
|
||||
uint32_t tohost_bit2 : 1;
|
||||
uint32_t tohost_bit3 : 1;
|
||||
uint32_t tohost_bit4 : 1;
|
||||
uint32_t tohost_bit5 : 1;
|
||||
uint32_t tohost_bit6 : 1;
|
||||
uint32_t tohost_bit7 : 1;
|
||||
uint32_t token0_1to0 : 1;
|
||||
uint32_t token1_1to0 : 1;
|
||||
uint32_t token0_0to1 : 1;
|
||||
uint32_t token1_0to1 : 1;
|
||||
uint32_t rx_sof : 1;
|
||||
uint32_t rx_eof : 1;
|
||||
uint32_t rx_start : 1;
|
||||
uint32_t tx_start : 1;
|
||||
uint32_t rx_udf : 1;
|
||||
uint32_t tx_ovf : 1;
|
||||
uint32_t rx_pf_valid : 1;
|
||||
uint32_t ext_bit0 : 1;
|
||||
uint32_t ext_bit1 : 1;
|
||||
uint32_t ext_bit2 : 1;
|
||||
uint32_t ext_bit3 : 1;
|
||||
uint32_t rx_new_packet : 1;
|
||||
uint32_t rd_retry : 1;
|
||||
uint32_t gpio_sdio : 1;
|
||||
uint32_t reserved26 : 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_int_st;
|
||||
uint32_t reserved_5c;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reg_slc0_len : 20;
|
||||
uint32_t reg_slc0_len_check : 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} pkt_len;
|
||||
union {
|
||||
struct {
|
||||
uint32_t state0 : 8;
|
||||
uint32_t state1 : 8;
|
||||
uint32_t state2 : 8;
|
||||
uint32_t state3 : 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} state_w0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t state4 : 8;
|
||||
uint32_t state5 : 8;
|
||||
uint32_t state6 : 8;
|
||||
uint32_t state7 : 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} state_w1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf0 : 8;
|
||||
uint32_t conf1 : 8;
|
||||
uint32_t conf2 : 8;
|
||||
uint32_t conf3 : 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf4 : 8;
|
||||
uint32_t conf5 : 8;
|
||||
uint32_t conf6 : 8;
|
||||
uint32_t conf7 : 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf8 : 8;
|
||||
uint32_t conf9 : 8;
|
||||
uint32_t conf10 : 8;
|
||||
uint32_t conf11 : 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf12 : 8;
|
||||
uint32_t conf13 : 8;
|
||||
uint32_t conf14 : 8;
|
||||
uint32_t conf15 : 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w3;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf16 : 8; /*SLC timeout value*/
|
||||
uint32_t conf17 : 8; /*SLC timeout enable*/
|
||||
uint32_t conf18 : 8;
|
||||
uint32_t conf19 : 8; /*Interrupt to target CPU*/
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w4;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf20 : 8;
|
||||
uint32_t conf21 : 8;
|
||||
uint32_t conf22 : 8;
|
||||
uint32_t conf23 : 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w5;
|
||||
union {
|
||||
struct {
|
||||
uint32_t win_cmd : 16;
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} win_cmd;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf24 : 8;
|
||||
uint32_t conf25 : 8;
|
||||
uint32_t conf26 : 8;
|
||||
uint32_t conf27 : 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w6;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf28 : 8;
|
||||
uint32_t conf29 : 8;
|
||||
uint32_t conf30 : 8;
|
||||
uint32_t conf31 : 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w7;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reg_slc0_len0 : 20;
|
||||
uint32_t reg_slc0_len0_check : 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} pkt_len0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reg_slc0_len1 : 20;
|
||||
uint32_t reg_slc0_len1_check : 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} pkt_len1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reg_slc0_len2 : 20;
|
||||
uint32_t reg_slc0_len2_check : 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} pkt_len2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf32 : 8;
|
||||
uint32_t conf33 : 8;
|
||||
uint32_t conf34 : 8;
|
||||
uint32_t conf35 : 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w8;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf36 : 8;
|
||||
uint32_t conf37 : 8;
|
||||
uint32_t conf38 : 8;
|
||||
uint32_t conf39 : 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w9;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf40 : 8;
|
||||
uint32_t conf41 : 8;
|
||||
uint32_t conf42 : 8;
|
||||
uint32_t conf43 : 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w10;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf44 : 8;
|
||||
uint32_t conf45 : 8;
|
||||
uint32_t conf46 : 8;
|
||||
uint32_t conf47 : 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w11;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf48 : 8;
|
||||
uint32_t conf49 : 8;
|
||||
uint32_t conf50 : 8;
|
||||
uint32_t conf51 : 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w12;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf52 : 8;
|
||||
uint32_t conf53 : 8;
|
||||
uint32_t conf54 : 8;
|
||||
uint32_t conf55 : 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w13;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf56 : 8;
|
||||
uint32_t conf57 : 8;
|
||||
uint32_t conf58 : 8;
|
||||
uint32_t conf59 : 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w14;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf60 : 8;
|
||||
uint32_t conf61 : 8;
|
||||
uint32_t conf62 : 8;
|
||||
uint32_t conf63 : 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w15;
|
||||
uint32_t check_sum0;
|
||||
uint32_t check_sum1;
|
||||
uint32_t reserved_c4;
|
||||
union {
|
||||
struct {
|
||||
uint32_t token0_wd : 12;
|
||||
uint32_t reserved12 : 4;
|
||||
uint32_t token1_wd : 12;
|
||||
uint32_t reserved28 : 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_token_wdata;
|
||||
uint32_t reserved_cc;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slc0_token0_dec : 1;
|
||||
uint32_t slc0_token1_dec : 1;
|
||||
uint32_t slc0_token0_wr : 1;
|
||||
uint32_t slc0_token1_wr : 1;
|
||||
uint32_t reserved4 : 4;
|
||||
uint32_t slc0_len_wr : 1;
|
||||
uint32_t reserved9 : 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} token_con;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tohost_bit0 : 1;
|
||||
uint32_t tohost_bit1 : 1;
|
||||
uint32_t tohost_bit2 : 1;
|
||||
uint32_t tohost_bit3 : 1;
|
||||
uint32_t tohost_bit4 : 1;
|
||||
uint32_t tohost_bit5 : 1;
|
||||
uint32_t tohost_bit6 : 1;
|
||||
uint32_t tohost_bit7 : 1;
|
||||
uint32_t token0_1to0 : 1;
|
||||
uint32_t token1_1to0 : 1;
|
||||
uint32_t token0_0to1 : 1;
|
||||
uint32_t token1_0to1 : 1;
|
||||
uint32_t rx_sof : 1;
|
||||
uint32_t rx_eof : 1;
|
||||
uint32_t rx_start : 1;
|
||||
uint32_t tx_start : 1;
|
||||
uint32_t rx_udf : 1;
|
||||
uint32_t tx_ovf : 1;
|
||||
uint32_t rx_pf_valid : 1;
|
||||
uint32_t ext_bit0 : 1;
|
||||
uint32_t ext_bit1 : 1;
|
||||
uint32_t ext_bit2 : 1;
|
||||
uint32_t ext_bit3 : 1;
|
||||
uint32_t rx_new_packet : 1;
|
||||
uint32_t rd_retry : 1;
|
||||
uint32_t gpio_sdio : 1;
|
||||
uint32_t reserved26 : 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_int_clr;
|
||||
uint32_t reserved_d8;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tohost_bit0 : 1;
|
||||
uint32_t tohost_bit1 : 1;
|
||||
uint32_t tohost_bit2 : 1;
|
||||
uint32_t tohost_bit3 : 1;
|
||||
uint32_t tohost_bit4 : 1;
|
||||
uint32_t tohost_bit5 : 1;
|
||||
uint32_t tohost_bit6 : 1;
|
||||
uint32_t tohost_bit7 : 1;
|
||||
uint32_t token0_1to0 : 1;
|
||||
uint32_t token1_1to0 : 1;
|
||||
uint32_t token0_0to1 : 1;
|
||||
uint32_t token1_0to1 : 1;
|
||||
uint32_t rx_sof : 1;
|
||||
uint32_t rx_eof : 1;
|
||||
uint32_t rx_start : 1;
|
||||
uint32_t tx_start : 1;
|
||||
uint32_t rx_udf : 1;
|
||||
uint32_t tx_ovf : 1;
|
||||
uint32_t rx_pf_valid : 1;
|
||||
uint32_t ext_bit0 : 1;
|
||||
uint32_t ext_bit1 : 1;
|
||||
uint32_t ext_bit2 : 1;
|
||||
uint32_t ext_bit3 : 1;
|
||||
uint32_t rx_new_packet : 1;
|
||||
uint32_t rd_retry : 1;
|
||||
uint32_t gpio_sdio : 1;
|
||||
uint32_t reserved26 : 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_func1_int_ena;
|
||||
uint32_t reserved_e0;
|
||||
uint32_t reserved_e4;
|
||||
uint32_t reserved_e8;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tohost_bit0 : 1;
|
||||
uint32_t tohost_bit1 : 1;
|
||||
uint32_t tohost_bit2 : 1;
|
||||
uint32_t tohost_bit3 : 1;
|
||||
uint32_t tohost_bit4 : 1;
|
||||
uint32_t tohost_bit5 : 1;
|
||||
uint32_t tohost_bit6 : 1;
|
||||
uint32_t tohost_bit7 : 1;
|
||||
uint32_t token0_1to0 : 1;
|
||||
uint32_t token1_1to0 : 1;
|
||||
uint32_t token0_0to1 : 1;
|
||||
uint32_t token1_0to1 : 1;
|
||||
uint32_t rx_sof : 1;
|
||||
uint32_t rx_eof : 1;
|
||||
uint32_t rx_start : 1;
|
||||
uint32_t tx_start : 1;
|
||||
uint32_t rx_udf : 1;
|
||||
uint32_t tx_ovf : 1;
|
||||
uint32_t rx_pf_valid : 1;
|
||||
uint32_t ext_bit0 : 1;
|
||||
uint32_t ext_bit1 : 1;
|
||||
uint32_t ext_bit2 : 1;
|
||||
uint32_t ext_bit3 : 1;
|
||||
uint32_t rx_new_packet : 1;
|
||||
uint32_t rd_retry : 1;
|
||||
uint32_t gpio_sdio : 1;
|
||||
uint32_t reserved26 : 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_int_ena;
|
||||
uint32_t reserved_f0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t infor : 20;
|
||||
uint32_t reserved20 : 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_rx_infor;
|
||||
uint32_t reserved_f8;
|
||||
uint32_t slc0_len_wd;
|
||||
uint32_t apbwin_wdata;
|
||||
union {
|
||||
struct {
|
||||
uint32_t addr : 28;
|
||||
uint32_t wr : 1;
|
||||
uint32_t start : 1;
|
||||
uint32_t bus : 1;
|
||||
uint32_t reserved31 : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} apbwin_conf;
|
||||
uint32_t apbwin_rdata;
|
||||
union {
|
||||
struct {
|
||||
uint32_t bit7_clraddr : 9;
|
||||
uint32_t bit6_clraddr : 9;
|
||||
uint32_t reserved18 : 14;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_rdclr;
|
||||
uint32_t reserved_110;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tohost_bit01 : 1;
|
||||
uint32_t tohost_bit11 : 1;
|
||||
uint32_t tohost_bit21 : 1;
|
||||
uint32_t tohost_bit31 : 1;
|
||||
uint32_t tohost_bit41 : 1;
|
||||
uint32_t tohost_bit51 : 1;
|
||||
uint32_t tohost_bit61 : 1;
|
||||
uint32_t tohost_bit71 : 1;
|
||||
uint32_t token0_1to01 : 1;
|
||||
uint32_t token1_1to01 : 1;
|
||||
uint32_t token0_0to11 : 1;
|
||||
uint32_t token1_0to11 : 1;
|
||||
uint32_t rx_sof1 : 1;
|
||||
uint32_t rx_eof1 : 1;
|
||||
uint32_t rx_start1 : 1;
|
||||
uint32_t tx_start1 : 1;
|
||||
uint32_t rx_udf1 : 1;
|
||||
uint32_t tx_ovf1 : 1;
|
||||
uint32_t rx_pf_valid1 : 1;
|
||||
uint32_t ext_bit01 : 1;
|
||||
uint32_t ext_bit11 : 1;
|
||||
uint32_t ext_bit21 : 1;
|
||||
uint32_t ext_bit31 : 1;
|
||||
uint32_t rx_new_packet1 : 1;
|
||||
uint32_t rd_retry1 : 1;
|
||||
uint32_t gpio_sdio1 : 1;
|
||||
uint32_t reserved26 : 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_int_ena1;
|
||||
uint32_t reserved_118;
|
||||
uint32_t reserved_11c;
|
||||
uint32_t reserved_120;
|
||||
uint32_t reserved_124;
|
||||
uint32_t reserved_128;
|
||||
uint32_t reserved_12c;
|
||||
uint32_t reserved_130;
|
||||
uint32_t reserved_134;
|
||||
uint32_t reserved_138;
|
||||
uint32_t reserved_13c;
|
||||
uint32_t reserved_140;
|
||||
uint32_t reserved_144;
|
||||
uint32_t reserved_148;
|
||||
uint32_t reserved_14c;
|
||||
uint32_t reserved_150;
|
||||
uint32_t reserved_154;
|
||||
uint32_t reserved_158;
|
||||
uint32_t reserved_15c;
|
||||
uint32_t reserved_160;
|
||||
uint32_t reserved_164;
|
||||
uint32_t reserved_168;
|
||||
uint32_t reserved_16c;
|
||||
uint32_t reserved_170;
|
||||
uint32_t reserved_174;
|
||||
uint32_t date;
|
||||
uint32_t id;
|
||||
uint32_t reserved_180;
|
||||
uint32_t reserved_184;
|
||||
uint32_t reserved_188;
|
||||
uint32_t reserved_18c;
|
||||
uint32_t reserved_190;
|
||||
uint32_t reserved_194;
|
||||
uint32_t reserved_198;
|
||||
uint32_t reserved_19c;
|
||||
uint32_t reserved_1a0;
|
||||
uint32_t reserved_1a4;
|
||||
uint32_t reserved_1a8;
|
||||
uint32_t reserved_1ac;
|
||||
uint32_t reserved_1b0;
|
||||
uint32_t reserved_1b4;
|
||||
uint32_t reserved_1b8;
|
||||
uint32_t reserved_1bc;
|
||||
uint32_t reserved_1c0;
|
||||
uint32_t reserved_1c4;
|
||||
uint32_t reserved_1c8;
|
||||
uint32_t reserved_1cc;
|
||||
uint32_t reserved_1d0;
|
||||
uint32_t reserved_1d4;
|
||||
uint32_t reserved_1d8;
|
||||
uint32_t reserved_1dc;
|
||||
uint32_t reserved_1e0;
|
||||
uint32_t reserved_1e4;
|
||||
uint32_t reserved_1e8;
|
||||
uint32_t reserved_1ec;
|
||||
union {
|
||||
struct {
|
||||
uint32_t frc_sdio11 : 5;
|
||||
uint32_t frc_sdio20 : 5;
|
||||
uint32_t frc_neg_samp : 5;
|
||||
uint32_t frc_pos_samp : 5;
|
||||
uint32_t frc_quick_in : 5;
|
||||
uint32_t sdio20_int_delay : 1;
|
||||
uint32_t sdio_pad_pullup : 1;
|
||||
uint32_t hspeed_con_en : 1;
|
||||
uint32_t reserved28 : 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sdio20_mode : 5;
|
||||
uint32_t sdio_neg_samp : 5;
|
||||
uint32_t sdio_quick_in : 5;
|
||||
uint32_t reserved15 : 17;
|
||||
};
|
||||
uint32_t val;
|
||||
} inf_st;
|
||||
} host_dev_t;
|
||||
extern host_dev_t HOST;
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /*_SOC_HOST_STRUCT_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,988 +0,0 @@
|
||||
/** Copyright 2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Group: Timing registers */
|
||||
/** Type of scl_low_period register
|
||||
* Configures the low level width of the SCL
|
||||
* Clock
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** scl_low_period : R/W; bitpos: [8:0]; default: 0;
|
||||
* This register is used to configure for how long SCL remains low in master mode, in
|
||||
* I2C module clock cycles.
|
||||
*/
|
||||
uint32_t scl_low_period:9;
|
||||
uint32_t reserved_9:23;
|
||||
};
|
||||
uint32_t val;
|
||||
} i2c_scl_low_period_reg_t;
|
||||
|
||||
/** Type of sda_hold register
|
||||
* Configures the hold time after a negative SCL edge.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sda_hold_time : R/W; bitpos: [8:0]; default: 0;
|
||||
* This register is used to configure the time to hold the data after the negative
|
||||
* edge of SCL, in I2C module clock cycles.
|
||||
*/
|
||||
uint32_t sda_hold_time:9;
|
||||
uint32_t reserved_9:23;
|
||||
};
|
||||
uint32_t val;
|
||||
} i2c_sda_hold_reg_t;
|
||||
|
||||
/** Type of sda_sample register
|
||||
* Configures the sample time after a positive SCL edge.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sda_sample_time : R/W; bitpos: [8:0]; default: 0;
|
||||
* This register is used to configure for how long SDA is sampled, in I2C module clock
|
||||
* cycles.
|
||||
*/
|
||||
uint32_t sda_sample_time:9;
|
||||
uint32_t reserved_9:23;
|
||||
};
|
||||
uint32_t val;
|
||||
} i2c_sda_sample_reg_t;
|
||||
|
||||
/** Type of scl_high_period register
|
||||
* Configures the high level width of SCL
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** scl_high_period : R/W; bitpos: [8:0]; default: 0;
|
||||
* This register is used to configure for how long SCL remains high in master mode, in
|
||||
* I2C module clock cycles.
|
||||
*/
|
||||
uint32_t scl_high_period:9;
|
||||
/** scl_wait_high_period : R/W; bitpos: [15:9]; default: 0;
|
||||
* This register is used to configure for the SCL_FSM's waiting period for SCL high
|
||||
* level in master mode, in I2C module clock cycles.
|
||||
*/
|
||||
uint32_t scl_wait_high_period:7;
|
||||
uint32_t reserved_16:16;
|
||||
};
|
||||
uint32_t val;
|
||||
} i2c_scl_high_period_reg_t;
|
||||
|
||||
/** Type of scl_start_hold register
|
||||
* Configures the delay between the SDA and SCL negative edge for a start condition
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** scl_start_hold_time : R/W; bitpos: [8:0]; default: 8;
|
||||
* This register is used to configure the time between the negative edge
|
||||
* of SDA and the negative edge of SCL for a START condition, in I2C module clock
|
||||
* cycles.
|
||||
*/
|
||||
uint32_t scl_start_hold_time:9;
|
||||
uint32_t reserved_9:23;
|
||||
};
|
||||
uint32_t val;
|
||||
} i2c_scl_start_hold_reg_t;
|
||||
|
||||
/** Type of scl_rstart_setup register
|
||||
* Configures the delay between the positive
|
||||
* edge of SCL and the negative edge of SDA
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** scl_rstart_setup_time : R/W; bitpos: [8:0]; default: 8;
|
||||
* This register is used to configure the time between the positive
|
||||
* edge of SCL and the negative edge of SDA for a RESTART condition, in I2C module
|
||||
* clock cycles.
|
||||
*/
|
||||
uint32_t scl_rstart_setup_time:9;
|
||||
uint32_t reserved_9:23;
|
||||
};
|
||||
uint32_t val;
|
||||
} i2c_scl_rstart_setup_reg_t;
|
||||
|
||||
/** Type of scl_stop_hold register
|
||||
* Configures the delay after the SCL clock
|
||||
* edge for a stop condition
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** scl_stop_hold_time : R/W; bitpos: [8:0]; default: 8;
|
||||
* This register is used to configure the delay after the STOP condition,
|
||||
* in I2C module clock cycles.
|
||||
*/
|
||||
uint32_t scl_stop_hold_time:9;
|
||||
uint32_t reserved_9:23;
|
||||
};
|
||||
uint32_t val;
|
||||
} i2c_scl_stop_hold_reg_t;
|
||||
|
||||
/** Type of scl_stop_setup register
|
||||
* Configures the delay between the SDA and
|
||||
* SCL positive edge for a stop condition
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** scl_stop_setup_time : R/W; bitpos: [8:0]; default: 8;
|
||||
* This register is used to configure the time between the positive edge
|
||||
* of SCL and the positive edge of SDA, in I2C module clock cycles.
|
||||
*/
|
||||
uint32_t scl_stop_setup_time:9;
|
||||
uint32_t reserved_9:23;
|
||||
};
|
||||
uint32_t val;
|
||||
} i2c_scl_stop_setup_reg_t;
|
||||
|
||||
/** Type of scl_st_time_out register
|
||||
* SCL status time out register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** scl_st_to_i2c : R/W; bitpos: [4:0]; default: 16;
|
||||
* The threshold value of SCL_FSM state unchanged period. It should be o more than 23
|
||||
*/
|
||||
uint32_t scl_st_to_i2c:5;
|
||||
uint32_t reserved_5:27;
|
||||
};
|
||||
uint32_t val;
|
||||
} i2c_scl_st_time_out_reg_t;
|
||||
|
||||
/** Type of scl_main_st_time_out register
|
||||
* SCL main status time out register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** scl_main_st_to_i2c : R/W; bitpos: [4:0]; default: 16;
|
||||
* The threshold value of SCL_MAIN_FSM state unchanged period.nIt should be o more
|
||||
* than 23
|
||||
*/
|
||||
uint32_t scl_main_st_to_i2c:5;
|
||||
uint32_t reserved_5:27;
|
||||
};
|
||||
uint32_t val;
|
||||
} i2c_scl_main_st_time_out_reg_t;
|
||||
|
||||
|
||||
/** Group: Configuration registers */
|
||||
/** Type of ctr register
|
||||
* Transmission setting
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sda_force_out : R/W; bitpos: [0]; default: 1;
|
||||
* 0: direct output; 1: open drain output.
|
||||
*/
|
||||
uint32_t sda_force_out:1;
|
||||
/** scl_force_out : R/W; bitpos: [1]; default: 1;
|
||||
* 0: direct output; 1: open drain output.
|
||||
*/
|
||||
uint32_t scl_force_out:1;
|
||||
/** sample_scl_level : R/W; bitpos: [2]; default: 0;
|
||||
* This register is used to select the sample mode.
|
||||
* 1: sample SDA data on the SCL low level.
|
||||
* 0: sample SDA data on the SCL high level.
|
||||
*/
|
||||
uint32_t sample_scl_level:1;
|
||||
/** rx_full_ack_level : R/W; bitpos: [3]; default: 1;
|
||||
* This register is used to configure the ACK value that need to sent by master when
|
||||
* the rx_fifo_cnt has reached the threshold.
|
||||
*/
|
||||
uint32_t rx_full_ack_level:1;
|
||||
/** ms_mode : R/W; bitpos: [4]; default: 0;
|
||||
* Set this bit to configure the module as an I2C Master. Clear this bit to configure
|
||||
* the
|
||||
* module as an I2C Slave.
|
||||
*/
|
||||
uint32_t ms_mode:1;
|
||||
/** trans_start : WT; bitpos: [5]; default: 0;
|
||||
* Set this bit to start sending the data in txfifo.
|
||||
*/
|
||||
uint32_t trans_start:1;
|
||||
/** tx_lsb_first : R/W; bitpos: [6]; default: 0;
|
||||
* This bit is used to control the sending mode for data needing to be sent.
|
||||
* 1: send data from the least significant bit;
|
||||
* 0: send data from the most significant bit.
|
||||
*/
|
||||
uint32_t tx_lsb_first:1;
|
||||
/** rx_lsb_first : R/W; bitpos: [7]; default: 0;
|
||||
* This bit is used to control the storage mode for received data.
|
||||
* 1: receive data from the least significant bit;
|
||||
* 0: receive data from the most significant bit.
|
||||
*/
|
||||
uint32_t rx_lsb_first:1;
|
||||
/** clk_en : R/W; bitpos: [8]; default: 0;
|
||||
* Reserved
|
||||
*/
|
||||
uint32_t clk_en:1;
|
||||
/** arbitration_en : R/W; bitpos: [9]; default: 1;
|
||||
* This is the enable bit for arbitration_lost.
|
||||
*/
|
||||
uint32_t arbitration_en:1;
|
||||
/** fsm_rst : WT; bitpos: [10]; default: 0;
|
||||
* This register is used to reset the scl FMS.
|
||||
*/
|
||||
uint32_t fsm_rst:1;
|
||||
/** conf_upgate : WT; bitpos: [11]; default: 0;
|
||||
* synchronization bit
|
||||
*/
|
||||
uint32_t conf_upgate:1;
|
||||
/** slv_tx_auto_start_en : R/W; bitpos: [12]; default: 0;
|
||||
* This is the enable bit for slave to send data automatically
|
||||
*/
|
||||
uint32_t slv_tx_auto_start_en:1;
|
||||
/** addr_10bit_rw_check_en : R/W; bitpos: [13]; default: 0;
|
||||
* This is the enable bit to check if the r/w bit of 10bit addressing consists with
|
||||
* I2C protocol
|
||||
*/
|
||||
uint32_t addr_10bit_rw_check_en:1;
|
||||
/** addr_broadcasting_en : R/W; bitpos: [14]; default: 0;
|
||||
* This is the enable bit to support the 7bit general call function.
|
||||
*/
|
||||
uint32_t addr_broadcasting_en:1;
|
||||
uint32_t reserved_15:17;
|
||||
};
|
||||
uint32_t val;
|
||||
} i2c_ctr_reg_t;
|
||||
|
||||
/** Type of to register
|
||||
* Setting time out control for receiving data.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** time_out_value : R/W; bitpos: [4:0]; default: 16;
|
||||
* This register is used to configure the timeout for receiving a data bit in APB
|
||||
* clock cycles.
|
||||
*/
|
||||
uint32_t time_out_value:5;
|
||||
/** time_out_en : R/W; bitpos: [5]; default: 0;
|
||||
* This is the enable bit for time out control.
|
||||
*/
|
||||
uint32_t time_out_en:1;
|
||||
uint32_t reserved_6:26;
|
||||
};
|
||||
uint32_t val;
|
||||
} i2c_to_reg_t;
|
||||
|
||||
/** Type of slave_addr register
|
||||
* Local slave address setting
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** slave_addr : R/W; bitpos: [14:0]; default: 0;
|
||||
* When configured as an I2C Slave, this field is used to configure the slave address.
|
||||
*/
|
||||
uint32_t slave_addr:15;
|
||||
uint32_t reserved_15:16;
|
||||
/** addr_10bit_en : R/W; bitpos: [31]; default: 0;
|
||||
* This field is used to enable the slave 10-bit addressing mode in master mode.
|
||||
*/
|
||||
uint32_t addr_10bit_en:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} i2c_slave_addr_reg_t;
|
||||
|
||||
/** Type of fifo_conf register
|
||||
* FIFO configuration register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** rxfifo_wm_thrhd : R/W; bitpos: [4:0]; default: 11;
|
||||
* The water mark threshold of rx FIFO in nonfifo access mode. When
|
||||
* reg_reg_fifo_prt_en is 1 and rx FIFO counter is bigger than
|
||||
* reg_rxfifo_wm_thrhd[4:0], reg_rxfifo_wm_int_raw bit will be valid.
|
||||
*/
|
||||
uint32_t rxfifo_wm_thrhd:5;
|
||||
/** txfifo_wm_thrhd : R/W; bitpos: [9:5]; default: 4;
|
||||
* The water mark threshold of tx FIFO in nonfifo access mode. When
|
||||
* reg_reg_fifo_prt_en is 1 and tx FIFO counter is smaller than
|
||||
* reg_txfifo_wm_thrhd[4:0], reg_txfifo_wm_int_raw bit will be valid.
|
||||
*/
|
||||
uint32_t txfifo_wm_thrhd:5;
|
||||
/** nonfifo_en : R/W; bitpos: [10]; default: 0;
|
||||
* Set this bit to enable APB nonfifo access.
|
||||
*/
|
||||
uint32_t nonfifo_en:1;
|
||||
/** fifo_addr_cfg_en : R/W; bitpos: [11]; default: 0;
|
||||
* When this bit is set to 1, the byte received after the I2C address byte represents
|
||||
* the offset address in the I2C Slave RAM.
|
||||
*/
|
||||
uint32_t fifo_addr_cfg_en:1;
|
||||
/** rx_fifo_rst : R/W; bitpos: [12]; default: 0;
|
||||
* Set this bit to reset rx-fifo.
|
||||
*/
|
||||
uint32_t rx_fifo_rst:1;
|
||||
/** tx_fifo_rst : R/W; bitpos: [13]; default: 0;
|
||||
* Set this bit to reset tx-fifo.
|
||||
*/
|
||||
uint32_t tx_fifo_rst:1;
|
||||
/** fifo_prt_en : R/W; bitpos: [14]; default: 1;
|
||||
* The control enable bit of FIFO pointer in non-fifo access mode. This bit controls
|
||||
* the valid bits and the interrupts of tx/rx_fifo overflow, underflow, full and empty.
|
||||
*/
|
||||
uint32_t fifo_prt_en:1;
|
||||
uint32_t reserved_15:17;
|
||||
};
|
||||
uint32_t val;
|
||||
} i2c_fifo_conf_reg_t;
|
||||
|
||||
/** Type of filter_cfg register
|
||||
* SCL and SDA filter configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** scl_filter_thres : R/W; bitpos: [3:0]; default: 0;
|
||||
* When a pulse on the SCL input has smaller width than this register value
|
||||
* in I2C module clock cycles, the I2C controller will ignore that pulse.
|
||||
*/
|
||||
uint32_t scl_filter_thres:4;
|
||||
/** sda_filter_thres : R/W; bitpos: [7:4]; default: 0;
|
||||
* When a pulse on the SDA input has smaller width than this register value
|
||||
* in I2C module clock cycles, the I2C controller will ignore that pulse.
|
||||
*/
|
||||
uint32_t sda_filter_thres:4;
|
||||
/** scl_filter_en : R/W; bitpos: [8]; default: 1;
|
||||
* This is the filter enable bit for SCL.
|
||||
*/
|
||||
uint32_t scl_filter_en:1;
|
||||
/** sda_filter_en : R/W; bitpos: [9]; default: 1;
|
||||
* This is the filter enable bit for SDA.
|
||||
*/
|
||||
uint32_t sda_filter_en:1;
|
||||
uint32_t reserved_10:22;
|
||||
};
|
||||
uint32_t val;
|
||||
} i2c_filter_cfg_reg_t;
|
||||
|
||||
/** Type of clk_conf register
|
||||
* I2C CLK configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** sclk_div_num : R/W; bitpos: [7:0]; default: 0;
|
||||
* the integral part of the fractional divisor for i2c module
|
||||
*/
|
||||
uint32_t sclk_div_num:8;
|
||||
/** sclk_div_a : R/W; bitpos: [13:8]; default: 0;
|
||||
* the numerator of the fractional part of the fractional divisor for i2c module
|
||||
*/
|
||||
uint32_t sclk_div_a:6;
|
||||
/** sclk_div_b : R/W; bitpos: [19:14]; default: 0;
|
||||
* the denominator of the fractional part of the fractional divisor for i2c module
|
||||
*/
|
||||
uint32_t sclk_div_b:6;
|
||||
/** sclk_sel : R/W; bitpos: [20]; default: 0;
|
||||
* The clock selection for i2c module:0-XTAL;1-CLK_8MHz.
|
||||
*/
|
||||
uint32_t sclk_sel:1;
|
||||
/** sclk_active : R/W; bitpos: [21]; default: 1;
|
||||
* The clock switch for i2c module
|
||||
*/
|
||||
uint32_t sclk_active:1;
|
||||
uint32_t reserved_22:10;
|
||||
};
|
||||
uint32_t val;
|
||||
} i2c_clk_conf_reg_t;
|
||||
|
||||
/** Type of scl_sp_conf register
|
||||
* Power configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** scl_rst_slv_en : R/W/SC; bitpos: [0]; default: 0;
|
||||
* When I2C master is IDLE, set this bit to send out SCL pulses. The number of pulses
|
||||
* equals to reg_scl_rst_slv_num[4:0].
|
||||
*/
|
||||
uint32_t scl_rst_slv_en:1;
|
||||
/** scl_rst_slv_num : R/W; bitpos: [5:1]; default: 0;
|
||||
* Configure the pulses of SCL generated in I2C master mode. Valid when
|
||||
* reg_scl_rst_slv_en is 1.
|
||||
*/
|
||||
uint32_t scl_rst_slv_num:5;
|
||||
/** scl_pd_en : R/W; bitpos: [6]; default: 0;
|
||||
* The power down enable bit for the I2C output SCL line. 1: Power down. 0: Not power
|
||||
* down. Set reg_scl_force_out and reg_scl_pd_en to 1 to stretch SCL low.
|
||||
*/
|
||||
uint32_t scl_pd_en:1;
|
||||
/** sda_pd_en : R/W; bitpos: [7]; default: 0;
|
||||
* The power down enable bit for the I2C output SDA line. 1: Power down. 0: Not power
|
||||
* down. Set reg_sda_force_out and reg_sda_pd_en to 1 to stretch SDA low.
|
||||
*/
|
||||
uint32_t sda_pd_en:1;
|
||||
uint32_t reserved_8:24;
|
||||
};
|
||||
uint32_t val;
|
||||
} i2c_scl_sp_conf_reg_t;
|
||||
|
||||
/** Type of scl_stretch_conf register
|
||||
* Set SCL stretch of I2C slave
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** stretch_protect_num : R/W; bitpos: [9:0]; default: 0;
|
||||
* Configure the period of I2C slave stretching SCL line.
|
||||
*/
|
||||
uint32_t stretch_protect_num:10;
|
||||
/** slave_scl_stretch_en : R/W; bitpos: [10]; default: 0;
|
||||
* The enable bit for slave SCL stretch function. 1: Enable. 0: Disable. The SCL
|
||||
* output line will be stretched low when reg_slave_scl_stretch_en is 1 and stretch
|
||||
* event happens. The stretch cause can be seen in reg_stretch_cause.
|
||||
*/
|
||||
uint32_t slave_scl_stretch_en:1;
|
||||
/** slave_scl_stretch_clr : WT; bitpos: [11]; default: 0;
|
||||
* Set this bit to clear the I2C slave SCL stretch function.
|
||||
*/
|
||||
uint32_t slave_scl_stretch_clr:1;
|
||||
/** slave_byte_ack_ctl_en : R/W; bitpos: [12]; default: 0;
|
||||
* The enable bit for slave to control ACK level function.
|
||||
*/
|
||||
uint32_t slave_byte_ack_ctl_en:1;
|
||||
/** slave_byte_ack_lvl : R/W; bitpos: [13]; default: 0;
|
||||
* Set the ACK level when slave controlling ACK level function enables.
|
||||
*/
|
||||
uint32_t slave_byte_ack_lvl:1;
|
||||
uint32_t reserved_14:18;
|
||||
};
|
||||
uint32_t val;
|
||||
} i2c_scl_stretch_conf_reg_t;
|
||||
|
||||
|
||||
/** Group: Status registers */
|
||||
/** Type of sr register
|
||||
* Describe I2C work status.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** resp_rec : RO; bitpos: [0]; default: 0;
|
||||
* The received ACK value in master mode or slave mode. 0: ACK, 1: NACK.
|
||||
*/
|
||||
uint32_t resp_rec:1;
|
||||
/** slave_rw : RO; bitpos: [1]; default: 0;
|
||||
* When in slave mode, 1: master reads from slave; 0: master writes to slave.
|
||||
*/
|
||||
uint32_t slave_rw:1;
|
||||
uint32_t reserved_2:1;
|
||||
/** arb_lost : RO; bitpos: [3]; default: 0;
|
||||
* When the I2C controller loses control of SCL line, this register changes to 1.
|
||||
*/
|
||||
uint32_t arb_lost:1;
|
||||
/** bus_busy : RO; bitpos: [4]; default: 0;
|
||||
* 1: the I2C bus is busy transferring data; 0: the I2C bus is in idle state.
|
||||
*/
|
||||
uint32_t bus_busy:1;
|
||||
/** slave_addressed : RO; bitpos: [5]; default: 0;
|
||||
* When configured as an I2C Slave, and the address sent by the master is
|
||||
* equal to the address of the slave, then this bit will be of high level.
|
||||
*/
|
||||
uint32_t slave_addressed:1;
|
||||
uint32_t reserved_6:2;
|
||||
/** rxfifo_cnt : RO; bitpos: [13:8]; default: 0;
|
||||
* This field represents the amount of data needed to be sent.
|
||||
*/
|
||||
uint32_t rxfifo_cnt:6;
|
||||
/** stretch_cause : RO; bitpos: [15:14]; default: 3;
|
||||
* The cause of stretching SCL low in slave mode. 0: stretching SCL low at the
|
||||
* beginning of I2C read data state. 1: stretching SCL low when I2C Tx FIFO is empty
|
||||
* in slave mode. 2: stretching SCL low when I2C Rx FIFO is full in slave mode.
|
||||
*/
|
||||
uint32_t stretch_cause:2;
|
||||
uint32_t reserved_16:2;
|
||||
/** txfifo_cnt : RO; bitpos: [23:18]; default: 0;
|
||||
* This field stores the amount of received data in RAM.
|
||||
*/
|
||||
uint32_t txfifo_cnt:6;
|
||||
/** scl_main_state_last : RO; bitpos: [26:24]; default: 0;
|
||||
* This field indicates the states of the I2C module state machine.
|
||||
* 0: Idle; 1: Address shift; 2: ACK address; 3: Rx data; 4: Tx data; 5: Send ACK; 6:
|
||||
* Wait ACK
|
||||
*/
|
||||
uint32_t scl_main_state_last:3;
|
||||
uint32_t reserved_27:1;
|
||||
/** scl_state_last : RO; bitpos: [30:28]; default: 0;
|
||||
* This field indicates the states of the state machine used to produce SCL.
|
||||
* 0: Idle; 1: Start; 2: Negative edge; 3: Low; 4: Positive edge; 5: High; 6: Stop
|
||||
*/
|
||||
uint32_t scl_state_last:3;
|
||||
uint32_t reserved_31:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} i2c_sr_reg_t;
|
||||
|
||||
/** Type of fifo_st register
|
||||
* FIFO status register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** rxfifo_raddr : RO; bitpos: [4:0]; default: 0;
|
||||
* This is the offset address of the APB reading from rxfifo
|
||||
*/
|
||||
uint32_t rxfifo_raddr:5;
|
||||
/** rxfifo_waddr : RO; bitpos: [9:5]; default: 0;
|
||||
* This is the offset address of i2c module receiving data and writing to rxfifo.
|
||||
*/
|
||||
uint32_t rxfifo_waddr:5;
|
||||
/** txfifo_raddr : RO; bitpos: [14:10]; default: 0;
|
||||
* This is the offset address of i2c module reading from txfifo.
|
||||
*/
|
||||
uint32_t txfifo_raddr:5;
|
||||
/** txfifo_waddr : RO; bitpos: [19:15]; default: 0;
|
||||
* This is the offset address of APB bus writing to txfifo.
|
||||
*/
|
||||
uint32_t txfifo_waddr:5;
|
||||
uint32_t reserved_20:2;
|
||||
/** slave_rw_point : RO; bitpos: [29:22]; default: 0;
|
||||
* The received data in I2C slave mode.
|
||||
*/
|
||||
uint32_t slave_rw_point:8;
|
||||
uint32_t reserved_30:2;
|
||||
};
|
||||
uint32_t val;
|
||||
} i2c_fifo_st_reg_t;
|
||||
|
||||
/** Type of data register
|
||||
* Rx FIFO read data.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** fifo_rdata : RO; bitpos: [7:0]; default: 0;
|
||||
* The value of rx FIFO read data.
|
||||
*/
|
||||
uint32_t fifo_rdata:8;
|
||||
uint32_t reserved_8:24;
|
||||
};
|
||||
uint32_t val;
|
||||
} i2c_data_reg_t;
|
||||
|
||||
|
||||
/** Group: Interrupt registers */
|
||||
/** Type of int_raw register
|
||||
* Raw interrupt status
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** rxfifo_wm_int_raw : R/SS/WTC; bitpos: [0]; default: 0;
|
||||
* The raw interrupt bit for I2C_RXFIFO_WM_INT interrupt.
|
||||
*/
|
||||
uint32_t rxfifo_wm_int_raw:1;
|
||||
/** txfifo_wm_int_raw : R/SS/WTC; bitpos: [1]; default: 1;
|
||||
* The raw interrupt bit for I2C_TXFIFO_WM_INT interrupt.
|
||||
*/
|
||||
uint32_t txfifo_wm_int_raw:1;
|
||||
/** rxfifo_ovf_int_raw : R/SS/WTC; bitpos: [2]; default: 0;
|
||||
* The raw interrupt bit for I2C_RXFIFO_OVF_INT interrupt.
|
||||
*/
|
||||
uint32_t rxfifo_ovf_int_raw:1;
|
||||
/** end_detect_int_raw : R/SS/WTC; bitpos: [3]; default: 0;
|
||||
* The raw interrupt bit for the I2C_END_DETECT_INT interrupt.
|
||||
*/
|
||||
uint32_t end_detect_int_raw:1;
|
||||
/** byte_trans_done_int_raw : R/SS/WTC; bitpos: [4]; default: 0;
|
||||
* The raw interrupt bit for the I2C_END_DETECT_INT interrupt.
|
||||
*/
|
||||
uint32_t byte_trans_done_int_raw:1;
|
||||
/** arbitration_lost_int_raw : R/SS/WTC; bitpos: [5]; default: 0;
|
||||
* The raw interrupt bit for the I2C_ARBITRATION_LOST_INT interrupt.
|
||||
*/
|
||||
uint32_t arbitration_lost_int_raw:1;
|
||||
/** mst_txfifo_udf_int_raw : R/SS/WTC; bitpos: [6]; default: 0;
|
||||
* The raw interrupt bit for I2C_TRANS_COMPLETE_INT interrupt.
|
||||
*/
|
||||
uint32_t mst_txfifo_udf_int_raw:1;
|
||||
/** trans_complete_int_raw : R/SS/WTC; bitpos: [7]; default: 0;
|
||||
* The raw interrupt bit for the I2C_TRANS_COMPLETE_INT interrupt.
|
||||
*/
|
||||
uint32_t trans_complete_int_raw:1;
|
||||
/** time_out_int_raw : R/SS/WTC; bitpos: [8]; default: 0;
|
||||
* The raw interrupt bit for the I2C_TIME_OUT_INT interrupt.
|
||||
*/
|
||||
uint32_t time_out_int_raw:1;
|
||||
/** trans_start_int_raw : R/SS/WTC; bitpos: [9]; default: 0;
|
||||
* The raw interrupt bit for the I2C_TRANS_START_INT interrupt.
|
||||
*/
|
||||
uint32_t trans_start_int_raw:1;
|
||||
/** nack_int_raw : R/SS/WTC; bitpos: [10]; default: 0;
|
||||
* The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt.
|
||||
*/
|
||||
uint32_t nack_int_raw:1;
|
||||
/** txfifo_ovf_int_raw : R/SS/WTC; bitpos: [11]; default: 0;
|
||||
* The raw interrupt bit for I2C_TXFIFO_OVF_INT interrupt.
|
||||
*/
|
||||
uint32_t txfifo_ovf_int_raw:1;
|
||||
/** rxfifo_udf_int_raw : R/SS/WTC; bitpos: [12]; default: 0;
|
||||
* The raw interrupt bit for I2C_RXFIFO_UDF_INT interrupt.
|
||||
*/
|
||||
uint32_t rxfifo_udf_int_raw:1;
|
||||
/** scl_st_to_int_raw : R/SS/WTC; bitpos: [13]; default: 0;
|
||||
* The raw interrupt bit for I2C_SCL_ST_TO_INT interrupt.
|
||||
*/
|
||||
uint32_t scl_st_to_int_raw:1;
|
||||
/** scl_main_st_to_int_raw : R/SS/WTC; bitpos: [14]; default: 0;
|
||||
* The raw interrupt bit for I2C_SCL_MAIN_ST_TO_INT interrupt.
|
||||
*/
|
||||
uint32_t scl_main_st_to_int_raw:1;
|
||||
/** det_start_int_raw : R/SS/WTC; bitpos: [15]; default: 0;
|
||||
* The raw interrupt bit for I2C_DET_START_INT interrupt.
|
||||
*/
|
||||
uint32_t det_start_int_raw:1;
|
||||
/** slave_stretch_int_raw : R/SS/WTC; bitpos: [16]; default: 0;
|
||||
* The raw interrupt bit for I2C_SLAVE_STRETCH_INT interrupt.
|
||||
*/
|
||||
uint32_t slave_stretch_int_raw:1;
|
||||
/** general_call_int_raw : R/SS/WTC; bitpos: [17]; default: 0;
|
||||
* The raw interrupt bit for I2C_GENARAL_CALL_INT interrupt.
|
||||
*/
|
||||
uint32_t general_call_int_raw:1;
|
||||
uint32_t reserved_18:14;
|
||||
};
|
||||
uint32_t val;
|
||||
} i2c_int_raw_reg_t;
|
||||
|
||||
/** Type of int_clr register
|
||||
* Interrupt clear bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** rxfifo_wm_int_clr : WT; bitpos: [0]; default: 0;
|
||||
* Set this bit to clear I2C_RXFIFO_WM_INT interrupt.
|
||||
*/
|
||||
uint32_t rxfifo_wm_int_clr:1;
|
||||
/** txfifo_wm_int_clr : WT; bitpos: [1]; default: 0;
|
||||
* Set this bit to clear I2C_TXFIFO_WM_INT interrupt.
|
||||
*/
|
||||
uint32_t txfifo_wm_int_clr:1;
|
||||
/** rxfifo_ovf_int_clr : WT; bitpos: [2]; default: 0;
|
||||
* Set this bit to clear I2C_RXFIFO_OVF_INT interrupt.
|
||||
*/
|
||||
uint32_t rxfifo_ovf_int_clr:1;
|
||||
/** end_detect_int_clr : WT; bitpos: [3]; default: 0;
|
||||
* Set this bit to clear the I2C_END_DETECT_INT interrupt.
|
||||
*/
|
||||
uint32_t end_detect_int_clr:1;
|
||||
/** byte_trans_done_int_clr : WT; bitpos: [4]; default: 0;
|
||||
* Set this bit to clear the I2C_END_DETECT_INT interrupt.
|
||||
*/
|
||||
uint32_t byte_trans_done_int_clr:1;
|
||||
/** arbitration_lost_int_clr : WT; bitpos: [5]; default: 0;
|
||||
* Set this bit to clear the I2C_ARBITRATION_LOST_INT interrupt.
|
||||
*/
|
||||
uint32_t arbitration_lost_int_clr:1;
|
||||
/** mst_txfifo_udf_int_clr : WT; bitpos: [6]; default: 0;
|
||||
* Set this bit to clear I2C_TRANS_COMPLETE_INT interrupt.
|
||||
*/
|
||||
uint32_t mst_txfifo_udf_int_clr:1;
|
||||
/** trans_complete_int_clr : WT; bitpos: [7]; default: 0;
|
||||
* Set this bit to clear the I2C_TRANS_COMPLETE_INT interrupt.
|
||||
*/
|
||||
uint32_t trans_complete_int_clr:1;
|
||||
/** time_out_int_clr : WT; bitpos: [8]; default: 0;
|
||||
* Set this bit to clear the I2C_TIME_OUT_INT interrupt.
|
||||
*/
|
||||
uint32_t time_out_int_clr:1;
|
||||
/** trans_start_int_clr : WT; bitpos: [9]; default: 0;
|
||||
* Set this bit to clear the I2C_TRANS_START_INT interrupt.
|
||||
*/
|
||||
uint32_t trans_start_int_clr:1;
|
||||
/** nack_int_clr : WT; bitpos: [10]; default: 0;
|
||||
* Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt.
|
||||
*/
|
||||
uint32_t nack_int_clr:1;
|
||||
/** txfifo_ovf_int_clr : WT; bitpos: [11]; default: 0;
|
||||
* Set this bit to clear I2C_TXFIFO_OVF_INT interrupt.
|
||||
*/
|
||||
uint32_t txfifo_ovf_int_clr:1;
|
||||
/** rxfifo_udf_int_clr : WT; bitpos: [12]; default: 0;
|
||||
* Set this bit to clear I2C_RXFIFO_UDF_INT interrupt.
|
||||
*/
|
||||
uint32_t rxfifo_udf_int_clr:1;
|
||||
/** scl_st_to_int_clr : WT; bitpos: [13]; default: 0;
|
||||
* Set this bit to clear I2C_SCL_ST_TO_INT interrupt.
|
||||
*/
|
||||
uint32_t scl_st_to_int_clr:1;
|
||||
/** scl_main_st_to_int_clr : WT; bitpos: [14]; default: 0;
|
||||
* Set this bit to clear I2C_SCL_MAIN_ST_TO_INT interrupt.
|
||||
*/
|
||||
uint32_t scl_main_st_to_int_clr:1;
|
||||
/** det_start_int_clr : WT; bitpos: [15]; default: 0;
|
||||
* Set this bit to clear I2C_DET_START_INT interrupt.
|
||||
*/
|
||||
uint32_t det_start_int_clr:1;
|
||||
/** slave_stretch_int_clr : WT; bitpos: [16]; default: 0;
|
||||
* Set this bit to clear I2C_SLAVE_STRETCH_INT interrupt.
|
||||
*/
|
||||
uint32_t slave_stretch_int_clr:1;
|
||||
/** general_call_int_clr : WT; bitpos: [17]; default: 0;
|
||||
* Set this bit for I2C_GENARAL_CALL_INT interrupt.
|
||||
*/
|
||||
uint32_t general_call_int_clr:1;
|
||||
uint32_t reserved_18:14;
|
||||
};
|
||||
uint32_t val;
|
||||
} i2c_int_clr_reg_t;
|
||||
|
||||
/** Type of int_ena register
|
||||
* Interrupt enable bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** rxfifo_wm_int_ena : R/W; bitpos: [0]; default: 0;
|
||||
* The interrupt enable bit for I2C_RXFIFO_WM_INT interrupt.
|
||||
*/
|
||||
uint32_t rxfifo_wm_int_ena:1;
|
||||
/** txfifo_wm_int_ena : R/W; bitpos: [1]; default: 0;
|
||||
* The interrupt enable bit for I2C_TXFIFO_WM_INT interrupt.
|
||||
*/
|
||||
uint32_t txfifo_wm_int_ena:1;
|
||||
/** rxfifo_ovf_int_ena : R/W; bitpos: [2]; default: 0;
|
||||
* The interrupt enable bit for I2C_RXFIFO_OVF_INT interrupt.
|
||||
*/
|
||||
uint32_t rxfifo_ovf_int_ena:1;
|
||||
/** end_detect_int_ena : R/W; bitpos: [3]; default: 0;
|
||||
* The interrupt enable bit for the I2C_END_DETECT_INT interrupt.
|
||||
*/
|
||||
uint32_t end_detect_int_ena:1;
|
||||
/** byte_trans_done_int_ena : R/W; bitpos: [4]; default: 0;
|
||||
* The interrupt enable bit for the I2C_END_DETECT_INT interrupt.
|
||||
*/
|
||||
uint32_t byte_trans_done_int_ena:1;
|
||||
/** arbitration_lost_int_ena : R/W; bitpos: [5]; default: 0;
|
||||
* The interrupt enable bit for the I2C_ARBITRATION_LOST_INT interrupt.
|
||||
*/
|
||||
uint32_t arbitration_lost_int_ena:1;
|
||||
/** mst_txfifo_udf_int_ena : R/W; bitpos: [6]; default: 0;
|
||||
* The interrupt enable bit for I2C_TRANS_COMPLETE_INT interrupt.
|
||||
*/
|
||||
uint32_t mst_txfifo_udf_int_ena:1;
|
||||
/** trans_complete_int_ena : R/W; bitpos: [7]; default: 0;
|
||||
* The interrupt enable bit for the I2C_TRANS_COMPLETE_INT interrupt.
|
||||
*/
|
||||
uint32_t trans_complete_int_ena:1;
|
||||
/** time_out_int_ena : R/W; bitpos: [8]; default: 0;
|
||||
* The interrupt enable bit for the I2C_TIME_OUT_INT interrupt.
|
||||
*/
|
||||
uint32_t time_out_int_ena:1;
|
||||
/** trans_start_int_ena : R/W; bitpos: [9]; default: 0;
|
||||
* The interrupt enable bit for the I2C_TRANS_START_INT interrupt.
|
||||
*/
|
||||
uint32_t trans_start_int_ena:1;
|
||||
/** nack_int_ena : R/W; bitpos: [10]; default: 0;
|
||||
* The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt.
|
||||
*/
|
||||
uint32_t nack_int_ena:1;
|
||||
/** txfifo_ovf_int_ena : R/W; bitpos: [11]; default: 0;
|
||||
* The interrupt enable bit for I2C_TXFIFO_OVF_INT interrupt.
|
||||
*/
|
||||
uint32_t txfifo_ovf_int_ena:1;
|
||||
/** rxfifo_udf_int_ena : R/W; bitpos: [12]; default: 0;
|
||||
* The interrupt enable bit for I2C_RXFIFO_UDF_INT interrupt.
|
||||
*/
|
||||
uint32_t rxfifo_udf_int_ena:1;
|
||||
/** scl_st_to_int_ena : R/W; bitpos: [13]; default: 0;
|
||||
* The interrupt enable bit for I2C_SCL_ST_TO_INT interrupt.
|
||||
*/
|
||||
uint32_t scl_st_to_int_ena:1;
|
||||
/** scl_main_st_to_int_ena : R/W; bitpos: [14]; default: 0;
|
||||
* The interrupt enable bit for I2C_SCL_MAIN_ST_TO_INT interrupt.
|
||||
*/
|
||||
uint32_t scl_main_st_to_int_ena:1;
|
||||
/** det_start_int_ena : R/W; bitpos: [15]; default: 0;
|
||||
* The interrupt enable bit for I2C_DET_START_INT interrupt.
|
||||
*/
|
||||
uint32_t det_start_int_ena:1;
|
||||
/** slave_stretch_int_ena : R/W; bitpos: [16]; default: 0;
|
||||
* The interrupt enable bit for I2C_SLAVE_STRETCH_INT interrupt.
|
||||
*/
|
||||
uint32_t slave_stretch_int_ena:1;
|
||||
/** general_call_int_ena : R/W; bitpos: [17]; default: 0;
|
||||
* The interrupt enable bit for I2C_GENARAL_CALL_INT interrupt.
|
||||
*/
|
||||
uint32_t general_call_int_ena:1;
|
||||
uint32_t reserved_18:14;
|
||||
};
|
||||
uint32_t val;
|
||||
} i2c_int_ena_reg_t;
|
||||
|
||||
/** Type of int_status register
|
||||
* Status of captured I2C communication events
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** rxfifo_wm_int_st : RO; bitpos: [0]; default: 0;
|
||||
* The masked interrupt status bit for I2C_RXFIFO_WM_INT interrupt.
|
||||
*/
|
||||
uint32_t rxfifo_wm_int_st:1;
|
||||
/** txfifo_wm_int_st : RO; bitpos: [1]; default: 0;
|
||||
* The masked interrupt status bit for I2C_TXFIFO_WM_INT interrupt.
|
||||
*/
|
||||
uint32_t txfifo_wm_int_st:1;
|
||||
/** rxfifo_ovf_int_st : RO; bitpos: [2]; default: 0;
|
||||
* The masked interrupt status bit for I2C_RXFIFO_OVF_INT interrupt.
|
||||
*/
|
||||
uint32_t rxfifo_ovf_int_st:1;
|
||||
/** end_detect_int_st : RO; bitpos: [3]; default: 0;
|
||||
* The masked interrupt status bit for the I2C_END_DETECT_INT interrupt.
|
||||
*/
|
||||
uint32_t end_detect_int_st:1;
|
||||
/** byte_trans_done_int_st : RO; bitpos: [4]; default: 0;
|
||||
* The masked interrupt status bit for the I2C_END_DETECT_INT interrupt.
|
||||
*/
|
||||
uint32_t byte_trans_done_int_st:1;
|
||||
/** arbitration_lost_int_st : RO; bitpos: [5]; default: 0;
|
||||
* The masked interrupt status bit for the I2C_ARBITRATION_LOST_INT interrupt.
|
||||
*/
|
||||
uint32_t arbitration_lost_int_st:1;
|
||||
/** mst_txfifo_udf_int_st : RO; bitpos: [6]; default: 0;
|
||||
* The masked interrupt status bit for I2C_TRANS_COMPLETE_INT interrupt.
|
||||
*/
|
||||
uint32_t mst_txfifo_udf_int_st:1;
|
||||
/** trans_complete_int_st : RO; bitpos: [7]; default: 0;
|
||||
* The masked interrupt status bit for the I2C_TRANS_COMPLETE_INT interrupt.
|
||||
*/
|
||||
uint32_t trans_complete_int_st:1;
|
||||
/** time_out_int_st : RO; bitpos: [8]; default: 0;
|
||||
* The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt.
|
||||
*/
|
||||
uint32_t time_out_int_st:1;
|
||||
/** trans_start_int_st : RO; bitpos: [9]; default: 0;
|
||||
* The masked interrupt status bit for the I2C_TRANS_START_INT interrupt.
|
||||
*/
|
||||
uint32_t trans_start_int_st:1;
|
||||
/** nack_int_st : RO; bitpos: [10]; default: 0;
|
||||
* The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt.
|
||||
*/
|
||||
uint32_t nack_int_st:1;
|
||||
/** txfifo_ovf_int_st : RO; bitpos: [11]; default: 0;
|
||||
* The masked interrupt status bit for I2C_TXFIFO_OVF_INT interrupt.
|
||||
*/
|
||||
uint32_t txfifo_ovf_int_st:1;
|
||||
/** rxfifo_udf_int_st : RO; bitpos: [12]; default: 0;
|
||||
* The masked interrupt status bit for I2C_RXFIFO_UDF_INT interrupt.
|
||||
*/
|
||||
uint32_t rxfifo_udf_int_st:1;
|
||||
/** scl_st_to_int_st : RO; bitpos: [13]; default: 0;
|
||||
* The masked interrupt status bit for I2C_SCL_ST_TO_INT interrupt.
|
||||
*/
|
||||
uint32_t scl_st_to_int_st:1;
|
||||
/** scl_main_st_to_int_st : RO; bitpos: [14]; default: 0;
|
||||
* The masked interrupt status bit for I2C_SCL_MAIN_ST_TO_INT interrupt.
|
||||
*/
|
||||
uint32_t scl_main_st_to_int_st:1;
|
||||
/** det_start_int_st : RO; bitpos: [15]; default: 0;
|
||||
* The masked interrupt status bit for I2C_DET_START_INT interrupt.
|
||||
*/
|
||||
uint32_t det_start_int_st:1;
|
||||
/** slave_stretch_int_st : RO; bitpos: [16]; default: 0;
|
||||
* The masked interrupt status bit for I2C_SLAVE_STRETCH_INT interrupt.
|
||||
*/
|
||||
uint32_t slave_stretch_int_st:1;
|
||||
/** general_call_int_st : RO; bitpos: [17]; default: 0;
|
||||
* The masked interrupt status bit for I2C_GENARAL_CALL_INT interrupt.
|
||||
*/
|
||||
uint32_t general_call_int_st:1;
|
||||
uint32_t reserved_18:14;
|
||||
};
|
||||
uint32_t val;
|
||||
} i2c_int_status_reg_t;
|
||||
|
||||
|
||||
/** Group: Command registers */
|
||||
/** Type of command register
|
||||
* I2C command register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** command0 : R/W; bitpos: [13:0]; default: 0;
|
||||
* This is the content of command 0. It consists of three parts:
|
||||
* op_code is the command, 0: RSTART; 1: WRITE; 2: READ; 3: STOP; 4: END.
|
||||
* Byte_num represents the number of bytes that need to be sent or received.
|
||||
* ack_check_en, ack_exp and ack are used to control the ACK bit. See I2C cmd
|
||||
* structure for more
|
||||
* Information.
|
||||
*/
|
||||
uint32_t command:14;
|
||||
uint32_t reserved_14:17;
|
||||
/** command0_done : R/W/SS; bitpos: [31]; default: 0;
|
||||
* When command 0 is done in I2C Master mode, this bit changes to high
|
||||
* level.
|
||||
*/
|
||||
uint32_t command_done:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} i2c_comd_reg_t;
|
||||
|
||||
|
||||
/** Group: Version register */
|
||||
/** Type of date register
|
||||
* Version register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** date : R/W; bitpos: [31:0]; default: 537330177;
|
||||
* This is the the version register.
|
||||
*/
|
||||
uint32_t date:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} i2c_date_reg_t;
|
||||
|
||||
typedef struct {
|
||||
volatile i2c_scl_low_period_reg_t scl_low_period;
|
||||
volatile i2c_ctr_reg_t ctr;
|
||||
volatile i2c_sr_reg_t sr;
|
||||
volatile i2c_to_reg_t to;
|
||||
volatile i2c_slave_addr_reg_t slave_addr;
|
||||
volatile i2c_fifo_st_reg_t fifo_st;
|
||||
volatile i2c_fifo_conf_reg_t fifo_conf;
|
||||
volatile i2c_data_reg_t data;
|
||||
volatile i2c_int_raw_reg_t int_raw;
|
||||
volatile i2c_int_clr_reg_t int_clr;
|
||||
volatile i2c_int_ena_reg_t int_ena;
|
||||
volatile i2c_int_status_reg_t int_status;
|
||||
volatile i2c_sda_hold_reg_t sda_hold;
|
||||
volatile i2c_sda_sample_reg_t sda_sample;
|
||||
volatile i2c_scl_high_period_reg_t scl_high_period;
|
||||
uint32_t reserved_03c;
|
||||
volatile i2c_scl_start_hold_reg_t scl_start_hold;
|
||||
volatile i2c_scl_rstart_setup_reg_t scl_rstart_setup;
|
||||
volatile i2c_scl_stop_hold_reg_t scl_stop_hold;
|
||||
volatile i2c_scl_stop_setup_reg_t scl_stop_setup;
|
||||
volatile i2c_filter_cfg_reg_t filter_cfg;
|
||||
volatile i2c_clk_conf_reg_t clk_conf;
|
||||
volatile i2c_comd_reg_t comd[8];
|
||||
volatile i2c_scl_st_time_out_reg_t scl_st_time_out;
|
||||
volatile i2c_scl_main_st_time_out_reg_t scl_main_st_time_out;
|
||||
volatile i2c_scl_sp_conf_reg_t scl_sp_conf;
|
||||
volatile i2c_scl_stretch_conf_reg_t scl_stretch_conf;
|
||||
uint32_t reserved_088[28];
|
||||
volatile i2c_date_reg_t date;
|
||||
uint32_t reserved_0fc;
|
||||
volatile uint32_t txfifo_mem[32];
|
||||
volatile uint32_t rxfifo_mem[32];
|
||||
} i2c_dev_t;
|
||||
|
||||
extern i2c_dev_t I2C0;
|
||||
extern i2c_dev_t I2C1;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(i2c_dev_t) == 0x200, "Invalid size of i2c_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,337 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct i2s_dev_s {
|
||||
uint32_t reserved_0;
|
||||
uint32_t reserved_4;
|
||||
uint32_t reserved_8;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_done : 1; /*The raw interrupt status bit for the i2s_rx_done_int interrupt*/
|
||||
uint32_t tx_done : 1; /*The raw interrupt status bit for the i2s_tx_done_int interrupt*/
|
||||
uint32_t rx_hung : 1; /*The raw interrupt status bit for the i2s_rx_hung_int interrupt*/
|
||||
uint32_t tx_hung : 1; /*The raw interrupt status bit for the i2s_tx_hung_int interrupt*/
|
||||
uint32_t reserved4 : 28; /*Reserve*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_done : 1; /*The masked interrupt status bit for the i2s_rx_done_int interrupt*/
|
||||
uint32_t tx_done : 1; /*The masked interrupt status bit for the i2s_tx_done_int interrupt*/
|
||||
uint32_t rx_hung : 1; /*The masked interrupt status bit for the i2s_rx_hung_int interrupt*/
|
||||
uint32_t tx_hung : 1; /*The masked interrupt status bit for the i2s_tx_hung_int interrupt*/
|
||||
uint32_t reserved4 : 28; /*Reserve*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_done : 1; /*The interrupt enable bit for the i2s_rx_done_int interrupt*/
|
||||
uint32_t tx_done : 1; /*The interrupt enable bit for the i2s_tx_done_int interrupt*/
|
||||
uint32_t rx_hung : 1; /*The interrupt enable bit for the i2s_rx_hung_int interrupt*/
|
||||
uint32_t tx_hung : 1; /*The interrupt enable bit for the i2s_tx_hung_int interrupt*/
|
||||
uint32_t reserved4 : 28; /*Reserve*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_done : 1; /*Set this bit to clear the i2s_rx_done_int interrupt*/
|
||||
uint32_t tx_done : 1; /*Set this bit to clear the i2s_tx_done_int interrupt*/
|
||||
uint32_t rx_hung : 1; /*Set this bit to clear the i2s_rx_hung_int interrupt*/
|
||||
uint32_t tx_hung : 1; /*Set this bit to clear the i2s_tx_hung_int interrupt*/
|
||||
uint32_t reserved4 : 28; /*Reserve*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_clr;
|
||||
uint32_t reserved_1c;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_reset : 1; /*Set this bit to reset receiver*/
|
||||
uint32_t rx_fifo_reset : 1; /*Set this bit to reset Rx AFIFO*/
|
||||
uint32_t rx_start : 1; /*Set this bit to start receiving data*/
|
||||
uint32_t rx_slave_mod : 1; /*Set this bit to enable slave receiver mode*/
|
||||
uint32_t reserved4 : 1; /* Reserved*/
|
||||
uint32_t rx_mono : 1; /*Set this bit to enable receiver in mono mode*/
|
||||
uint32_t reserved6 : 1; /*Reserve*/
|
||||
uint32_t rx_big_endian : 1; /*I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.*/
|
||||
uint32_t rx_update : 1; /*Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done.*/
|
||||
uint32_t rx_mono_fst_vld : 1; /*1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode.*/
|
||||
uint32_t rx_pcm_conf : 2; /*I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &*/
|
||||
uint32_t rx_pcm_bypass : 1; /*Set this bit to bypass Compress/Decompress module for received data.*/
|
||||
uint32_t rx_stop_mode : 2; /*0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.*/
|
||||
uint32_t rx_left_align : 1; /*1: I2S RX left alignment mode. 0: I2S RX right alignment mode.*/
|
||||
uint32_t rx_24_fill_en : 1; /*1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.*/
|
||||
uint32_t rx_ws_idle_pol : 1; /*0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel. */
|
||||
uint32_t rx_bit_order : 1; /*I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first.*/
|
||||
uint32_t rx_tdm_en : 1; /*1: Enable I2S TDM Rx mode . 0: Disable.*/
|
||||
uint32_t rx_pdm_en : 1; /*1: Enable I2S PDM Rx mode . 0: Disable.*/
|
||||
uint32_t rx_pdm2pcm_en : 1; /*1: Enable PDM2PCM RX mode. 0: DIsable.*/
|
||||
uint32_t rx_pdm_sinc_dsr_16_en : 1; /*Configure the down sampling rate of PDM RX filter group1 module. 1: The down sampling rate is 128. 0: down sampling rate is 64.*/
|
||||
uint32_t reserved23 : 9; /*Reserve*/
|
||||
};
|
||||
uint32_t val;
|
||||
} rx_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tx_reset : 1; /*Set this bit to reset transmitter*/
|
||||
uint32_t tx_fifo_reset : 1; /*Set this bit to reset Tx AFIFO*/
|
||||
uint32_t tx_start : 1; /*Set this bit to start transmitting data */
|
||||
uint32_t tx_slave_mod : 1; /*Set this bit to enable slave transmitter mode */
|
||||
uint32_t reserved4 : 1; /* Reserved*/
|
||||
uint32_t tx_mono : 1; /*Set this bit to enable transmitter in mono mode */
|
||||
uint32_t tx_chan_equal : 1; /*1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.*/
|
||||
uint32_t tx_big_endian : 1; /*I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.*/
|
||||
uint32_t tx_update : 1; /*Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done.*/
|
||||
uint32_t tx_mono_fst_vld : 1; /*1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode.*/
|
||||
uint32_t tx_pcm_conf : 2; /*I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &*/
|
||||
uint32_t tx_pcm_bypass : 1; /*Set this bit to bypass Compress/Decompress module for transmitted data.*/
|
||||
uint32_t tx_stop_en : 1; /*Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy*/
|
||||
uint32_t reserved14 : 1; /* Reserved*/
|
||||
uint32_t tx_left_align : 1; /*1: I2S TX left alignment mode. 0: I2S TX right alignment mode.*/
|
||||
uint32_t tx_24_fill_en : 1; /*1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode*/
|
||||
uint32_t tx_ws_idle_pol : 1; /*0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel. */
|
||||
uint32_t tx_bit_order : 1; /*I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first.*/
|
||||
uint32_t tx_tdm_en : 1; /*1: Enable I2S TDM Tx mode . 0: Disable.*/
|
||||
uint32_t tx_pdm_en : 1; /*1: Enable I2S PDM Tx mode . 0: Disable.*/
|
||||
uint32_t reserved21 : 3; /*Reserved*/
|
||||
uint32_t tx_chan_mod : 3; /*I2S transmitter channel mode configuration bits.*/
|
||||
uint32_t sig_loopback : 1; /*Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals.*/
|
||||
uint32_t reserved28 : 4; /*Reserve*/
|
||||
};
|
||||
uint32_t val;
|
||||
} tx_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_tdm_ws_width : 7; /* The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck*/
|
||||
uint32_t rx_bck_div_num : 6; /*Bit clock configuration bits in receiver mode. */
|
||||
uint32_t rx_bits_mod : 5; /*Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode.*/
|
||||
uint32_t rx_half_sample_bits : 6; /*I2S Rx half sample bits -1.*/
|
||||
uint32_t rx_tdm_chan_bits : 5; /*The Rx bit number for each channel minus 1in TDM mode.*/
|
||||
uint32_t rx_msb_shift : 1; /*Set this bit to enable receiver in Phillips standard mode*/
|
||||
uint32_t reserved30 : 2; /* Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} rx_conf1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tx_tdm_ws_width : 7; /* The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck*/
|
||||
uint32_t tx_bck_div_num : 6; /*Bit clock configuration bits in transmitter mode. */
|
||||
uint32_t tx_bits_mod : 5; /*Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode.*/
|
||||
uint32_t tx_half_sample_bits : 6; /* I2S Tx half sample bits -1.*/
|
||||
uint32_t tx_tdm_chan_bits : 5; /*The Tx bit number for each channel minus 1in TDM mode.*/
|
||||
uint32_t tx_msb_shift : 1; /*Set this bit to enable transmitter in Phillips standard mode*/
|
||||
uint32_t tx_bck_no_dly : 1; /*1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode.*/
|
||||
uint32_t reserved31 : 1; /* Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} tx_conf1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_clkm_div_num : 8; /*Integral I2S clock divider value*/
|
||||
uint32_t reserved8 : 18; /* Reserved*/
|
||||
uint32_t rx_clk_active : 1; /*I2S Rx module clock enable signal.*/
|
||||
uint32_t rx_clk_sel : 2; /*Select I2S Rx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.*/
|
||||
uint32_t mclk_sel : 1; /* 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT. */
|
||||
uint32_t reserved30 : 2; /* Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} rx_clkm_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tx_clkm_div_num : 8; /*Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div. */
|
||||
uint32_t reserved8 : 18; /* Reserved*/
|
||||
uint32_t tx_clk_active : 1; /*I2S Tx module clock enable signal.*/
|
||||
uint32_t tx_clk_sel : 2; /*Select I2S Tx module source clock. 0: XTAL clock. 1: PLL240M. 2: PLL160M. 3: I2S_MCLK_in.*/
|
||||
uint32_t clk_en : 1; /*Set this bit to enable clk gate*/
|
||||
uint32_t reserved30 : 2; /* Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} tx_clkm_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_clkm_div_z : 9; /*For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b). */
|
||||
uint32_t rx_clkm_div_y : 9; /*For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)). */
|
||||
uint32_t rx_clkm_div_x : 9; /*For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. */
|
||||
uint32_t rx_clkm_div_yn1 : 1; /*For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1. */
|
||||
uint32_t reserved28 : 4; /* Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} rx_clkm_div_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tx_clkm_div_z : 9; /*For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b). */
|
||||
uint32_t tx_clkm_div_y : 9; /*For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)). */
|
||||
uint32_t tx_clkm_div_x : 9; /*For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. */
|
||||
uint32_t tx_clkm_div_yn1 : 1; /*For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1. */
|
||||
uint32_t reserved28 : 4; /* Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} tx_clkm_div_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tx_hp_bypass : 1; /*I2S TX PDM bypass hp filter or not. The option has been removed.*/
|
||||
uint32_t tx_sinc_osr2 : 4; /*I2S TX PDM OSR2 value*/
|
||||
uint32_t tx_prescale : 8; /*I2S TX PDM prescale for sigmadelta*/
|
||||
uint32_t tx_hp_in_shift : 2; /*I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4*/
|
||||
uint32_t tx_lp_in_shift : 2; /*I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4*/
|
||||
uint32_t tx_sinc_in_shift : 2; /*I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4*/
|
||||
uint32_t tx_sigmadelta_in_shift : 2; /*I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4*/
|
||||
uint32_t tx_sigmadelta_dither2 : 1; /*I2S TX PDM sigmadelta dither2 value*/
|
||||
uint32_t tx_sigmadelta_dither : 1; /*I2S TX PDM sigmadelta dither value*/
|
||||
uint32_t tx_dac_2out_en : 1; /*I2S TX PDM dac mode enable*/
|
||||
uint32_t tx_dac_mode_en : 1; /*I2S TX PDM dac 2channel enable*/
|
||||
uint32_t pcm2pdm_conv_en : 1; /*I2S TX PDM Converter enable*/
|
||||
uint32_t reserved26 : 6; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} tx_pcm2pdm_conf; // Only available on I2S0
|
||||
union {
|
||||
struct {
|
||||
uint32_t tx_pdm_fp : 10; /*I2S TX PDM Fp*/
|
||||
uint32_t tx_pdm_fs : 10; /*I2S TX PDM Fs*/
|
||||
uint32_t tx_iir_hp_mult12_5 : 3; /*The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0])*/
|
||||
uint32_t tx_iir_hp_mult12_0 : 3; /*The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0])*/
|
||||
uint32_t reserved26 : 6; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} tx_pcm2pdm_conf1; // Only available on I2S0
|
||||
uint32_t reserved_48;
|
||||
uint32_t reserved_4c;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_tdm_chan0_en : 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_chan1_en : 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_chan2_en : 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_chan3_en : 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_chan4_en : 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_chan5_en : 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_chan6_en : 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_chan7_en : 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable, just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_chan8_en : 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_chan9_en : 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_chan10_en : 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_chan11_en : 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_chan12_en : 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_chan13_en : 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_chan14_en : 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_chan15_en : 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable, just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_tot_chan_num : 4; /*The total channel number of I2S TX TDM mode.*/
|
||||
uint32_t reserved20 : 12; /* Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} rx_tdm_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tx_tdm_chan0_en : 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_chan1_en : 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_chan2_en : 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_chan3_en : 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_chan4_en : 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_chan5_en : 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_chan6_en : 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_chan7_en : 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_chan8_en : 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_chan9_en : 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_chan10_en : 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_chan11_en : 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_chan12_en : 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_chan13_en : 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_chan14_en : 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_chan15_en : 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable, just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_tot_chan_num : 4; /*The total channel number of I2S TX TDM mode.*/
|
||||
uint32_t tx_tdm_skip_msk_en : 1; /*When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels.*/
|
||||
uint32_t reserved21 : 11; /* Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} tx_tdm_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_sd_in_dm : 2; /*The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
uint32_t reserved2 : 2;
|
||||
uint32_t rx_sd1_in_dm : 2; /*The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
uint32_t reserved6 : 2;
|
||||
uint32_t rx_sd2_in_dm : 2; /*The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
uint32_t reserved10 : 2;
|
||||
uint32_t rx_sd3_in_dm : 2; /*The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
uint32_t reserved14 : 2;
|
||||
uint32_t rx_ws_out_dm : 2; /*The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
uint32_t reserved18 : 2; /* Reserved*/
|
||||
uint32_t rx_bck_out_dm : 2; /*The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
uint32_t reserved22 : 2; /* Reserved*/
|
||||
uint32_t rx_ws_in_dm : 2; /*The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
uint32_t reserved26 : 2; /* Reserved*/
|
||||
uint32_t rx_bck_in_dm : 2; /*The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
uint32_t reserved30 : 2; /* Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} rx_timing;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tx_sd_out_dm : 2; /*The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
uint32_t reserved2 : 2; /* Reserved*/
|
||||
uint32_t tx_sd1_out_dm : 2; /*The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
uint32_t reserved6 : 10; /* Reserved*/
|
||||
uint32_t tx_ws_out_dm : 2; /*The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
uint32_t reserved18 : 2; /* Reserved*/
|
||||
uint32_t tx_bck_out_dm : 2; /*The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
uint32_t reserved22 : 2; /* Reserved*/
|
||||
uint32_t tx_ws_in_dm : 2; /*The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
uint32_t reserved26 : 2; /* Reserved*/
|
||||
uint32_t tx_bck_in_dm : 2; /*The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
uint32_t reserved30 : 2; /* Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} tx_timing;
|
||||
union {
|
||||
struct {
|
||||
uint32_t fifo_timeout : 8; /*the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value */
|
||||
uint32_t fifo_timeout_shift : 3; /*The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift*/
|
||||
uint32_t fifo_timeout_ena : 1; /*The enable bit for FIFO timeout*/
|
||||
uint32_t reserved12 : 20; /* Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} lc_hung_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_eof_num : 12; /*The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.*/
|
||||
uint32_t reserved12 : 20; /* Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} rx_eof_num;
|
||||
uint32_t conf_single_data; /*the right channel or left channel put out constant value stored in this register according to tx_chan_mod and reg_tx_msb_right*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t tx_idle : 1; /*1: i2s_tx is idle state. 0: i2s_tx is working.*/
|
||||
uint32_t reserved1 : 31; /* Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} state;
|
||||
uint32_t reserved_70;
|
||||
uint32_t reserved_74;
|
||||
uint32_t reserved_78;
|
||||
uint32_t reserved_7c;
|
||||
union {
|
||||
struct {
|
||||
uint32_t date : 28; /*I2S version control register*/
|
||||
uint32_t reserved28 : 4; /* Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} date;
|
||||
} i2s_dev_t;
|
||||
extern i2s_dev_t I2S0;
|
||||
extern i2s_dev_t I2S1;
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,871 +0,0 @@
|
||||
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_INTERRUPT_CORE0_REG_H_
|
||||
#define _SOC_INTERRUPT_CORE0_REG_H_
|
||||
|
||||
|
||||
#include "soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define DR_REG_INTERRUPT_CORE0_BASE DR_REG_INTERRUPT_BASE
|
||||
|
||||
#define INTERRUPT_CORE0_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x000)
|
||||
/* INTERRUPT_CORE0_MAC_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_MAC_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_MAC_INTR_MAP_M ((INTERRUPT_CORE0_MAC_INTR_MAP_V)<<(INTERRUPT_CORE0_MAC_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_MAC_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_MAC_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x004)
|
||||
/* INTERRUPT_CORE0_MAC_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_MAC_NMI_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_MAC_NMI_MAP_M ((INTERRUPT_CORE0_MAC_NMI_MAP_V)<<(INTERRUPT_CORE0_MAC_NMI_MAP_S))
|
||||
#define INTERRUPT_CORE0_MAC_NMI_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_MAC_NMI_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x008)
|
||||
/* INTERRUPT_CORE0_PWR_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_PWR_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_PWR_INTR_MAP_M ((INTERRUPT_CORE0_PWR_INTR_MAP_V)<<(INTERRUPT_CORE0_PWR_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_PWR_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_PWR_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_BB_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x00C)
|
||||
/* INTERRUPT_CORE0_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_BB_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_BB_INT_MAP_M ((INTERRUPT_CORE0_BB_INT_MAP_V)<<(INTERRUPT_CORE0_BB_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_BB_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_BB_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_BT_MAC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x010)
|
||||
/* INTERRUPT_CORE0_BT_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_BT_MAC_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_BT_MAC_INT_MAP_M ((INTERRUPT_CORE0_BT_MAC_INT_MAP_V)<<(INTERRUPT_CORE0_BT_MAC_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_BT_MAC_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_BT_MAC_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_BT_BB_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x014)
|
||||
/* INTERRUPT_CORE0_BT_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_BT_BB_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_BT_BB_INT_MAP_M ((INTERRUPT_CORE0_BT_BB_INT_MAP_V)<<(INTERRUPT_CORE0_BT_BB_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_BT_BB_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_BT_BB_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x018)
|
||||
/* INTERRUPT_CORE0_BT_BB_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_BT_BB_NMI_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_BT_BB_NMI_MAP_M ((INTERRUPT_CORE0_BT_BB_NMI_MAP_V)<<(INTERRUPT_CORE0_BT_BB_NMI_MAP_S))
|
||||
#define INTERRUPT_CORE0_BT_BB_NMI_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_BT_BB_NMI_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_RWBT_IRQ_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x01C)
|
||||
/* INTERRUPT_CORE0_RWBT_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_RWBT_IRQ_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_RWBT_IRQ_MAP_M ((INTERRUPT_CORE0_RWBT_IRQ_MAP_V)<<(INTERRUPT_CORE0_RWBT_IRQ_MAP_S))
|
||||
#define INTERRUPT_CORE0_RWBT_IRQ_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_RWBT_IRQ_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x020)
|
||||
/* INTERRUPT_CORE0_RWBLE_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_RWBLE_IRQ_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_M ((INTERRUPT_CORE0_RWBLE_IRQ_MAP_V)<<(INTERRUPT_CORE0_RWBLE_IRQ_MAP_S))
|
||||
#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_RWBT_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x024)
|
||||
/* INTERRUPT_CORE0_RWBT_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_RWBT_NMI_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_RWBT_NMI_MAP_M ((INTERRUPT_CORE0_RWBT_NMI_MAP_V)<<(INTERRUPT_CORE0_RWBT_NMI_MAP_S))
|
||||
#define INTERRUPT_CORE0_RWBT_NMI_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_RWBT_NMI_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_RWBLE_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x028)
|
||||
/* INTERRUPT_CORE0_RWBLE_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_RWBLE_NMI_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_RWBLE_NMI_MAP_M ((INTERRUPT_CORE0_RWBLE_NMI_MAP_V)<<(INTERRUPT_CORE0_RWBLE_NMI_MAP_S))
|
||||
#define INTERRUPT_CORE0_RWBLE_NMI_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_RWBLE_NMI_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_I2C_MST_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x02C)
|
||||
/* INTERRUPT_CORE0_I2C_MST_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_I2C_MST_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_I2C_MST_INT_MAP_M ((INTERRUPT_CORE0_I2C_MST_INT_MAP_V)<<(INTERRUPT_CORE0_I2C_MST_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_I2C_MST_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_I2C_MST_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_SLC0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x030)
|
||||
/* INTERRUPT_CORE0_SLC0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_SLC0_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_SLC0_INTR_MAP_M ((INTERRUPT_CORE0_SLC0_INTR_MAP_V)<<(INTERRUPT_CORE0_SLC0_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_SLC0_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_SLC0_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_SLC1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x034)
|
||||
/* INTERRUPT_CORE0_SLC1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_SLC1_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_SLC1_INTR_MAP_M ((INTERRUPT_CORE0_SLC1_INTR_MAP_V)<<(INTERRUPT_CORE0_SLC1_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_SLC1_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_SLC1_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x038)
|
||||
/* INTERRUPT_CORE0_UHCI0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_UHCI0_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_UHCI0_INTR_MAP_M ((INTERRUPT_CORE0_UHCI0_INTR_MAP_V)<<(INTERRUPT_CORE0_UHCI0_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_UHCI0_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_UHCI0_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_UHCI1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x03C)
|
||||
/* INTERRUPT_CORE0_UHCI1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_UHCI1_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_UHCI1_INTR_MAP_M ((INTERRUPT_CORE0_UHCI1_INTR_MAP_V)<<(INTERRUPT_CORE0_UHCI1_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_UHCI1_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_UHCI1_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x040)
|
||||
/* INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_M ((INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V)<<(INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S))
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x044)
|
||||
/* INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_M ((INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V)<<(INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S))
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x048)
|
||||
/* INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP_M ((INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP_V)<<(INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP_S))
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x04C)
|
||||
/* INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP_M ((INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP_V)<<(INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP_S))
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_SPI_INTR_1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x050)
|
||||
/* INTERRUPT_CORE0_SPI_INTR_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_SPI_INTR_1_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_SPI_INTR_1_MAP_M ((INTERRUPT_CORE0_SPI_INTR_1_MAP_V)<<(INTERRUPT_CORE0_SPI_INTR_1_MAP_S))
|
||||
#define INTERRUPT_CORE0_SPI_INTR_1_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_SPI_INTR_1_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_SPI_INTR_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x054)
|
||||
/* INTERRUPT_CORE0_SPI_INTR_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_SPI_INTR_2_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_SPI_INTR_2_MAP_M ((INTERRUPT_CORE0_SPI_INTR_2_MAP_V)<<(INTERRUPT_CORE0_SPI_INTR_2_MAP_S))
|
||||
#define INTERRUPT_CORE0_SPI_INTR_2_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_SPI_INTR_2_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_SPI_INTR_3_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x058)
|
||||
/* INTERRUPT_CORE0_SPI_INTR_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_SPI_INTR_3_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_SPI_INTR_3_MAP_M ((INTERRUPT_CORE0_SPI_INTR_3_MAP_V)<<(INTERRUPT_CORE0_SPI_INTR_3_MAP_S))
|
||||
#define INTERRUPT_CORE0_SPI_INTR_3_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_SPI_INTR_3_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_SPI_INTR_4_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x05C)
|
||||
/* INTERRUPT_CORE0_SPI_INTR_4_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_SPI_INTR_4_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_SPI_INTR_4_MAP_M ((INTERRUPT_CORE0_SPI_INTR_4_MAP_V)<<(INTERRUPT_CORE0_SPI_INTR_4_MAP_S))
|
||||
#define INTERRUPT_CORE0_SPI_INTR_4_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_SPI_INTR_4_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x060)
|
||||
/* INTERRUPT_CORE0_LCD_CAM_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_LCD_CAM_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_M ((INTERRUPT_CORE0_LCD_CAM_INT_MAP_V)<<(INTERRUPT_CORE0_LCD_CAM_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_I2S0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x064)
|
||||
/* INTERRUPT_CORE0_I2S0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_I2S0_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_I2S0_INT_MAP_M ((INTERRUPT_CORE0_I2S0_INT_MAP_V)<<(INTERRUPT_CORE0_I2S0_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_I2S0_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_I2S0_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_I2S1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x068)
|
||||
/* INTERRUPT_CORE0_I2S1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_I2S1_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_I2S1_INT_MAP_M ((INTERRUPT_CORE0_I2S1_INT_MAP_V)<<(INTERRUPT_CORE0_I2S1_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_I2S1_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_I2S1_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_UART_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x06C)
|
||||
/* INTERRUPT_CORE0_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_UART_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_UART_INTR_MAP_M ((INTERRUPT_CORE0_UART_INTR_MAP_V)<<(INTERRUPT_CORE0_UART_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_UART_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_UART_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x070)
|
||||
/* INTERRUPT_CORE0_UART1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_UART1_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_UART1_INTR_MAP_M ((INTERRUPT_CORE0_UART1_INTR_MAP_V)<<(INTERRUPT_CORE0_UART1_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_UART1_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_UART1_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_UART2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x074)
|
||||
/* INTERRUPT_CORE0_UART2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_UART2_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_UART2_INTR_MAP_M ((INTERRUPT_CORE0_UART2_INTR_MAP_V)<<(INTERRUPT_CORE0_UART2_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_UART2_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_UART2_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x078)
|
||||
/* INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP_M ((INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP_V)<<(INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP_S))
|
||||
#define INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_PWM0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x07C)
|
||||
/* INTERRUPT_CORE0_PWM0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_PWM0_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_PWM0_INTR_MAP_M ((INTERRUPT_CORE0_PWM0_INTR_MAP_V)<<(INTERRUPT_CORE0_PWM0_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_PWM0_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_PWM0_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_PWM1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x080)
|
||||
/* INTERRUPT_CORE0_PWM1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_PWM1_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_PWM1_INTR_MAP_M ((INTERRUPT_CORE0_PWM1_INTR_MAP_V)<<(INTERRUPT_CORE0_PWM1_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_PWM1_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_PWM1_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_PWM2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x084)
|
||||
/* INTERRUPT_CORE0_PWM2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_PWM2_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_PWM2_INTR_MAP_M ((INTERRUPT_CORE0_PWM2_INTR_MAP_V)<<(INTERRUPT_CORE0_PWM2_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_PWM2_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_PWM2_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_PWM3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x088)
|
||||
/* INTERRUPT_CORE0_PWM3_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_PWM3_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_PWM3_INTR_MAP_M ((INTERRUPT_CORE0_PWM3_INTR_MAP_V)<<(INTERRUPT_CORE0_PWM3_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_PWM3_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_PWM3_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_LEDC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x08C)
|
||||
/* INTERRUPT_CORE0_LEDC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_LEDC_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_LEDC_INT_MAP_M ((INTERRUPT_CORE0_LEDC_INT_MAP_V)<<(INTERRUPT_CORE0_LEDC_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_LEDC_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_LEDC_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_EFUSE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x090)
|
||||
/* INTERRUPT_CORE0_EFUSE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_EFUSE_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_EFUSE_INT_MAP_M ((INTERRUPT_CORE0_EFUSE_INT_MAP_V)<<(INTERRUPT_CORE0_EFUSE_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_EFUSE_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_EFUSE_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CAN_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x094)
|
||||
/* INTERRUPT_CORE0_CAN_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CAN_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_CAN_INT_MAP_M ((INTERRUPT_CORE0_CAN_INT_MAP_V)<<(INTERRUPT_CORE0_CAN_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_CAN_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_CAN_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x098)
|
||||
/* INTERRUPT_CORE0_USB_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_USB_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_USB_INTR_MAP_M ((INTERRUPT_CORE0_USB_INTR_MAP_V)<<(INTERRUPT_CORE0_USB_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_USB_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_USB_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x09C)
|
||||
/* INTERRUPT_CORE0_RTC_CORE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_M ((INTERRUPT_CORE0_RTC_CORE_INTR_MAP_V)<<(INTERRUPT_CORE0_RTC_CORE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0A0)
|
||||
/* INTERRUPT_CORE0_RMT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_RMT_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_RMT_INTR_MAP_M ((INTERRUPT_CORE0_RMT_INTR_MAP_V)<<(INTERRUPT_CORE0_RMT_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_RMT_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_RMT_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_PCNT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0A4)
|
||||
/* INTERRUPT_CORE0_PCNT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_PCNT_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_PCNT_INTR_MAP_M ((INTERRUPT_CORE0_PCNT_INTR_MAP_V)<<(INTERRUPT_CORE0_PCNT_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_PCNT_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_PCNT_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0A8)
|
||||
/* INTERRUPT_CORE0_I2C_EXT0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_M ((INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V)<<(INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0AC)
|
||||
/* INTERRUPT_CORE0_I2C_EXT1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_M ((INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_V)<<(INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_SPI2_DMA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0B0)
|
||||
/* INTERRUPT_CORE0_SPI2_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_SPI2_DMA_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_SPI2_DMA_INT_MAP_M ((INTERRUPT_CORE0_SPI2_DMA_INT_MAP_V)<<(INTERRUPT_CORE0_SPI2_DMA_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_SPI2_DMA_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_SPI2_DMA_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_SPI3_DMA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0B4)
|
||||
/* INTERRUPT_CORE0_SPI3_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_SPI3_DMA_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_SPI3_DMA_INT_MAP_M ((INTERRUPT_CORE0_SPI3_DMA_INT_MAP_V)<<(INTERRUPT_CORE0_SPI3_DMA_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_SPI3_DMA_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_SPI3_DMA_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_SPI4_DMA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0B8)
|
||||
/* INTERRUPT_CORE0_SPI4_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_SPI4_DMA_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_SPI4_DMA_INT_MAP_M ((INTERRUPT_CORE0_SPI4_DMA_INT_MAP_V)<<(INTERRUPT_CORE0_SPI4_DMA_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_SPI4_DMA_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_SPI4_DMA_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_WDG_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0BC)
|
||||
/* INTERRUPT_CORE0_WDG_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_WDG_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_WDG_INT_MAP_M ((INTERRUPT_CORE0_WDG_INT_MAP_V)<<(INTERRUPT_CORE0_WDG_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_WDG_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_WDG_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_TIMER_INT1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0C0)
|
||||
/* INTERRUPT_CORE0_TIMER_INT1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_TIMER_INT1_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_TIMER_INT1_MAP_M ((INTERRUPT_CORE0_TIMER_INT1_MAP_V)<<(INTERRUPT_CORE0_TIMER_INT1_MAP_S))
|
||||
#define INTERRUPT_CORE0_TIMER_INT1_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_TIMER_INT1_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_TIMER_INT2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0C4)
|
||||
/* INTERRUPT_CORE0_TIMER_INT2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_TIMER_INT2_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_TIMER_INT2_MAP_M ((INTERRUPT_CORE0_TIMER_INT2_MAP_V)<<(INTERRUPT_CORE0_TIMER_INT2_MAP_S))
|
||||
#define INTERRUPT_CORE0_TIMER_INT2_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_TIMER_INT2_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_TG_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0C8)
|
||||
/* INTERRUPT_CORE0_TG_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_TG_T0_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_TG_T0_INT_MAP_M ((INTERRUPT_CORE0_TG_T0_INT_MAP_V)<<(INTERRUPT_CORE0_TG_T0_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_TG_T0_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_TG_T0_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_TG_T1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0CC)
|
||||
/* INTERRUPT_CORE0_TG_T1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_TG_T1_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_TG_T1_INT_MAP_M ((INTERRUPT_CORE0_TG_T1_INT_MAP_V)<<(INTERRUPT_CORE0_TG_T1_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_TG_T1_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_TG_T1_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_TG_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0D0)
|
||||
/* INTERRUPT_CORE0_TG_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_TG_WDT_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_TG_WDT_INT_MAP_M ((INTERRUPT_CORE0_TG_WDT_INT_MAP_V)<<(INTERRUPT_CORE0_TG_WDT_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_TG_WDT_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_TG_WDT_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_TG1_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0D4)
|
||||
/* INTERRUPT_CORE0_TG1_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_TG1_T0_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_TG1_T0_INT_MAP_M ((INTERRUPT_CORE0_TG1_T0_INT_MAP_V)<<(INTERRUPT_CORE0_TG1_T0_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_TG1_T0_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_TG1_T0_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_TG1_T1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0D8)
|
||||
/* INTERRUPT_CORE0_TG1_T1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_TG1_T1_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_TG1_T1_INT_MAP_M ((INTERRUPT_CORE0_TG1_T1_INT_MAP_V)<<(INTERRUPT_CORE0_TG1_T1_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_TG1_T1_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_TG1_T1_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0DC)
|
||||
/* INTERRUPT_CORE0_TG1_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_TG1_WDT_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_M ((INTERRUPT_CORE0_TG1_WDT_INT_MAP_V)<<(INTERRUPT_CORE0_TG1_WDT_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0E0)
|
||||
/* INTERRUPT_CORE0_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CACHE_IA_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_M ((INTERRUPT_CORE0_CACHE_IA_INT_MAP_V)<<(INTERRUPT_CORE0_CACHE_IA_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0E4)
|
||||
/* INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_M ((INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0E8)
|
||||
/* INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_M ((INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0EC)
|
||||
/* INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_M ((INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V)<<(INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0F0)
|
||||
/* INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_M ((INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_V)<<(INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0F4)
|
||||
/* INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP_M ((INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP_V)<<(INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0F8)
|
||||
/* INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_M ((INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_V)<<(INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0FC)
|
||||
/* INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP_M ((INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP_V)<<(INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x100)
|
||||
/* INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_M ((INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_V)<<(INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_APB_ADC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x104)
|
||||
/* INTERRUPT_CORE0_APB_ADC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_APB_ADC_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_APB_ADC_INT_MAP_M ((INTERRUPT_CORE0_APB_ADC_INT_MAP_V)<<(INTERRUPT_CORE0_APB_ADC_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_APB_ADC_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_APB_ADC_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_DMA_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x108)
|
||||
/* INTERRUPT_CORE0_DMA_IN_CH0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_DMA_IN_CH0_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_DMA_IN_CH0_INT_MAP_M ((INTERRUPT_CORE0_DMA_IN_CH0_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_IN_CH0_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_DMA_IN_CH0_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_DMA_IN_CH0_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_DMA_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10C)
|
||||
/* INTERRUPT_CORE0_DMA_IN_CH1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_DMA_IN_CH1_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_DMA_IN_CH1_INT_MAP_M ((INTERRUPT_CORE0_DMA_IN_CH1_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_IN_CH1_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_DMA_IN_CH1_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_DMA_IN_CH1_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_DMA_IN_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x110)
|
||||
/* INTERRUPT_CORE0_DMA_IN_CH2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_DMA_IN_CH2_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_DMA_IN_CH2_INT_MAP_M ((INTERRUPT_CORE0_DMA_IN_CH2_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_IN_CH2_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_DMA_IN_CH2_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_DMA_IN_CH2_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_DMA_IN_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x114)
|
||||
/* INTERRUPT_CORE0_DMA_IN_CH3_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_DMA_IN_CH3_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_DMA_IN_CH3_INT_MAP_M ((INTERRUPT_CORE0_DMA_IN_CH3_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_IN_CH3_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_DMA_IN_CH3_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_DMA_IN_CH3_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_DMA_IN_CH4_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x118)
|
||||
/* INTERRUPT_CORE0_DMA_IN_CH4_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_DMA_IN_CH4_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_DMA_IN_CH4_INT_MAP_M ((INTERRUPT_CORE0_DMA_IN_CH4_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_IN_CH4_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_DMA_IN_CH4_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_DMA_IN_CH4_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_DMA_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x11C)
|
||||
/* INTERRUPT_CORE0_DMA_OUT_CH0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_DMA_OUT_CH0_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_DMA_OUT_CH0_INT_MAP_M ((INTERRUPT_CORE0_DMA_OUT_CH0_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_OUT_CH0_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_DMA_OUT_CH0_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_DMA_OUT_CH0_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_DMA_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x120)
|
||||
/* INTERRUPT_CORE0_DMA_OUT_CH1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_DMA_OUT_CH1_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_DMA_OUT_CH1_INT_MAP_M ((INTERRUPT_CORE0_DMA_OUT_CH1_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_OUT_CH1_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_DMA_OUT_CH1_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_DMA_OUT_CH1_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_DMA_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x124)
|
||||
/* INTERRUPT_CORE0_DMA_OUT_CH2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_DMA_OUT_CH2_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_DMA_OUT_CH2_INT_MAP_M ((INTERRUPT_CORE0_DMA_OUT_CH2_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_OUT_CH2_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_DMA_OUT_CH2_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_DMA_OUT_CH2_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_DMA_OUT_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x128)
|
||||
/* INTERRUPT_CORE0_DMA_OUT_CH3_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_DMA_OUT_CH3_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_DMA_OUT_CH3_INT_MAP_M ((INTERRUPT_CORE0_DMA_OUT_CH3_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_OUT_CH3_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_DMA_OUT_CH3_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_DMA_OUT_CH3_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_DMA_OUT_CH4_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x12C)
|
||||
/* INTERRUPT_CORE0_DMA_OUT_CH4_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_DMA_OUT_CH4_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_DMA_OUT_CH4_INT_MAP_M ((INTERRUPT_CORE0_DMA_OUT_CH4_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_OUT_CH4_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_DMA_OUT_CH4_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_DMA_OUT_CH4_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_RSA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x130)
|
||||
/* INTERRUPT_CORE0_RSA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_RSA_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_RSA_INT_MAP_M ((INTERRUPT_CORE0_RSA_INT_MAP_V)<<(INTERRUPT_CORE0_RSA_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_RSA_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_RSA_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_AES_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x134)
|
||||
/* INTERRUPT_CORE0_AES_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_AES_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_AES_INT_MAP_M ((INTERRUPT_CORE0_AES_INT_MAP_V)<<(INTERRUPT_CORE0_AES_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_AES_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_AES_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_SHA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x138)
|
||||
/* INTERRUPT_CORE0_SHA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_SHA_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_SHA_INT_MAP_M ((INTERRUPT_CORE0_SHA_INT_MAP_V)<<(INTERRUPT_CORE0_SHA_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_SHA_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_SHA_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x13C)
|
||||
/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S))
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x140)
|
||||
/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S))
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x144)
|
||||
/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S))
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x148)
|
||||
/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V)<<(INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S))
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14C)
|
||||
/* INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_M ((INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V)<<(INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x150)
|
||||
/* INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x154)
|
||||
/* INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x158)
|
||||
/* INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x15C)
|
||||
/* INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x160)
|
||||
/* INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x164)
|
||||
/* INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x168)
|
||||
/* INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x16C)
|
||||
/* INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x170)
|
||||
/* INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V)<<(INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x174)
|
||||
/* INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_BACKUP_PMS_VIOLATE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x178)
|
||||
/* INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_M ((INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V)<<(INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x17C)
|
||||
/* INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_M ((INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_V)<<(INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x180)
|
||||
/* INTERRUPT_CORE0_USB_DEVICE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_M ((INTERRUPT_CORE0_USB_DEVICE_INT_MAP_V)<<(INTERRUPT_CORE0_USB_DEVICE_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_USB_DEVICE_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_PERI_BACKUP_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x184)
|
||||
/* INTERRUPT_CORE0_PERI_BACKUP_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_PERI_BACKUP_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_PERI_BACKUP_INT_MAP_M ((INTERRUPT_CORE0_PERI_BACKUP_INT_MAP_V)<<(INTERRUPT_CORE0_PERI_BACKUP_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_PERI_BACKUP_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_PERI_BACKUP_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_DMA_EXTMEM_REJECT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x188)
|
||||
/* INTERRUPT_CORE0_DMA_EXTMEM_REJECT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_DMA_EXTMEM_REJECT_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_DMA_EXTMEM_REJECT_INT_MAP_M ((INTERRUPT_CORE0_DMA_EXTMEM_REJECT_INT_MAP_V)<<(INTERRUPT_CORE0_DMA_EXTMEM_REJECT_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_DMA_EXTMEM_REJECT_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_DMA_EXTMEM_REJECT_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_INTR_STATUS_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x18C)
|
||||
/* INTERRUPT_CORE0_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_INTR_STATUS_0 0xFFFFFFFF
|
||||
#define INTERRUPT_CORE0_INTR_STATUS_0_M ((INTERRUPT_CORE0_INTR_STATUS_0_V)<<(INTERRUPT_CORE0_INTR_STATUS_0_S))
|
||||
#define INTERRUPT_CORE0_INTR_STATUS_0_V 0xFFFFFFFF
|
||||
#define INTERRUPT_CORE0_INTR_STATUS_0_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_INTR_STATUS_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x190)
|
||||
/* INTERRUPT_CORE0_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_INTR_STATUS_1 0xFFFFFFFF
|
||||
#define INTERRUPT_CORE0_INTR_STATUS_1_M ((INTERRUPT_CORE0_INTR_STATUS_1_V)<<(INTERRUPT_CORE0_INTR_STATUS_1_S))
|
||||
#define INTERRUPT_CORE0_INTR_STATUS_1_V 0xFFFFFFFF
|
||||
#define INTERRUPT_CORE0_INTR_STATUS_1_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_INTR_STATUS_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x194)
|
||||
/* INTERRUPT_CORE0_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_INTR_STATUS_2 0xFFFFFFFF
|
||||
#define INTERRUPT_CORE0_INTR_STATUS_2_M ((INTERRUPT_CORE0_INTR_STATUS_2_V)<<(INTERRUPT_CORE0_INTR_STATUS_2_S))
|
||||
#define INTERRUPT_CORE0_INTR_STATUS_2_V 0xFFFFFFFF
|
||||
#define INTERRUPT_CORE0_INTR_STATUS_2_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_INTR_STATUS_3_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x198)
|
||||
/* INTERRUPT_CORE0_INTR_STATUS_3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_INTR_STATUS_3 0xFFFFFFFF
|
||||
#define INTERRUPT_CORE0_INTR_STATUS_3_M ((INTERRUPT_CORE0_INTR_STATUS_3_V)<<(INTERRUPT_CORE0_INTR_STATUS_3_S))
|
||||
#define INTERRUPT_CORE0_INTR_STATUS_3_V 0xFFFFFFFF
|
||||
#define INTERRUPT_CORE0_INTR_STATUS_3_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x19c)
|
||||
/* INTERRUPT_CORE0_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CLK_EN (BIT(0))
|
||||
#define INTERRUPT_CORE0_CLK_EN_M (BIT(0))
|
||||
#define INTERRUPT_CORE0_CLK_EN_V 0x1
|
||||
#define INTERRUPT_CORE0_CLK_EN_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_INTERRUPT_DATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7FC)
|
||||
/* INTERRUPT_CORE0_INTERRUPT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2012300 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_INTERRUPT_DATE 0x0FFFFFFF
|
||||
#define INTERRUPT_CORE0_INTERRUPT_DATE_M ((INTERRUPT_CORE0_INTERRUPT_DATE_V)<<(INTERRUPT_CORE0_INTERRUPT_DATE_S))
|
||||
#define INTERRUPT_CORE0_INTERRUPT_DATE_V 0xFFFFFFF
|
||||
#define INTERRUPT_CORE0_INTERRUPT_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /*_SOC_INTERRUPT_CORE0_REG_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,871 +0,0 @@
|
||||
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_INTERRUPT_CORE1_REG_H_
|
||||
#define _SOC_INTERRUPT_CORE1_REG_H_
|
||||
|
||||
|
||||
#include "soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define DR_REG_INTERRUPT_CORE1_BASE DR_REG_INTERRUPT_BASE
|
||||
|
||||
#define INTERRUPT_CORE1_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x800)
|
||||
/* INTERRUPT_CORE1_MAC_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_MAC_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_MAC_INTR_MAP_M ((INTERRUPT_CORE1_MAC_INTR_MAP_V)<<(INTERRUPT_CORE1_MAC_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_MAC_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_MAC_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x804)
|
||||
/* INTERRUPT_CORE1_MAC_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_MAC_NMI_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_MAC_NMI_MAP_M ((INTERRUPT_CORE1_MAC_NMI_MAP_V)<<(INTERRUPT_CORE1_MAC_NMI_MAP_S))
|
||||
#define INTERRUPT_CORE1_MAC_NMI_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_MAC_NMI_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x808)
|
||||
/* INTERRUPT_CORE1_PWR_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_PWR_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_PWR_INTR_MAP_M ((INTERRUPT_CORE1_PWR_INTR_MAP_V)<<(INTERRUPT_CORE1_PWR_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_PWR_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_PWR_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_BB_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x80C)
|
||||
/* INTERRUPT_CORE1_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_BB_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_BB_INT_MAP_M ((INTERRUPT_CORE1_BB_INT_MAP_V)<<(INTERRUPT_CORE1_BB_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_BB_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_BB_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_BT_MAC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x810)
|
||||
/* INTERRUPT_CORE1_BT_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_BT_MAC_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_BT_MAC_INT_MAP_M ((INTERRUPT_CORE1_BT_MAC_INT_MAP_V)<<(INTERRUPT_CORE1_BT_MAC_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_BT_MAC_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_BT_MAC_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_BT_BB_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x814)
|
||||
/* INTERRUPT_CORE1_BT_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_BT_BB_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_BT_BB_INT_MAP_M ((INTERRUPT_CORE1_BT_BB_INT_MAP_V)<<(INTERRUPT_CORE1_BT_BB_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_BT_BB_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_BT_BB_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x818)
|
||||
/* INTERRUPT_CORE1_BT_BB_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_BT_BB_NMI_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_BT_BB_NMI_MAP_M ((INTERRUPT_CORE1_BT_BB_NMI_MAP_V)<<(INTERRUPT_CORE1_BT_BB_NMI_MAP_S))
|
||||
#define INTERRUPT_CORE1_BT_BB_NMI_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_BT_BB_NMI_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_RWBT_IRQ_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x81C)
|
||||
/* INTERRUPT_CORE1_RWBT_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_RWBT_IRQ_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_RWBT_IRQ_MAP_M ((INTERRUPT_CORE1_RWBT_IRQ_MAP_V)<<(INTERRUPT_CORE1_RWBT_IRQ_MAP_S))
|
||||
#define INTERRUPT_CORE1_RWBT_IRQ_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_RWBT_IRQ_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_RWBLE_IRQ_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x820)
|
||||
/* INTERRUPT_CORE1_RWBLE_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_RWBLE_IRQ_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_RWBLE_IRQ_MAP_M ((INTERRUPT_CORE1_RWBLE_IRQ_MAP_V)<<(INTERRUPT_CORE1_RWBLE_IRQ_MAP_S))
|
||||
#define INTERRUPT_CORE1_RWBLE_IRQ_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_RWBLE_IRQ_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_RWBT_NMI_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x824)
|
||||
/* INTERRUPT_CORE1_RWBT_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_RWBT_NMI_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_RWBT_NMI_MAP_M ((INTERRUPT_CORE1_RWBT_NMI_MAP_V)<<(INTERRUPT_CORE1_RWBT_NMI_MAP_S))
|
||||
#define INTERRUPT_CORE1_RWBT_NMI_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_RWBT_NMI_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_RWBLE_NMI_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x828)
|
||||
/* INTERRUPT_CORE1_RWBLE_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_RWBLE_NMI_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_RWBLE_NMI_MAP_M ((INTERRUPT_CORE1_RWBLE_NMI_MAP_V)<<(INTERRUPT_CORE1_RWBLE_NMI_MAP_S))
|
||||
#define INTERRUPT_CORE1_RWBLE_NMI_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_RWBLE_NMI_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_I2C_MST_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x82C)
|
||||
/* INTERRUPT_CORE1_I2C_MST_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_I2C_MST_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_I2C_MST_INT_MAP_M ((INTERRUPT_CORE1_I2C_MST_INT_MAP_V)<<(INTERRUPT_CORE1_I2C_MST_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_I2C_MST_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_I2C_MST_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_SLC0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x830)
|
||||
/* INTERRUPT_CORE1_SLC0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_SLC0_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_SLC0_INTR_MAP_M ((INTERRUPT_CORE1_SLC0_INTR_MAP_V)<<(INTERRUPT_CORE1_SLC0_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_SLC0_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_SLC0_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_SLC1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x834)
|
||||
/* INTERRUPT_CORE1_SLC1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_SLC1_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_SLC1_INTR_MAP_M ((INTERRUPT_CORE1_SLC1_INTR_MAP_V)<<(INTERRUPT_CORE1_SLC1_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_SLC1_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_SLC1_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x838)
|
||||
/* INTERRUPT_CORE1_UHCI0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_UHCI0_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_UHCI0_INTR_MAP_M ((INTERRUPT_CORE1_UHCI0_INTR_MAP_V)<<(INTERRUPT_CORE1_UHCI0_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_UHCI0_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_UHCI0_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_UHCI1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x83C)
|
||||
/* INTERRUPT_CORE1_UHCI1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_UHCI1_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_UHCI1_INTR_MAP_M ((INTERRUPT_CORE1_UHCI1_INTR_MAP_V)<<(INTERRUPT_CORE1_UHCI1_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_UHCI1_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_UHCI1_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x840)
|
||||
/* INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_MAP_M ((INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_MAP_V)<<(INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_MAP_S))
|
||||
#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x844)
|
||||
/* INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_NMI_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_NMI_MAP_M ((INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_NMI_MAP_V)<<(INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_NMI_MAP_S))
|
||||
#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_NMI_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_NMI_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x848)
|
||||
/* INTERRUPT_CORE1_GPIO_INTERRUPT_APP_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_MAP_M ((INTERRUPT_CORE1_GPIO_INTERRUPT_APP_MAP_V)<<(INTERRUPT_CORE1_GPIO_INTERRUPT_APP_MAP_S))
|
||||
#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_NMI_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x84C)
|
||||
/* INTERRUPT_CORE1_GPIO_INTERRUPT_APP_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_NMI_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_NMI_MAP_M ((INTERRUPT_CORE1_GPIO_INTERRUPT_APP_NMI_MAP_V)<<(INTERRUPT_CORE1_GPIO_INTERRUPT_APP_NMI_MAP_S))
|
||||
#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_NMI_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_NMI_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_SPI_INTR_1_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x850)
|
||||
/* INTERRUPT_CORE1_SPI_INTR_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_SPI_INTR_1_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_SPI_INTR_1_MAP_M ((INTERRUPT_CORE1_SPI_INTR_1_MAP_V)<<(INTERRUPT_CORE1_SPI_INTR_1_MAP_S))
|
||||
#define INTERRUPT_CORE1_SPI_INTR_1_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_SPI_INTR_1_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_SPI_INTR_2_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x854)
|
||||
/* INTERRUPT_CORE1_SPI_INTR_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_SPI_INTR_2_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_SPI_INTR_2_MAP_M ((INTERRUPT_CORE1_SPI_INTR_2_MAP_V)<<(INTERRUPT_CORE1_SPI_INTR_2_MAP_S))
|
||||
#define INTERRUPT_CORE1_SPI_INTR_2_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_SPI_INTR_2_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_SPI_INTR_3_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x858)
|
||||
/* INTERRUPT_CORE1_SPI_INTR_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_SPI_INTR_3_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_SPI_INTR_3_MAP_M ((INTERRUPT_CORE1_SPI_INTR_3_MAP_V)<<(INTERRUPT_CORE1_SPI_INTR_3_MAP_S))
|
||||
#define INTERRUPT_CORE1_SPI_INTR_3_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_SPI_INTR_3_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_SPI_INTR_4_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x85C)
|
||||
/* INTERRUPT_CORE1_SPI_INTR_4_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_SPI_INTR_4_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_SPI_INTR_4_MAP_M ((INTERRUPT_CORE1_SPI_INTR_4_MAP_V)<<(INTERRUPT_CORE1_SPI_INTR_4_MAP_S))
|
||||
#define INTERRUPT_CORE1_SPI_INTR_4_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_SPI_INTR_4_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_LCD_CAM_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x860)
|
||||
/* INTERRUPT_CORE1_LCD_CAM_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_LCD_CAM_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_LCD_CAM_INT_MAP_M ((INTERRUPT_CORE1_LCD_CAM_INT_MAP_V)<<(INTERRUPT_CORE1_LCD_CAM_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_LCD_CAM_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_LCD_CAM_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_I2S0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x864)
|
||||
/* INTERRUPT_CORE1_I2S0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_I2S0_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_I2S0_INT_MAP_M ((INTERRUPT_CORE1_I2S0_INT_MAP_V)<<(INTERRUPT_CORE1_I2S0_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_I2S0_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_I2S0_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_I2S1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x868)
|
||||
/* INTERRUPT_CORE1_I2S1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_I2S1_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_I2S1_INT_MAP_M ((INTERRUPT_CORE1_I2S1_INT_MAP_V)<<(INTERRUPT_CORE1_I2S1_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_I2S1_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_I2S1_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_UART_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x86C)
|
||||
/* INTERRUPT_CORE1_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_UART_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_UART_INTR_MAP_M ((INTERRUPT_CORE1_UART_INTR_MAP_V)<<(INTERRUPT_CORE1_UART_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_UART_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_UART_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x870)
|
||||
/* INTERRUPT_CORE1_UART1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_UART1_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_UART1_INTR_MAP_M ((INTERRUPT_CORE1_UART1_INTR_MAP_V)<<(INTERRUPT_CORE1_UART1_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_UART1_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_UART1_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_UART2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x874)
|
||||
/* INTERRUPT_CORE1_UART2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_UART2_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_UART2_INTR_MAP_M ((INTERRUPT_CORE1_UART2_INTR_MAP_V)<<(INTERRUPT_CORE1_UART2_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_UART2_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_UART2_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_SDIO_HOST_INTERRUPT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x878)
|
||||
/* INTERRUPT_CORE1_SDIO_HOST_INTERRUPT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_SDIO_HOST_INTERRUPT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_SDIO_HOST_INTERRUPT_MAP_M ((INTERRUPT_CORE1_SDIO_HOST_INTERRUPT_MAP_V)<<(INTERRUPT_CORE1_SDIO_HOST_INTERRUPT_MAP_S))
|
||||
#define INTERRUPT_CORE1_SDIO_HOST_INTERRUPT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_SDIO_HOST_INTERRUPT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_PWM0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x87C)
|
||||
/* INTERRUPT_CORE1_PWM0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_PWM0_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_PWM0_INTR_MAP_M ((INTERRUPT_CORE1_PWM0_INTR_MAP_V)<<(INTERRUPT_CORE1_PWM0_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_PWM0_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_PWM0_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_PWM1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x880)
|
||||
/* INTERRUPT_CORE1_PWM1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_PWM1_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_PWM1_INTR_MAP_M ((INTERRUPT_CORE1_PWM1_INTR_MAP_V)<<(INTERRUPT_CORE1_PWM1_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_PWM1_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_PWM1_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_PWM2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x884)
|
||||
/* INTERRUPT_CORE1_PWM2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_PWM2_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_PWM2_INTR_MAP_M ((INTERRUPT_CORE1_PWM2_INTR_MAP_V)<<(INTERRUPT_CORE1_PWM2_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_PWM2_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_PWM2_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_PWM3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x888)
|
||||
/* INTERRUPT_CORE1_PWM3_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_PWM3_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_PWM3_INTR_MAP_M ((INTERRUPT_CORE1_PWM3_INTR_MAP_V)<<(INTERRUPT_CORE1_PWM3_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_PWM3_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_PWM3_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_LEDC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x88C)
|
||||
/* INTERRUPT_CORE1_LEDC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_LEDC_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_LEDC_INT_MAP_M ((INTERRUPT_CORE1_LEDC_INT_MAP_V)<<(INTERRUPT_CORE1_LEDC_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_LEDC_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_LEDC_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_EFUSE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x890)
|
||||
/* INTERRUPT_CORE1_EFUSE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_EFUSE_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_EFUSE_INT_MAP_M ((INTERRUPT_CORE1_EFUSE_INT_MAP_V)<<(INTERRUPT_CORE1_EFUSE_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_EFUSE_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_EFUSE_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_CAN_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x894)
|
||||
/* INTERRUPT_CORE1_CAN_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_CAN_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_CAN_INT_MAP_M ((INTERRUPT_CORE1_CAN_INT_MAP_V)<<(INTERRUPT_CORE1_CAN_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_CAN_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_CAN_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_USB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x898)
|
||||
/* INTERRUPT_CORE1_USB_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_USB_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_USB_INTR_MAP_M ((INTERRUPT_CORE1_USB_INTR_MAP_V)<<(INTERRUPT_CORE1_USB_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_USB_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_USB_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_RTC_CORE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x89C)
|
||||
/* INTERRUPT_CORE1_RTC_CORE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_RTC_CORE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_RTC_CORE_INTR_MAP_M ((INTERRUPT_CORE1_RTC_CORE_INTR_MAP_V)<<(INTERRUPT_CORE1_RTC_CORE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_RTC_CORE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_RTC_CORE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8A0)
|
||||
/* INTERRUPT_CORE1_RMT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_RMT_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_RMT_INTR_MAP_M ((INTERRUPT_CORE1_RMT_INTR_MAP_V)<<(INTERRUPT_CORE1_RMT_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_RMT_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_RMT_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_PCNT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8A4)
|
||||
/* INTERRUPT_CORE1_PCNT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_PCNT_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_PCNT_INTR_MAP_M ((INTERRUPT_CORE1_PCNT_INTR_MAP_V)<<(INTERRUPT_CORE1_PCNT_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_PCNT_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_PCNT_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8A8)
|
||||
/* INTERRUPT_CORE1_I2C_EXT0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_I2C_EXT0_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_I2C_EXT0_INTR_MAP_M ((INTERRUPT_CORE1_I2C_EXT0_INTR_MAP_V)<<(INTERRUPT_CORE1_I2C_EXT0_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_I2C_EXT0_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_I2C_EXT0_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_I2C_EXT1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8AC)
|
||||
/* INTERRUPT_CORE1_I2C_EXT1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_I2C_EXT1_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_I2C_EXT1_INTR_MAP_M ((INTERRUPT_CORE1_I2C_EXT1_INTR_MAP_V)<<(INTERRUPT_CORE1_I2C_EXT1_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_I2C_EXT1_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_I2C_EXT1_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_SPI2_DMA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8B0)
|
||||
/* INTERRUPT_CORE1_SPI2_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_SPI2_DMA_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_SPI2_DMA_INT_MAP_M ((INTERRUPT_CORE1_SPI2_DMA_INT_MAP_V)<<(INTERRUPT_CORE1_SPI2_DMA_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_SPI2_DMA_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_SPI2_DMA_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_SPI3_DMA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8B4)
|
||||
/* INTERRUPT_CORE1_SPI3_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_SPI3_DMA_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_SPI3_DMA_INT_MAP_M ((INTERRUPT_CORE1_SPI3_DMA_INT_MAP_V)<<(INTERRUPT_CORE1_SPI3_DMA_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_SPI3_DMA_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_SPI3_DMA_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_SPI4_DMA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8B8)
|
||||
/* INTERRUPT_CORE1_SPI4_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_SPI4_DMA_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_SPI4_DMA_INT_MAP_M ((INTERRUPT_CORE1_SPI4_DMA_INT_MAP_V)<<(INTERRUPT_CORE1_SPI4_DMA_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_SPI4_DMA_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_SPI4_DMA_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_WDG_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8BC)
|
||||
/* INTERRUPT_CORE1_WDG_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_WDG_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_WDG_INT_MAP_M ((INTERRUPT_CORE1_WDG_INT_MAP_V)<<(INTERRUPT_CORE1_WDG_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_WDG_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_WDG_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_TIMER_INT1_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8C0)
|
||||
/* INTERRUPT_CORE1_TIMER_INT1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_TIMER_INT1_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_TIMER_INT1_MAP_M ((INTERRUPT_CORE1_TIMER_INT1_MAP_V)<<(INTERRUPT_CORE1_TIMER_INT1_MAP_S))
|
||||
#define INTERRUPT_CORE1_TIMER_INT1_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_TIMER_INT1_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_TIMER_INT2_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8C4)
|
||||
/* INTERRUPT_CORE1_TIMER_INT2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_TIMER_INT2_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_TIMER_INT2_MAP_M ((INTERRUPT_CORE1_TIMER_INT2_MAP_V)<<(INTERRUPT_CORE1_TIMER_INT2_MAP_S))
|
||||
#define INTERRUPT_CORE1_TIMER_INT2_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_TIMER_INT2_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_TG_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8C8)
|
||||
/* INTERRUPT_CORE1_TG_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_TG_T0_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_TG_T0_INT_MAP_M ((INTERRUPT_CORE1_TG_T0_INT_MAP_V)<<(INTERRUPT_CORE1_TG_T0_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_TG_T0_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_TG_T0_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_TG_T1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8CC)
|
||||
/* INTERRUPT_CORE1_TG_T1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_TG_T1_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_TG_T1_INT_MAP_M ((INTERRUPT_CORE1_TG_T1_INT_MAP_V)<<(INTERRUPT_CORE1_TG_T1_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_TG_T1_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_TG_T1_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_TG_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8D0)
|
||||
/* INTERRUPT_CORE1_TG_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_TG_WDT_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_TG_WDT_INT_MAP_M ((INTERRUPT_CORE1_TG_WDT_INT_MAP_V)<<(INTERRUPT_CORE1_TG_WDT_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_TG_WDT_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_TG_WDT_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_TG1_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8D4)
|
||||
/* INTERRUPT_CORE1_TG1_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_TG1_T0_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_TG1_T0_INT_MAP_M ((INTERRUPT_CORE1_TG1_T0_INT_MAP_V)<<(INTERRUPT_CORE1_TG1_T0_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_TG1_T0_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_TG1_T0_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_TG1_T1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8D8)
|
||||
/* INTERRUPT_CORE1_TG1_T1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_TG1_T1_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_TG1_T1_INT_MAP_M ((INTERRUPT_CORE1_TG1_T1_INT_MAP_V)<<(INTERRUPT_CORE1_TG1_T1_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_TG1_T1_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_TG1_T1_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_TG1_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8DC)
|
||||
/* INTERRUPT_CORE1_TG1_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_TG1_WDT_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_TG1_WDT_INT_MAP_M ((INTERRUPT_CORE1_TG1_WDT_INT_MAP_V)<<(INTERRUPT_CORE1_TG1_WDT_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_TG1_WDT_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_TG1_WDT_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_CACHE_IA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8E0)
|
||||
/* INTERRUPT_CORE1_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_CACHE_IA_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_CACHE_IA_INT_MAP_M ((INTERRUPT_CORE1_CACHE_IA_INT_MAP_V)<<(INTERRUPT_CORE1_CACHE_IA_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_CACHE_IA_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_CACHE_IA_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8E4)
|
||||
/* INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_M ((INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_V)<<(INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8E8)
|
||||
/* INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_M ((INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_V)<<(INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8EC)
|
||||
/* INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_M ((INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_V)<<(INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_SPI_MEM_REJECT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8F0)
|
||||
/* INTERRUPT_CORE1_SPI_MEM_REJECT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_SPI_MEM_REJECT_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_SPI_MEM_REJECT_INTR_MAP_M ((INTERRUPT_CORE1_SPI_MEM_REJECT_INTR_MAP_V)<<(INTERRUPT_CORE1_SPI_MEM_REJECT_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_SPI_MEM_REJECT_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_SPI_MEM_REJECT_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_DCACHE_PRELOAD_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8F4)
|
||||
/* INTERRUPT_CORE1_DCACHE_PRELOAD_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_DCACHE_PRELOAD_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_DCACHE_PRELOAD_INT_MAP_M ((INTERRUPT_CORE1_DCACHE_PRELOAD_INT_MAP_V)<<(INTERRUPT_CORE1_DCACHE_PRELOAD_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_DCACHE_PRELOAD_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_DCACHE_PRELOAD_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_ICACHE_PRELOAD_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8F8)
|
||||
/* INTERRUPT_CORE1_ICACHE_PRELOAD_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_ICACHE_PRELOAD_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_ICACHE_PRELOAD_INT_MAP_M ((INTERRUPT_CORE1_ICACHE_PRELOAD_INT_MAP_V)<<(INTERRUPT_CORE1_ICACHE_PRELOAD_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_ICACHE_PRELOAD_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_ICACHE_PRELOAD_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_DCACHE_SYNC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8FC)
|
||||
/* INTERRUPT_CORE1_DCACHE_SYNC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_DCACHE_SYNC_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_DCACHE_SYNC_INT_MAP_M ((INTERRUPT_CORE1_DCACHE_SYNC_INT_MAP_V)<<(INTERRUPT_CORE1_DCACHE_SYNC_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_DCACHE_SYNC_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_DCACHE_SYNC_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_ICACHE_SYNC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x900)
|
||||
/* INTERRUPT_CORE1_ICACHE_SYNC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_ICACHE_SYNC_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_ICACHE_SYNC_INT_MAP_M ((INTERRUPT_CORE1_ICACHE_SYNC_INT_MAP_V)<<(INTERRUPT_CORE1_ICACHE_SYNC_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_ICACHE_SYNC_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_ICACHE_SYNC_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_APB_ADC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x904)
|
||||
/* INTERRUPT_CORE1_APB_ADC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_APB_ADC_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_APB_ADC_INT_MAP_M ((INTERRUPT_CORE1_APB_ADC_INT_MAP_V)<<(INTERRUPT_CORE1_APB_ADC_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_APB_ADC_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_APB_ADC_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_DMA_IN_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x908)
|
||||
/* INTERRUPT_CORE1_DMA_IN_CH0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_DMA_IN_CH0_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_DMA_IN_CH0_INT_MAP_M ((INTERRUPT_CORE1_DMA_IN_CH0_INT_MAP_V)<<(INTERRUPT_CORE1_DMA_IN_CH0_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_DMA_IN_CH0_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_DMA_IN_CH0_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_DMA_IN_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x90C)
|
||||
/* INTERRUPT_CORE1_DMA_IN_CH1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_DMA_IN_CH1_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_DMA_IN_CH1_INT_MAP_M ((INTERRUPT_CORE1_DMA_IN_CH1_INT_MAP_V)<<(INTERRUPT_CORE1_DMA_IN_CH1_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_DMA_IN_CH1_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_DMA_IN_CH1_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_DMA_IN_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x910)
|
||||
/* INTERRUPT_CORE1_DMA_IN_CH2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_DMA_IN_CH2_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_DMA_IN_CH2_INT_MAP_M ((INTERRUPT_CORE1_DMA_IN_CH2_INT_MAP_V)<<(INTERRUPT_CORE1_DMA_IN_CH2_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_DMA_IN_CH2_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_DMA_IN_CH2_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_DMA_IN_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x914)
|
||||
/* INTERRUPT_CORE1_DMA_IN_CH3_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_DMA_IN_CH3_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_DMA_IN_CH3_INT_MAP_M ((INTERRUPT_CORE1_DMA_IN_CH3_INT_MAP_V)<<(INTERRUPT_CORE1_DMA_IN_CH3_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_DMA_IN_CH3_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_DMA_IN_CH3_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_DMA_IN_CH4_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x918)
|
||||
/* INTERRUPT_CORE1_DMA_IN_CH4_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_DMA_IN_CH4_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_DMA_IN_CH4_INT_MAP_M ((INTERRUPT_CORE1_DMA_IN_CH4_INT_MAP_V)<<(INTERRUPT_CORE1_DMA_IN_CH4_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_DMA_IN_CH4_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_DMA_IN_CH4_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_DMA_OUT_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x91C)
|
||||
/* INTERRUPT_CORE1_DMA_OUT_CH0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_DMA_OUT_CH0_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_DMA_OUT_CH0_INT_MAP_M ((INTERRUPT_CORE1_DMA_OUT_CH0_INT_MAP_V)<<(INTERRUPT_CORE1_DMA_OUT_CH0_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_DMA_OUT_CH0_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_DMA_OUT_CH0_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_DMA_OUT_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x920)
|
||||
/* INTERRUPT_CORE1_DMA_OUT_CH1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_DMA_OUT_CH1_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_DMA_OUT_CH1_INT_MAP_M ((INTERRUPT_CORE1_DMA_OUT_CH1_INT_MAP_V)<<(INTERRUPT_CORE1_DMA_OUT_CH1_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_DMA_OUT_CH1_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_DMA_OUT_CH1_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_DMA_OUT_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x924)
|
||||
/* INTERRUPT_CORE1_DMA_OUT_CH2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_DMA_OUT_CH2_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_DMA_OUT_CH2_INT_MAP_M ((INTERRUPT_CORE1_DMA_OUT_CH2_INT_MAP_V)<<(INTERRUPT_CORE1_DMA_OUT_CH2_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_DMA_OUT_CH2_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_DMA_OUT_CH2_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_DMA_OUT_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x928)
|
||||
/* INTERRUPT_CORE1_DMA_OUT_CH3_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_DMA_OUT_CH3_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_DMA_OUT_CH3_INT_MAP_M ((INTERRUPT_CORE1_DMA_OUT_CH3_INT_MAP_V)<<(INTERRUPT_CORE1_DMA_OUT_CH3_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_DMA_OUT_CH3_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_DMA_OUT_CH3_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_DMA_OUT_CH4_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x92C)
|
||||
/* INTERRUPT_CORE1_DMA_OUT_CH4_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_DMA_OUT_CH4_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_DMA_OUT_CH4_INT_MAP_M ((INTERRUPT_CORE1_DMA_OUT_CH4_INT_MAP_V)<<(INTERRUPT_CORE1_DMA_OUT_CH4_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_DMA_OUT_CH4_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_DMA_OUT_CH4_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_RSA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x930)
|
||||
/* INTERRUPT_CORE1_RSA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_RSA_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_RSA_INT_MAP_M ((INTERRUPT_CORE1_RSA_INT_MAP_V)<<(INTERRUPT_CORE1_RSA_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_RSA_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_RSA_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_AES_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x934)
|
||||
/* INTERRUPT_CORE1_AES_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_AES_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_AES_INT_MAP_M ((INTERRUPT_CORE1_AES_INT_MAP_V)<<(INTERRUPT_CORE1_AES_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_AES_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_AES_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_SHA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x938)
|
||||
/* INTERRUPT_CORE1_SHA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_SHA_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_SHA_INT_MAP_M ((INTERRUPT_CORE1_SHA_INT_MAP_V)<<(INTERRUPT_CORE1_SHA_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_SHA_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_SHA_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x93C)
|
||||
/* INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP_M ((INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP_V)<<(INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP_S))
|
||||
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x940)
|
||||
/* INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP_M ((INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP_V)<<(INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP_S))
|
||||
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x944)
|
||||
/* INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP_M ((INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP_V)<<(INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP_S))
|
||||
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x948)
|
||||
/* INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP_M ((INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP_V)<<(INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP_S))
|
||||
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x94C)
|
||||
/* INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP_M ((INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP_V)<<(INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x950)
|
||||
/* INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x954)
|
||||
/* INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x958)
|
||||
/* INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x95C)
|
||||
/* INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x960)
|
||||
/* INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_M ((INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V)<<(INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x964)
|
||||
/* INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x968)
|
||||
/* INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x96C)
|
||||
/* INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x970)
|
||||
/* INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_M ((INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V)<<(INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_BACKUP_PMS_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x974)
|
||||
/* INTERRUPT_CORE1_BACKUP_PMS_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_BACKUP_PMS_VIOLATE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_BACKUP_PMS_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE1_BACKUP_PMS_VIOLATE_INTR_MAP_V)<<(INTERRUPT_CORE1_BACKUP_PMS_VIOLATE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_BACKUP_PMS_VIOLATE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_BACKUP_PMS_VIOLATE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x978)
|
||||
/* INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP_M ((INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP_V)<<(INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x97C)
|
||||
/* INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP_M ((INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP_V)<<(INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_USB_DEVICE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x980)
|
||||
/* INTERRUPT_CORE1_USB_DEVICE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_USB_DEVICE_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_USB_DEVICE_INT_MAP_M ((INTERRUPT_CORE1_USB_DEVICE_INT_MAP_V)<<(INTERRUPT_CORE1_USB_DEVICE_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_USB_DEVICE_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_USB_DEVICE_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_PERI_BACKUP_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x984)
|
||||
/* INTERRUPT_CORE1_PERI_BACKUP_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_PERI_BACKUP_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_PERI_BACKUP_INT_MAP_M ((INTERRUPT_CORE1_PERI_BACKUP_INT_MAP_V)<<(INTERRUPT_CORE1_PERI_BACKUP_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_PERI_BACKUP_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_PERI_BACKUP_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_DMA_EXTMEM_REJECT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x988)
|
||||
/* INTERRUPT_CORE1_DMA_EXTMEM_REJECT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_DMA_EXTMEM_REJECT_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_DMA_EXTMEM_REJECT_INT_MAP_M ((INTERRUPT_CORE1_DMA_EXTMEM_REJECT_INT_MAP_V)<<(INTERRUPT_CORE1_DMA_EXTMEM_REJECT_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_DMA_EXTMEM_REJECT_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_DMA_EXTMEM_REJECT_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_INTR_STATUS_0_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x98C)
|
||||
/* INTERRUPT_CORE1_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_INTR_STATUS_0 0xFFFFFFFF
|
||||
#define INTERRUPT_CORE1_INTR_STATUS_0_M ((INTERRUPT_CORE1_INTR_STATUS_0_V)<<(INTERRUPT_CORE1_INTR_STATUS_0_S))
|
||||
#define INTERRUPT_CORE1_INTR_STATUS_0_V 0xFFFFFFFF
|
||||
#define INTERRUPT_CORE1_INTR_STATUS_0_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_INTR_STATUS_1_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x990)
|
||||
/* INTERRUPT_CORE1_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_INTR_STATUS_1 0xFFFFFFFF
|
||||
#define INTERRUPT_CORE1_INTR_STATUS_1_M ((INTERRUPT_CORE1_INTR_STATUS_1_V)<<(INTERRUPT_CORE1_INTR_STATUS_1_S))
|
||||
#define INTERRUPT_CORE1_INTR_STATUS_1_V 0xFFFFFFFF
|
||||
#define INTERRUPT_CORE1_INTR_STATUS_1_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_INTR_STATUS_2_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x994)
|
||||
/* INTERRUPT_CORE1_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_INTR_STATUS_2 0xFFFFFFFF
|
||||
#define INTERRUPT_CORE1_INTR_STATUS_2_M ((INTERRUPT_CORE1_INTR_STATUS_2_V)<<(INTERRUPT_CORE1_INTR_STATUS_2_S))
|
||||
#define INTERRUPT_CORE1_INTR_STATUS_2_V 0xFFFFFFFF
|
||||
#define INTERRUPT_CORE1_INTR_STATUS_2_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_INTR_STATUS_3_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x998)
|
||||
/* INTERRUPT_CORE1_INTR_STATUS_3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_INTR_STATUS_3 0xFFFFFFFF
|
||||
#define INTERRUPT_CORE1_INTR_STATUS_3_M ((INTERRUPT_CORE1_INTR_STATUS_3_V)<<(INTERRUPT_CORE1_INTR_STATUS_3_S))
|
||||
#define INTERRUPT_CORE1_INTR_STATUS_3_V 0xFFFFFFFF
|
||||
#define INTERRUPT_CORE1_INTR_STATUS_3_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x99c)
|
||||
/* INTERRUPT_CORE1_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_CLK_EN (BIT(0))
|
||||
#define INTERRUPT_CORE1_CLK_EN_M (BIT(0))
|
||||
#define INTERRUPT_CORE1_CLK_EN_V 0x1
|
||||
#define INTERRUPT_CORE1_CLK_EN_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_INTERRUPT_DATE_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xFFC)
|
||||
/* INTERRUPT_CORE1_INTERRUPT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2012300 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_INTERRUPT_DATE 0x0FFFFFFF
|
||||
#define INTERRUPT_CORE1_INTERRUPT_DATE_M ((INTERRUPT_CORE1_INTERRUPT_DATE_V)<<(INTERRUPT_CORE1_INTERRUPT_DATE_S))
|
||||
#define INTERRUPT_CORE1_INTERRUPT_DATE_V 0xFFFFFFF
|
||||
#define INTERRUPT_CORE1_INTERRUPT_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /*_SOC_INTERRUPT_CORE1_REG_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,436 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include "soc.h"
|
||||
|
||||
/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
|
||||
/* Output enable in sleep mode */
|
||||
#define SLP_OE (BIT(0))
|
||||
#define SLP_OE_M (BIT(0))
|
||||
#define SLP_OE_V 1
|
||||
#define SLP_OE_S 0
|
||||
/* Pin used for wakeup from sleep */
|
||||
#define SLP_SEL (BIT(1))
|
||||
#define SLP_SEL_M (BIT(1))
|
||||
#define SLP_SEL_V 1
|
||||
#define SLP_SEL_S 1
|
||||
/* Pulldown enable in sleep mode */
|
||||
#define SLP_PD (BIT(2))
|
||||
#define SLP_PD_M (BIT(2))
|
||||
#define SLP_PD_V 1
|
||||
#define SLP_PD_S 2
|
||||
/* Pullup enable in sleep mode */
|
||||
#define SLP_PU (BIT(3))
|
||||
#define SLP_PU_M (BIT(3))
|
||||
#define SLP_PU_V 1
|
||||
#define SLP_PU_S 3
|
||||
/* Input enable in sleep mode */
|
||||
#define SLP_IE (BIT(4))
|
||||
#define SLP_IE_M (BIT(4))
|
||||
#define SLP_IE_V 1
|
||||
#define SLP_IE_S 4
|
||||
/* Drive strength in sleep mode */
|
||||
#define SLP_DRV 0x3
|
||||
#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S)
|
||||
#define SLP_DRV_V 0x3
|
||||
#define SLP_DRV_S 5
|
||||
/* Pulldown enable */
|
||||
#define FUN_PD (BIT(7))
|
||||
#define FUN_PD_M (BIT(7))
|
||||
#define FUN_PD_V 1
|
||||
#define FUN_PD_S 7
|
||||
/* Pullup enable */
|
||||
#define FUN_PU (BIT(8))
|
||||
#define FUN_PU_M (BIT(8))
|
||||
#define FUN_PU_V 1
|
||||
#define FUN_PU_S 8
|
||||
/* Input enable */
|
||||
#define FUN_IE (BIT(9))
|
||||
#define FUN_IE_M (FUN_IE_V << FUN_IE_S)
|
||||
#define FUN_IE_V 1
|
||||
#define FUN_IE_S 9
|
||||
/* Drive strength */
|
||||
#define FUN_DRV 0x3
|
||||
#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)
|
||||
#define FUN_DRV_V 0x3
|
||||
#define FUN_DRV_S 10
|
||||
/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */
|
||||
#define MCU_SEL 0x7
|
||||
#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
|
||||
#define MCU_SEL_V 0x7
|
||||
#define MCU_SEL_S 12
|
||||
/* Pin filter (Pulse width shorter than 2 clock cycles will be filtered out) */
|
||||
#define FILTER_EN (BIT(15))
|
||||
#define FILTER_EN_M (FILTER_EN_V << FILTER_EN_S)
|
||||
#define FILTER_EN_V 1
|
||||
#define FILTER_EN_S 15
|
||||
|
||||
#define PIN_SLP_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_IE)
|
||||
#define PIN_SLP_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE)
|
||||
#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_OE)
|
||||
#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE)
|
||||
#define PIN_SLP_PULLUP_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PU)
|
||||
#define PIN_SLP_PULLUP_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU)
|
||||
#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PD)
|
||||
#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD)
|
||||
#define PIN_SLP_SEL_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_SEL)
|
||||
#define PIN_SLP_SEL_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL)
|
||||
|
||||
#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
|
||||
#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
|
||||
#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
|
||||
#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU)
|
||||
#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU)
|
||||
#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD)
|
||||
#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD)
|
||||
#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
|
||||
#define PIN_FILTER_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FILTER_EN)
|
||||
#define PIN_FILTER_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FILTER_EN)
|
||||
|
||||
#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_GPIO0_U
|
||||
#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_GPIO1_U
|
||||
#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_GPIO2_U
|
||||
#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_GPIO3_U
|
||||
#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_GPIO4_U
|
||||
#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_GPIO5_U
|
||||
#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_GPIO6_U
|
||||
#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_GPIO7_U
|
||||
#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_GPIO8_U
|
||||
#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_GPIO9_U
|
||||
#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_GPIO10_U
|
||||
#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_GPIO11_U
|
||||
#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_GPIO12_U
|
||||
#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_GPIO13_U
|
||||
#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_GPIO14_U
|
||||
#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_XTAL_32K_P_U
|
||||
#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_XTAL_32K_N_U
|
||||
#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_DAC_1_U
|
||||
#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_DAC_2_U
|
||||
#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_GPIO19_U
|
||||
#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_GPIO20_U
|
||||
#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_GPIO21_U
|
||||
#define IO_MUX_GPIO26_REG PERIPHS_IO_MUX_SPICS1_U
|
||||
#define IO_MUX_GPIO27_REG PERIPHS_IO_MUX_SPIHD_U
|
||||
#define IO_MUX_GPIO28_REG PERIPHS_IO_MUX_SPIWP_U
|
||||
#define IO_MUX_GPIO29_REG PERIPHS_IO_MUX_SPICS0_U
|
||||
#define IO_MUX_GPIO30_REG PERIPHS_IO_MUX_SPICLK_U
|
||||
#define IO_MUX_GPIO31_REG PERIPHS_IO_MUX_SPIQ_U
|
||||
#define IO_MUX_GPIO32_REG PERIPHS_IO_MUX_SPID_U
|
||||
#define IO_MUX_GPIO33_REG PERIPHS_IO_MUX_GPIO33_U
|
||||
#define IO_MUX_GPIO34_REG PERIPHS_IO_MUX_GPIO34_U
|
||||
#define IO_MUX_GPIO35_REG PERIPHS_IO_MUX_GPIO35_U
|
||||
#define IO_MUX_GPIO36_REG PERIPHS_IO_MUX_GPIO36_U
|
||||
#define IO_MUX_GPIO37_REG PERIPHS_IO_MUX_GPIO37_U
|
||||
#define IO_MUX_GPIO38_REG PERIPHS_IO_MUX_GPIO38_U
|
||||
#define IO_MUX_GPIO39_REG PERIPHS_IO_MUX_MTCK_U
|
||||
#define IO_MUX_GPIO40_REG PERIPHS_IO_MUX_MTDO_U
|
||||
#define IO_MUX_GPIO41_REG PERIPHS_IO_MUX_MTDI_U
|
||||
#define IO_MUX_GPIO42_REG PERIPHS_IO_MUX_MTMS_U
|
||||
#define IO_MUX_GPIO43_REG PERIPHS_IO_MUX_U0TXD_U
|
||||
#define IO_MUX_GPIO44_REG PERIPHS_IO_MUX_U0RXD_U
|
||||
#define IO_MUX_GPIO45_REG PERIPHS_IO_MUX_GPIO45_U
|
||||
#define IO_MUX_GPIO46_REG PERIPHS_IO_MUX_GPIO46_U
|
||||
#define IO_MUX_GPIO47_REG PERIPHS_IO_MUX_SPICLK_P_U
|
||||
#define IO_MUX_GPIO48_REG PERIPHS_IO_MUX_SPICLK_N_U
|
||||
|
||||
#define PIN_FUNC_GPIO 1
|
||||
|
||||
#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
|
||||
#define GPIO_PAD_PULLUP(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
|
||||
#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
|
||||
|
||||
#define SPI_CS1_GPIO_NUM 26
|
||||
#define SPI_HD_GPIO_NUM 27
|
||||
#define SPI_WP_GPIO_NUM 28
|
||||
#define SPI_CS0_GPIO_NUM 29
|
||||
#define SPI_CLK_GPIO_NUM 30
|
||||
#define SPI_Q_GPIO_NUM 31
|
||||
#define SPI_D_GPIO_NUM 32
|
||||
#define SPI_D4_GPIO_NUM 33
|
||||
#define SPI_D5_GPIO_NUM 34
|
||||
#define SPI_D6_GPIO_NUM 35
|
||||
#define SPI_D7_GPIO_NUM 36
|
||||
#define SPI_DQS_GPIO_NUM 37
|
||||
#define SD_CLK_GPIO_NUM 12
|
||||
#define SD_CMD_GPIO_NUM 11
|
||||
#define SD_DATA0_GPIO_NUM 13
|
||||
#define SD_DATA1_GPIO_NUM 14
|
||||
#define SD_DATA2_GPIO_NUM 9
|
||||
#define SD_DATA3_GPIO_NUM 10
|
||||
#define USB_INT_PHY0_DM_GPIO_NUM 19
|
||||
#define USB_INT_PHY0_DP_GPIO_NUM 20
|
||||
#define XTAL32K_P_GPIO_NUM 15
|
||||
#define XTAL32K_N_GPIO_NUM 16
|
||||
|
||||
#define MAX_RTC_GPIO_NUM 21
|
||||
#define MAX_PAD_GPIO_NUM 48
|
||||
#define MAX_GPIO_NUM 53
|
||||
|
||||
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
|
||||
#define PIN_CTRL (REG_IO_MUX_BASE +0x00)
|
||||
#define PAD_POWER_SEL BIT(15)
|
||||
#define PAD_POWER_SEL_V 0x1
|
||||
#define PAD_POWER_SEL_M BIT(15)
|
||||
#define PAD_POWER_SEL_S 15
|
||||
|
||||
|
||||
#define PAD_POWER_SWITCH_DELAY 0x7
|
||||
#define PAD_POWER_SWITCH_DELAY_V 0x7
|
||||
#define PAD_POWER_SWITCH_DELAY_M (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S)
|
||||
#define PAD_POWER_SWITCH_DELAY_S 12
|
||||
|
||||
|
||||
#define CLK_OUT3 0xf
|
||||
#define CLK_OUT3_V CLK_OUT3
|
||||
#define CLK_OUT3_S 8
|
||||
#define CLK_OUT3_M (CLK_OUT3_V << CLK_OUT3_S)
|
||||
#define CLK_OUT2 0xf
|
||||
#define CLK_OUT2_V CLK_OUT2
|
||||
#define CLK_OUT2_S 4
|
||||
#define CLK_OUT2_M (CLK_OUT2_V << CLK_OUT2_S)
|
||||
#define CLK_OUT1 0xf
|
||||
#define CLK_OUT1_V CLK_OUT1
|
||||
#define CLK_OUT1_S 0
|
||||
#define CLK_OUT1_M (CLK_OUT1_V << CLK_OUT1_S)
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO0_U (REG_IO_MUX_BASE +0x04)
|
||||
#define FUNC_GPIO0_GPIO0 1
|
||||
#define FUNC_GPIO0_GPIO0_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO1_U (REG_IO_MUX_BASE +0x08)
|
||||
#define FUNC_GPIO1_GPIO1 1
|
||||
#define FUNC_GPIO1_GPIO1_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO2_U (REG_IO_MUX_BASE +0x0c)
|
||||
#define FUNC_GPIO2_GPIO2 1
|
||||
#define FUNC_GPIO2_GPIO2_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO3_U (REG_IO_MUX_BASE +0x10)
|
||||
#define FUNC_GPIO3_GPIO3 1
|
||||
#define FUNC_GPIO3_GPIO3_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO4_U (REG_IO_MUX_BASE +0x14)
|
||||
#define FUNC_GPIO4_GPIO4 1
|
||||
#define FUNC_GPIO4_GPIO4_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO5_U (REG_IO_MUX_BASE +0x18)
|
||||
#define FUNC_GPIO5_GPIO5 1
|
||||
#define FUNC_GPIO5_GPIO5_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO6_U (REG_IO_MUX_BASE +0x1c)
|
||||
#define FUNC_GPIO6_GPIO6 1
|
||||
#define FUNC_GPIO6_GPIO6_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO7_U (REG_IO_MUX_BASE +0x20)
|
||||
#define FUNC_GPIO7_GPIO7 1
|
||||
#define FUNC_GPIO7_GPIO7_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO8_U (REG_IO_MUX_BASE +0x24)
|
||||
#define FUNC_GPIO8_SUBSPICS1 3
|
||||
#define FUNC_GPIO8_GPIO8 1
|
||||
#define FUNC_GPIO8_GPIO8_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO9_U (REG_IO_MUX_BASE +0x28)
|
||||
#define FUNC_GPIO9_FSPIHD 4
|
||||
#define FUNC_GPIO9_SUBSPIHD 3
|
||||
#define FUNC_GPIO9_GPIO9 1
|
||||
#define FUNC_GPIO9_GPIO9_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO10_U (REG_IO_MUX_BASE +0x2c)
|
||||
#define FUNC_GPIO10_FSPICS0 4
|
||||
#define FUNC_GPIO10_SUBSPICS0 3
|
||||
#define FUNC_GPIO10_FSPIIO4 2
|
||||
#define FUNC_GPIO10_GPIO10 1
|
||||
#define FUNC_GPIO10_GPIO10_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO11_U (REG_IO_MUX_BASE +0x30)
|
||||
#define FUNC_GPIO11_FSPID 4
|
||||
#define FUNC_GPIO11_SUBSPID 3
|
||||
#define FUNC_GPIO11_FSPIIO5 2
|
||||
#define FUNC_GPIO11_GPIO11 1
|
||||
#define FUNC_GPIO11_GPIO11_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO12_U (REG_IO_MUX_BASE +0x34)
|
||||
#define FUNC_GPIO12_FSPICLK 4
|
||||
#define FUNC_GPIO12_SUBSPICLK 3
|
||||
#define FUNC_GPIO12_FSPIIO6 2
|
||||
#define FUNC_GPIO12_GPIO12 1
|
||||
#define FUNC_GPIO12_GPIO12_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO13_U (REG_IO_MUX_BASE +0x38)
|
||||
#define FUNC_GPIO13_FSPIQ 4
|
||||
#define FUNC_GPIO13_SUBSPIQ 3
|
||||
#define FUNC_GPIO13_FSPIIO7 2
|
||||
#define FUNC_GPIO13_GPIO13 1
|
||||
#define FUNC_GPIO13_GPIO13_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO14_U (REG_IO_MUX_BASE +0x3c)
|
||||
#define FUNC_GPIO14_FSPIWP 4
|
||||
#define FUNC_GPIO14_SUBSPIWP 3
|
||||
#define FUNC_GPIO14_FSPIDQS 2
|
||||
#define FUNC_GPIO14_GPIO14 1
|
||||
#define FUNC_GPIO14_GPIO14_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_XTAL_32K_P_U (REG_IO_MUX_BASE +0x40)
|
||||
#define FUNC_XTAL_32K_P_U0RTS 2
|
||||
#define FUNC_XTAL_32K_P_GPIO15 1
|
||||
#define FUNC_XTAL_32K_P_GPIO15_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_XTAL_32K_N_U (REG_IO_MUX_BASE +0x44)
|
||||
#define FUNC_XTAL_32K_N_U0CTS 2
|
||||
#define FUNC_XTAL_32K_N_GPIO16 1
|
||||
#define FUNC_XTAL_32K_N_GPIO16_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_DAC_1_U (REG_IO_MUX_BASE +0x48)
|
||||
#define FUNC_DAC_1_U1TXD 2
|
||||
#define FUNC_DAC_1_GPIO17 1
|
||||
#define FUNC_DAC_1_GPIO17_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_DAC_2_U (REG_IO_MUX_BASE +0x4c)
|
||||
#define FUNC_DAC_2_CLK_OUT3 3
|
||||
#define FUNC_DAC_2_U1RXD 2
|
||||
#define FUNC_DAC_2_GPIO18 1
|
||||
#define FUNC_DAC_2_GPIO18_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO19_U (REG_IO_MUX_BASE +0x50)
|
||||
#define FUNC_GPIO19_CLK_OUT2 3
|
||||
#define FUNC_GPIO19_U1RTS 2
|
||||
#define FUNC_GPIO19_GPIO19 1
|
||||
#define FUNC_GPIO19_GPIO19_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO20_U (REG_IO_MUX_BASE +0x54)
|
||||
#define FUNC_GPIO20_CLK_OUT1 3
|
||||
#define FUNC_GPIO20_U1CTS 2
|
||||
#define FUNC_GPIO20_GPIO20 1
|
||||
#define FUNC_GPIO20_GPIO20_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO21_U (REG_IO_MUX_BASE +0x58)
|
||||
#define FUNC_GPIO21_GPIO21 1
|
||||
#define FUNC_GPIO21_GPIO21_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_SPICS1_U (REG_IO_MUX_BASE +0x6c)
|
||||
#define FUNC_SPICS1_GPIO26 1
|
||||
#define FUNC_SPICS1_SPICS1 0
|
||||
|
||||
#define PERIPHS_IO_MUX_SPIHD_U (REG_IO_MUX_BASE +0x70)
|
||||
#define FUNC_SPIHD_GPIO27 1
|
||||
#define FUNC_SPIHD_SPIHD 0
|
||||
|
||||
#define PERIPHS_IO_MUX_SPIWP_U (REG_IO_MUX_BASE +0x74)
|
||||
#define FUNC_SPIWP_GPIO28 1
|
||||
#define FUNC_SPIWP_SPIWP 0
|
||||
|
||||
#define PERIPHS_IO_MUX_SPICS0_U (REG_IO_MUX_BASE +0x78)
|
||||
#define FUNC_SPICS0_GPIO29 1
|
||||
#define FUNC_SPICS0_SPICS0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_SPICLK_U (REG_IO_MUX_BASE +0x7c)
|
||||
#define FUNC_SPICLK_GPIO30 1
|
||||
#define FUNC_SPICLK_SPICLK 0
|
||||
|
||||
#define PERIPHS_IO_MUX_SPIQ_U (REG_IO_MUX_BASE +0x80)
|
||||
#define FUNC_SPIQ_GPIO31 1
|
||||
#define FUNC_SPIQ_SPIQ 0
|
||||
|
||||
#define PERIPHS_IO_MUX_SPID_U (REG_IO_MUX_BASE +0x84)
|
||||
#define FUNC_SPID_GPIO32 1
|
||||
#define FUNC_SPID_SPID 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO33_U (REG_IO_MUX_BASE +0x88)
|
||||
#define FUNC_GPIO33_SPIIO4 4
|
||||
#define FUNC_GPIO33_SUBSPIHD 3
|
||||
#define FUNC_GPIO33_FSPIHD 2
|
||||
#define FUNC_GPIO33_GPIO33 1
|
||||
#define FUNC_GPIO33_GPIO33_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO34_U (REG_IO_MUX_BASE +0x8c)
|
||||
#define FUNC_GPIO34_SPIIO5 4
|
||||
#define FUNC_GPIO34_SUBSPICS0 3
|
||||
#define FUNC_GPIO34_FSPICS0 2
|
||||
#define FUNC_GPIO34_GPIO34 1
|
||||
#define FUNC_GPIO34_GPIO34_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO35_U (REG_IO_MUX_BASE +0x90)
|
||||
#define FUNC_GPIO35_SPIIO6 4
|
||||
#define FUNC_GPIO35_SUBSPID 3
|
||||
#define FUNC_GPIO35_FSPID 2
|
||||
#define FUNC_GPIO35_GPIO35 1
|
||||
#define FUNC_GPIO35_GPIO35_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO36_U (REG_IO_MUX_BASE +0x94)
|
||||
#define FUNC_GPIO36_SPIIO7 4
|
||||
#define FUNC_GPIO36_SUBSPICLK 3
|
||||
#define FUNC_GPIO36_FSPICLK 2
|
||||
#define FUNC_GPIO36_GPIO36 1
|
||||
#define FUNC_GPIO36_GPIO36_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO37_U (REG_IO_MUX_BASE +0x98)
|
||||
#define FUNC_GPIO37_SPIDQS 4
|
||||
#define FUNC_GPIO37_SUBSPIQ 3
|
||||
#define FUNC_GPIO37_FSPIQ 2
|
||||
#define FUNC_GPIO37_GPIO37 1
|
||||
#define FUNC_GPIO37_GPIO37_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO38_U (REG_IO_MUX_BASE +0x9c)
|
||||
#define FUNC_GPIO38_SUBSPIWP 3
|
||||
#define FUNC_GPIO38_FSPIWP 2
|
||||
#define FUNC_GPIO38_GPIO38 1
|
||||
#define FUNC_GPIO38_GPIO38_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_MTCK_U (REG_IO_MUX_BASE +0xa0)
|
||||
#define FUNC_MTCK_SUBSPICS1 3
|
||||
#define FUNC_MTCK_CLK_OUT3 2
|
||||
#define FUNC_MTCK_GPIO39 1
|
||||
#define FUNC_MTCK_MTCK 0
|
||||
|
||||
#define PERIPHS_IO_MUX_MTDO_U (REG_IO_MUX_BASE +0xa4)
|
||||
#define FUNC_MTDO_CLK_OUT2 2
|
||||
#define FUNC_MTDO_GPIO40 1
|
||||
#define FUNC_MTDO_MTDO 0
|
||||
|
||||
#define PERIPHS_IO_MUX_MTDI_U (REG_IO_MUX_BASE +0xa8)
|
||||
#define FUNC_MTDI_CLK_OUT1 2
|
||||
#define FUNC_MTDI_GPIO41 1
|
||||
#define FUNC_MTDI_MTDI 0
|
||||
|
||||
#define PERIPHS_IO_MUX_MTMS_U (REG_IO_MUX_BASE +0xac)
|
||||
#define FUNC_MTMS_GPIO42 1
|
||||
#define FUNC_MTMS_MTMS 0
|
||||
|
||||
#define PERIPHS_IO_MUX_U0TXD_U (REG_IO_MUX_BASE +0xb0)
|
||||
#define FUNC_U0TXD_CLK_OUT1 2
|
||||
#define FUNC_U0TXD_GPIO43 1
|
||||
#define FUNC_U0TXD_U0TXD 0
|
||||
|
||||
#define PERIPHS_IO_MUX_U0RXD_U (REG_IO_MUX_BASE +0xb4)
|
||||
#define FUNC_U0RXD_CLK_OUT2 2
|
||||
#define FUNC_U0RXD_GPIO44 1
|
||||
#define FUNC_U0RXD_U0RXD 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO45_U (REG_IO_MUX_BASE +0xb8)
|
||||
#define FUNC_GPIO45_GPIO45 1
|
||||
#define FUNC_GPIO45_GPIO45_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO46_U (REG_IO_MUX_BASE +0xbc)
|
||||
#define FUNC_GPIO46_GPIO46 1
|
||||
#define FUNC_GPIO46_GPIO46_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_SPICLK_P_U (REG_IO_MUX_BASE +0xc0)
|
||||
#define FUNC_SPICLK_P_SUBSPICLK_DIFF 2
|
||||
#define FUNC_SPICLK_P_GPIO47 1
|
||||
#define FUNC_SPICLK_P_SPICLK_DIFF 0
|
||||
|
||||
#define PERIPHS_IO_MUX_SPICLK_N_U (REG_IO_MUX_BASE +0xc4)
|
||||
#define FUNC_SPICLK_N_SUBSPICLK_DIFF 2
|
||||
#define FUNC_SPICLK_N_GPIO48 1
|
||||
#define FUNC_SPICLK_N_SPICLK_DIFF 0
|
||||
|
||||
|
||||
#define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0xfc)
|
||||
#define IO_MUX_DATE 0xFFFFFFFF
|
||||
#define IO_MUX_DATE_S 0
|
||||
#define IO_MUX_DATE_VERSION 0x1907160
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,795 +0,0 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Group: LCD configuration registers */
|
||||
/** Type of lcd_clock register
|
||||
* LCD clock configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** lcd_clkcnt_n : R/W; bitpos: [5:0]; default: 0;
|
||||
* f<SUB>LCD_PCLK</SUB>
|
||||
* = f<SUB>LCD_CLK</SUB>/(LCD_CAM_LCD_CLKCNT_N + 1) when LCD_CAM_LCD_CLK_EQU_SYSCLK is
|
||||
* 0. Note: this field must not be configured to 0.
|
||||
*/
|
||||
uint32_t lcd_clkcnt_n: 6;
|
||||
/** lcd_clk_equ_sysclk : R/W; bitpos: [6]; default: 0;
|
||||
* 1: f<SUB>LCD_PCLK</SUB>
|
||||
* = f<SUB>LCD_CLK</SUB>. 0: f<SUB>LCD_PCLK</SUB>
|
||||
* = f<SUB>LCD_CLK</SUB>/(LCD_CAM_LCD_CLKCNT_N + 1).
|
||||
*/
|
||||
uint32_t lcd_clk_equ_sysclk: 1;
|
||||
/** lcd_ck_idle_edge : R/W; bitpos: [7]; default: 0;
|
||||
* 1: LCD_PCLK line is high in idle. 0: LCD_PCLK line is low in idle.
|
||||
*/
|
||||
uint32_t lcd_ck_idle_edge: 1;
|
||||
/** lcd_ck_out_edge : R/W; bitpos: [8]; default: 0;
|
||||
* 1: LCD_PCLK is high in the first half clock cycle. 0: LCD_PCLK is low in the first
|
||||
* half clock cycle.
|
||||
*/
|
||||
uint32_t lcd_ck_out_edge: 1;
|
||||
/** lcd_clkm_div_num : R/W; bitpos: [16:9]; default: 0;
|
||||
* Integral LCD clock divider value.
|
||||
*/
|
||||
uint32_t lcd_clkm_div_num: 8;
|
||||
/** lcd_clkm_div_b : R/W; bitpos: [22:17]; default: 0;
|
||||
* Fractional clock divider numerator value.
|
||||
*/
|
||||
uint32_t lcd_clkm_div_b: 6;
|
||||
/** lcd_clkm_div_a : R/W; bitpos: [28:23]; default: 0;
|
||||
* Fractional clock divider denominator value.
|
||||
*/
|
||||
uint32_t lcd_clkm_div_a: 6;
|
||||
/** lcd_clk_sel : R/W; bitpos: [30:29]; default: 0;
|
||||
* Select LCD module source clock. 0: clock source is disabled. 1: XTAL_CLK. 2:
|
||||
* PLL_D2_CLK. 3: PLL_F160M_CLK.
|
||||
*/
|
||||
uint32_t lcd_clk_sel: 2;
|
||||
/** clk_en : R/W; bitpos: [31]; default: 0;
|
||||
* Set this bit to force enable the clock for all configuration registers. Clock gate
|
||||
* is not used.
|
||||
*/
|
||||
uint32_t clk_en: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} lcd_cam_lcd_clock_reg_t;
|
||||
|
||||
/** Type of lcd_rgb_yuv register
|
||||
* LCD data format conversion register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0: 20;
|
||||
/** lcd_conv_8bits_data_inv : R/W; bitpos: [20]; default: 0;
|
||||
* Swap every two 8-bit input data. 1: Enabled. 0: Disabled.
|
||||
*/
|
||||
uint32_t lcd_conv_8bits_data_inv: 1;
|
||||
/** lcd_conv_txtorx : R/W; bitpos: [21]; default: 0;
|
||||
* 0: txtorx mode off. 1: txtorx mode on.
|
||||
*/
|
||||
uint32_t lcd_conv_txtorx: 1;
|
||||
/** lcd_conv_yuv2yuv_mode : R/W; bitpos: [23:22]; default: 0;
|
||||
* In YUV-to-YUV mode, 0: data is converted to YUV422 format. 1: data is converted to
|
||||
* YUV420 format. 2: data is converted to YUV411 format. 3: disabled. To enable
|
||||
* YUV-to-YUV mode, LCD_CAM_LCD_CONV_TRANS_MODE must be set to 1.
|
||||
*/
|
||||
uint32_t lcd_conv_yuv2yuv_mode: 2;
|
||||
/** lcd_conv_yuv_mode : R/W; bitpos: [25:24]; default: 0;
|
||||
* In YUV-to-YUV mode and YUV-to-RGB mode, LCD_CAM_LCD_CONV_YUV_MODE decides the YUV
|
||||
* mode of input data. 0: input data is in YUV422 format. 1: input data is in YUV420
|
||||
* format. 2: input data is in YUV411 format. In RGB-to-YUV mode, 0: data is converted
|
||||
* to YUV422 format. 1: data is converted to YUV420 format. 2: data is converted to
|
||||
* YUV411 format.
|
||||
*/
|
||||
uint32_t lcd_conv_yuv_mode: 2;
|
||||
/** lcd_conv_protocol_mode : R/W; bitpos: [26]; default: 0;
|
||||
* 0: BT601. 1: BT709.
|
||||
*/
|
||||
uint32_t lcd_conv_protocol_mode: 1;
|
||||
/** lcd_conv_data_out_mode : R/W; bitpos: [27]; default: 0;
|
||||
* Configure color range for output data. 0: limited color range. 1: full color range.
|
||||
*/
|
||||
uint32_t lcd_conv_data_out_mode: 1;
|
||||
/** lcd_conv_data_in_mode : R/W; bitpos: [28]; default: 0;
|
||||
* Configure color range for input data. 0: limited color range. 1: full color range.
|
||||
*/
|
||||
uint32_t lcd_conv_data_in_mode: 1;
|
||||
/** lcd_conv_mode_8bits_on : R/W; bitpos: [29]; default: 0;
|
||||
* 0: 16-bit mode. 1: 8-bit mode.
|
||||
*/
|
||||
uint32_t lcd_conv_mode_8bits_on: 1;
|
||||
/** lcd_conv_trans_mode : R/W; bitpos: [30]; default: 0;
|
||||
* 0: converted to RGB format. 1: converted to YUV format.
|
||||
*/
|
||||
uint32_t lcd_conv_trans_mode: 1;
|
||||
/** lcd_conv_bypass : R/W; bitpos: [31]; default: 0;
|
||||
* 0: Bypass converter. 1: Enable converter.
|
||||
*/
|
||||
uint32_t lcd_conv_bypass: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} lcd_cam_lcd_rgb_yuv_reg_t;
|
||||
|
||||
/** Type of lcd_user register
|
||||
* LCD user configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** lcd_dout_cyclelen : R/W; bitpos: [12:0]; default: 0;
|
||||
* Configure the cycles for DOUT phase of LCD module. The cycles = this value + 1.
|
||||
*/
|
||||
uint32_t lcd_dout_cyclelen: 13;
|
||||
/** lcd_always_out_en : R/W; bitpos: [13]; default: 0;
|
||||
* LCD continues outputting data when LCD is in DOUT phase, till LCD_CAM_LCD_START is
|
||||
* cleared or LCD_CAM_LCD_RESET is set.
|
||||
*/
|
||||
uint32_t lcd_always_out_en: 1;
|
||||
uint32_t reserved_14: 5;
|
||||
/** lcd_8bits_order : R/W; bitpos: [19]; default: 0;
|
||||
* 1: Swap every two data bytes, valid in 8-bit mode. 0: Do not swap.
|
||||
*/
|
||||
uint32_t lcd_8bits_order: 1;
|
||||
/** lcd_update : R/W; bitpos: [20]; default: 0;
|
||||
* 1: Update LCD registers. This bit is cleared by hardware. 0: Do not care.
|
||||
*/
|
||||
uint32_t lcd_update: 1;
|
||||
/** lcd_bit_order : R/W; bitpos: [21]; default: 0;
|
||||
* 1: Change data bit order. Change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in 8-bit
|
||||
* mode, and bits[15:0] to bits[0:15] in 16-bit mode. 0: Do not change.
|
||||
*/
|
||||
uint32_t lcd_bit_order: 1;
|
||||
/** lcd_byte_order : R/W; bitpos: [22]; default: 0;
|
||||
* 1: Invert data byte order, only valid in 16-bit mode. 0: Do not invert.
|
||||
*/
|
||||
uint32_t lcd_byte_order: 1;
|
||||
/** lcd_2byte_en : R/W; bitpos: [23]; default: 0;
|
||||
* 1: The width of output LCD data is 16 bits. 0: The width of output LCD data is 8
|
||||
* bits.
|
||||
*/
|
||||
uint32_t lcd_2byte_en: 1;
|
||||
/** lcd_dout : R/W; bitpos: [24]; default: 0;
|
||||
* 1: Be able to send data out in LCD sequence when LCD starts. 0: Disable.
|
||||
*/
|
||||
uint32_t lcd_dout: 1;
|
||||
/** lcd_dummy : R/W; bitpos: [25]; default: 0;
|
||||
* 1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable.
|
||||
*/
|
||||
uint32_t lcd_dummy: 1;
|
||||
/** lcd_cmd : R/W; bitpos: [26]; default: 0;
|
||||
* 1: Be able to send command in LCD sequence when LCD starts. 0: Disable.
|
||||
*/
|
||||
uint32_t lcd_cmd: 1;
|
||||
/** lcd_start : R/W; bitpos: [27]; default: 0;
|
||||
* LCD starts sending data enable signal, valid in high level.
|
||||
*/
|
||||
uint32_t lcd_start: 1;
|
||||
/** lcd_reset : WO; bitpos: [28]; default: 0;
|
||||
* Reset LCD module.
|
||||
*/
|
||||
uint32_t lcd_reset: 1;
|
||||
/** lcd_dummy_cyclelen : R/W; bitpos: [30:29]; default: 0;
|
||||
* Configure DUMMY cycles. DUMMY cycles = this value + 1.
|
||||
*/
|
||||
uint32_t lcd_dummy_cyclelen: 2;
|
||||
/** lcd_cmd_2_cycle_en : R/W; bitpos: [31]; default: 0;
|
||||
* The cycle length of command phase. 1: 2 cycles. 0: 1 cycle.
|
||||
*/
|
||||
uint32_t lcd_cmd_2_cycle_en: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} lcd_cam_lcd_user_reg_t;
|
||||
|
||||
/** Type of lcd_misc register
|
||||
* LCD MISC configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0: 1;
|
||||
/** lcd_afifo_threshold_num : R/W; bitpos: [5:1]; default: 17;
|
||||
* Set the threshold for Async Tx FIFO full event.
|
||||
*/
|
||||
uint32_t lcd_afifo_threshold_num: 5;
|
||||
/** lcd_vfk_cyclelen : R/W; bitpos: [11:6]; default: 0;
|
||||
* Configure the setup cycles in LCD non-RGB mode. Setup cycles expected = this value
|
||||
* + 1.
|
||||
*/
|
||||
uint32_t lcd_vfk_cyclelen: 6;
|
||||
/** lcd_vbk_cyclelen : R/W; bitpos: [24:12]; default: 0;
|
||||
* Configure the hold time cycles in LCD non-RGB mode. Hold cycles expected = this
|
||||
* value + 1. %Configure the cycles for vertical back blank region in LCD RGB mode,
|
||||
* the cycles = this value + 1. Or configure the hold time cycles in LCD non-RGB mode,
|
||||
* the cycles = this value + 1.
|
||||
*/
|
||||
uint32_t lcd_vbk_cyclelen: 13;
|
||||
/** lcd_next_frame_en : R/W; bitpos: [25]; default: 0;
|
||||
* 1: Send the next frame data when the current frame is sent out. 0: LCD stops when
|
||||
* the current frame is sent out.
|
||||
*/
|
||||
uint32_t lcd_next_frame_en: 1;
|
||||
/** lcd_bk_en : R/W; bitpos: [26]; default: 0;
|
||||
* 1: Enable blank region when LCD sends data out. 0: No blank region.
|
||||
*/
|
||||
uint32_t lcd_bk_en: 1;
|
||||
/** lcd_afifo_reset : WO; bitpos: [27]; default: 0;
|
||||
* Async Tx FIFO reset signal.
|
||||
*/
|
||||
uint32_t lcd_afifo_reset: 1;
|
||||
/** lcd_cd_data_set : R/W; bitpos: [28]; default: 0;
|
||||
* 1: LCD_CD = !LCD_CAM_LCD_CD_IDLE_EDGE when LCD is in DOUT phase. 0: LCD_CD =
|
||||
* LCD_CAM_LCD_CD_IDLE_EDGE.
|
||||
*/
|
||||
uint32_t lcd_cd_data_set: 1;
|
||||
/** lcd_cd_dummy_set : R/W; bitpos: [29]; default: 0;
|
||||
* 1: LCD_CD = !LCD_CAM_LCD_CD_IDLE_EDGE when LCD is in DUMMY phase. 0: LCD_CD =
|
||||
* LCD_CAM_LCD_CD_IDLE_EDGE.
|
||||
*/
|
||||
uint32_t lcd_cd_dummy_set: 1;
|
||||
/** lcd_cd_cmd_set : R/W; bitpos: [30]; default: 0;
|
||||
* 1: LCD_CD = !LCD_CAM_LCD_CD_IDLE_EDGE when LCD is in CMD phase. 0: LCD_CD =
|
||||
* LCD_CAM_LCD_CD_IDLE_EDGE.
|
||||
*/
|
||||
uint32_t lcd_cd_cmd_set: 1;
|
||||
/** lcd_cd_idle_edge : R/W; bitpos: [31]; default: 0;
|
||||
* The default value of LCD_CD.
|
||||
*/
|
||||
uint32_t lcd_cd_idle_edge: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} lcd_cam_lcd_misc_reg_t;
|
||||
|
||||
/** Type of lcd_ctrl register
|
||||
* LCD signal configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** lcd_hb_front : R/W; bitpos: [10:0]; default: 0;
|
||||
* It is the horizontal blank front porch of a frame.
|
||||
*/
|
||||
uint32_t lcd_hb_front: 11;
|
||||
/** lcd_va_height : R/W; bitpos: [20:11]; default: 0;
|
||||
* It is the vertical active height of a frame.
|
||||
*/
|
||||
uint32_t lcd_va_height: 10;
|
||||
/** lcd_vt_height : R/W; bitpos: [30:21]; default: 0;
|
||||
* It is the vertical total height of a frame.
|
||||
*/
|
||||
uint32_t lcd_vt_height: 10;
|
||||
/** lcd_rgb_mode_en : R/W; bitpos: [31]; default: 0;
|
||||
* 1: Enable RGB mode, and input VSYNC, HSYNC, and DE signals. 0: Disable.
|
||||
*/
|
||||
uint32_t lcd_rgb_mode_en: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} lcd_cam_lcd_ctrl_reg_t;
|
||||
|
||||
/** Type of lcd_ctrl1 register
|
||||
* LCD signal configuration register 1
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** lcd_vb_front : R/W; bitpos: [7:0]; default: 0;
|
||||
* It is the vertical blank front porch of a frame.
|
||||
*/
|
||||
uint32_t lcd_vb_front: 8;
|
||||
/** lcd_ha_width : R/W; bitpos: [19:8]; default: 0;
|
||||
* It is the horizontal active width of a frame.
|
||||
*/
|
||||
uint32_t lcd_ha_width: 12;
|
||||
/** lcd_ht_width : R/W; bitpos: [31:20]; default: 0;
|
||||
* It is the horizontal total width of a frame.
|
||||
*/
|
||||
uint32_t lcd_ht_width: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} lcd_cam_lcd_ctrl1_reg_t;
|
||||
|
||||
/** Type of lcd_ctrl2 register
|
||||
* LCD signal configuration register 2
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** lcd_vsync_width : R/W; bitpos: [6:0]; default: 0;
|
||||
* It is the width of LCD_VSYNC active pulse in a line.
|
||||
*/
|
||||
uint32_t lcd_vsync_width: 7;
|
||||
/** lcd_vsync_idle_pol : R/W; bitpos: [7]; default: 0;
|
||||
* It is the idle value of LCD_VSYNC.
|
||||
*/
|
||||
uint32_t lcd_vsync_idle_pol: 1;
|
||||
/** lcd_de_idle_pol : R/W; bitpos: [8]; default: 0;
|
||||
* It is the idle value of LCD_DE.
|
||||
*/
|
||||
uint32_t lcd_de_idle_pol: 1;
|
||||
/** lcd_hs_blank_en : R/W; bitpos: [9]; default: 0;
|
||||
* 1: The pulse of LCD_HSYNC is out in vertical blanking lines in RGB mode. 0:
|
||||
* LCD_HSYNC pulse is valid only in active region lines in RGB mode.
|
||||
*/
|
||||
uint32_t lcd_hs_blank_en: 1;
|
||||
uint32_t reserved_10: 6;
|
||||
/** lcd_hsync_width : R/W; bitpos: [22:16]; default: 0;
|
||||
* It is the width of LCD_HSYNC active pulse in a line.
|
||||
*/
|
||||
uint32_t lcd_hsync_width: 7;
|
||||
/** lcd_hsync_idle_pol : R/W; bitpos: [23]; default: 0;
|
||||
* It is the idle value of LCD_HSYNC.
|
||||
*/
|
||||
uint32_t lcd_hsync_idle_pol: 1;
|
||||
/** lcd_hsync_position : R/W; bitpos: [31:24]; default: 0;
|
||||
* It is the position of LCD_HSYNC active pulse in a line.
|
||||
*/
|
||||
uint32_t lcd_hsync_position: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} lcd_cam_lcd_ctrl2_reg_t;
|
||||
|
||||
/** Type of lcd_cmd_val register
|
||||
* LCD command value configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** lcd_cmd_value : R/W; bitpos: [31:0]; default: 0;
|
||||
* The LCD write command value.
|
||||
*/
|
||||
uint32_t lcd_cmd_value: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} lcd_cam_lcd_cmd_val_reg_t;
|
||||
|
||||
/** Type of lcd_dly_mode register
|
||||
* LCD signal delay configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** lcd_cd_mode : R/W; bitpos: [1:0]; default: 0;
|
||||
* The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delay. 1:
|
||||
* delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK.
|
||||
*/
|
||||
uint32_t lcd_cd_mode: 2;
|
||||
/** lcd_de_mode : R/W; bitpos: [3:2]; default: 0;
|
||||
* The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delay. 1:
|
||||
* delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK.
|
||||
*/
|
||||
uint32_t lcd_de_mode: 2;
|
||||
/** lcd_hsync_mode : R/W; bitpos: [5:4]; default: 0;
|
||||
* The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delay.
|
||||
* 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK.
|
||||
*/
|
||||
uint32_t lcd_hsync_mode: 2;
|
||||
/** lcd_vsync_mode : R/W; bitpos: [7:6]; default: 0;
|
||||
* The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delay.
|
||||
* 1: delayed by the rising edge of LCD_CLK. 2: delay by the falling edge of LCD_CLK.
|
||||
*/
|
||||
uint32_t lcd_vsync_mode: 2;
|
||||
uint32_t reserved_8: 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} lcd_cam_lcd_dly_mode_reg_t;
|
||||
|
||||
/** Type of lcd_data_dout_mode register
|
||||
* LCD data delay configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** dout0_mode : R/W; bitpos: [1:0]; default: 0;
|
||||
* The output data bit 0 is delayed by module clock LCD_CLK. 0: output without delay.
|
||||
* 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK.
|
||||
*/
|
||||
uint32_t dout0_mode: 2;
|
||||
/** dout1_mode : R/W; bitpos: [3:2]; default: 0;
|
||||
* The output data bit 1 is delayed by module clock LCD_CLK. 0: output without delay.
|
||||
* 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK.
|
||||
*/
|
||||
uint32_t dout1_mode: 2;
|
||||
/** dout2_mode : R/W; bitpos: [5:4]; default: 0;
|
||||
* The output data bit 2 is delayed by module clock LCD_CLK. 0: output without delay.
|
||||
* 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK.
|
||||
*/
|
||||
uint32_t dout2_mode: 2;
|
||||
/** dout3_mode : R/W; bitpos: [7:6]; default: 0;
|
||||
* The output data bit 3 is delayed by module clock LCD_CLK. 0: output without delay.
|
||||
* 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK.
|
||||
*/
|
||||
uint32_t dout3_mode: 2;
|
||||
/** dout4_mode : R/W; bitpos: [9:8]; default: 0;
|
||||
* The output data bit 4 is delayed by module clock LCD_CLK. 0: output without delay.
|
||||
* 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK.
|
||||
*/
|
||||
uint32_t dout4_mode: 2;
|
||||
/** dout5_mode : R/W; bitpos: [11:10]; default: 0;
|
||||
* The output data bit 5 is delayed by module clock LCD_CLK. 0: output without delay.
|
||||
* 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK.
|
||||
*/
|
||||
uint32_t dout5_mode: 2;
|
||||
/** dout6_mode : R/W; bitpos: [13:12]; default: 0;
|
||||
* The output data bit 6 is delayed by module clock LCD_CLK. 0: output without delay.
|
||||
* 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK.
|
||||
*/
|
||||
uint32_t dout6_mode: 2;
|
||||
/** dout7_mode : R/W; bitpos: [15:14]; default: 0;
|
||||
* The output data bit 7 is delayed by module clock LCD_CLK. 0: output without delay.
|
||||
* 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK.
|
||||
*/
|
||||
uint32_t dout7_mode: 2;
|
||||
/** dout8_mode : R/W; bitpos: [17:16]; default: 0;
|
||||
* The output data bit 8 is delayed by module clock LCD_CLK. 0: output without delay.
|
||||
* 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK.
|
||||
*/
|
||||
uint32_t dout8_mode: 2;
|
||||
/** dout9_mode : R/W; bitpos: [19:18]; default: 0;
|
||||
* The output data bit 9 is delayed by module clock LCD_CLK. 0: output without delay.
|
||||
* 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK.
|
||||
*/
|
||||
uint32_t dout9_mode: 2;
|
||||
/** dout10_mode : R/W; bitpos: [21:20]; default: 0;
|
||||
* The output data bit 10 is delayed by module clock LCD_CLK. 0: output without delay.
|
||||
* 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK.
|
||||
*/
|
||||
uint32_t dout10_mode: 2;
|
||||
/** dout11_mode : R/W; bitpos: [23:22]; default: 0;
|
||||
* The output data bit 11 is delayed by module clock LCD_CLK. 0: output without delay.
|
||||
* 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK.
|
||||
*/
|
||||
uint32_t dout11_mode: 2;
|
||||
/** dout12_mode : R/W; bitpos: [25:24]; default: 0;
|
||||
* The output data bit 12 is delayed by module clock LCD_CLK. 0: output without delay.
|
||||
* 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK.
|
||||
*/
|
||||
uint32_t dout12_mode: 2;
|
||||
/** dout13_mode : R/W; bitpos: [27:26]; default: 0;
|
||||
* The output data bit 13 is delayed by module clock LCD_CLK. 0: output without delay.
|
||||
* 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK.
|
||||
*/
|
||||
uint32_t dout13_mode: 2;
|
||||
/** dout14_mode : R/W; bitpos: [29:28]; default: 0;
|
||||
* The output data bit 14 is delayed by module clock LCD_CLK. 0: output without delay.
|
||||
* 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK.
|
||||
*/
|
||||
uint32_t dout14_mode: 2;
|
||||
/** dout15_mode : R/W; bitpos: [31:30]; default: 0;
|
||||
* The output data bit 15 is delayed by module clock LCD_CLK. 0: output without delay.
|
||||
* 1: delayed by the rising edge of LCD_CLK. 2: delayed by the falling edge of LCD_CLK.
|
||||
*/
|
||||
uint32_t dout15_mode: 2;
|
||||
};
|
||||
uint32_t val;
|
||||
} lcd_cam_lcd_data_dout_mode_reg_t;
|
||||
|
||||
|
||||
/** Group: Camera configuration registers */
|
||||
/** Type of cam_ctrl register
|
||||
* Camera clock configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** cam_stop_en : R/W; bitpos: [0]; default: 0;
|
||||
* Camera stop enable signal, 1: camera stops when GDMA Rx FIFO is full. 0: Do not
|
||||
* stop.
|
||||
*/
|
||||
uint32_t cam_stop_en: 1;
|
||||
/** cam_vsync_filter_thres : R/W; bitpos: [3:1]; default: 0;
|
||||
* Filter threshold value for CAM_VSYNC signal.
|
||||
*/
|
||||
uint32_t cam_vsync_filter_thres: 3;
|
||||
/** cam_update : R/W; bitpos: [4]; default: 0;
|
||||
* 1: Update camera registers. This bit is cleared by hardware. 0: Do not care.
|
||||
*/
|
||||
uint32_t cam_update: 1;
|
||||
/** cam_byte_order : R/W; bitpos: [5]; default: 0;
|
||||
* 1: Invert data byte order, only valid in 16-bit mode. 0: Do not change.
|
||||
*/
|
||||
uint32_t cam_byte_order: 1;
|
||||
/** cam_bit_order : R/W; bitpos: [6]; default: 0;
|
||||
* 1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in 8-bit
|
||||
* mode, and bits[15:0] to bits[0:15] in 16-bit mode. 0: Do not change.
|
||||
*/
|
||||
uint32_t cam_bit_order: 1;
|
||||
/** cam_line_int_en : R/W; bitpos: [7]; default: 0;
|
||||
* 1: Enable to generate LCD_CAM_CAM_HS_INT. 0: Disable.
|
||||
*/
|
||||
uint32_t cam_line_int_en: 1;
|
||||
/** cam_vs_eof_en : R/W; bitpos: [8]; default: 0;
|
||||
* 1: Enable CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by
|
||||
* LCD_CAM_CAM_REC_DATA_BYTELEN.
|
||||
*/
|
||||
uint32_t cam_vs_eof_en: 1;
|
||||
/** cam_clkm_div_num : R/W; bitpos: [16:9]; default: 0;
|
||||
* Integral camera clock divider value.
|
||||
*/
|
||||
uint32_t cam_clkm_div_num: 8;
|
||||
/** cam_clkm_div_b : R/W; bitpos: [22:17]; default: 0;
|
||||
* Fractional clock divider numerator value.
|
||||
*/
|
||||
uint32_t cam_clkm_div_b: 6;
|
||||
/** cam_clkm_div_a : R/W; bitpos: [28:23]; default: 0;
|
||||
* Fractional clock divider denominator value.
|
||||
*/
|
||||
uint32_t cam_clkm_div_a: 6;
|
||||
/** cam_clk_sel : R/W; bitpos: [30:29]; default: 0;
|
||||
* Select camera module source clock. 0: Clock source is disabled. 1: XTAL_CLK. 2:
|
||||
* PLL_D2_CLK. 3: PLL_F160M_CLK.
|
||||
*/
|
||||
uint32_t cam_clk_sel: 2;
|
||||
uint32_t reserved_31: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} lcd_cam_cam_ctrl_reg_t;
|
||||
|
||||
/** Type of cam_ctrl1 register
|
||||
* Camera control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** cam_rec_data_bytelen : R/W; bitpos: [15:0]; default: 0;
|
||||
* Configure camera received data byte length. When the length of received data
|
||||
* reaches this value + 1, GDMA in_suc_eof_int is triggered.
|
||||
*/
|
||||
uint32_t cam_rec_data_bytelen: 16;
|
||||
/** cam_line_int_num : R/W; bitpos: [21:16]; default: 0;
|
||||
* Configure line number. When the number of received lines reaches this value + 1,
|
||||
* LCD_CAM_CAM_HS_INT is triggered.
|
||||
*/
|
||||
uint32_t cam_line_int_num: 6;
|
||||
/** cam_clk_inv : R/W; bitpos: [22]; default: 0;
|
||||
* 1: Invert the input signal CAM_PCLK. 0: Do not invert.
|
||||
*/
|
||||
uint32_t cam_clk_inv: 1;
|
||||
/** cam_vsync_filter_en : R/W; bitpos: [23]; default: 0;
|
||||
* 1: Enable CAM_VSYNC filter function. 0: Bypass.
|
||||
*/
|
||||
uint32_t cam_vsync_filter_en: 1;
|
||||
/** cam_2byte_en : R/W; bitpos: [24]; default: 0;
|
||||
* 1: The width of input data is 16 bits. 0: The width of input data is 8 bits.
|
||||
*/
|
||||
uint32_t cam_2byte_en: 1;
|
||||
/** cam_de_inv : R/W; bitpos: [25]; default: 0;
|
||||
* CAM_DE invert enable signal, valid in high level.
|
||||
*/
|
||||
uint32_t cam_de_inv: 1;
|
||||
/** cam_hsync_inv : R/W; bitpos: [26]; default: 0;
|
||||
* CAM_HSYNC invert enable signal, valid in high level.
|
||||
*/
|
||||
uint32_t cam_hsync_inv: 1;
|
||||
/** cam_vsync_inv : R/W; bitpos: [27]; default: 0;
|
||||
* CAM_VSYNC invert enable signal, valid in high level.
|
||||
*/
|
||||
uint32_t cam_vsync_inv: 1;
|
||||
/** cam_vh_de_mode_en : R/W; bitpos: [28]; default: 0;
|
||||
* 1: Input control signals are CAM_DE and CAM_HSYNC. CAM_VSYNC is 1. 0: Input control
|
||||
* signals are CAM_DE and CAM_VSYNC. CAM_HSYNC and CAM_DE are all 1 at the the same
|
||||
* time.
|
||||
*/
|
||||
uint32_t cam_vh_de_mode_en: 1;
|
||||
/** cam_start : R/W; bitpos: [29]; default: 0;
|
||||
* Camera module start signal.
|
||||
*/
|
||||
uint32_t cam_start: 1;
|
||||
/** cam_reset : WO; bitpos: [30]; default: 0;
|
||||
* Camera module reset signal.
|
||||
*/
|
||||
uint32_t cam_reset: 1;
|
||||
/** cam_afifo_reset : WO; bitpos: [31]; default: 0;
|
||||
* Camera Async Rx FIFO reset signal.
|
||||
*/
|
||||
uint32_t cam_afifo_reset: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} lcd_cam_cam_ctrl1_reg_t;
|
||||
|
||||
/** Type of cam_rgb_yuv register
|
||||
* Camera data format conversion register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0: 21;
|
||||
/** cam_conv_8bits_data_inv : R/W; bitpos: [21]; default: 0;
|
||||
* Swap every two 8-bit input data. 1: Enabled. 0: Disabled.
|
||||
*/
|
||||
uint32_t cam_conv_8bits_data_inv: 1;
|
||||
/** cam_conv_yuv2yuv_mode : R/W; bitpos: [23:22]; default: 0;
|
||||
* In YUV-to-YUV mode, 0: data is converted to YUV422 format. 1: data is converted to
|
||||
* YUV420 format. 2: data is converted to YUV411 format. 3: disabled. To enable
|
||||
* YUV-to-YUV mode, LCD_CAM_CAM_CONV_TRANS_MODE must be set to 1.
|
||||
*/
|
||||
uint32_t cam_conv_yuv2yuv_mode: 2;
|
||||
/** cam_conv_yuv_mode : R/W; bitpos: [25:24]; default: 0;
|
||||
* In YUV-to-YUV mode and YUV-to-RGB mode, LCD_CAM_CAM_CONV_YUV_MODE decides the YUV
|
||||
* mode of input data. 0: input data is in YUV422 format. 1: input data is in YUV420
|
||||
* format. 2: input data is in YUV411 format. In RGB-to-YUV mode, 0: data is converted
|
||||
* to YUV422 format. 1: data is converted to YUV420 format. 2: data is converted to
|
||||
* YUV411 format.
|
||||
*/
|
||||
uint32_t cam_conv_yuv_mode: 2;
|
||||
/** cam_conv_protocol_mode : R/W; bitpos: [26]; default: 0;
|
||||
* 0: BT601. 1: BT709.
|
||||
*/
|
||||
uint32_t cam_conv_protocol_mode: 1;
|
||||
/** cam_conv_data_out_mode : R/W; bitpos: [27]; default: 0;
|
||||
* Configure color range for output data. 0: limited color range. 1: full color range.
|
||||
*/
|
||||
uint32_t cam_conv_data_out_mode: 1;
|
||||
/** cam_conv_data_in_mode : R/W; bitpos: [28]; default: 0;
|
||||
* Configure color range for input data. 0: limited color range. 1: full color range.
|
||||
*/
|
||||
uint32_t cam_conv_data_in_mode: 1;
|
||||
/** cam_conv_mode_8bits_on : R/W; bitpos: [29]; default: 0;
|
||||
* 0: 16-bit mode. 1: 8-bit mode.
|
||||
*/
|
||||
uint32_t cam_conv_mode_8bits_on: 1;
|
||||
/** cam_conv_trans_mode : R/W; bitpos: [30]; default: 0;
|
||||
* 0: converted to RGB format. 1: converted to YUV format.
|
||||
*/
|
||||
uint32_t cam_conv_trans_mode: 1;
|
||||
/** cam_conv_bypass : R/W; bitpos: [31]; default: 0;
|
||||
* 0: Bypass converter. 1: Enable converter.
|
||||
*/
|
||||
uint32_t cam_conv_bypass: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} lcd_cam_cam_rgb_yuv_reg_t;
|
||||
|
||||
|
||||
/** Group: Interrupt registers */
|
||||
/** Type of lc_dma_int_ena register
|
||||
* LCD_CAM GDMA interrupt enable register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** lcd_vsync_int_ena : R/W; bitpos: [0]; default: 0;
|
||||
* The enable bit for LCD_CAM_LCD_VSYNC_INT interrupt.
|
||||
*/
|
||||
uint32_t lcd_vsync_int_ena: 1;
|
||||
/** lcd_trans_done_int_ena : R/W; bitpos: [1]; default: 0;
|
||||
* The enable bit for LCD_CAM_LCD_TRANS_DONE_INT interrupt.
|
||||
*/
|
||||
uint32_t lcd_trans_done_int_ena: 1;
|
||||
/** cam_vsync_int_ena : R/W; bitpos: [2]; default: 0;
|
||||
* The enable bit for LCD_CAM_CAM_VSYNC_INT interrupt.
|
||||
*/
|
||||
uint32_t cam_vsync_int_ena: 1;
|
||||
/** cam_hs_int_ena : R/W; bitpos: [3]; default: 0;
|
||||
* The enable bit for LCD_CAM_CAM_HS_INT interrupt.
|
||||
*/
|
||||
uint32_t cam_hs_int_ena: 1;
|
||||
uint32_t reserved_4: 28;
|
||||
};
|
||||
uint32_t val;
|
||||
} lcd_cam_lc_dma_int_ena_reg_t;
|
||||
|
||||
/** Type of lc_dma_int_raw register
|
||||
* LCD_CAM GDMA raw interrupt status register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** lcd_vsync_int_raw : RO; bitpos: [0]; default: 0;
|
||||
* The raw bit for LCD_CAM_LCD_VSYNC_INT interrupt.
|
||||
*/
|
||||
uint32_t lcd_vsync_int_raw: 1;
|
||||
/** lcd_trans_done_int_raw : RO; bitpos: [1]; default: 0;
|
||||
* The raw bit for LCD_CAM_LCD_TRANS_DONE_INT interrupt.
|
||||
*/
|
||||
uint32_t lcd_trans_done_int_raw: 1;
|
||||
/** cam_vsync_int_raw : RO; bitpos: [2]; default: 0;
|
||||
* The raw bit for LCD_CAM_CAM_VSYNC_INT interrupt.
|
||||
*/
|
||||
uint32_t cam_vsync_int_raw: 1;
|
||||
/** cam_hs_int_raw : RO; bitpos: [3]; default: 0;
|
||||
* The raw bit for LCD_CAM_CAM_HS_INT interrupt.
|
||||
*/
|
||||
uint32_t cam_hs_int_raw: 1;
|
||||
uint32_t reserved_4: 28;
|
||||
};
|
||||
uint32_t val;
|
||||
} lcd_cam_lc_dma_int_raw_reg_t;
|
||||
|
||||
/** Type of lc_dma_int_st register
|
||||
* LCD_CAM GDMA masked interrupt status register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** lcd_vsync_int_st : RO; bitpos: [0]; default: 0;
|
||||
* The status bit for LCD_CAM_LCD_VSYNC_INT interrupt.
|
||||
*/
|
||||
uint32_t lcd_vsync_int_st: 1;
|
||||
/** lcd_trans_done_int_st : RO; bitpos: [1]; default: 0;
|
||||
* The status bit for LCD_CAM_LCD_TRANS_DONE_INT interrupt.
|
||||
*/
|
||||
uint32_t lcd_trans_done_int_st: 1;
|
||||
/** cam_vsync_int_st : RO; bitpos: [2]; default: 0;
|
||||
* The status bit for LCD_CAM_CAM_VSYNC_INT interrupt.
|
||||
*/
|
||||
uint32_t cam_vsync_int_st: 1;
|
||||
/** cam_hs_int_st : RO; bitpos: [3]; default: 0;
|
||||
* The status bit for LCD_CAM_CAM_HS_INT interrupt.
|
||||
*/
|
||||
uint32_t cam_hs_int_st: 1;
|
||||
uint32_t reserved_4: 28;
|
||||
};
|
||||
uint32_t val;
|
||||
} lcd_cam_lc_dma_int_st_reg_t;
|
||||
|
||||
/** Type of lc_dma_int_clr register
|
||||
* LCD_CAM GDMA interrupt clear register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** lcd_vsync_int_clr : WO; bitpos: [0]; default: 0;
|
||||
* The clear bit for LCD_CAM_LCD_VSYNC_INT interrupt.
|
||||
*/
|
||||
uint32_t lcd_vsync_int_clr: 1;
|
||||
/** lcd_trans_done_int_clr : WO; bitpos: [1]; default: 0;
|
||||
* The clear bit for LCD_CAM_LCD_TRANS_DONE_INT interrupt.
|
||||
*/
|
||||
uint32_t lcd_trans_done_int_clr: 1;
|
||||
/** cam_vsync_int_clr : WO; bitpos: [2]; default: 0;
|
||||
* The clear bit for LCD_CAM_CAM_VSYNC_INT interrupt.
|
||||
*/
|
||||
uint32_t cam_vsync_int_clr: 1;
|
||||
/** cam_hs_int_clr : WO; bitpos: [3]; default: 0;
|
||||
* The clear bit for LCD_CAM_CAM_HS_INT interrupt.
|
||||
*/
|
||||
uint32_t cam_hs_int_clr: 1;
|
||||
uint32_t reserved_4: 28;
|
||||
};
|
||||
uint32_t val;
|
||||
} lcd_cam_lc_dma_int_clr_reg_t;
|
||||
|
||||
|
||||
/** Group: Version register */
|
||||
/** Type of lc_reg_date register
|
||||
* Version control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** lc_date : R/W; bitpos: [27:0]; default: 33566752;
|
||||
* Version control register
|
||||
*/
|
||||
uint32_t lc_date: 28;
|
||||
uint32_t reserved_28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} lcd_cam_lc_reg_date_reg_t;
|
||||
|
||||
|
||||
typedef struct lcd_cam_dev_t {
|
||||
volatile lcd_cam_lcd_clock_reg_t lcd_clock;
|
||||
volatile lcd_cam_cam_ctrl_reg_t cam_ctrl;
|
||||
volatile lcd_cam_cam_ctrl1_reg_t cam_ctrl1;
|
||||
volatile lcd_cam_cam_rgb_yuv_reg_t cam_rgb_yuv;
|
||||
volatile lcd_cam_lcd_rgb_yuv_reg_t lcd_rgb_yuv;
|
||||
volatile lcd_cam_lcd_user_reg_t lcd_user;
|
||||
volatile lcd_cam_lcd_misc_reg_t lcd_misc;
|
||||
volatile lcd_cam_lcd_ctrl_reg_t lcd_ctrl;
|
||||
volatile lcd_cam_lcd_ctrl1_reg_t lcd_ctrl1;
|
||||
volatile lcd_cam_lcd_ctrl2_reg_t lcd_ctrl2;
|
||||
volatile lcd_cam_lcd_cmd_val_reg_t lcd_cmd_val;
|
||||
uint32_t reserved_02c;
|
||||
volatile lcd_cam_lcd_dly_mode_reg_t lcd_dly_mode;
|
||||
uint32_t reserved_034;
|
||||
volatile lcd_cam_lcd_data_dout_mode_reg_t lcd_data_dout_mode;
|
||||
uint32_t reserved_03c[10];
|
||||
volatile lcd_cam_lc_dma_int_ena_reg_t lc_dma_int_ena;
|
||||
volatile lcd_cam_lc_dma_int_raw_reg_t lc_dma_int_raw;
|
||||
volatile lcd_cam_lc_dma_int_st_reg_t lc_dma_int_st;
|
||||
volatile lcd_cam_lc_dma_int_clr_reg_t lc_dma_int_clr;
|
||||
uint32_t reserved_074[34];
|
||||
volatile lcd_cam_lc_reg_date_reg_t lc_reg_date;
|
||||
} lcd_cam_dev_t;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(lcd_cam_dev_t) == 0x100, "Invalid size of lcd_cam_dev_t structure");
|
||||
#endif
|
||||
|
||||
extern lcd_cam_dev_t LCD_CAM;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,225 +0,0 @@
|
||||
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef volatile struct ledc_dev_s {
|
||||
struct {
|
||||
struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t timer_sel: 2;
|
||||
uint32_t sig_out_en: 1;
|
||||
uint32_t idle_lv: 1;
|
||||
uint32_t low_speed_update: 1;
|
||||
uint32_t ovf_num: 10;
|
||||
uint32_t ovf_cnt_en: 1;
|
||||
uint32_t ovf_cnt_rst: 1;
|
||||
uint32_t ovf_cnt_rst_st: 1;
|
||||
uint32_t reserved18: 14;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t hpoint: 14;
|
||||
uint32_t reserved14: 18;
|
||||
};
|
||||
uint32_t val;
|
||||
} hpoint;
|
||||
union {
|
||||
struct {
|
||||
uint32_t duty: 19;
|
||||
uint32_t reserved19: 13;
|
||||
};
|
||||
uint32_t val;
|
||||
} duty;
|
||||
union {
|
||||
struct {
|
||||
uint32_t duty_scale: 10;
|
||||
uint32_t duty_cycle: 10;
|
||||
uint32_t duty_num: 10;
|
||||
uint32_t duty_inc: 1;
|
||||
uint32_t duty_start: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t duty_read: 19;
|
||||
uint32_t reserved19: 13;
|
||||
};
|
||||
uint32_t val;
|
||||
} duty_rd;
|
||||
} channel[8];
|
||||
} channel_group[1];
|
||||
struct {
|
||||
struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t duty_resolution: 4;
|
||||
uint32_t clock_divider: 18;
|
||||
uint32_t pause: 1;
|
||||
uint32_t rst: 1;
|
||||
uint32_t tick_sel: 1;
|
||||
uint32_t low_speed_update: 1;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t timer_cnt: 14;
|
||||
uint32_t reserved14: 18;
|
||||
};
|
||||
uint32_t val;
|
||||
} value;
|
||||
} timer[4];
|
||||
} timer_group[1];
|
||||
union {
|
||||
struct {
|
||||
uint32_t lstimer0_ovf: 1;
|
||||
uint32_t lstimer1_ovf: 1;
|
||||
uint32_t lstimer2_ovf: 1;
|
||||
uint32_t lstimer3_ovf: 1;
|
||||
uint32_t duty_chng_end_lsch0: 1;
|
||||
uint32_t duty_chng_end_lsch1: 1;
|
||||
uint32_t duty_chng_end_lsch2: 1;
|
||||
uint32_t duty_chng_end_lsch3: 1;
|
||||
uint32_t duty_chng_end_lsch4: 1;
|
||||
uint32_t duty_chng_end_lsch5: 1;
|
||||
uint32_t duty_chng_end_lsch6: 1;
|
||||
uint32_t duty_chng_end_lsch7: 1;
|
||||
uint32_t ovf_cnt_lsch0: 1;
|
||||
uint32_t ovf_cnt_lsch1: 1;
|
||||
uint32_t ovf_cnt_lsch2: 1;
|
||||
uint32_t ovf_cnt_lsch3: 1;
|
||||
uint32_t ovf_cnt_lsch4: 1;
|
||||
uint32_t ovf_cnt_lsch5: 1;
|
||||
uint32_t ovf_cnt_lsch6: 1;
|
||||
uint32_t ovf_cnt_lsch7: 1;
|
||||
uint32_t reserved20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t lstimer0_ovf: 1;
|
||||
uint32_t lstimer1_ovf: 1;
|
||||
uint32_t lstimer2_ovf: 1;
|
||||
uint32_t lstimer3_ovf: 1;
|
||||
uint32_t duty_chng_end_lsch0: 1;
|
||||
uint32_t duty_chng_end_lsch1: 1;
|
||||
uint32_t duty_chng_end_lsch2: 1;
|
||||
uint32_t duty_chng_end_lsch3: 1;
|
||||
uint32_t duty_chng_end_lsch4: 1;
|
||||
uint32_t duty_chng_end_lsch5: 1;
|
||||
uint32_t duty_chng_end_lsch6: 1;
|
||||
uint32_t duty_chng_end_lsch7: 1;
|
||||
uint32_t ovf_cnt_lsch0: 1;
|
||||
uint32_t ovf_cnt_lsch1: 1;
|
||||
uint32_t ovf_cnt_lsch2: 1;
|
||||
uint32_t ovf_cnt_lsch3: 1;
|
||||
uint32_t ovf_cnt_lsch4: 1;
|
||||
uint32_t ovf_cnt_lsch5: 1;
|
||||
uint32_t ovf_cnt_lsch6: 1;
|
||||
uint32_t ovf_cnt_lsch7: 1;
|
||||
uint32_t reserved20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t lstimer0_ovf: 1;
|
||||
uint32_t lstimer1_ovf: 1;
|
||||
uint32_t lstimer2_ovf: 1;
|
||||
uint32_t lstimer3_ovf: 1;
|
||||
uint32_t duty_chng_end_lsch0: 1;
|
||||
uint32_t duty_chng_end_lsch1: 1;
|
||||
uint32_t duty_chng_end_lsch2: 1;
|
||||
uint32_t duty_chng_end_lsch3: 1;
|
||||
uint32_t duty_chng_end_lsch4: 1;
|
||||
uint32_t duty_chng_end_lsch5: 1;
|
||||
uint32_t duty_chng_end_lsch6: 1;
|
||||
uint32_t duty_chng_end_lsch7: 1;
|
||||
uint32_t ovf_cnt_lsch0: 1;
|
||||
uint32_t ovf_cnt_lsch1: 1;
|
||||
uint32_t ovf_cnt_lsch2: 1;
|
||||
uint32_t ovf_cnt_lsch3: 1;
|
||||
uint32_t ovf_cnt_lsch4: 1;
|
||||
uint32_t ovf_cnt_lsch5: 1;
|
||||
uint32_t ovf_cnt_lsch6: 1;
|
||||
uint32_t ovf_cnt_lsch7: 1;
|
||||
uint32_t reserved20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t lstimer0_ovf: 1;
|
||||
uint32_t lstimer1_ovf: 1;
|
||||
uint32_t lstimer2_ovf: 1;
|
||||
uint32_t lstimer3_ovf: 1;
|
||||
uint32_t duty_chng_end_lsch0: 1;
|
||||
uint32_t duty_chng_end_lsch1: 1;
|
||||
uint32_t duty_chng_end_lsch2: 1;
|
||||
uint32_t duty_chng_end_lsch3: 1;
|
||||
uint32_t duty_chng_end_lsch4: 1;
|
||||
uint32_t duty_chng_end_lsch5: 1;
|
||||
uint32_t duty_chng_end_lsch6: 1;
|
||||
uint32_t duty_chng_end_lsch7: 1;
|
||||
uint32_t ovf_cnt_lsch0: 1;
|
||||
uint32_t ovf_cnt_lsch1: 1;
|
||||
uint32_t ovf_cnt_lsch2: 1;
|
||||
uint32_t ovf_cnt_lsch3: 1;
|
||||
uint32_t ovf_cnt_lsch4: 1;
|
||||
uint32_t ovf_cnt_lsch5: 1;
|
||||
uint32_t ovf_cnt_lsch6: 1;
|
||||
uint32_t ovf_cnt_lsch7: 1;
|
||||
uint32_t reserved20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t apb_clk_sel: 2;
|
||||
uint32_t reserved2: 29;
|
||||
uint32_t clk_en: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf;
|
||||
uint32_t reserved_d4;
|
||||
uint32_t reserved_d8;
|
||||
uint32_t reserved_dc;
|
||||
uint32_t reserved_e0;
|
||||
uint32_t reserved_e4;
|
||||
uint32_t reserved_e8;
|
||||
uint32_t reserved_ec;
|
||||
uint32_t reserved_f0;
|
||||
uint32_t reserved_f4;
|
||||
uint32_t reserved_f8;
|
||||
uint32_t date; /**/
|
||||
} ledc_dev_t;
|
||||
|
||||
extern ledc_dev_t LEDC;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,407 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Group: Configuration Register */
|
||||
/** Type of un_conf0 register
|
||||
* Configuration register 0 for unit n
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** filter_thres_un : R/W; bitpos: [9:0]; default: 16;
|
||||
* This sets the maximum threshold, in APB_CLK cycles, for the filter.
|
||||
*
|
||||
* Any pulses with width less than this will be ignored when the filter is enabled.
|
||||
*/
|
||||
uint32_t filter_thres_un: 10;
|
||||
/** filter_en_un : R/W; bitpos: [10]; default: 1;
|
||||
* This is the enable bit for unit n's input filter.
|
||||
*/
|
||||
uint32_t filter_en_un: 1;
|
||||
/** thr_zero_en_un : R/W; bitpos: [11]; default: 1;
|
||||
* This is the enable bit for unit n's zero comparator.
|
||||
*/
|
||||
uint32_t thr_zero_en_un: 1;
|
||||
/** thr_h_lim_en_un : R/W; bitpos: [12]; default: 1;
|
||||
* This is the enable bit for unit n's thr_h_lim comparator.
|
||||
*/
|
||||
uint32_t thr_h_lim_en_un: 1;
|
||||
/** thr_l_lim_en_un : R/W; bitpos: [13]; default: 1;
|
||||
* This is the enable bit for unit n's thr_l_lim comparator.
|
||||
*/
|
||||
uint32_t thr_l_lim_en_un: 1;
|
||||
/** thr_thres0_en_un : R/W; bitpos: [14]; default: 0;
|
||||
* This is the enable bit for unit n's thres0 comparator.
|
||||
*/
|
||||
uint32_t thr_thres0_en_un: 1;
|
||||
/** thr_thres1_en_un : R/W; bitpos: [15]; default: 0;
|
||||
* This is the enable bit for unit n's thres1 comparator.
|
||||
*/
|
||||
uint32_t thr_thres1_en_un: 1;
|
||||
/** ch0_neg_mode_un : R/W; bitpos: [17:16]; default: 0;
|
||||
* This register sets the behavior when the signal input of channel 0 detects a
|
||||
* negative edge.
|
||||
*
|
||||
* 1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter
|
||||
*/
|
||||
uint32_t ch0_neg_mode_un: 2;
|
||||
/** ch0_pos_mode_un : R/W; bitpos: [19:18]; default: 0;
|
||||
* This register sets the behavior when the signal input of channel 0 detects a
|
||||
* positive edge.
|
||||
*
|
||||
* 1: Increase the counter;2: Decrease the counter;0, 3: No effect on counter
|
||||
*/
|
||||
uint32_t ch0_pos_mode_un: 2;
|
||||
/** ch0_hctrl_mode_un : R/W; bitpos: [21:20]; default: 0;
|
||||
* This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
|
||||
* modified when the control signal is high.
|
||||
*
|
||||
* 0: No modification;1: Invert behavior (increase -> decrease, decrease ->
|
||||
* increase);2, 3: Inhibit counter modification
|
||||
*/
|
||||
uint32_t ch0_hctrl_mode_un: 2;
|
||||
/** ch0_lctrl_mode_un : R/W; bitpos: [23:22]; default: 0;
|
||||
* This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
|
||||
* modified when the control signal is low.
|
||||
*
|
||||
* 0: No modification;1: Invert behavior (increase -> decrease, decrease ->
|
||||
* increase);2, 3: Inhibit counter modification
|
||||
*/
|
||||
uint32_t ch0_lctrl_mode_un: 2;
|
||||
/** ch1_neg_mode_un : R/W; bitpos: [25:24]; default: 0;
|
||||
* This register sets the behavior when the signal input of channel 1 detects a
|
||||
* negative edge.
|
||||
*
|
||||
* 1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter
|
||||
*/
|
||||
uint32_t ch1_neg_mode_un: 2;
|
||||
/** ch1_pos_mode_un : R/W; bitpos: [27:26]; default: 0;
|
||||
* This register sets the behavior when the signal input of channel 1 detects a
|
||||
* positive edge.
|
||||
*
|
||||
* 1: Increment the counter;2: Decrement the counter;0, 3: No effect on counter
|
||||
*/
|
||||
uint32_t ch1_pos_mode_un: 2;
|
||||
/** ch1_hctrl_mode_un : R/W; bitpos: [29:28]; default: 0;
|
||||
* This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
|
||||
* modified when the control signal is high.
|
||||
*
|
||||
* 0: No modification;1: Invert behavior (increase -> decrease, decrease ->
|
||||
* increase);2, 3: Inhibit counter modification
|
||||
*/
|
||||
uint32_t ch1_hctrl_mode_un: 2;
|
||||
/** ch1_lctrl_mode_un : R/W; bitpos: [31:30]; default: 0;
|
||||
* This register configures how the CHn_POS_MODE/CHn_NEG_MODE settings will be
|
||||
* modified when the control signal is low.
|
||||
*
|
||||
* 0: No modification;1: Invert behavior (increase -> decrease, decrease ->
|
||||
* increase);2, 3: Inhibit counter modification
|
||||
*/
|
||||
uint32_t ch1_lctrl_mode_un: 2;
|
||||
};
|
||||
uint32_t val;
|
||||
} pcnt_un_conf0_reg_t;
|
||||
|
||||
/** Type of un_conf1 register
|
||||
* Configuration register 1 for unit n
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** cnt_thres0_un : R/W; bitpos: [15:0]; default: 0;
|
||||
* This register is used to configure the thres0 value for unit n.
|
||||
*/
|
||||
uint32_t cnt_thres0_un: 16;
|
||||
/** cnt_thres1_un : R/W; bitpos: [31:16]; default: 0;
|
||||
* This register is used to configure the thres1 value for unit n.
|
||||
*/
|
||||
uint32_t cnt_thres1_un: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} pcnt_un_conf1_reg_t;
|
||||
|
||||
/** Type of un_conf2 register
|
||||
* Configuration register 2 for unit n
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** cnt_h_lim_un : R/W; bitpos: [15:0]; default: 0;
|
||||
* This register is used to configure the thr_h_lim value for unit n.
|
||||
*/
|
||||
uint32_t cnt_h_lim_un: 16;
|
||||
/** cnt_l_lim_un : R/W; bitpos: [31:16]; default: 0;
|
||||
* This register is used to configure the thr_l_lim value for unit n.
|
||||
*/
|
||||
uint32_t cnt_l_lim_un: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} pcnt_un_conf2_reg_t;
|
||||
|
||||
|
||||
/** Type of ctrl register
|
||||
* Control register for all counters
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** pulse_cnt_rst_u0 : R/W; bitpos: [0]; default: 1;
|
||||
* Set this bit to clear unit 0's counter.
|
||||
*/
|
||||
uint32_t pulse_cnt_rst_u0: 1;
|
||||
/** cnt_pause_u0 : R/W; bitpos: [1]; default: 0;
|
||||
* Set this bit to freeze unit 0's counter.
|
||||
*/
|
||||
uint32_t cnt_pause_u0: 1;
|
||||
/** pulse_cnt_rst_u1 : R/W; bitpos: [2]; default: 1;
|
||||
* Set this bit to clear unit 1's counter.
|
||||
*/
|
||||
uint32_t pulse_cnt_rst_u1: 1;
|
||||
/** cnt_pause_u1 : R/W; bitpos: [3]; default: 0;
|
||||
* Set this bit to freeze unit 1's counter.
|
||||
*/
|
||||
uint32_t cnt_pause_u1: 1;
|
||||
/** pulse_cnt_rst_u2 : R/W; bitpos: [4]; default: 1;
|
||||
* Set this bit to clear unit 2's counter.
|
||||
*/
|
||||
uint32_t pulse_cnt_rst_u2: 1;
|
||||
/** cnt_pause_u2 : R/W; bitpos: [5]; default: 0;
|
||||
* Set this bit to freeze unit 2's counter.
|
||||
*/
|
||||
uint32_t cnt_pause_u2: 1;
|
||||
/** pulse_cnt_rst_u3 : R/W; bitpos: [6]; default: 1;
|
||||
* Set this bit to clear unit 3's counter.
|
||||
*/
|
||||
uint32_t pulse_cnt_rst_u3: 1;
|
||||
/** cnt_pause_u3 : R/W; bitpos: [7]; default: 0;
|
||||
* Set this bit to freeze unit 3's counter.
|
||||
*/
|
||||
uint32_t cnt_pause_u3: 1;
|
||||
uint32_t reserved_8: 8;
|
||||
/** clk_en : R/W; bitpos: [16]; default: 0;
|
||||
* The registers clock gate enable signal of PCNT module. 1: the registers can be read
|
||||
* and written by application. 0: the registers can not be read or written by
|
||||
* application
|
||||
*/
|
||||
uint32_t clk_en: 1;
|
||||
uint32_t reserved_17: 15;
|
||||
};
|
||||
uint32_t val;
|
||||
} pcnt_ctrl_reg_t;
|
||||
|
||||
|
||||
/** Group: Status Register */
|
||||
/** Type of un_cnt register
|
||||
* Counter value for unit n
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** pulse_cnt_un : RO; bitpos: [15:0]; default: 0;
|
||||
* This register stores the current pulse count value for unit n.
|
||||
*/
|
||||
uint32_t pulse_cnt_un: 16;
|
||||
uint32_t reserved_16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} pcnt_un_cnt_reg_t;
|
||||
|
||||
/** Type of un_status register
|
||||
* PNCT UNITn status register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** cnt_thr_zero_mode_un : RO; bitpos: [1:0]; default: 0;
|
||||
* The pulse counter status of PCNT_Un corresponding to 0. 0: pulse counter decreases
|
||||
* from positive to 0. 1: pulse counter increases from negative to 0. 2: pulse counter
|
||||
* is negative. 3: pulse counter is positive.
|
||||
*/
|
||||
uint32_t cnt_thr_zero_mode_un: 2;
|
||||
/** cnt_thr_thres1_lat_un : RO; bitpos: [2]; default: 0;
|
||||
* The latched value of thres1 event of PCNT_Un when threshold event interrupt is
|
||||
* valid. 1: the current pulse counter equals to thres1 and thres1 event is valid. 0:
|
||||
* others
|
||||
*/
|
||||
uint32_t cnt_thr_thres1_lat_un: 1;
|
||||
/** cnt_thr_thres0_lat_un : RO; bitpos: [3]; default: 0;
|
||||
* The latched value of thres0 event of PCNT_Un when threshold event interrupt is
|
||||
* valid. 1: the current pulse counter equals to thres0 and thres0 event is valid. 0:
|
||||
* others
|
||||
*/
|
||||
uint32_t cnt_thr_thres0_lat_un: 1;
|
||||
/** cnt_thr_l_lim_lat_un : RO; bitpos: [4]; default: 0;
|
||||
* The latched value of low limit event of PCNT_Un when threshold event interrupt is
|
||||
* valid. 1: the current pulse counter equals to thr_l_lim and low limit event is
|
||||
* valid. 0: others
|
||||
*/
|
||||
uint32_t cnt_thr_l_lim_lat_un: 1;
|
||||
/** cnt_thr_h_lim_lat_un : RO; bitpos: [5]; default: 0;
|
||||
* The latched value of high limit event of PCNT_Un when threshold event interrupt is
|
||||
* valid. 1: the current pulse counter equals to thr_h_lim and high limit event is
|
||||
* valid. 0: others
|
||||
*/
|
||||
uint32_t cnt_thr_h_lim_lat_un: 1;
|
||||
/** cnt_thr_zero_lat_un : RO; bitpos: [6]; default: 0;
|
||||
* The latched value of zero threshold event of PCNT_Un when threshold event interrupt
|
||||
* is valid. 1: the current pulse counter equals to 0 and zero threshold event is
|
||||
* valid. 0: others
|
||||
*/
|
||||
uint32_t cnt_thr_zero_lat_un: 1;
|
||||
uint32_t reserved_7: 25;
|
||||
};
|
||||
uint32_t val;
|
||||
} pcnt_un_status_reg_t;
|
||||
|
||||
|
||||
/** Group: Interrupt Register */
|
||||
/** Type of int_raw register
|
||||
* Interrupt raw status register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** cnt_thr_event_u0_int_raw : RO; bitpos: [0]; default: 0;
|
||||
* The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
|
||||
*/
|
||||
uint32_t cnt_thr_event_u0_int_raw: 1;
|
||||
/** cnt_thr_event_u1_int_raw : RO; bitpos: [1]; default: 0;
|
||||
* The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
|
||||
*/
|
||||
uint32_t cnt_thr_event_u1_int_raw: 1;
|
||||
/** cnt_thr_event_u2_int_raw : RO; bitpos: [2]; default: 0;
|
||||
* The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
|
||||
*/
|
||||
uint32_t cnt_thr_event_u2_int_raw: 1;
|
||||
/** cnt_thr_event_u3_int_raw : RO; bitpos: [3]; default: 0;
|
||||
* The raw interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
|
||||
*/
|
||||
uint32_t cnt_thr_event_u3_int_raw: 1;
|
||||
uint32_t reserved_4: 28;
|
||||
};
|
||||
uint32_t val;
|
||||
} pcnt_int_raw_reg_t;
|
||||
|
||||
/** Type of int_st register
|
||||
* Interrupt status register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** cnt_thr_event_u0_int_st : RO; bitpos: [0]; default: 0;
|
||||
* The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
|
||||
*/
|
||||
uint32_t cnt_thr_event_u0_int_st: 1;
|
||||
/** cnt_thr_event_u1_int_st : RO; bitpos: [1]; default: 0;
|
||||
* The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
|
||||
*/
|
||||
uint32_t cnt_thr_event_u1_int_st: 1;
|
||||
/** cnt_thr_event_u2_int_st : RO; bitpos: [2]; default: 0;
|
||||
* The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
|
||||
*/
|
||||
uint32_t cnt_thr_event_u2_int_st: 1;
|
||||
/** cnt_thr_event_u3_int_st : RO; bitpos: [3]; default: 0;
|
||||
* The masked interrupt status bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
|
||||
*/
|
||||
uint32_t cnt_thr_event_u3_int_st: 1;
|
||||
uint32_t reserved_4: 28;
|
||||
};
|
||||
uint32_t val;
|
||||
} pcnt_int_st_reg_t;
|
||||
|
||||
/** Type of int_ena register
|
||||
* Interrupt enable register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** cnt_thr_event_u0_int_ena : R/W; bitpos: [0]; default: 0;
|
||||
* The interrupt enable bit for the PCNT_CNT_THR_EVENT_U0_INT interrupt.
|
||||
*/
|
||||
uint32_t cnt_thr_event_u0_int_ena: 1;
|
||||
/** cnt_thr_event_u1_int_ena : R/W; bitpos: [1]; default: 0;
|
||||
* The interrupt enable bit for the PCNT_CNT_THR_EVENT_U1_INT interrupt.
|
||||
*/
|
||||
uint32_t cnt_thr_event_u1_int_ena: 1;
|
||||
/** cnt_thr_event_u2_int_ena : R/W; bitpos: [2]; default: 0;
|
||||
* The interrupt enable bit for the PCNT_CNT_THR_EVENT_U2_INT interrupt.
|
||||
*/
|
||||
uint32_t cnt_thr_event_u2_int_ena: 1;
|
||||
/** cnt_thr_event_u3_int_ena : R/W; bitpos: [3]; default: 0;
|
||||
* The interrupt enable bit for the PCNT_CNT_THR_EVENT_U3_INT interrupt.
|
||||
*/
|
||||
uint32_t cnt_thr_event_u3_int_ena: 1;
|
||||
uint32_t reserved_4: 28;
|
||||
};
|
||||
uint32_t val;
|
||||
} pcnt_int_ena_reg_t;
|
||||
|
||||
/** Type of int_clr register
|
||||
* Interrupt clear register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** cnt_thr_event_u0_int_clr : WO; bitpos: [0]; default: 0;
|
||||
* Set this bit to clear the PCNT_CNT_THR_EVENT_U0_INT interrupt.
|
||||
*/
|
||||
uint32_t cnt_thr_event_u0_int_clr: 1;
|
||||
/** cnt_thr_event_u1_int_clr : WO; bitpos: [1]; default: 0;
|
||||
* Set this bit to clear the PCNT_CNT_THR_EVENT_U1_INT interrupt.
|
||||
*/
|
||||
uint32_t cnt_thr_event_u1_int_clr: 1;
|
||||
/** cnt_thr_event_u2_int_clr : WO; bitpos: [2]; default: 0;
|
||||
* Set this bit to clear the PCNT_CNT_THR_EVENT_U2_INT interrupt.
|
||||
*/
|
||||
uint32_t cnt_thr_event_u2_int_clr: 1;
|
||||
/** cnt_thr_event_u3_int_clr : WO; bitpos: [3]; default: 0;
|
||||
* Set this bit to clear the PCNT_CNT_THR_EVENT_U3_INT interrupt.
|
||||
*/
|
||||
uint32_t cnt_thr_event_u3_int_clr: 1;
|
||||
uint32_t reserved_4: 28;
|
||||
};
|
||||
uint32_t val;
|
||||
} pcnt_int_clr_reg_t;
|
||||
|
||||
|
||||
/** Group: Version Register */
|
||||
/** Type of date register
|
||||
* PCNT version control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** date : R/W; bitpos: [31:0]; default: 419898881;
|
||||
* This is the PCNT version control register.
|
||||
*/
|
||||
uint32_t date: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} pcnt_date_reg_t;
|
||||
|
||||
|
||||
typedef struct pcnt_dev_t {
|
||||
volatile struct {
|
||||
pcnt_un_conf0_reg_t conf0;
|
||||
pcnt_un_conf1_reg_t conf1;
|
||||
pcnt_un_conf2_reg_t conf2;
|
||||
} conf_unit[4];
|
||||
volatile pcnt_un_cnt_reg_t cnt_unit[4];
|
||||
volatile pcnt_int_raw_reg_t int_raw;
|
||||
volatile pcnt_int_st_reg_t int_st;
|
||||
volatile pcnt_int_ena_reg_t int_ena;
|
||||
volatile pcnt_int_clr_reg_t int_clr;
|
||||
volatile pcnt_un_status_reg_t status_unit[4];
|
||||
volatile pcnt_ctrl_reg_t ctrl;
|
||||
uint32_t reserved_064[38];
|
||||
volatile pcnt_date_reg_t date;
|
||||
} pcnt_dev_t;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(pcnt_dev_t) == 0x100, "Invalid size of pcnt_dev_t structure");
|
||||
#endif
|
||||
|
||||
extern pcnt_dev_t PCNT;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,198 +0,0 @@
|
||||
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_PERI_BACKUP_REG_H_
|
||||
#define _SOC_PERI_BACKUP_REG_H_
|
||||
|
||||
|
||||
#include "soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define PERI_BACKUP_CONFIG_REG (DR_REG_PERI_BACKUP_BASE + 0x0)
|
||||
/* PERI_BACKUP_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define PERI_BACKUP_ENA (BIT(31))
|
||||
#define PERI_BACKUP_ENA_M (BIT(31))
|
||||
#define PERI_BACKUP_ENA_V 0x1
|
||||
#define PERI_BACKUP_ENA_S 31
|
||||
/* PERI_BACKUP_TO_MEM : R/W ;bitpos:[30] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define PERI_BACKUP_TO_MEM (BIT(30))
|
||||
#define PERI_BACKUP_TO_MEM_M (BIT(30))
|
||||
#define PERI_BACKUP_TO_MEM_V 0x1
|
||||
#define PERI_BACKUP_TO_MEM_S 30
|
||||
/* PERI_BACKUP_START : WT ;bitpos:[29] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define PERI_BACKUP_START (BIT(29))
|
||||
#define PERI_BACKUP_START_M (BIT(29))
|
||||
#define PERI_BACKUP_START_V 0x1
|
||||
#define PERI_BACKUP_START_S 29
|
||||
/* PERI_BACKUP_SIZE : R/W ;bitpos:[28:19] ;default: 10'd0 ; */
|
||||
/*description: .*/
|
||||
#define PERI_BACKUP_SIZE 0x000003FF
|
||||
#define PERI_BACKUP_SIZE_M ((PERI_BACKUP_SIZE_V)<<(PERI_BACKUP_SIZE_S))
|
||||
#define PERI_BACKUP_SIZE_V 0x3FF
|
||||
#define PERI_BACKUP_SIZE_S 19
|
||||
/* PERI_BACKUP_TOUT_THRES : R/W ;bitpos:[18:9] ;default: 10'd50 ; */
|
||||
/*description: .*/
|
||||
#define PERI_BACKUP_TOUT_THRES 0x000003FF
|
||||
#define PERI_BACKUP_TOUT_THRES_M ((PERI_BACKUP_TOUT_THRES_V)<<(PERI_BACKUP_TOUT_THRES_S))
|
||||
#define PERI_BACKUP_TOUT_THRES_V 0x3FF
|
||||
#define PERI_BACKUP_TOUT_THRES_S 9
|
||||
/* PERI_BACKUP_BURST_LIMIT : R/W ;bitpos:[8:4] ;default: 5'd8 ; */
|
||||
/*description: .*/
|
||||
#define PERI_BACKUP_BURST_LIMIT 0x0000001F
|
||||
#define PERI_BACKUP_BURST_LIMIT_M ((PERI_BACKUP_BURST_LIMIT_V)<<(PERI_BACKUP_BURST_LIMIT_S))
|
||||
#define PERI_BACKUP_BURST_LIMIT_V 0x1F
|
||||
#define PERI_BACKUP_BURST_LIMIT_S 4
|
||||
/* PERI_BACKUP_ADDR_MAP_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define PERI_BACKUP_ADDR_MAP_MODE (BIT(3))
|
||||
#define PERI_BACKUP_ADDR_MAP_MODE_M (BIT(3))
|
||||
#define PERI_BACKUP_ADDR_MAP_MODE_V 0x1
|
||||
#define PERI_BACKUP_ADDR_MAP_MODE_S 3
|
||||
/* PERI_BACKUP_FLOW_ERR : RO ;bitpos:[2:0] ;default: 3'd0 ; */
|
||||
/*description: .*/
|
||||
#define PERI_BACKUP_FLOW_ERR 0x00000007
|
||||
#define PERI_BACKUP_FLOW_ERR_M ((PERI_BACKUP_FLOW_ERR_V)<<(PERI_BACKUP_FLOW_ERR_S))
|
||||
#define PERI_BACKUP_FLOW_ERR_V 0x7
|
||||
#define PERI_BACKUP_FLOW_ERR_S 0
|
||||
|
||||
#define PERI_BACKUP_APB_ADDR_REG (DR_REG_PERI_BACKUP_BASE + 0x4)
|
||||
/* PERI_BACKUP_APB_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
|
||||
/*description: .*/
|
||||
#define PERI_BACKUP_APB_START_ADDR 0xFFFFFFFF
|
||||
#define PERI_BACKUP_APB_START_ADDR_M ((PERI_BACKUP_APB_START_ADDR_V)<<(PERI_BACKUP_APB_START_ADDR_S))
|
||||
#define PERI_BACKUP_APB_START_ADDR_V 0xFFFFFFFF
|
||||
#define PERI_BACKUP_APB_START_ADDR_S 0
|
||||
|
||||
#define PERI_BACKUP_MEM_ADDR_REG (DR_REG_PERI_BACKUP_BASE + 0x8)
|
||||
/* PERI_BACKUP_MEM_START_ADDR : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
|
||||
/*description: .*/
|
||||
#define PERI_BACKUP_MEM_START_ADDR 0xFFFFFFFF
|
||||
#define PERI_BACKUP_MEM_START_ADDR_M ((PERI_BACKUP_MEM_START_ADDR_V)<<(PERI_BACKUP_MEM_START_ADDR_S))
|
||||
#define PERI_BACKUP_MEM_START_ADDR_V 0xFFFFFFFF
|
||||
#define PERI_BACKUP_MEM_START_ADDR_S 0
|
||||
|
||||
#define PERI_BACKUP_REG_MAP0_REG (DR_REG_PERI_BACKUP_BASE + 0xC)
|
||||
/* PERI_BACKUP_MAP0 : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
|
||||
/*description: .*/
|
||||
#define PERI_BACKUP_MAP0 0xFFFFFFFF
|
||||
#define PERI_BACKUP_MAP0_M ((PERI_BACKUP_MAP0_V)<<(PERI_BACKUP_MAP0_S))
|
||||
#define PERI_BACKUP_MAP0_V 0xFFFFFFFF
|
||||
#define PERI_BACKUP_MAP0_S 0
|
||||
|
||||
#define PERI_BACKUP_REG_MAP1_REG (DR_REG_PERI_BACKUP_BASE + 0x10)
|
||||
/* PERI_BACKUP_MAP1 : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
|
||||
/*description: .*/
|
||||
#define PERI_BACKUP_MAP1 0xFFFFFFFF
|
||||
#define PERI_BACKUP_MAP1_M ((PERI_BACKUP_MAP1_V)<<(PERI_BACKUP_MAP1_S))
|
||||
#define PERI_BACKUP_MAP1_V 0xFFFFFFFF
|
||||
#define PERI_BACKUP_MAP1_S 0
|
||||
|
||||
#define PERI_BACKUP_REG_MAP2_REG (DR_REG_PERI_BACKUP_BASE + 0x14)
|
||||
/* PERI_BACKUP_MAP2 : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
|
||||
/*description: .*/
|
||||
#define PERI_BACKUP_MAP2 0xFFFFFFFF
|
||||
#define PERI_BACKUP_MAP2_M ((PERI_BACKUP_MAP2_V)<<(PERI_BACKUP_MAP2_S))
|
||||
#define PERI_BACKUP_MAP2_V 0xFFFFFFFF
|
||||
#define PERI_BACKUP_MAP2_S 0
|
||||
|
||||
#define PERI_BACKUP_REG_MAP3_REG (DR_REG_PERI_BACKUP_BASE + 0x18)
|
||||
/* PERI_BACKUP_MAP3 : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
|
||||
/*description: .*/
|
||||
#define PERI_BACKUP_MAP3 0xFFFFFFFF
|
||||
#define PERI_BACKUP_MAP3_M ((PERI_BACKUP_MAP3_V)<<(PERI_BACKUP_MAP3_S))
|
||||
#define PERI_BACKUP_MAP3_V 0xFFFFFFFF
|
||||
#define PERI_BACKUP_MAP3_S 0
|
||||
|
||||
#define PERI_BACKUP_INT_RAW_REG (DR_REG_PERI_BACKUP_BASE + 0x1C)
|
||||
/* PERI_BACKUP_ERR_INT_RAW : R/SS/WTC ;bitpos:[1] ;default: 1'd0 ; */
|
||||
/*description: .*/
|
||||
#define PERI_BACKUP_ERR_INT_RAW (BIT(1))
|
||||
#define PERI_BACKUP_ERR_INT_RAW_M (BIT(1))
|
||||
#define PERI_BACKUP_ERR_INT_RAW_V 0x1
|
||||
#define PERI_BACKUP_ERR_INT_RAW_S 1
|
||||
/* PERI_BACKUP_DONE_INT_RAW : R/SS/WTC ;bitpos:[0] ;default: 1'd0 ; */
|
||||
/*description: .*/
|
||||
#define PERI_BACKUP_DONE_INT_RAW (BIT(0))
|
||||
#define PERI_BACKUP_DONE_INT_RAW_M (BIT(0))
|
||||
#define PERI_BACKUP_DONE_INT_RAW_V 0x1
|
||||
#define PERI_BACKUP_DONE_INT_RAW_S 0
|
||||
|
||||
#define PERI_BACKUP_INT_ST_REG (DR_REG_PERI_BACKUP_BASE + 0x20)
|
||||
/* PERI_BACKUP_ERR_INT_ST : RO ;bitpos:[1] ;default: 1'd0 ; */
|
||||
/*description: .*/
|
||||
#define PERI_BACKUP_ERR_INT_ST (BIT(1))
|
||||
#define PERI_BACKUP_ERR_INT_ST_M (BIT(1))
|
||||
#define PERI_BACKUP_ERR_INT_ST_V 0x1
|
||||
#define PERI_BACKUP_ERR_INT_ST_S 1
|
||||
/* PERI_BACKUP_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'd0 ; */
|
||||
/*description: .*/
|
||||
#define PERI_BACKUP_DONE_INT_ST (BIT(0))
|
||||
#define PERI_BACKUP_DONE_INT_ST_M (BIT(0))
|
||||
#define PERI_BACKUP_DONE_INT_ST_V 0x1
|
||||
#define PERI_BACKUP_DONE_INT_ST_S 0
|
||||
|
||||
#define PERI_BACKUP_INT_ENA_REG (DR_REG_PERI_BACKUP_BASE + 0x24)
|
||||
/* PERI_BACKUP_ERR_INT_ENA : R/W ;bitpos:[1] ;default: 1'd0 ; */
|
||||
/*description: .*/
|
||||
#define PERI_BACKUP_ERR_INT_ENA (BIT(1))
|
||||
#define PERI_BACKUP_ERR_INT_ENA_M (BIT(1))
|
||||
#define PERI_BACKUP_ERR_INT_ENA_V 0x1
|
||||
#define PERI_BACKUP_ERR_INT_ENA_S 1
|
||||
/* PERI_BACKUP_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'd0 ; */
|
||||
/*description: .*/
|
||||
#define PERI_BACKUP_DONE_INT_ENA (BIT(0))
|
||||
#define PERI_BACKUP_DONE_INT_ENA_M (BIT(0))
|
||||
#define PERI_BACKUP_DONE_INT_ENA_V 0x1
|
||||
#define PERI_BACKUP_DONE_INT_ENA_S 0
|
||||
|
||||
#define PERI_BACKUP_INT_CLR_REG (DR_REG_PERI_BACKUP_BASE + 0x28)
|
||||
/* PERI_BACKUP_ERR_INT_CLR : WT ;bitpos:[1] ;default: 1'd0 ; */
|
||||
/*description: .*/
|
||||
#define PERI_BACKUP_ERR_INT_CLR (BIT(1))
|
||||
#define PERI_BACKUP_ERR_INT_CLR_M (BIT(1))
|
||||
#define PERI_BACKUP_ERR_INT_CLR_V 0x1
|
||||
#define PERI_BACKUP_ERR_INT_CLR_S 1
|
||||
/* PERI_BACKUP_DONE_INT_CLR : WT ;bitpos:[0] ;default: 1'd0 ; */
|
||||
/*description: .*/
|
||||
#define PERI_BACKUP_DONE_INT_CLR (BIT(0))
|
||||
#define PERI_BACKUP_DONE_INT_CLR_M (BIT(0))
|
||||
#define PERI_BACKUP_DONE_INT_CLR_V 0x1
|
||||
#define PERI_BACKUP_DONE_INT_CLR_S 0
|
||||
|
||||
#define PERI_BACKUP_DATE_REG (DR_REG_PERI_BACKUP_BASE + 0xFC)
|
||||
/* PERI_BACKUP_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: register file clk gating.*/
|
||||
#define PERI_BACKUP_CLK_EN (BIT(31))
|
||||
#define PERI_BACKUP_CLK_EN_M (BIT(31))
|
||||
#define PERI_BACKUP_CLK_EN_V 0x1
|
||||
#define PERI_BACKUP_CLK_EN_S 31
|
||||
/* PERI_BACKUP_DATE : R/W ;bitpos:[27:0] ;default: 28'h2012300 ; */
|
||||
/*description: .*/
|
||||
#define PERI_BACKUP_DATE 0x0FFFFFFF
|
||||
#define PERI_BACKUP_DATE_M ((PERI_BACKUP_DATE_V)<<(PERI_BACKUP_DATE_S))
|
||||
#define PERI_BACKUP_DATE_V 0xFFFFFFF
|
||||
#define PERI_BACKUP_DATE_S 0
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /*_SOC_PERI_BACKUP_REG_H_ */
|
||||
@@ -1,143 +0,0 @@
|
||||
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_PERI_BACKUP_STRUCT_H_
|
||||
#define _SOC_PERI_BACKUP_STRUCT_H_
|
||||
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct peri_backup_dev_s {
|
||||
union {
|
||||
struct {
|
||||
uint32_t reg_peri_backup_flow_err : 3;
|
||||
uint32_t reg_peri_backup_addr_map_mode : 1;
|
||||
uint32_t reg_peri_backup_burst_limit : 5;
|
||||
uint32_t reg_peri_backup_tout_thres : 10;
|
||||
uint32_t reg_peri_backup_size : 10;
|
||||
uint32_t reg_peri_backup_start : 1;
|
||||
uint32_t reg_peri_backup_to_mem : 1;
|
||||
uint32_t reg_peri_backup_ena : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} config;
|
||||
uint32_t apb_addr;
|
||||
uint32_t mem_addr;
|
||||
uint32_t reg_map0;
|
||||
uint32_t reg_map1;
|
||||
uint32_t reg_map2;
|
||||
uint32_t reg_map3;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reg_peri_backup_done_int_raw : 1;
|
||||
uint32_t reg_peri_backup_err_int_raw : 1;
|
||||
uint32_t reserved2 : 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reg_peri_backup_done_int_st : 1;
|
||||
uint32_t reg_peri_backup_err_int_st : 1;
|
||||
uint32_t reserved2 : 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reg_peri_backup_done_int_ena : 1;
|
||||
uint32_t reg_peri_backup_err_int_ena : 1;
|
||||
uint32_t reserved2 : 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reg_peri_backup_done_int_clr : 1;
|
||||
uint32_t reg_peri_backup_err_int_clr : 1;
|
||||
uint32_t reserved2 : 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_clr;
|
||||
uint32_t reserved_2c;
|
||||
uint32_t reserved_30;
|
||||
uint32_t reserved_34;
|
||||
uint32_t reserved_38;
|
||||
uint32_t reserved_3c;
|
||||
uint32_t reserved_40;
|
||||
uint32_t reserved_44;
|
||||
uint32_t reserved_48;
|
||||
uint32_t reserved_4c;
|
||||
uint32_t reserved_50;
|
||||
uint32_t reserved_54;
|
||||
uint32_t reserved_58;
|
||||
uint32_t reserved_5c;
|
||||
uint32_t reserved_60;
|
||||
uint32_t reserved_64;
|
||||
uint32_t reserved_68;
|
||||
uint32_t reserved_6c;
|
||||
uint32_t reserved_70;
|
||||
uint32_t reserved_74;
|
||||
uint32_t reserved_78;
|
||||
uint32_t reserved_7c;
|
||||
uint32_t reserved_80;
|
||||
uint32_t reserved_84;
|
||||
uint32_t reserved_88;
|
||||
uint32_t reserved_8c;
|
||||
uint32_t reserved_90;
|
||||
uint32_t reserved_94;
|
||||
uint32_t reserved_98;
|
||||
uint32_t reserved_9c;
|
||||
uint32_t reserved_a0;
|
||||
uint32_t reserved_a4;
|
||||
uint32_t reserved_a8;
|
||||
uint32_t reserved_ac;
|
||||
uint32_t reserved_b0;
|
||||
uint32_t reserved_b4;
|
||||
uint32_t reserved_b8;
|
||||
uint32_t reserved_bc;
|
||||
uint32_t reserved_c0;
|
||||
uint32_t reserved_c4;
|
||||
uint32_t reserved_c8;
|
||||
uint32_t reserved_cc;
|
||||
uint32_t reserved_d0;
|
||||
uint32_t reserved_d4;
|
||||
uint32_t reserved_d8;
|
||||
uint32_t reserved_dc;
|
||||
uint32_t reserved_e0;
|
||||
uint32_t reserved_e4;
|
||||
uint32_t reserved_e8;
|
||||
uint32_t reserved_ec;
|
||||
uint32_t reserved_f0;
|
||||
uint32_t reserved_f4;
|
||||
uint32_t reserved_f8;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reg_date : 28;
|
||||
uint32_t reserved28 : 3;
|
||||
uint32_t reg_clk_en : 1; /*register file clk gating*/
|
||||
};
|
||||
uint32_t val;
|
||||
} date;
|
||||
} peri_backup_dev_t;
|
||||
extern peri_backup_dev_t PERI_BACKUP;
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /*_SOC_PERI_BACKUP_STRUCT_H_ */
|
||||
@@ -1,64 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#define DR_REG_UART_BASE 0x60000000
|
||||
#define DR_REG_SPI1_BASE 0x60002000
|
||||
#define DR_REG_SPI0_BASE 0x60003000
|
||||
#define DR_REG_GPIO_BASE 0x60004000
|
||||
#define DR_REG_GPIO_SD_BASE 0x60004f00
|
||||
#define DR_REG_FE2_BASE 0x60005000
|
||||
#define DR_REG_FE_BASE 0x60006000
|
||||
#define DR_REG_EFUSE_BASE 0x60007000
|
||||
#define DR_REG_RTCCNTL_BASE 0x60008000
|
||||
#define DR_REG_RTCIO_BASE 0x60008400
|
||||
#define DR_REG_SENS_BASE 0x60008800
|
||||
#define DR_REG_RTC_I2C_BASE 0x60008C00
|
||||
#define DR_REG_IO_MUX_BASE 0x60009000
|
||||
#define DR_REG_HINF_BASE 0x6000B000
|
||||
#define DR_REG_UHCI1_BASE 0x6000C000
|
||||
#define DR_REG_I2S_BASE 0x6000F000
|
||||
#define DR_REG_UART1_BASE 0x60010000
|
||||
#define DR_REG_BT_BASE 0x60011000
|
||||
#define DR_REG_I2C_EXT_BASE 0x60013000
|
||||
#define DR_REG_UHCI0_BASE 0x60014000
|
||||
#define DR_REG_SLCHOST_BASE 0x60015000
|
||||
#define DR_REG_RMT_BASE 0x60016000
|
||||
#define DR_REG_PCNT_BASE 0x60017000
|
||||
#define DR_REG_SLC_BASE 0x60018000
|
||||
#define DR_REG_LEDC_BASE 0x60019000
|
||||
#define DR_REG_NRX_BASE 0x6001CC00
|
||||
#define DR_REG_BB_BASE 0x6001D000
|
||||
#define DR_REG_PWM0_BASE 0x6001E000
|
||||
#define DR_REG_TIMERGROUP0_BASE 0x6001F000
|
||||
#define DR_REG_TIMERGROUP1_BASE 0x60020000
|
||||
#define DR_REG_RTC_SLOWMEM_BASE 0x60021000
|
||||
#define DR_REG_SYSTIMER_BASE 0x60023000
|
||||
#define DR_REG_SPI2_BASE 0x60024000
|
||||
#define DR_REG_SPI3_BASE 0x60025000
|
||||
#define DR_REG_SYSCON_BASE 0x60026000
|
||||
#define DR_REG_APB_CTRL_BASE 0x60026000 /* Old name for SYSCON, to be removed */
|
||||
#define DR_REG_I2C1_EXT_BASE 0x60027000
|
||||
#define DR_REG_SDMMC_BASE 0x60028000
|
||||
#define DR_REG_PERI_BACKUP_BASE 0x6002A000
|
||||
#define DR_REG_TWAI_BASE 0x6002B000
|
||||
#define DR_REG_PWM1_BASE 0x6002C000
|
||||
#define DR_REG_I2S1_BASE 0x6002D000
|
||||
#define DR_REG_UART2_BASE 0x6002E000
|
||||
#define DR_REG_USB_SERIAL_JTAG_BASE 0x60038000
|
||||
#define DR_REG_USB_WRAP_BASE 0x60039000
|
||||
#define DR_REG_AES_BASE 0x6003A000
|
||||
#define DR_REG_SHA_BASE 0x6003B000
|
||||
#define DR_REG_RSA_BASE 0x6003C000
|
||||
#define DR_REG_HMAC_BASE 0x6003E000
|
||||
#define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003D000
|
||||
#define DR_REG_GDMA_BASE 0x6003F000
|
||||
#define DR_REG_APB_SARADC_BASE 0x60040000
|
||||
#define DR_REG_LCD_CAM_BASE 0x60041000
|
||||
#define DR_REG_SYSTEM_BASE 0x600C0000
|
||||
#define DR_REG_SENSITIVE_BASE 0x600C1000
|
||||
#define DR_REG_INTERRUPT_BASE 0x600C2000
|
||||
#define DR_REG_EXTMEM_BASE 0x600C4000
|
||||
#define DR_REG_ASSIST_DEBUG_BASE 0x600CE000
|
||||
#define DR_REG_WCL_BASE 0x600D0000
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,873 +0,0 @@
|
||||
/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** RTC_I2C_SCL_LOW_REG register
|
||||
* configure low scl period
|
||||
*/
|
||||
#define RTC_I2C_SCL_LOW_REG (DR_REG_RTC_I2C_BASE + 0x0)
|
||||
/** RTC_I2C_SCL_LOW_PERIOD_REG : R/W; bitpos: [19:0]; default: 256;
|
||||
* time period that scl =0
|
||||
*/
|
||||
#define RTC_I2C_SCL_LOW_PERIOD_REG 0x000FFFFFU
|
||||
#define RTC_I2C_SCL_LOW_PERIOD_REG_M (RTC_I2C_SCL_LOW_PERIOD_REG_V << RTC_I2C_SCL_LOW_PERIOD_REG_S)
|
||||
#define RTC_I2C_SCL_LOW_PERIOD_REG_V 0x000FFFFFU
|
||||
#define RTC_I2C_SCL_LOW_PERIOD_REG_S 0
|
||||
|
||||
/** RTC_I2C_CTRL_REG register
|
||||
* configure i2c ctrl
|
||||
*/
|
||||
#define RTC_I2C_CTRL_REG (DR_REG_RTC_I2C_BASE + 0x4)
|
||||
/** RTC_I2C_SDA_FORCE_OUT : R/W; bitpos: [0]; default: 0;
|
||||
* 1=push pull,0=open drain
|
||||
*/
|
||||
#define RTC_I2C_SDA_FORCE_OUT (BIT(0))
|
||||
#define RTC_I2C_SDA_FORCE_OUT_M (RTC_I2C_SDA_FORCE_OUT_V << RTC_I2C_SDA_FORCE_OUT_S)
|
||||
#define RTC_I2C_SDA_FORCE_OUT_V 0x00000001U
|
||||
#define RTC_I2C_SDA_FORCE_OUT_S 0
|
||||
/** RTC_I2C_SCL_FORCE_OUT : R/W; bitpos: [1]; default: 0;
|
||||
* 1=push pull,0=open drain
|
||||
*/
|
||||
#define RTC_I2C_SCL_FORCE_OUT (BIT(1))
|
||||
#define RTC_I2C_SCL_FORCE_OUT_M (RTC_I2C_SCL_FORCE_OUT_V << RTC_I2C_SCL_FORCE_OUT_S)
|
||||
#define RTC_I2C_SCL_FORCE_OUT_V 0x00000001U
|
||||
#define RTC_I2C_SCL_FORCE_OUT_S 1
|
||||
/** RTC_I2C_MS_MODE : R/W; bitpos: [2]; default: 0;
|
||||
* 1=master,0=slave
|
||||
*/
|
||||
#define RTC_I2C_MS_MODE (BIT(2))
|
||||
#define RTC_I2C_MS_MODE_M (RTC_I2C_MS_MODE_V << RTC_I2C_MS_MODE_S)
|
||||
#define RTC_I2C_MS_MODE_V 0x00000001U
|
||||
#define RTC_I2C_MS_MODE_S 2
|
||||
/** RTC_I2C_TRANS_START : R/W; bitpos: [3]; default: 0;
|
||||
* force start
|
||||
*/
|
||||
#define RTC_I2C_TRANS_START (BIT(3))
|
||||
#define RTC_I2C_TRANS_START_M (RTC_I2C_TRANS_START_V << RTC_I2C_TRANS_START_S)
|
||||
#define RTC_I2C_TRANS_START_V 0x00000001U
|
||||
#define RTC_I2C_TRANS_START_S 3
|
||||
/** RTC_I2C_TX_LSB_FIRST : R/W; bitpos: [4]; default: 0;
|
||||
* transit lsb first
|
||||
*/
|
||||
#define RTC_I2C_TX_LSB_FIRST (BIT(4))
|
||||
#define RTC_I2C_TX_LSB_FIRST_M (RTC_I2C_TX_LSB_FIRST_V << RTC_I2C_TX_LSB_FIRST_S)
|
||||
#define RTC_I2C_TX_LSB_FIRST_V 0x00000001U
|
||||
#define RTC_I2C_TX_LSB_FIRST_S 4
|
||||
/** RTC_I2C_RX_LSB_FIRST : R/W; bitpos: [5]; default: 0;
|
||||
* receive lsb first
|
||||
*/
|
||||
#define RTC_I2C_RX_LSB_FIRST (BIT(5))
|
||||
#define RTC_I2C_RX_LSB_FIRST_M (RTC_I2C_RX_LSB_FIRST_V << RTC_I2C_RX_LSB_FIRST_S)
|
||||
#define RTC_I2C_RX_LSB_FIRST_V 0x00000001U
|
||||
#define RTC_I2C_RX_LSB_FIRST_S 5
|
||||
/** RTC_I2C_I2C_CTRL_CLK_GATE_EN : R/W; bitpos: [29]; default: 0;
|
||||
* configure i2c ctrl clk enable
|
||||
*/
|
||||
#define RTC_I2C_I2C_CTRL_CLK_GATE_EN (BIT(29))
|
||||
#define RTC_I2C_I2C_CTRL_CLK_GATE_EN_M (RTC_I2C_I2C_CTRL_CLK_GATE_EN_V << RTC_I2C_I2C_CTRL_CLK_GATE_EN_S)
|
||||
#define RTC_I2C_I2C_CTRL_CLK_GATE_EN_V 0x00000001U
|
||||
#define RTC_I2C_I2C_CTRL_CLK_GATE_EN_S 29
|
||||
/** RTC_I2C_I2C_RESET : R/W; bitpos: [30]; default: 0;
|
||||
* rtc i2c sw reset
|
||||
*/
|
||||
#define RTC_I2C_I2C_RESET (BIT(30))
|
||||
#define RTC_I2C_I2C_RESET_M (RTC_I2C_I2C_RESET_V << RTC_I2C_I2C_RESET_S)
|
||||
#define RTC_I2C_I2C_RESET_V 0x00000001U
|
||||
#define RTC_I2C_I2C_RESET_S 30
|
||||
/** RTC_I2C_I2CCLK_EN : R/W; bitpos: [31]; default: 0;
|
||||
* rtc i2c reg clk gating
|
||||
*/
|
||||
#define RTC_I2C_I2CCLK_EN (BIT(31))
|
||||
#define RTC_I2C_I2CCLK_EN_M (RTC_I2C_I2CCLK_EN_V << RTC_I2C_I2CCLK_EN_S)
|
||||
#define RTC_I2C_I2CCLK_EN_V 0x00000001U
|
||||
#define RTC_I2C_I2CCLK_EN_S 31
|
||||
|
||||
/** RTC_I2C_STATUS_REG register
|
||||
* get i2c status
|
||||
*/
|
||||
#define RTC_I2C_STATUS_REG (DR_REG_RTC_I2C_BASE + 0x8)
|
||||
/** RTC_I2C_ACK_REC : RO; bitpos: [0]; default: 0;
|
||||
* ack response
|
||||
*/
|
||||
#define RTC_I2C_ACK_REC (BIT(0))
|
||||
#define RTC_I2C_ACK_REC_M (RTC_I2C_ACK_REC_V << RTC_I2C_ACK_REC_S)
|
||||
#define RTC_I2C_ACK_REC_V 0x00000001U
|
||||
#define RTC_I2C_ACK_REC_S 0
|
||||
/** RTC_I2C_SLAVE_RW : RO; bitpos: [1]; default: 0;
|
||||
* slave read or write
|
||||
*/
|
||||
#define RTC_I2C_SLAVE_RW (BIT(1))
|
||||
#define RTC_I2C_SLAVE_RW_M (RTC_I2C_SLAVE_RW_V << RTC_I2C_SLAVE_RW_S)
|
||||
#define RTC_I2C_SLAVE_RW_V 0x00000001U
|
||||
#define RTC_I2C_SLAVE_RW_S 1
|
||||
/** RTC_I2C_ARB_LOST : RO; bitpos: [2]; default: 0;
|
||||
* arbitration is lost
|
||||
*/
|
||||
#define RTC_I2C_ARB_LOST (BIT(2))
|
||||
#define RTC_I2C_ARB_LOST_M (RTC_I2C_ARB_LOST_V << RTC_I2C_ARB_LOST_S)
|
||||
#define RTC_I2C_ARB_LOST_V 0x00000001U
|
||||
#define RTC_I2C_ARB_LOST_S 2
|
||||
/** RTC_I2C_BUS_BUSY : RO; bitpos: [3]; default: 0;
|
||||
* bus is busy
|
||||
*/
|
||||
#define RTC_I2C_BUS_BUSY (BIT(3))
|
||||
#define RTC_I2C_BUS_BUSY_M (RTC_I2C_BUS_BUSY_V << RTC_I2C_BUS_BUSY_S)
|
||||
#define RTC_I2C_BUS_BUSY_V 0x00000001U
|
||||
#define RTC_I2C_BUS_BUSY_S 3
|
||||
/** RTC_I2C_SLAVE_ADDRESSED : RO; bitpos: [4]; default: 0;
|
||||
* slave reg sub address
|
||||
*/
|
||||
#define RTC_I2C_SLAVE_ADDRESSED (BIT(4))
|
||||
#define RTC_I2C_SLAVE_ADDRESSED_M (RTC_I2C_SLAVE_ADDRESSED_V << RTC_I2C_SLAVE_ADDRESSED_S)
|
||||
#define RTC_I2C_SLAVE_ADDRESSED_V 0x00000001U
|
||||
#define RTC_I2C_SLAVE_ADDRESSED_S 4
|
||||
/** RTC_I2C_BYTE_TRANS : RO; bitpos: [5]; default: 0;
|
||||
* One byte transit done
|
||||
*/
|
||||
#define RTC_I2C_BYTE_TRANS (BIT(5))
|
||||
#define RTC_I2C_BYTE_TRANS_M (RTC_I2C_BYTE_TRANS_V << RTC_I2C_BYTE_TRANS_S)
|
||||
#define RTC_I2C_BYTE_TRANS_V 0x00000001U
|
||||
#define RTC_I2C_BYTE_TRANS_S 5
|
||||
/** RTC_I2C_OP_CNT : RO; bitpos: [7:6]; default: 0;
|
||||
* which operation is working
|
||||
*/
|
||||
#define RTC_I2C_OP_CNT 0x00000003U
|
||||
#define RTC_I2C_OP_CNT_M (RTC_I2C_OP_CNT_V << RTC_I2C_OP_CNT_S)
|
||||
#define RTC_I2C_OP_CNT_V 0x00000003U
|
||||
#define RTC_I2C_OP_CNT_S 6
|
||||
/** RTC_I2C_SHIFT_REG : RO; bitpos: [23:16]; default: 0;
|
||||
* shifter content
|
||||
*/
|
||||
#define RTC_I2C_SHIFT_REG 0x000000FFU
|
||||
#define RTC_I2C_SHIFT_REG_M (RTC_I2C_SHIFT_REG_V << RTC_I2C_SHIFT_REG_S)
|
||||
#define RTC_I2C_SHIFT_REG_V 0x000000FFU
|
||||
#define RTC_I2C_SHIFT_REG_S 16
|
||||
/** RTC_I2C_SCL_MAIN_STATE_LAST : RO; bitpos: [26:24]; default: 0;
|
||||
* i2c last main status
|
||||
*/
|
||||
#define RTC_I2C_SCL_MAIN_STATE_LAST 0x00000007U
|
||||
#define RTC_I2C_SCL_MAIN_STATE_LAST_M (RTC_I2C_SCL_MAIN_STATE_LAST_V << RTC_I2C_SCL_MAIN_STATE_LAST_S)
|
||||
#define RTC_I2C_SCL_MAIN_STATE_LAST_V 0x00000007U
|
||||
#define RTC_I2C_SCL_MAIN_STATE_LAST_S 24
|
||||
/** RTC_I2C_SCL_STATE_LAST : RO; bitpos: [30:28]; default: 0;
|
||||
* scl last status
|
||||
*/
|
||||
#define RTC_I2C_SCL_STATE_LAST 0x00000007U
|
||||
#define RTC_I2C_SCL_STATE_LAST_M (RTC_I2C_SCL_STATE_LAST_V << RTC_I2C_SCL_STATE_LAST_S)
|
||||
#define RTC_I2C_SCL_STATE_LAST_V 0x00000007U
|
||||
#define RTC_I2C_SCL_STATE_LAST_S 28
|
||||
|
||||
/** RTC_I2C_TO_REG register
|
||||
* configure time out
|
||||
*/
|
||||
#define RTC_I2C_TO_REG (DR_REG_RTC_I2C_BASE + 0xc)
|
||||
/** RTC_I2C_TIME_OUT_REG : R/W; bitpos: [19:0]; default: 65536;
|
||||
* time out threshold
|
||||
*/
|
||||
#define RTC_I2C_TIME_OUT_REG 0x000FFFFFU
|
||||
#define RTC_I2C_TIME_OUT_REG_M (RTC_I2C_TIME_OUT_REG_V << RTC_I2C_TIME_OUT_REG_S)
|
||||
#define RTC_I2C_TIME_OUT_REG_V 0x000FFFFFU
|
||||
#define RTC_I2C_TIME_OUT_REG_S 0
|
||||
|
||||
/** RTC_I2C_SLAVE_ADDR_REG register
|
||||
* configure slave id
|
||||
*/
|
||||
#define RTC_I2C_SLAVE_ADDR_REG (DR_REG_RTC_I2C_BASE + 0x10)
|
||||
/** RTC_I2C_SLAVE_ADDR : R/W; bitpos: [14:0]; default: 0;
|
||||
* slave address
|
||||
*/
|
||||
#define RTC_I2C_SLAVE_ADDR 0x00007FFFU
|
||||
#define RTC_I2C_SLAVE_ADDR_M (RTC_I2C_SLAVE_ADDR_V << RTC_I2C_SLAVE_ADDR_S)
|
||||
#define RTC_I2C_SLAVE_ADDR_V 0x00007FFFU
|
||||
#define RTC_I2C_SLAVE_ADDR_S 0
|
||||
/** RTC_I2C_ADDR_10BIT_EN : R/W; bitpos: [31]; default: 0;
|
||||
* i2c 10bit mode enable
|
||||
*/
|
||||
#define RTC_I2C_ADDR_10BIT_EN (BIT(31))
|
||||
#define RTC_I2C_ADDR_10BIT_EN_M (RTC_I2C_ADDR_10BIT_EN_V << RTC_I2C_ADDR_10BIT_EN_S)
|
||||
#define RTC_I2C_ADDR_10BIT_EN_V 0x00000001U
|
||||
#define RTC_I2C_ADDR_10BIT_EN_S 31
|
||||
|
||||
/** RTC_I2C_SCL_HIGH_REG register
|
||||
* configure high scl period
|
||||
*/
|
||||
#define RTC_I2C_SCL_HIGH_REG (DR_REG_RTC_I2C_BASE + 0x14)
|
||||
/** RTC_I2C_SCL_HIGH_PERIOD_REG : R/W; bitpos: [19:0]; default: 256;
|
||||
* time period that scl = 1
|
||||
*/
|
||||
#define RTC_I2C_SCL_HIGH_PERIOD_REG 0x000FFFFFU
|
||||
#define RTC_I2C_SCL_HIGH_PERIOD_REG_M (RTC_I2C_SCL_HIGH_PERIOD_REG_V << RTC_I2C_SCL_HIGH_PERIOD_REG_S)
|
||||
#define RTC_I2C_SCL_HIGH_PERIOD_REG_V 0x000FFFFFU
|
||||
#define RTC_I2C_SCL_HIGH_PERIOD_REG_S 0
|
||||
|
||||
/** RTC_I2C_SDA_DUTY_REG register
|
||||
* configure sda duty
|
||||
*/
|
||||
#define RTC_I2C_SDA_DUTY_REG (DR_REG_RTC_I2C_BASE + 0x18)
|
||||
/** RTC_I2C_SDA_DUTY_NUM : R/W; bitpos: [19:0]; default: 16;
|
||||
* time period for SDA to toggle after SCL goes low
|
||||
*/
|
||||
#define RTC_I2C_SDA_DUTY_NUM 0x000FFFFFU
|
||||
#define RTC_I2C_SDA_DUTY_NUM_M (RTC_I2C_SDA_DUTY_NUM_V << RTC_I2C_SDA_DUTY_NUM_S)
|
||||
#define RTC_I2C_SDA_DUTY_NUM_V 0x000FFFFFU
|
||||
#define RTC_I2C_SDA_DUTY_NUM_S 0
|
||||
|
||||
/** RTC_I2C_SCL_START_PERIOD_REG register
|
||||
* configure scl start period
|
||||
*/
|
||||
#define RTC_I2C_SCL_START_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x1c)
|
||||
/** RTC_I2C_SCL_START_PERIOD : R/W; bitpos: [19:0]; default: 8;
|
||||
* time period for SCL to toggle after I2C start is triggered
|
||||
*/
|
||||
#define RTC_I2C_SCL_START_PERIOD 0x000FFFFFU
|
||||
#define RTC_I2C_SCL_START_PERIOD_M (RTC_I2C_SCL_START_PERIOD_V << RTC_I2C_SCL_START_PERIOD_S)
|
||||
#define RTC_I2C_SCL_START_PERIOD_V 0x000FFFFFU
|
||||
#define RTC_I2C_SCL_START_PERIOD_S 0
|
||||
|
||||
/** RTC_I2C_SCL_STOP_PERIOD_REG register
|
||||
* configure scl stop period
|
||||
*/
|
||||
#define RTC_I2C_SCL_STOP_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x20)
|
||||
/** RTC_I2C_SCL_STOP_PERIOD : R/W; bitpos: [19:0]; default: 8;
|
||||
* time period for SCL to stop after I2C end is triggered
|
||||
*/
|
||||
#define RTC_I2C_SCL_STOP_PERIOD 0x000FFFFFU
|
||||
#define RTC_I2C_SCL_STOP_PERIOD_M (RTC_I2C_SCL_STOP_PERIOD_V << RTC_I2C_SCL_STOP_PERIOD_S)
|
||||
#define RTC_I2C_SCL_STOP_PERIOD_V 0x000FFFFFU
|
||||
#define RTC_I2C_SCL_STOP_PERIOD_S 0
|
||||
|
||||
/** RTC_I2C_INT_CLR_REG register
|
||||
* interrupt clear register
|
||||
*/
|
||||
#define RTC_I2C_INT_CLR_REG (DR_REG_RTC_I2C_BASE + 0x24)
|
||||
/** RTC_I2C_SLAVE_TRAN_COMP_INT_CLR : WO; bitpos: [0]; default: 0;
|
||||
* clear slave transit complete interrupt
|
||||
*/
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR (BIT(0))
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_M (RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_V << RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_S)
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_V 0x00000001U
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_S 0
|
||||
/** RTC_I2C_ARBITRATION_LOST_INT_CLR : WO; bitpos: [1]; default: 0;
|
||||
* clear arbitration lost interrupt
|
||||
*/
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_CLR (BIT(1))
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_CLR_M (RTC_I2C_ARBITRATION_LOST_INT_CLR_V << RTC_I2C_ARBITRATION_LOST_INT_CLR_S)
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_CLR_V 0x00000001U
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_CLR_S 1
|
||||
/** RTC_I2C_MASTER_TRAN_COMP_INT_CLR : WO; bitpos: [2]; default: 0;
|
||||
* clear master transit complete interrupt
|
||||
*/
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR (BIT(2))
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_M (RTC_I2C_MASTER_TRAN_COMP_INT_CLR_V << RTC_I2C_MASTER_TRAN_COMP_INT_CLR_S)
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_V 0x00000001U
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_S 2
|
||||
/** RTC_I2C_TRANS_COMPLETE_INT_CLR : WO; bitpos: [3]; default: 0;
|
||||
* clear transit complete interrupt
|
||||
*/
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_CLR (BIT(3))
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_CLR_M (RTC_I2C_TRANS_COMPLETE_INT_CLR_V << RTC_I2C_TRANS_COMPLETE_INT_CLR_S)
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_CLR_V 0x00000001U
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_CLR_S 3
|
||||
/** RTC_I2C_TIME_OUT_INT_CLR : WO; bitpos: [4]; default: 0;
|
||||
* clear time out interrupt
|
||||
*/
|
||||
#define RTC_I2C_TIME_OUT_INT_CLR (BIT(4))
|
||||
#define RTC_I2C_TIME_OUT_INT_CLR_M (RTC_I2C_TIME_OUT_INT_CLR_V << RTC_I2C_TIME_OUT_INT_CLR_S)
|
||||
#define RTC_I2C_TIME_OUT_INT_CLR_V 0x00000001U
|
||||
#define RTC_I2C_TIME_OUT_INT_CLR_S 4
|
||||
/** RTC_I2C_ACK_ERR_INT_CLR : WO; bitpos: [5]; default: 0;
|
||||
* clear ack error interrupt
|
||||
*/
|
||||
#define RTC_I2C_ACK_ERR_INT_CLR (BIT(5))
|
||||
#define RTC_I2C_ACK_ERR_INT_CLR_M (RTC_I2C_ACK_ERR_INT_CLR_V << RTC_I2C_ACK_ERR_INT_CLR_S)
|
||||
#define RTC_I2C_ACK_ERR_INT_CLR_V 0x00000001U
|
||||
#define RTC_I2C_ACK_ERR_INT_CLR_S 5
|
||||
/** RTC_I2C_RX_DATA_INT_CLR : WO; bitpos: [6]; default: 0;
|
||||
* clear receive data interrupt
|
||||
*/
|
||||
#define RTC_I2C_RX_DATA_INT_CLR (BIT(6))
|
||||
#define RTC_I2C_RX_DATA_INT_CLR_M (RTC_I2C_RX_DATA_INT_CLR_V << RTC_I2C_RX_DATA_INT_CLR_S)
|
||||
#define RTC_I2C_RX_DATA_INT_CLR_V 0x00000001U
|
||||
#define RTC_I2C_RX_DATA_INT_CLR_S 6
|
||||
/** RTC_I2C_TX_DATA_INT_CLR : WO; bitpos: [7]; default: 0;
|
||||
* clear transit load data complete interrupt
|
||||
*/
|
||||
#define RTC_I2C_TX_DATA_INT_CLR (BIT(7))
|
||||
#define RTC_I2C_TX_DATA_INT_CLR_M (RTC_I2C_TX_DATA_INT_CLR_V << RTC_I2C_TX_DATA_INT_CLR_S)
|
||||
#define RTC_I2C_TX_DATA_INT_CLR_V 0x00000001U
|
||||
#define RTC_I2C_TX_DATA_INT_CLR_S 7
|
||||
/** RTC_I2C_DETECT_START_INT_CLR : WO; bitpos: [8]; default: 0;
|
||||
* clear detect start interrupt
|
||||
*/
|
||||
#define RTC_I2C_DETECT_START_INT_CLR (BIT(8))
|
||||
#define RTC_I2C_DETECT_START_INT_CLR_M (RTC_I2C_DETECT_START_INT_CLR_V << RTC_I2C_DETECT_START_INT_CLR_S)
|
||||
#define RTC_I2C_DETECT_START_INT_CLR_V 0x00000001U
|
||||
#define RTC_I2C_DETECT_START_INT_CLR_S 8
|
||||
|
||||
/** RTC_I2C_INT_RAW_REG register
|
||||
* interrupt raw register
|
||||
*/
|
||||
#define RTC_I2C_INT_RAW_REG (DR_REG_RTC_I2C_BASE + 0x28)
|
||||
/** RTC_I2C_SLAVE_TRAN_COMP_INT_RAW : RO; bitpos: [0]; default: 0;
|
||||
* slave transit complete interrupt raw
|
||||
*/
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW (BIT(0))
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_M (RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_V << RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_S)
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_V 0x00000001U
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_S 0
|
||||
/** RTC_I2C_ARBITRATION_LOST_INT_RAW : RO; bitpos: [1]; default: 0;
|
||||
* arbitration lost interrupt raw
|
||||
*/
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_RAW (BIT(1))
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_RAW_M (RTC_I2C_ARBITRATION_LOST_INT_RAW_V << RTC_I2C_ARBITRATION_LOST_INT_RAW_S)
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_RAW_V 0x00000001U
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_RAW_S 1
|
||||
/** RTC_I2C_MASTER_TRAN_COMP_INT_RAW : RO; bitpos: [2]; default: 0;
|
||||
* master transit complete interrupt raw
|
||||
*/
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW (BIT(2))
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_M (RTC_I2C_MASTER_TRAN_COMP_INT_RAW_V << RTC_I2C_MASTER_TRAN_COMP_INT_RAW_S)
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_V 0x00000001U
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_S 2
|
||||
/** RTC_I2C_TRANS_COMPLETE_INT_RAW : RO; bitpos: [3]; default: 0;
|
||||
* transit complete interrupt raw
|
||||
*/
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_RAW (BIT(3))
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_RAW_M (RTC_I2C_TRANS_COMPLETE_INT_RAW_V << RTC_I2C_TRANS_COMPLETE_INT_RAW_S)
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_RAW_V 0x00000001U
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_RAW_S 3
|
||||
/** RTC_I2C_TIME_OUT_INT_RAW : RO; bitpos: [4]; default: 0;
|
||||
* time out interrupt raw
|
||||
*/
|
||||
#define RTC_I2C_TIME_OUT_INT_RAW (BIT(4))
|
||||
#define RTC_I2C_TIME_OUT_INT_RAW_M (RTC_I2C_TIME_OUT_INT_RAW_V << RTC_I2C_TIME_OUT_INT_RAW_S)
|
||||
#define RTC_I2C_TIME_OUT_INT_RAW_V 0x00000001U
|
||||
#define RTC_I2C_TIME_OUT_INT_RAW_S 4
|
||||
/** RTC_I2C_ACK_ERR_INT_RAW : RO; bitpos: [5]; default: 0;
|
||||
* ack error interrupt raw
|
||||
*/
|
||||
#define RTC_I2C_ACK_ERR_INT_RAW (BIT(5))
|
||||
#define RTC_I2C_ACK_ERR_INT_RAW_M (RTC_I2C_ACK_ERR_INT_RAW_V << RTC_I2C_ACK_ERR_INT_RAW_S)
|
||||
#define RTC_I2C_ACK_ERR_INT_RAW_V 0x00000001U
|
||||
#define RTC_I2C_ACK_ERR_INT_RAW_S 5
|
||||
/** RTC_I2C_RX_DATA_INT_RAW : RO; bitpos: [6]; default: 0;
|
||||
* receive data interrupt raw
|
||||
*/
|
||||
#define RTC_I2C_RX_DATA_INT_RAW (BIT(6))
|
||||
#define RTC_I2C_RX_DATA_INT_RAW_M (RTC_I2C_RX_DATA_INT_RAW_V << RTC_I2C_RX_DATA_INT_RAW_S)
|
||||
#define RTC_I2C_RX_DATA_INT_RAW_V 0x00000001U
|
||||
#define RTC_I2C_RX_DATA_INT_RAW_S 6
|
||||
/** RTC_I2C_TX_DATA_INT_RAW : RO; bitpos: [7]; default: 0;
|
||||
* transit data interrupt raw
|
||||
*/
|
||||
#define RTC_I2C_TX_DATA_INT_RAW (BIT(7))
|
||||
#define RTC_I2C_TX_DATA_INT_RAW_M (RTC_I2C_TX_DATA_INT_RAW_V << RTC_I2C_TX_DATA_INT_RAW_S)
|
||||
#define RTC_I2C_TX_DATA_INT_RAW_V 0x00000001U
|
||||
#define RTC_I2C_TX_DATA_INT_RAW_S 7
|
||||
/** RTC_I2C_DETECT_START_INT_RAW : RO; bitpos: [8]; default: 0;
|
||||
* detect start interrupt raw
|
||||
*/
|
||||
#define RTC_I2C_DETECT_START_INT_RAW (BIT(8))
|
||||
#define RTC_I2C_DETECT_START_INT_RAW_M (RTC_I2C_DETECT_START_INT_RAW_V << RTC_I2C_DETECT_START_INT_RAW_S)
|
||||
#define RTC_I2C_DETECT_START_INT_RAW_V 0x00000001U
|
||||
#define RTC_I2C_DETECT_START_INT_RAW_S 8
|
||||
|
||||
/** RTC_I2C_INT_ST_REG register
|
||||
* interrupt state register
|
||||
*/
|
||||
#define RTC_I2C_INT_ST_REG (DR_REG_RTC_I2C_BASE + 0x2c)
|
||||
/** RTC_I2C_SLAVE_TRAN_COMP_INT_ST : RO; bitpos: [0]; default: 0;
|
||||
* slave transit complete interrupt state
|
||||
*/
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST (BIT(0))
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_M (RTC_I2C_SLAVE_TRAN_COMP_INT_ST_V << RTC_I2C_SLAVE_TRAN_COMP_INT_ST_S)
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_V 0x00000001U
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_S 0
|
||||
/** RTC_I2C_ARBITRATION_LOST_INT_ST : RO; bitpos: [1]; default: 0;
|
||||
* arbitration lost interrupt state
|
||||
*/
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_ST (BIT(1))
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_ST_M (RTC_I2C_ARBITRATION_LOST_INT_ST_V << RTC_I2C_ARBITRATION_LOST_INT_ST_S)
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_ST_V 0x00000001U
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_ST_S 1
|
||||
/** RTC_I2C_MASTER_TRAN_COMP_INT_ST : RO; bitpos: [2]; default: 0;
|
||||
* master transit complete interrupt state
|
||||
*/
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_ST (BIT(2))
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_M (RTC_I2C_MASTER_TRAN_COMP_INT_ST_V << RTC_I2C_MASTER_TRAN_COMP_INT_ST_S)
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_V 0x00000001U
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_S 2
|
||||
/** RTC_I2C_TRANS_COMPLETE_INT_ST : RO; bitpos: [3]; default: 0;
|
||||
* transit complete interrupt state
|
||||
*/
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_ST (BIT(3))
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_ST_M (RTC_I2C_TRANS_COMPLETE_INT_ST_V << RTC_I2C_TRANS_COMPLETE_INT_ST_S)
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_ST_V 0x00000001U
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_ST_S 3
|
||||
/** RTC_I2C_TIME_OUT_INT_ST : RO; bitpos: [4]; default: 0;
|
||||
* time out interrupt state
|
||||
*/
|
||||
#define RTC_I2C_TIME_OUT_INT_ST (BIT(4))
|
||||
#define RTC_I2C_TIME_OUT_INT_ST_M (RTC_I2C_TIME_OUT_INT_ST_V << RTC_I2C_TIME_OUT_INT_ST_S)
|
||||
#define RTC_I2C_TIME_OUT_INT_ST_V 0x00000001U
|
||||
#define RTC_I2C_TIME_OUT_INT_ST_S 4
|
||||
/** RTC_I2C_ACK_ERR_INT_ST : RO; bitpos: [5]; default: 0;
|
||||
* ack error interrupt state
|
||||
*/
|
||||
#define RTC_I2C_ACK_ERR_INT_ST (BIT(5))
|
||||
#define RTC_I2C_ACK_ERR_INT_ST_M (RTC_I2C_ACK_ERR_INT_ST_V << RTC_I2C_ACK_ERR_INT_ST_S)
|
||||
#define RTC_I2C_ACK_ERR_INT_ST_V 0x00000001U
|
||||
#define RTC_I2C_ACK_ERR_INT_ST_S 5
|
||||
/** RTC_I2C_RX_DATA_INT_ST : RO; bitpos: [6]; default: 0;
|
||||
* receive data interrupt state
|
||||
*/
|
||||
#define RTC_I2C_RX_DATA_INT_ST (BIT(6))
|
||||
#define RTC_I2C_RX_DATA_INT_ST_M (RTC_I2C_RX_DATA_INT_ST_V << RTC_I2C_RX_DATA_INT_ST_S)
|
||||
#define RTC_I2C_RX_DATA_INT_ST_V 0x00000001U
|
||||
#define RTC_I2C_RX_DATA_INT_ST_S 6
|
||||
/** RTC_I2C_TX_DATA_INT_ST : RO; bitpos: [7]; default: 0;
|
||||
* transit data interrupt state
|
||||
*/
|
||||
#define RTC_I2C_TX_DATA_INT_ST (BIT(7))
|
||||
#define RTC_I2C_TX_DATA_INT_ST_M (RTC_I2C_TX_DATA_INT_ST_V << RTC_I2C_TX_DATA_INT_ST_S)
|
||||
#define RTC_I2C_TX_DATA_INT_ST_V 0x00000001U
|
||||
#define RTC_I2C_TX_DATA_INT_ST_S 7
|
||||
/** RTC_I2C_DETECT_START_INT_ST : RO; bitpos: [8]; default: 0;
|
||||
* detect start interrupt state
|
||||
*/
|
||||
#define RTC_I2C_DETECT_START_INT_ST (BIT(8))
|
||||
#define RTC_I2C_DETECT_START_INT_ST_M (RTC_I2C_DETECT_START_INT_ST_V << RTC_I2C_DETECT_START_INT_ST_S)
|
||||
#define RTC_I2C_DETECT_START_INT_ST_V 0x00000001U
|
||||
#define RTC_I2C_DETECT_START_INT_ST_S 8
|
||||
|
||||
/** RTC_I2C_INT_ENA_REG register
|
||||
* interrupt enable register
|
||||
*/
|
||||
#define RTC_I2C_INT_ENA_REG (DR_REG_RTC_I2C_BASE + 0x30)
|
||||
/** RTC_I2C_SLAVE_TRAN_COMP_INT_ENA : R/W; bitpos: [0]; default: 0;
|
||||
* enable slave transit complete interrupt
|
||||
*/
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA (BIT(0))
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_M (RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_V << RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_S)
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_V 0x00000001U
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_S 0
|
||||
/** RTC_I2C_ARBITRATION_LOST_INT_ENA : R/W; bitpos: [1]; default: 0;
|
||||
* enable arbitration lost interrupt
|
||||
*/
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_ENA (BIT(1))
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_ENA_M (RTC_I2C_ARBITRATION_LOST_INT_ENA_V << RTC_I2C_ARBITRATION_LOST_INT_ENA_S)
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_ENA_V 0x00000001U
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_ENA_S 1
|
||||
/** RTC_I2C_MASTER_TRAN_COMP_INT_ENA : R/W; bitpos: [2]; default: 0;
|
||||
* enable master transit complete interrupt
|
||||
*/
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA (BIT(2))
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_M (RTC_I2C_MASTER_TRAN_COMP_INT_ENA_V << RTC_I2C_MASTER_TRAN_COMP_INT_ENA_S)
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_V 0x00000001U
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_S 2
|
||||
/** RTC_I2C_TRANS_COMPLETE_INT_ENA : R/W; bitpos: [3]; default: 0;
|
||||
* enable transit complete interrupt
|
||||
*/
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_ENA (BIT(3))
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_ENA_M (RTC_I2C_TRANS_COMPLETE_INT_ENA_V << RTC_I2C_TRANS_COMPLETE_INT_ENA_S)
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_ENA_V 0x00000001U
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_ENA_S 3
|
||||
/** RTC_I2C_TIME_OUT_INT_ENA : R/W; bitpos: [4]; default: 0;
|
||||
* enable time out interrupt
|
||||
*/
|
||||
#define RTC_I2C_TIME_OUT_INT_ENA (BIT(4))
|
||||
#define RTC_I2C_TIME_OUT_INT_ENA_M (RTC_I2C_TIME_OUT_INT_ENA_V << RTC_I2C_TIME_OUT_INT_ENA_S)
|
||||
#define RTC_I2C_TIME_OUT_INT_ENA_V 0x00000001U
|
||||
#define RTC_I2C_TIME_OUT_INT_ENA_S 4
|
||||
/** RTC_I2C_ACK_ERR_INT_ENA : R/W; bitpos: [5]; default: 0;
|
||||
* enable eack error interrupt
|
||||
*/
|
||||
#define RTC_I2C_ACK_ERR_INT_ENA (BIT(5))
|
||||
#define RTC_I2C_ACK_ERR_INT_ENA_M (RTC_I2C_ACK_ERR_INT_ENA_V << RTC_I2C_ACK_ERR_INT_ENA_S)
|
||||
#define RTC_I2C_ACK_ERR_INT_ENA_V 0x00000001U
|
||||
#define RTC_I2C_ACK_ERR_INT_ENA_S 5
|
||||
/** RTC_I2C_RX_DATA_INT_ENA : R/W; bitpos: [6]; default: 0;
|
||||
* enable receive data interrupt
|
||||
*/
|
||||
#define RTC_I2C_RX_DATA_INT_ENA (BIT(6))
|
||||
#define RTC_I2C_RX_DATA_INT_ENA_M (RTC_I2C_RX_DATA_INT_ENA_V << RTC_I2C_RX_DATA_INT_ENA_S)
|
||||
#define RTC_I2C_RX_DATA_INT_ENA_V 0x00000001U
|
||||
#define RTC_I2C_RX_DATA_INT_ENA_S 6
|
||||
/** RTC_I2C_TX_DATA_INT_ENA : R/W; bitpos: [7]; default: 0;
|
||||
* enable transit data interrupt
|
||||
*/
|
||||
#define RTC_I2C_TX_DATA_INT_ENA (BIT(7))
|
||||
#define RTC_I2C_TX_DATA_INT_ENA_M (RTC_I2C_TX_DATA_INT_ENA_V << RTC_I2C_TX_DATA_INT_ENA_S)
|
||||
#define RTC_I2C_TX_DATA_INT_ENA_V 0x00000001U
|
||||
#define RTC_I2C_TX_DATA_INT_ENA_S 7
|
||||
/** RTC_I2C_DETECT_START_INT_ENA : R/W; bitpos: [8]; default: 0;
|
||||
* enable detect start interrupt
|
||||
*/
|
||||
#define RTC_I2C_DETECT_START_INT_ENA (BIT(8))
|
||||
#define RTC_I2C_DETECT_START_INT_ENA_M (RTC_I2C_DETECT_START_INT_ENA_V << RTC_I2C_DETECT_START_INT_ENA_S)
|
||||
#define RTC_I2C_DETECT_START_INT_ENA_V 0x00000001U
|
||||
#define RTC_I2C_DETECT_START_INT_ENA_S 8
|
||||
|
||||
/** RTC_I2C_DATA_REG register
|
||||
* get i2c data status
|
||||
*/
|
||||
#define RTC_I2C_DATA_REG (DR_REG_RTC_I2C_BASE + 0x34)
|
||||
/** RTC_I2C_I2C_RDATA : RO; bitpos: [7:0]; default: 0;
|
||||
* data received
|
||||
*/
|
||||
#define RTC_I2C_I2C_RDATA 0x000000FFU
|
||||
#define RTC_I2C_I2C_RDATA_M (RTC_I2C_I2C_RDATA_V << RTC_I2C_I2C_RDATA_S)
|
||||
#define RTC_I2C_I2C_RDATA_V 0x000000FFU
|
||||
#define RTC_I2C_I2C_RDATA_S 0
|
||||
/** RTC_I2C_SLAVE_TX_DATA : R/W; bitpos: [15:8]; default: 0;
|
||||
* data sent by slave
|
||||
*/
|
||||
#define RTC_I2C_SLAVE_TX_DATA 0x000000FFU
|
||||
#define RTC_I2C_SLAVE_TX_DATA_M (RTC_I2C_SLAVE_TX_DATA_V << RTC_I2C_SLAVE_TX_DATA_S)
|
||||
#define RTC_I2C_SLAVE_TX_DATA_V 0x000000FFU
|
||||
#define RTC_I2C_SLAVE_TX_DATA_S 8
|
||||
/** RTC_I2C_I2C_DONE : RO; bitpos: [31]; default: 0;
|
||||
* i2c done
|
||||
*/
|
||||
#define RTC_I2C_I2C_DONE (BIT(31))
|
||||
#define RTC_I2C_I2C_DONE_M (RTC_I2C_I2C_DONE_V << RTC_I2C_I2C_DONE_S)
|
||||
#define RTC_I2C_I2C_DONE_V 0x00000001U
|
||||
#define RTC_I2C_I2C_DONE_S 31
|
||||
|
||||
/** RTC_I2C_CMD0_REG register
|
||||
* i2c commond0 register
|
||||
*/
|
||||
#define RTC_I2C_CMD0_REG (DR_REG_RTC_I2C_BASE + 0x38)
|
||||
/** RTC_I2C_COMMAND0 : R/W; bitpos: [13:0]; default: 2307;
|
||||
* command0
|
||||
*/
|
||||
#define RTC_I2C_COMMAND0 0x00003FFFU
|
||||
#define RTC_I2C_COMMAND0_M (RTC_I2C_COMMAND0_V << RTC_I2C_COMMAND0_S)
|
||||
#define RTC_I2C_COMMAND0_V 0x00003FFFU
|
||||
#define RTC_I2C_COMMAND0_S 0
|
||||
/** RTC_I2C_COMMAND0_DONE : RO; bitpos: [31]; default: 0;
|
||||
* command0_done
|
||||
*/
|
||||
#define RTC_I2C_COMMAND0_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND0_DONE_M (RTC_I2C_COMMAND0_DONE_V << RTC_I2C_COMMAND0_DONE_S)
|
||||
#define RTC_I2C_COMMAND0_DONE_V 0x00000001U
|
||||
#define RTC_I2C_COMMAND0_DONE_S 31
|
||||
|
||||
/** RTC_I2C_CMD1_REG register
|
||||
* i2c commond1 register
|
||||
*/
|
||||
#define RTC_I2C_CMD1_REG (DR_REG_RTC_I2C_BASE + 0x3c)
|
||||
/** RTC_I2C_COMMAND1 : R/W; bitpos: [13:0]; default: 6401;
|
||||
* command1
|
||||
*/
|
||||
#define RTC_I2C_COMMAND1 0x00003FFFU
|
||||
#define RTC_I2C_COMMAND1_M (RTC_I2C_COMMAND1_V << RTC_I2C_COMMAND1_S)
|
||||
#define RTC_I2C_COMMAND1_V 0x00003FFFU
|
||||
#define RTC_I2C_COMMAND1_S 0
|
||||
/** RTC_I2C_COMMAND1_DONE : RO; bitpos: [31]; default: 0;
|
||||
* command1_done
|
||||
*/
|
||||
#define RTC_I2C_COMMAND1_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND1_DONE_M (RTC_I2C_COMMAND1_DONE_V << RTC_I2C_COMMAND1_DONE_S)
|
||||
#define RTC_I2C_COMMAND1_DONE_V 0x00000001U
|
||||
#define RTC_I2C_COMMAND1_DONE_S 31
|
||||
|
||||
/** RTC_I2C_CMD2_REG register
|
||||
* i2c commond2 register
|
||||
*/
|
||||
#define RTC_I2C_CMD2_REG (DR_REG_RTC_I2C_BASE + 0x40)
|
||||
/** RTC_I2C_COMMAND2 : R/W; bitpos: [13:0]; default: 2306;
|
||||
* command2
|
||||
*/
|
||||
#define RTC_I2C_COMMAND2 0x00003FFFU
|
||||
#define RTC_I2C_COMMAND2_M (RTC_I2C_COMMAND2_V << RTC_I2C_COMMAND2_S)
|
||||
#define RTC_I2C_COMMAND2_V 0x00003FFFU
|
||||
#define RTC_I2C_COMMAND2_S 0
|
||||
/** RTC_I2C_COMMAND2_DONE : RO; bitpos: [31]; default: 0;
|
||||
* command2_done
|
||||
*/
|
||||
#define RTC_I2C_COMMAND2_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND2_DONE_M (RTC_I2C_COMMAND2_DONE_V << RTC_I2C_COMMAND2_DONE_S)
|
||||
#define RTC_I2C_COMMAND2_DONE_V 0x00000001U
|
||||
#define RTC_I2C_COMMAND2_DONE_S 31
|
||||
|
||||
/** RTC_I2C_CMD3_REG register
|
||||
* i2c commond3 register
|
||||
*/
|
||||
#define RTC_I2C_CMD3_REG (DR_REG_RTC_I2C_BASE + 0x44)
|
||||
/** RTC_I2C_COMMAND3 : R/W; bitpos: [13:0]; default: 257;
|
||||
* command3
|
||||
*/
|
||||
#define RTC_I2C_COMMAND3 0x00003FFFU
|
||||
#define RTC_I2C_COMMAND3_M (RTC_I2C_COMMAND3_V << RTC_I2C_COMMAND3_S)
|
||||
#define RTC_I2C_COMMAND3_V 0x00003FFFU
|
||||
#define RTC_I2C_COMMAND3_S 0
|
||||
/** RTC_I2C_COMMAND3_DONE : RO; bitpos: [31]; default: 0;
|
||||
* command3_done
|
||||
*/
|
||||
#define RTC_I2C_COMMAND3_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND3_DONE_M (RTC_I2C_COMMAND3_DONE_V << RTC_I2C_COMMAND3_DONE_S)
|
||||
#define RTC_I2C_COMMAND3_DONE_V 0x00000001U
|
||||
#define RTC_I2C_COMMAND3_DONE_S 31
|
||||
|
||||
/** RTC_I2C_CMD4_REG register
|
||||
* i2c commond4 register
|
||||
*/
|
||||
#define RTC_I2C_CMD4_REG (DR_REG_RTC_I2C_BASE + 0x48)
|
||||
/** RTC_I2C_COMMAND4 : R/W; bitpos: [13:0]; default: 2305;
|
||||
* command4
|
||||
*/
|
||||
#define RTC_I2C_COMMAND4 0x00003FFFU
|
||||
#define RTC_I2C_COMMAND4_M (RTC_I2C_COMMAND4_V << RTC_I2C_COMMAND4_S)
|
||||
#define RTC_I2C_COMMAND4_V 0x00003FFFU
|
||||
#define RTC_I2C_COMMAND4_S 0
|
||||
/** RTC_I2C_COMMAND4_DONE : RO; bitpos: [31]; default: 0;
|
||||
* command4_done
|
||||
*/
|
||||
#define RTC_I2C_COMMAND4_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND4_DONE_M (RTC_I2C_COMMAND4_DONE_V << RTC_I2C_COMMAND4_DONE_S)
|
||||
#define RTC_I2C_COMMAND4_DONE_V 0x00000001U
|
||||
#define RTC_I2C_COMMAND4_DONE_S 31
|
||||
|
||||
/** RTC_I2C_CMD5_REG register
|
||||
* i2c commond5_register
|
||||
*/
|
||||
#define RTC_I2C_CMD5_REG (DR_REG_RTC_I2C_BASE + 0x4c)
|
||||
/** RTC_I2C_COMMAND5 : R/W; bitpos: [13:0]; default: 5889;
|
||||
* command5
|
||||
*/
|
||||
#define RTC_I2C_COMMAND5 0x00003FFFU
|
||||
#define RTC_I2C_COMMAND5_M (RTC_I2C_COMMAND5_V << RTC_I2C_COMMAND5_S)
|
||||
#define RTC_I2C_COMMAND5_V 0x00003FFFU
|
||||
#define RTC_I2C_COMMAND5_S 0
|
||||
/** RTC_I2C_COMMAND5_DONE : RO; bitpos: [31]; default: 0;
|
||||
* command5_done
|
||||
*/
|
||||
#define RTC_I2C_COMMAND5_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND5_DONE_M (RTC_I2C_COMMAND5_DONE_V << RTC_I2C_COMMAND5_DONE_S)
|
||||
#define RTC_I2C_COMMAND5_DONE_V 0x00000001U
|
||||
#define RTC_I2C_COMMAND5_DONE_S 31
|
||||
|
||||
/** RTC_I2C_CMD6_REG register
|
||||
* i2c commond6 register
|
||||
*/
|
||||
#define RTC_I2C_CMD6_REG (DR_REG_RTC_I2C_BASE + 0x50)
|
||||
/** RTC_I2C_COMMAND6 : R/W; bitpos: [13:0]; default: 6401;
|
||||
* command6
|
||||
*/
|
||||
#define RTC_I2C_COMMAND6 0x00003FFFU
|
||||
#define RTC_I2C_COMMAND6_M (RTC_I2C_COMMAND6_V << RTC_I2C_COMMAND6_S)
|
||||
#define RTC_I2C_COMMAND6_V 0x00003FFFU
|
||||
#define RTC_I2C_COMMAND6_S 0
|
||||
/** RTC_I2C_COMMAND6_DONE : RO; bitpos: [31]; default: 0;
|
||||
* command6_done
|
||||
*/
|
||||
#define RTC_I2C_COMMAND6_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND6_DONE_M (RTC_I2C_COMMAND6_DONE_V << RTC_I2C_COMMAND6_DONE_S)
|
||||
#define RTC_I2C_COMMAND6_DONE_V 0x00000001U
|
||||
#define RTC_I2C_COMMAND6_DONE_S 31
|
||||
|
||||
/** RTC_I2C_CMD7_REG register
|
||||
* i2c commond7 register
|
||||
*/
|
||||
#define RTC_I2C_CMD7_REG (DR_REG_RTC_I2C_BASE + 0x54)
|
||||
/** RTC_I2C_COMMAND7 : R/W; bitpos: [13:0]; default: 2308;
|
||||
* command7
|
||||
*/
|
||||
#define RTC_I2C_COMMAND7 0x00003FFFU
|
||||
#define RTC_I2C_COMMAND7_M (RTC_I2C_COMMAND7_V << RTC_I2C_COMMAND7_S)
|
||||
#define RTC_I2C_COMMAND7_V 0x00003FFFU
|
||||
#define RTC_I2C_COMMAND7_S 0
|
||||
/** RTC_I2C_COMMAND7_DONE : RO; bitpos: [31]; default: 0;
|
||||
* command7_done
|
||||
*/
|
||||
#define RTC_I2C_COMMAND7_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND7_DONE_M (RTC_I2C_COMMAND7_DONE_V << RTC_I2C_COMMAND7_DONE_S)
|
||||
#define RTC_I2C_COMMAND7_DONE_V 0x00000001U
|
||||
#define RTC_I2C_COMMAND7_DONE_S 31
|
||||
|
||||
/** RTC_I2C_CMD8_REG register
|
||||
* i2c commond8 register
|
||||
*/
|
||||
#define RTC_I2C_CMD8_REG (DR_REG_RTC_I2C_BASE + 0x58)
|
||||
/** RTC_I2C_COMMAND8 : R/W; bitpos: [13:0]; default: 6401;
|
||||
* command8
|
||||
*/
|
||||
#define RTC_I2C_COMMAND8 0x00003FFFU
|
||||
#define RTC_I2C_COMMAND8_M (RTC_I2C_COMMAND8_V << RTC_I2C_COMMAND8_S)
|
||||
#define RTC_I2C_COMMAND8_V 0x00003FFFU
|
||||
#define RTC_I2C_COMMAND8_S 0
|
||||
/** RTC_I2C_COMMAND8_DONE : RO; bitpos: [31]; default: 0;
|
||||
* command8_done
|
||||
*/
|
||||
#define RTC_I2C_COMMAND8_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND8_DONE_M (RTC_I2C_COMMAND8_DONE_V << RTC_I2C_COMMAND8_DONE_S)
|
||||
#define RTC_I2C_COMMAND8_DONE_V 0x00000001U
|
||||
#define RTC_I2C_COMMAND8_DONE_S 31
|
||||
|
||||
/** RTC_I2C_CMD9_REG register
|
||||
* i2c commond9 register
|
||||
*/
|
||||
#define RTC_I2C_CMD9_REG (DR_REG_RTC_I2C_BASE + 0x5c)
|
||||
/** RTC_I2C_COMMAND9 : R/W; bitpos: [13:0]; default: 2307;
|
||||
* command9
|
||||
*/
|
||||
#define RTC_I2C_COMMAND9 0x00003FFFU
|
||||
#define RTC_I2C_COMMAND9_M (RTC_I2C_COMMAND9_V << RTC_I2C_COMMAND9_S)
|
||||
#define RTC_I2C_COMMAND9_V 0x00003FFFU
|
||||
#define RTC_I2C_COMMAND9_S 0
|
||||
/** RTC_I2C_COMMAND9_DONE : RO; bitpos: [31]; default: 0;
|
||||
* command9_done
|
||||
*/
|
||||
#define RTC_I2C_COMMAND9_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND9_DONE_M (RTC_I2C_COMMAND9_DONE_V << RTC_I2C_COMMAND9_DONE_S)
|
||||
#define RTC_I2C_COMMAND9_DONE_V 0x00000001U
|
||||
#define RTC_I2C_COMMAND9_DONE_S 31
|
||||
|
||||
/** RTC_I2C_CMD10_REG register
|
||||
* i2c commond10 register
|
||||
*/
|
||||
#define RTC_I2C_CMD10_REG (DR_REG_RTC_I2C_BASE + 0x60)
|
||||
/** RTC_I2C_COMMAND10 : R/W; bitpos: [13:0]; default: 257;
|
||||
* command10
|
||||
*/
|
||||
#define RTC_I2C_COMMAND10 0x00003FFFU
|
||||
#define RTC_I2C_COMMAND10_M (RTC_I2C_COMMAND10_V << RTC_I2C_COMMAND10_S)
|
||||
#define RTC_I2C_COMMAND10_V 0x00003FFFU
|
||||
#define RTC_I2C_COMMAND10_S 0
|
||||
/** RTC_I2C_COMMAND10_DONE : RO; bitpos: [31]; default: 0;
|
||||
* command10_done
|
||||
*/
|
||||
#define RTC_I2C_COMMAND10_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND10_DONE_M (RTC_I2C_COMMAND10_DONE_V << RTC_I2C_COMMAND10_DONE_S)
|
||||
#define RTC_I2C_COMMAND10_DONE_V 0x00000001U
|
||||
#define RTC_I2C_COMMAND10_DONE_S 31
|
||||
|
||||
/** RTC_I2C_CMD11_REG register
|
||||
* i2c commond11 register
|
||||
*/
|
||||
#define RTC_I2C_CMD11_REG (DR_REG_RTC_I2C_BASE + 0x64)
|
||||
/** RTC_I2C_COMMAND11 : R/W; bitpos: [13:0]; default: 2305;
|
||||
* command11
|
||||
*/
|
||||
#define RTC_I2C_COMMAND11 0x00003FFFU
|
||||
#define RTC_I2C_COMMAND11_M (RTC_I2C_COMMAND11_V << RTC_I2C_COMMAND11_S)
|
||||
#define RTC_I2C_COMMAND11_V 0x00003FFFU
|
||||
#define RTC_I2C_COMMAND11_S 0
|
||||
/** RTC_I2C_COMMAND11_DONE : RO; bitpos: [31]; default: 0;
|
||||
* command11_done
|
||||
*/
|
||||
#define RTC_I2C_COMMAND11_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND11_DONE_M (RTC_I2C_COMMAND11_DONE_V << RTC_I2C_COMMAND11_DONE_S)
|
||||
#define RTC_I2C_COMMAND11_DONE_V 0x00000001U
|
||||
#define RTC_I2C_COMMAND11_DONE_S 31
|
||||
|
||||
/** RTC_I2C_CMD12_REG register
|
||||
* i2c commond12 register
|
||||
*/
|
||||
#define RTC_I2C_CMD12_REG (DR_REG_RTC_I2C_BASE + 0x68)
|
||||
/** RTC_I2C_COMMAND12 : R/W; bitpos: [13:0]; default: 5889;
|
||||
* command12
|
||||
*/
|
||||
#define RTC_I2C_COMMAND12 0x00003FFFU
|
||||
#define RTC_I2C_COMMAND12_M (RTC_I2C_COMMAND12_V << RTC_I2C_COMMAND12_S)
|
||||
#define RTC_I2C_COMMAND12_V 0x00003FFFU
|
||||
#define RTC_I2C_COMMAND12_S 0
|
||||
/** RTC_I2C_COMMAND12_DONE : RO; bitpos: [31]; default: 0;
|
||||
* command12_done
|
||||
*/
|
||||
#define RTC_I2C_COMMAND12_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND12_DONE_M (RTC_I2C_COMMAND12_DONE_V << RTC_I2C_COMMAND12_DONE_S)
|
||||
#define RTC_I2C_COMMAND12_DONE_V 0x00000001U
|
||||
#define RTC_I2C_COMMAND12_DONE_S 31
|
||||
|
||||
/** RTC_I2C_CMD13_REG register
|
||||
* i2c commond13 register
|
||||
*/
|
||||
#define RTC_I2C_CMD13_REG (DR_REG_RTC_I2C_BASE + 0x6c)
|
||||
/** RTC_I2C_COMMAND13 : R/W; bitpos: [13:0]; default: 6401;
|
||||
* command13
|
||||
*/
|
||||
#define RTC_I2C_COMMAND13 0x00003FFFU
|
||||
#define RTC_I2C_COMMAND13_M (RTC_I2C_COMMAND13_V << RTC_I2C_COMMAND13_S)
|
||||
#define RTC_I2C_COMMAND13_V 0x00003FFFU
|
||||
#define RTC_I2C_COMMAND13_S 0
|
||||
/** RTC_I2C_COMMAND13_DONE : RO; bitpos: [31]; default: 0;
|
||||
* command13_done
|
||||
*/
|
||||
#define RTC_I2C_COMMAND13_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND13_DONE_M (RTC_I2C_COMMAND13_DONE_V << RTC_I2C_COMMAND13_DONE_S)
|
||||
#define RTC_I2C_COMMAND13_DONE_V 0x00000001U
|
||||
#define RTC_I2C_COMMAND13_DONE_S 31
|
||||
|
||||
/** RTC_I2C_CMD14_REG register
|
||||
* i2c commond14 register
|
||||
*/
|
||||
#define RTC_I2C_CMD14_REG (DR_REG_RTC_I2C_BASE + 0x70)
|
||||
/** RTC_I2C_COMMAND14 : R/W; bitpos: [13:0]; default: 0;
|
||||
* command14
|
||||
*/
|
||||
#define RTC_I2C_COMMAND14 0x00003FFFU
|
||||
#define RTC_I2C_COMMAND14_M (RTC_I2C_COMMAND14_V << RTC_I2C_COMMAND14_S)
|
||||
#define RTC_I2C_COMMAND14_V 0x00003FFFU
|
||||
#define RTC_I2C_COMMAND14_S 0
|
||||
/** RTC_I2C_COMMAND14_DONE : RO; bitpos: [31]; default: 0;
|
||||
* command14_done
|
||||
*/
|
||||
#define RTC_I2C_COMMAND14_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND14_DONE_M (RTC_I2C_COMMAND14_DONE_V << RTC_I2C_COMMAND14_DONE_S)
|
||||
#define RTC_I2C_COMMAND14_DONE_V 0x00000001U
|
||||
#define RTC_I2C_COMMAND14_DONE_S 31
|
||||
|
||||
/** RTC_I2C_CMD15_REG register
|
||||
* i2c commond15 register
|
||||
*/
|
||||
#define RTC_I2C_CMD15_REG (DR_REG_RTC_I2C_BASE + 0x74)
|
||||
/** RTC_I2C_COMMAND15 : R/W; bitpos: [13:0]; default: 0;
|
||||
* command15
|
||||
*/
|
||||
#define RTC_I2C_COMMAND15 0x00003FFFU
|
||||
#define RTC_I2C_COMMAND15_M (RTC_I2C_COMMAND15_V << RTC_I2C_COMMAND15_S)
|
||||
#define RTC_I2C_COMMAND15_V 0x00003FFFU
|
||||
#define RTC_I2C_COMMAND15_S 0
|
||||
/** RTC_I2C_COMMAND15_DONE : RO; bitpos: [31]; default: 0;
|
||||
* command15_done
|
||||
*/
|
||||
#define RTC_I2C_COMMAND15_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND15_DONE_M (RTC_I2C_COMMAND15_DONE_V << RTC_I2C_COMMAND15_DONE_S)
|
||||
#define RTC_I2C_COMMAND15_DONE_V 0x00000001U
|
||||
#define RTC_I2C_COMMAND15_DONE_S 31
|
||||
|
||||
/** RTC_I2C_DATE_REG register
|
||||
* version register
|
||||
*/
|
||||
#define RTC_I2C_DATE_REG (DR_REG_RTC_I2C_BASE + 0xfc)
|
||||
/** RTC_I2C_I2C_DATE : R/W; bitpos: [27:0]; default: 26235664;
|
||||
* version
|
||||
*/
|
||||
#define RTC_I2C_I2C_DATE 0x0FFFFFFFU
|
||||
#define RTC_I2C_I2C_DATE_M (RTC_I2C_I2C_DATE_V << RTC_I2C_I2C_DATE_S)
|
||||
#define RTC_I2C_I2C_DATE_V 0x0FFFFFFFU
|
||||
#define RTC_I2C_I2C_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,499 +0,0 @@
|
||||
/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Group: Configure Registers */
|
||||
/** Type of i2c_scl_low register
|
||||
* configure low scl period
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** i2c_scl_low_period_reg : R/W; bitpos: [19:0]; default: 256;
|
||||
* time period that scl =0
|
||||
*/
|
||||
uint32_t i2c_scl_low_period_reg:20;
|
||||
uint32_t reserved_20:12;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_i2c_scl_low_reg_t;
|
||||
|
||||
/** Type of i2c_ctrl register
|
||||
* configure i2c ctrl
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** i2c_sda_force_out : R/W; bitpos: [0]; default: 0;
|
||||
* 1=push pull,0=open drain
|
||||
*/
|
||||
uint32_t i2c_sda_force_out:1;
|
||||
/** i2c_scl_force_out : R/W; bitpos: [1]; default: 0;
|
||||
* 1=push pull,0=open drain
|
||||
*/
|
||||
uint32_t i2c_scl_force_out:1;
|
||||
/** i2c_ms_mode : R/W; bitpos: [2]; default: 0;
|
||||
* 1=master,0=slave
|
||||
*/
|
||||
uint32_t i2c_ms_mode:1;
|
||||
/** i2c_trans_start : R/W; bitpos: [3]; default: 0;
|
||||
* force start
|
||||
*/
|
||||
uint32_t i2c_trans_start:1;
|
||||
/** i2c_tx_lsb_first : R/W; bitpos: [4]; default: 0;
|
||||
* transit lsb first
|
||||
*/
|
||||
uint32_t i2c_tx_lsb_first:1;
|
||||
/** i2c_rx_lsb_first : R/W; bitpos: [5]; default: 0;
|
||||
* receive lsb first
|
||||
*/
|
||||
uint32_t i2c_rx_lsb_first:1;
|
||||
uint32_t reserved_6:23;
|
||||
/** i2c_i2c_ctrl_clk_gate_en : R/W; bitpos: [29]; default: 0;
|
||||
* configure i2c ctrl clk enable
|
||||
*/
|
||||
uint32_t i2c_i2c_ctrl_clk_gate_en:1;
|
||||
/** i2c_i2c_reset : R/W; bitpos: [30]; default: 0;
|
||||
* rtc i2c sw reset
|
||||
*/
|
||||
uint32_t i2c_i2c_reset:1;
|
||||
/** i2c_i2cclk_en : R/W; bitpos: [31]; default: 0;
|
||||
* rtc i2c reg clk gating
|
||||
*/
|
||||
uint32_t i2c_i2cclk_en:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_i2c_ctrl_reg_t;
|
||||
|
||||
/** Type of i2c_to register
|
||||
* configure time out
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** i2c_time_out_reg : R/W; bitpos: [19:0]; default: 65536;
|
||||
* time out threshold
|
||||
*/
|
||||
uint32_t i2c_time_out_reg:20;
|
||||
uint32_t reserved_20:12;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_i2c_to_reg_t;
|
||||
|
||||
/** Type of i2c_slave_addr register
|
||||
* configure slave id
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** i2c_slave_addr : R/W; bitpos: [14:0]; default: 0;
|
||||
* slave address
|
||||
*/
|
||||
uint32_t i2c_slave_addr:15;
|
||||
uint32_t reserved_15:16;
|
||||
/** i2c_addr_10bit_en : R/W; bitpos: [31]; default: 0;
|
||||
* i2c 10bit mode enable
|
||||
*/
|
||||
uint32_t i2c_addr_10bit_en:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_i2c_slave_addr_reg_t;
|
||||
|
||||
/** Type of i2c_scl_high register
|
||||
* configure high scl period
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** i2c_scl_high_period_reg : R/W; bitpos: [19:0]; default: 256;
|
||||
* time period that scl = 1
|
||||
*/
|
||||
uint32_t i2c_scl_high_period_reg:20;
|
||||
uint32_t reserved_20:12;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_i2c_scl_high_reg_t;
|
||||
|
||||
/** Type of i2c_sda_duty register
|
||||
* configure sda duty
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** i2c_sda_duty_num : R/W; bitpos: [19:0]; default: 16;
|
||||
* time period for SDA to toggle after SCL goes low
|
||||
*/
|
||||
uint32_t i2c_sda_duty_num:20;
|
||||
uint32_t reserved_20:12;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_i2c_sda_duty_reg_t;
|
||||
|
||||
/** Type of i2c_scl_start_period register
|
||||
* configure scl start period
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** i2c_scl_start_period : R/W; bitpos: [19:0]; default: 8;
|
||||
* time period for SCL to toggle after I2C start is triggered
|
||||
*/
|
||||
uint32_t i2c_scl_start_period:20;
|
||||
uint32_t reserved_20:12;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_i2c_scl_start_period_reg_t;
|
||||
|
||||
/** Type of i2c_scl_stop_period register
|
||||
* configure scl stop period
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** i2c_scl_stop_period : R/W; bitpos: [19:0]; default: 8;
|
||||
* time period for SCL to stop after I2C end is triggered
|
||||
*/
|
||||
uint32_t i2c_scl_stop_period:20;
|
||||
uint32_t reserved_20:12;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_i2c_scl_stop_period_reg_t;
|
||||
|
||||
/** Type of i2c_data register
|
||||
* get i2c data status
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** i2c_i2c_rdata : RO; bitpos: [7:0]; default: 0;
|
||||
* data received
|
||||
*/
|
||||
uint32_t i2c_i2c_rdata:8;
|
||||
/** i2c_slave_tx_data : R/W; bitpos: [15:8]; default: 0;
|
||||
* data sent by slave
|
||||
*/
|
||||
uint32_t i2c_slave_tx_data:8;
|
||||
uint32_t reserved_16:15;
|
||||
/** i2c_i2c_done : RO; bitpos: [31]; default: 0;
|
||||
* i2c done
|
||||
*/
|
||||
uint32_t i2c_i2c_done:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_i2c_data_reg_t;
|
||||
|
||||
/** Type of i2c_cmd register
|
||||
* i2c command register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** i2c_command : R/W; bitpos: [13:0]; default: 2307;
|
||||
* command
|
||||
*/
|
||||
uint32_t i2c_byte_num:8;
|
||||
uint32_t i2c_ack_en:1;
|
||||
uint32_t i2c_ack_exp:1;
|
||||
uint32_t i2c_ack_val:1;
|
||||
uint32_t i2c_op_code:3;
|
||||
uint32_t reserved14:17;
|
||||
/** i2c_command_done : RO; bitpos: [31]; default: 0;
|
||||
* command0_done
|
||||
*/
|
||||
uint32_t i2c_command_done:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_i2c_cmd_reg_t;
|
||||
|
||||
/** Group: status register */
|
||||
/** Type of i2c_status register
|
||||
* get i2c status
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** i2c_ack_rec : RO; bitpos: [0]; default: 0;
|
||||
* ack response
|
||||
*/
|
||||
uint32_t i2c_ack_rec:1;
|
||||
/** i2c_slave_rw : RO; bitpos: [1]; default: 0;
|
||||
* slave read or write
|
||||
*/
|
||||
uint32_t i2c_slave_rw:1;
|
||||
/** i2c_arb_lost : RO; bitpos: [2]; default: 0;
|
||||
* arbitration is lost
|
||||
*/
|
||||
uint32_t i2c_arb_lost:1;
|
||||
/** i2c_bus_busy : RO; bitpos: [3]; default: 0;
|
||||
* bus is busy
|
||||
*/
|
||||
uint32_t i2c_bus_busy:1;
|
||||
/** i2c_slave_addressed : RO; bitpos: [4]; default: 0;
|
||||
* slave reg sub address
|
||||
*/
|
||||
uint32_t i2c_slave_addressed:1;
|
||||
/** i2c_byte_trans : RO; bitpos: [5]; default: 0;
|
||||
* One byte transit done
|
||||
*/
|
||||
uint32_t i2c_byte_trans:1;
|
||||
/** i2c_op_cnt : RO; bitpos: [7:6]; default: 0;
|
||||
* which operation is working
|
||||
*/
|
||||
uint32_t i2c_op_cnt:2;
|
||||
uint32_t reserved_8:8;
|
||||
/** i2c_shift_reg : RO; bitpos: [23:16]; default: 0;
|
||||
* shifter content
|
||||
*/
|
||||
uint32_t i2c_shift_reg:8;
|
||||
/** i2c_scl_main_state_last : RO; bitpos: [26:24]; default: 0;
|
||||
* i2c last main status
|
||||
*/
|
||||
uint32_t i2c_scl_main_state_last:3;
|
||||
uint32_t reserved_27:1;
|
||||
/** i2c_scl_state_last : RO; bitpos: [30:28]; default: 0;
|
||||
* scl last status
|
||||
*/
|
||||
uint32_t i2c_scl_state_last:3;
|
||||
uint32_t reserved_31:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_i2c_status_reg_t;
|
||||
|
||||
|
||||
/** Group: interrupt Register */
|
||||
/** Type of i2c_int_clr register
|
||||
* interrupt clear register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** i2c_slave_tran_comp_int_clr : WO; bitpos: [0]; default: 0;
|
||||
* clear slave transit complete interrupt
|
||||
*/
|
||||
uint32_t i2c_slave_tran_comp_int_clr:1;
|
||||
/** i2c_arbitration_lost_int_clr : WO; bitpos: [1]; default: 0;
|
||||
* clear arbitration lost interrupt
|
||||
*/
|
||||
uint32_t i2c_arbitration_lost_int_clr:1;
|
||||
/** i2c_master_tran_comp_int_clr : WO; bitpos: [2]; default: 0;
|
||||
* clear master transit complete interrupt
|
||||
*/
|
||||
uint32_t i2c_master_tran_comp_int_clr:1;
|
||||
/** i2c_trans_complete_int_clr : WO; bitpos: [3]; default: 0;
|
||||
* clear transit complete interrupt
|
||||
*/
|
||||
uint32_t i2c_trans_complete_int_clr:1;
|
||||
/** i2c_time_out_int_clr : WO; bitpos: [4]; default: 0;
|
||||
* clear time out interrupt
|
||||
*/
|
||||
uint32_t i2c_time_out_int_clr:1;
|
||||
/** i2c_ack_err_int_clr : WO; bitpos: [5]; default: 0;
|
||||
* clear ack error interrupt
|
||||
*/
|
||||
uint32_t i2c_ack_err_int_clr:1;
|
||||
/** i2c_rx_data_int_clr : WO; bitpos: [6]; default: 0;
|
||||
* clear receive data interrupt
|
||||
*/
|
||||
uint32_t i2c_rx_data_int_clr:1;
|
||||
/** i2c_tx_data_int_clr : WO; bitpos: [7]; default: 0;
|
||||
* clear transit load data complete interrupt
|
||||
*/
|
||||
uint32_t i2c_tx_data_int_clr:1;
|
||||
/** i2c_detect_start_int_clr : WO; bitpos: [8]; default: 0;
|
||||
* clear detect start interrupt
|
||||
*/
|
||||
uint32_t i2c_detect_start_int_clr:1;
|
||||
uint32_t reserved_9:23;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_i2c_int_clr_reg_t;
|
||||
|
||||
/** Type of i2c_int_raw register
|
||||
* interrupt raw register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** i2c_slave_tran_comp_int_raw : RO; bitpos: [0]; default: 0;
|
||||
* slave transit complete interrupt raw
|
||||
*/
|
||||
uint32_t i2c_slave_tran_comp_int_raw:1;
|
||||
/** i2c_arbitration_lost_int_raw : RO; bitpos: [1]; default: 0;
|
||||
* arbitration lost interrupt raw
|
||||
*/
|
||||
uint32_t i2c_arbitration_lost_int_raw:1;
|
||||
/** i2c_master_tran_comp_int_raw : RO; bitpos: [2]; default: 0;
|
||||
* master transit complete interrupt raw
|
||||
*/
|
||||
uint32_t i2c_master_tran_comp_int_raw:1;
|
||||
/** i2c_trans_complete_int_raw : RO; bitpos: [3]; default: 0;
|
||||
* transit complete interrupt raw
|
||||
*/
|
||||
uint32_t i2c_trans_complete_int_raw:1;
|
||||
/** i2c_time_out_int_raw : RO; bitpos: [4]; default: 0;
|
||||
* time out interrupt raw
|
||||
*/
|
||||
uint32_t i2c_time_out_int_raw:1;
|
||||
/** i2c_ack_err_int_raw : RO; bitpos: [5]; default: 0;
|
||||
* ack error interrupt raw
|
||||
*/
|
||||
uint32_t i2c_ack_err_int_raw:1;
|
||||
/** i2c_rx_data_int_raw : RO; bitpos: [6]; default: 0;
|
||||
* receive data interrupt raw
|
||||
*/
|
||||
uint32_t i2c_rx_data_int_raw:1;
|
||||
/** i2c_tx_data_int_raw : RO; bitpos: [7]; default: 0;
|
||||
* transit data interrupt raw
|
||||
*/
|
||||
uint32_t i2c_tx_data_int_raw:1;
|
||||
/** i2c_detect_start_int_raw : RO; bitpos: [8]; default: 0;
|
||||
* detect start interrupt raw
|
||||
*/
|
||||
uint32_t i2c_detect_start_int_raw:1;
|
||||
uint32_t reserved_9:23;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_i2c_int_raw_reg_t;
|
||||
|
||||
/** Type of i2c_int_st register
|
||||
* interrupt state register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** i2c_slave_tran_comp_int_st : RO; bitpos: [0]; default: 0;
|
||||
* slave transit complete interrupt state
|
||||
*/
|
||||
uint32_t i2c_slave_tran_comp_int_st:1;
|
||||
/** i2c_arbitration_lost_int_st : RO; bitpos: [1]; default: 0;
|
||||
* arbitration lost interrupt state
|
||||
*/
|
||||
uint32_t i2c_arbitration_lost_int_st:1;
|
||||
/** i2c_master_tran_comp_int_st : RO; bitpos: [2]; default: 0;
|
||||
* master transit complete interrupt state
|
||||
*/
|
||||
uint32_t i2c_master_tran_comp_int_st:1;
|
||||
/** i2c_trans_complete_int_st : RO; bitpos: [3]; default: 0;
|
||||
* transit complete interrupt state
|
||||
*/
|
||||
uint32_t i2c_trans_complete_int_st:1;
|
||||
/** i2c_time_out_int_st : RO; bitpos: [4]; default: 0;
|
||||
* time out interrupt state
|
||||
*/
|
||||
uint32_t i2c_time_out_int_st:1;
|
||||
/** i2c_ack_err_int_st : RO; bitpos: [5]; default: 0;
|
||||
* ack error interrupt state
|
||||
*/
|
||||
uint32_t i2c_ack_err_int_st:1;
|
||||
/** i2c_rx_data_int_st : RO; bitpos: [6]; default: 0;
|
||||
* receive data interrupt state
|
||||
*/
|
||||
uint32_t i2c_rx_data_int_st:1;
|
||||
/** i2c_tx_data_int_st : RO; bitpos: [7]; default: 0;
|
||||
* transit data interrupt state
|
||||
*/
|
||||
uint32_t i2c_tx_data_int_st:1;
|
||||
/** i2c_detect_start_int_st : RO; bitpos: [8]; default: 0;
|
||||
* detect start interrupt state
|
||||
*/
|
||||
uint32_t i2c_detect_start_int_st:1;
|
||||
uint32_t reserved_9:23;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_i2c_int_st_reg_t;
|
||||
|
||||
/** Type of i2c_int_ena register
|
||||
* interrupt enable register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** i2c_slave_tran_comp_int_ena : R/W; bitpos: [0]; default: 0;
|
||||
* enable slave transit complete interrupt
|
||||
*/
|
||||
uint32_t i2c_slave_tran_comp_int_ena:1;
|
||||
/** i2c_arbitration_lost_int_ena : R/W; bitpos: [1]; default: 0;
|
||||
* enable arbitration lost interrupt
|
||||
*/
|
||||
uint32_t i2c_arbitration_lost_int_ena:1;
|
||||
/** i2c_master_tran_comp_int_ena : R/W; bitpos: [2]; default: 0;
|
||||
* enable master transit complete interrupt
|
||||
*/
|
||||
uint32_t i2c_master_tran_comp_int_ena:1;
|
||||
/** i2c_trans_complete_int_ena : R/W; bitpos: [3]; default: 0;
|
||||
* enable transit complete interrupt
|
||||
*/
|
||||
uint32_t i2c_trans_complete_int_ena:1;
|
||||
/** i2c_time_out_int_ena : R/W; bitpos: [4]; default: 0;
|
||||
* enable time out interrupt
|
||||
*/
|
||||
uint32_t i2c_time_out_int_ena:1;
|
||||
/** i2c_ack_err_int_ena : R/W; bitpos: [5]; default: 0;
|
||||
* enable eack error interrupt
|
||||
*/
|
||||
uint32_t i2c_ack_err_int_ena:1;
|
||||
/** i2c_rx_data_int_ena : R/W; bitpos: [6]; default: 0;
|
||||
* enable receive data interrupt
|
||||
*/
|
||||
uint32_t i2c_rx_data_int_ena:1;
|
||||
/** i2c_tx_data_int_ena : R/W; bitpos: [7]; default: 0;
|
||||
* enable transit data interrupt
|
||||
*/
|
||||
uint32_t i2c_tx_data_int_ena:1;
|
||||
/** i2c_detect_start_int_ena : R/W; bitpos: [8]; default: 0;
|
||||
* enable detect start interrupt
|
||||
*/
|
||||
uint32_t i2c_detect_start_int_ena:1;
|
||||
uint32_t reserved_9:23;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_i2c_int_ena_reg_t;
|
||||
|
||||
|
||||
/** Group: version Registers */
|
||||
/** Type of i2c_date register
|
||||
* version register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** i2c_i2c_date : R/W; bitpos: [27:0]; default: 26235664;
|
||||
* version
|
||||
*/
|
||||
uint32_t i2c_i2c_date:28;
|
||||
uint32_t reserved_28:4;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_i2c_date_reg_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
volatile rtc_i2c_scl_low_reg_t i2c_scl_low;
|
||||
volatile rtc_i2c_ctrl_reg_t i2c_ctrl;
|
||||
volatile rtc_i2c_status_reg_t i2c_status;
|
||||
volatile rtc_i2c_to_reg_t i2c_to;
|
||||
volatile rtc_i2c_slave_addr_reg_t i2c_slave_addr;
|
||||
volatile rtc_i2c_scl_high_reg_t i2c_scl_high;
|
||||
volatile rtc_i2c_sda_duty_reg_t i2c_sda_duty;
|
||||
volatile rtc_i2c_scl_start_period_reg_t i2c_scl_start_period;
|
||||
volatile rtc_i2c_scl_stop_period_reg_t i2c_scl_stop_period;
|
||||
volatile rtc_i2c_int_clr_reg_t i2c_int_clr;
|
||||
volatile rtc_i2c_int_raw_reg_t i2c_int_raw;
|
||||
volatile rtc_i2c_int_st_reg_t i2c_int_st;
|
||||
volatile rtc_i2c_int_ena_reg_t i2c_int_ena;
|
||||
volatile rtc_i2c_data_reg_t i2c_data;
|
||||
volatile rtc_i2c_cmd_reg_t i2c_cmd[16];
|
||||
uint32_t reserved_078[33];
|
||||
volatile rtc_i2c_date_reg_t i2c_date;
|
||||
} rtc_i2c_dev_t;
|
||||
extern rtc_i2c_dev_t RTC_I2C;
|
||||
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(rtc_i2c_dev_t) == 0x100, "Invalid size of rtc_i2c_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,356 +0,0 @@
|
||||
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_RTC_IO_STRUCT_H_
|
||||
#define _SOC_RTC_IO_STRUCT_H_
|
||||
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct rtc_io_dev_s {
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 10;
|
||||
uint32_t data : 22; /*RTC GPIO 0 ~ 21 output data*/
|
||||
};
|
||||
uint32_t val;
|
||||
} out;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 10;
|
||||
uint32_t w1ts : 22; /*RTC GPIO 0 ~ 21 output data write 1 to set*/
|
||||
};
|
||||
uint32_t val;
|
||||
} out_w1ts;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 10;
|
||||
uint32_t w1tc : 22; /*RTC GPIO 0 ~ 21 output data write 1 to clear*/
|
||||
};
|
||||
uint32_t val;
|
||||
} out_w1tc;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 10;
|
||||
uint32_t enable : 22; /*RTC GPIO 0 ~ 21 enable*/
|
||||
};
|
||||
uint32_t val;
|
||||
} enable;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 10;
|
||||
uint32_t w1ts : 22; /*RTC GPIO 0 ~ 21 enable write 1 to set*/
|
||||
};
|
||||
uint32_t val;
|
||||
} enable_w1ts;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 10;
|
||||
uint32_t w1tc : 22; /*RTC GPIO 0 ~ 21 enable write 1 to clear*/
|
||||
};
|
||||
uint32_t val;
|
||||
} enable_w1tc;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 10;
|
||||
uint32_t status : 22; /*RTC GPIO 0 ~ 21 interrupt status*/
|
||||
};
|
||||
uint32_t val;
|
||||
} status;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 10;
|
||||
uint32_t w1ts : 22; /*RTC GPIO 0 ~ 21 interrupt status write 1 to set*/
|
||||
};
|
||||
uint32_t val;
|
||||
} status_w1ts;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 10;
|
||||
uint32_t w1tc : 22; /*RTC GPIO 0 ~ 21 interrupt status write 1 to clear*/
|
||||
};
|
||||
uint32_t val;
|
||||
} status_w1tc;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 10;
|
||||
uint32_t in : 22; /*RTC GPIO input data*/
|
||||
};
|
||||
uint32_t val;
|
||||
} in_val;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 2;
|
||||
uint32_t pad_driver : 1; /*if set to 0: normal output, if set to 1: open drain*/
|
||||
uint32_t reserved3 : 4;
|
||||
uint32_t int_type : 3; /*if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger*/
|
||||
uint32_t wakeup_enable : 1; /*RTC GPIO wakeup enable bit*/
|
||||
uint32_t reserved11 : 21;
|
||||
};
|
||||
uint32_t val;
|
||||
} pin[22];
|
||||
union {
|
||||
struct {
|
||||
uint32_t sel0 : 5;
|
||||
uint32_t sel1 : 5;
|
||||
uint32_t sel2 : 5;
|
||||
uint32_t sel3 : 5;
|
||||
uint32_t sel4 : 5;
|
||||
uint32_t no_gating_12m : 1;
|
||||
uint32_t reserved26 : 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} debug_sel;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 13;
|
||||
uint32_t fun_ie : 1; /*input enable in work mode*/
|
||||
uint32_t slp_oe : 1; /*output enable in sleep mode*/
|
||||
uint32_t slp_ie : 1; /*input enable in sleep mode*/
|
||||
uint32_t slp_sel : 1; /*1: enable sleep mode during sleep,0: no sleep mode*/
|
||||
uint32_t fun_sel : 2; /*function sel*/
|
||||
uint32_t mux_sel : 1; /*1: use RTC GPIO,0: use digital GPIO*/
|
||||
uint32_t xpd : 1; /*TOUCH_XPD*/
|
||||
uint32_t tie_opt : 1; /*TOUCH_TIE_OPT*/
|
||||
uint32_t start : 1; /*TOUCH_START*/
|
||||
uint32_t reserved23 : 4;
|
||||
uint32_t rue : 1; /*RUE*/
|
||||
uint32_t rde : 1; /*RDE*/
|
||||
uint32_t drv : 2; /*DRV*/
|
||||
uint32_t reserved31 : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} touch_pad[15];
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 13;
|
||||
uint32_t x32p_fun_ie : 1; /*input enable in work mode*/
|
||||
uint32_t x32p_slp_oe : 1; /*output enable in sleep mode*/
|
||||
uint32_t x32p_slp_ie : 1; /*input enable in sleep mode*/
|
||||
uint32_t x32p_slp_sel : 1; /*1: enable sleep mode during sleep,0: no sleep mode*/
|
||||
uint32_t x32p_fun_sel : 2; /*function sel*/
|
||||
uint32_t x32p_mux_sel : 1; /*1: use RTC GPIO,0: use digital GPIO*/
|
||||
uint32_t reserved20 : 7;
|
||||
uint32_t x32p_rue : 1; /*RUE*/
|
||||
uint32_t x32p_rde : 1; /*RDE*/
|
||||
uint32_t x32p_drv : 2; /*DRV*/
|
||||
uint32_t reserved31 : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} xtal_32p_pad;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 13;
|
||||
uint32_t x32n_fun_ie : 1; /*input enable in work mode*/
|
||||
uint32_t x32n_slp_oe : 1; /*output enable in sleep mode*/
|
||||
uint32_t x32n_slp_ie : 1; /*input enable in sleep mode*/
|
||||
uint32_t x32n_slp_sel : 1; /*1: enable sleep mode during sleep,0: no sleep mode*/
|
||||
uint32_t x32n_fun_sel : 2; /*function sel*/
|
||||
uint32_t x32n_mux_sel : 1; /*1: use RTC GPIO,0: use digital GPIO*/
|
||||
uint32_t reserved20 : 7;
|
||||
uint32_t x32n_rue : 1; /*RUE*/
|
||||
uint32_t x32n_rde : 1; /*RDE*/
|
||||
uint32_t x32n_drv : 2; /*DRV*/
|
||||
uint32_t reserved31 : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} xtal_32n_pad;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 3;
|
||||
uint32_t dac : 8; /*PDAC1_DAC*/
|
||||
uint32_t xpd_dac : 1; /*PDAC1_XPD_DAC*/
|
||||
uint32_t dac_xpd_force : 1; /*1: use reg_pdac1_xpd_dac to control PDAC1_XPD_DAC,0: use SAR ADC FSM to control PDAC1_XPD_DAC*/
|
||||
uint32_t fun_ie : 1; /*input enable in work mode*/
|
||||
uint32_t slp_oe : 1; /*output enable in sleep mode*/
|
||||
uint32_t slp_ie : 1; /*input enable in sleep mode*/
|
||||
uint32_t slp_sel : 1; /*1: enable sleep mode during sleep,0: no sleep mode*/
|
||||
uint32_t fun_sel : 2; /*PDAC1 function sel*/
|
||||
uint32_t mux_sel : 1; /*1: use RTC GPIO,0: use digital GPIO*/
|
||||
uint32_t reserved20 : 7;
|
||||
uint32_t rue : 1; /*PDAC1_RUE*/
|
||||
uint32_t rde : 1; /*PDAC1_RDE*/
|
||||
uint32_t drv : 2; /*PDAC1_DRV*/
|
||||
uint32_t reserved31 : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} pad_dac[2];
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 13;
|
||||
uint32_t rtc_pad19_fun_ie : 1; /*input enable in work mode*/
|
||||
uint32_t rtc_pad19_slp_oe : 1; /*output enable in sleep mode*/
|
||||
uint32_t rtc_pad19_slp_ie : 1; /*input enable in sleep mode*/
|
||||
uint32_t rtc_pad19_slp_sel : 1; /*1: enable sleep mode during sleep,0: no sleep mode*/
|
||||
uint32_t rtc_pad19_fun_sel : 2; /*function sel*/
|
||||
uint32_t rtc_pad19_mux_sel : 1; /*1: use RTC GPIO,0: use digital GPIO*/
|
||||
uint32_t reserved20 : 7;
|
||||
uint32_t rtc_pad19_rue : 1; /*RUE*/
|
||||
uint32_t rtc_pad19_rde : 1; /*RDE*/
|
||||
uint32_t rtc_pad19_drv : 2; /*DRV*/
|
||||
uint32_t reserved31 : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_pad19;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 13;
|
||||
uint32_t rtc_pad20_fun_ie : 1; /*input enable in work mode*/
|
||||
uint32_t rtc_pad20_slp_oe : 1; /*output enable in sleep mode*/
|
||||
uint32_t rtc_pad20_slp_ie : 1; /*input enable in sleep mode*/
|
||||
uint32_t rtc_pad20_slp_sel : 1; /*1: enable sleep mode during sleep,0: no sleep mode*/
|
||||
uint32_t rtc_pad20_fun_sel : 2; /*function sel*/
|
||||
uint32_t rtc_pad20_mux_sel : 1; /*1: use RTC GPIO,0: use digital GPIO*/
|
||||
uint32_t reserved20 : 7;
|
||||
uint32_t rtc_pad20_rue : 1; /*RUE*/
|
||||
uint32_t rtc_pad20_rde : 1; /*RDE*/
|
||||
uint32_t rtc_pad20_drv : 2; /*DRV*/
|
||||
uint32_t reserved31 : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_pad20;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 13;
|
||||
uint32_t rtc_pad21_fun_ie : 1; /*input enable in work mode*/
|
||||
uint32_t rtc_pad21_slp_oe : 1; /*output enable in sleep mode*/
|
||||
uint32_t rtc_pad21_slp_ie : 1; /*input enable in sleep mode*/
|
||||
uint32_t rtc_pad21_slp_sel : 1; /*1: enable sleep mode during sleep,0: no sleep mode*/
|
||||
uint32_t rtc_pad21_fun_sel : 2; /*function sel*/
|
||||
uint32_t rtc_pad21_mux_sel : 1; /*1: use RTC GPIO,0: use digital GPIO*/
|
||||
uint32_t reserved20 : 7;
|
||||
uint32_t rtc_pad21_rue : 1; /*RUE*/
|
||||
uint32_t rtc_pad21_rde : 1; /*RDE*/
|
||||
uint32_t rtc_pad21_drv : 2; /*DRV*/
|
||||
uint32_t reserved31 : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_pad21;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 27;
|
||||
uint32_t sel : 5;
|
||||
};
|
||||
uint32_t val;
|
||||
} ext_wakeup0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 27;
|
||||
uint32_t sel : 5; /*select RTC GPIO 0 ~ 17 to control XTAL*/
|
||||
};
|
||||
uint32_t val;
|
||||
} xtl_ext_ctr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 23;
|
||||
uint32_t debug_bit_sel : 5;
|
||||
uint32_t scl_sel : 2;
|
||||
uint32_t sda_sel : 2;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_i2c_io;
|
||||
union {
|
||||
struct {
|
||||
uint32_t io_touch_bufsel : 4; /*BUF_SEL when touch work without fsm*/
|
||||
uint32_t io_touch_bufmode : 1; /*BUF_MODE when touch work without fsm*/
|
||||
uint32_t reserved5 : 27;
|
||||
};
|
||||
uint32_t val;
|
||||
} touch_ctrl;
|
||||
uint32_t reserved_ec;
|
||||
uint32_t reserved_f0;
|
||||
uint32_t reserved_f4;
|
||||
uint32_t reserved_f8;
|
||||
uint32_t reserved_fc;
|
||||
uint32_t reserved_100;
|
||||
uint32_t reserved_104;
|
||||
uint32_t reserved_108;
|
||||
uint32_t reserved_10c;
|
||||
uint32_t reserved_110;
|
||||
uint32_t reserved_114;
|
||||
uint32_t reserved_118;
|
||||
uint32_t reserved_11c;
|
||||
uint32_t reserved_120;
|
||||
uint32_t reserved_124;
|
||||
uint32_t reserved_128;
|
||||
uint32_t reserved_12c;
|
||||
uint32_t reserved_130;
|
||||
uint32_t reserved_134;
|
||||
uint32_t reserved_138;
|
||||
uint32_t reserved_13c;
|
||||
uint32_t reserved_140;
|
||||
uint32_t reserved_144;
|
||||
uint32_t reserved_148;
|
||||
uint32_t reserved_14c;
|
||||
uint32_t reserved_150;
|
||||
uint32_t reserved_154;
|
||||
uint32_t reserved_158;
|
||||
uint32_t reserved_15c;
|
||||
uint32_t reserved_160;
|
||||
uint32_t reserved_164;
|
||||
uint32_t reserved_168;
|
||||
uint32_t reserved_16c;
|
||||
uint32_t reserved_170;
|
||||
uint32_t reserved_174;
|
||||
uint32_t reserved_178;
|
||||
uint32_t reserved_17c;
|
||||
uint32_t reserved_180;
|
||||
uint32_t reserved_184;
|
||||
uint32_t reserved_188;
|
||||
uint32_t reserved_18c;
|
||||
uint32_t reserved_190;
|
||||
uint32_t reserved_194;
|
||||
uint32_t reserved_198;
|
||||
uint32_t reserved_19c;
|
||||
uint32_t reserved_1a0;
|
||||
uint32_t reserved_1a4;
|
||||
uint32_t reserved_1a8;
|
||||
uint32_t reserved_1ac;
|
||||
uint32_t reserved_1b0;
|
||||
uint32_t reserved_1b4;
|
||||
uint32_t reserved_1b8;
|
||||
uint32_t reserved_1bc;
|
||||
uint32_t reserved_1c0;
|
||||
uint32_t reserved_1c4;
|
||||
uint32_t reserved_1c8;
|
||||
uint32_t reserved_1cc;
|
||||
uint32_t reserved_1d0;
|
||||
uint32_t reserved_1d4;
|
||||
uint32_t reserved_1d8;
|
||||
uint32_t reserved_1dc;
|
||||
uint32_t reserved_1e0;
|
||||
uint32_t reserved_1e4;
|
||||
uint32_t reserved_1e8;
|
||||
uint32_t reserved_1ec;
|
||||
uint32_t reserved_1f0;
|
||||
uint32_t reserved_1f4;
|
||||
uint32_t reserved_1f8;
|
||||
union {
|
||||
struct {
|
||||
uint32_t date : 28;
|
||||
uint32_t reserved28 : 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} date;
|
||||
} rtc_io_dev_t;
|
||||
extern rtc_io_dev_t RTCIO;
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /*_SOC_RTC_IO_STRUCT_H_ */
|
||||
@@ -1,94 +0,0 @@
|
||||
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#include "soc.h"
|
||||
|
||||
#define SDMMC_CTRL_REG (DR_REG_SDMMC_BASE + 0x00)
|
||||
#define SDMMC_PWREN_REG (DR_REG_SDMMC_BASE + 0x04)
|
||||
#define SDMMC_CLKDIV_REG (DR_REG_SDMMC_BASE + 0x08)
|
||||
#define SDMMC_CLKSRC_REG (DR_REG_SDMMC_BASE + 0x0c)
|
||||
#define SDMMC_CLKENA_REG (DR_REG_SDMMC_BASE + 0x10)
|
||||
#define SDMMC_TMOUT_REG (DR_REG_SDMMC_BASE + 0x14)
|
||||
#define SDMMC_CTYPE_REG (DR_REG_SDMMC_BASE + 0x18)
|
||||
#define SDMMC_BLKSIZ_REG (DR_REG_SDMMC_BASE + 0x1c)
|
||||
#define SDMMC_BYTCNT_REG (DR_REG_SDMMC_BASE + 0x20)
|
||||
#define SDMMC_INTMASK_REG (DR_REG_SDMMC_BASE + 0x24)
|
||||
#define SDMMC_CMDARG_REG (DR_REG_SDMMC_BASE + 0x28)
|
||||
#define SDMMC_CMD_REG (DR_REG_SDMMC_BASE + 0x2c)
|
||||
#define SDMMC_RESP0_REG (DR_REG_SDMMC_BASE + 0x30)
|
||||
#define SDMMC_RESP1_REG (DR_REG_SDMMC_BASE + 0x34)
|
||||
#define SDMMC_RESP2_REG (DR_REG_SDMMC_BASE + 0x38)
|
||||
#define SDMMC_RESP3_REG (DR_REG_SDMMC_BASE + 0x3c)
|
||||
|
||||
#define SDMMC_MINTSTS_REG (DR_REG_SDMMC_BASE + 0x40)
|
||||
#define SDMMC_RINTSTS_REG (DR_REG_SDMMC_BASE + 0x44)
|
||||
#define SDMMC_STATUS_REG (DR_REG_SDMMC_BASE + 0x48)
|
||||
#define SDMMC_FIFOTH_REG (DR_REG_SDMMC_BASE + 0x4c)
|
||||
#define SDMMC_CDETECT_REG (DR_REG_SDMMC_BASE + 0x50)
|
||||
#define SDMMC_WRTPRT_REG (DR_REG_SDMMC_BASE + 0x54)
|
||||
#define SDMMC_GPIO_REG (DR_REG_SDMMC_BASE + 0x58)
|
||||
#define SDMMC_TCBCNT_REG (DR_REG_SDMMC_BASE + 0x5c)
|
||||
#define SDMMC_TBBCNT_REG (DR_REG_SDMMC_BASE + 0x60)
|
||||
#define SDMMC_DEBNCE_REG (DR_REG_SDMMC_BASE + 0x64)
|
||||
#define SDMMC_USRID_REG (DR_REG_SDMMC_BASE + 0x68)
|
||||
#define SDMMC_VERID_REG (DR_REG_SDMMC_BASE + 0x6c)
|
||||
#define SDMMC_HCON_REG (DR_REG_SDMMC_BASE + 0x70)
|
||||
#define SDMMC_UHS_REG_REG (DR_REG_SDMMC_BASE + 0x74)
|
||||
#define SDMMC_RST_N_REG (DR_REG_SDMMC_BASE + 0x78)
|
||||
#define SDMMC_BMOD_REG (DR_REG_SDMMC_BASE + 0x80)
|
||||
#define SDMMC_PLDMND_REG (DR_REG_SDMMC_BASE + 0x84)
|
||||
#define SDMMC_DBADDR_REG (DR_REG_SDMMC_BASE + 0x88)
|
||||
#define SDMMC_DBADDRU_REG (DR_REG_SDMMC_BASE + 0x8c)
|
||||
#define SDMMC_IDSTS_REG (DR_REG_SDMMC_BASE + 0x8c)
|
||||
#define SDMMC_IDINTEN_REG (DR_REG_SDMMC_BASE + 0x90)
|
||||
#define SDMMC_DSCADDR_REG (DR_REG_SDMMC_BASE + 0x94)
|
||||
#define SDMMC_DSCADDRL_REG (DR_REG_SDMMC_BASE + 0x98)
|
||||
#define SDMMC_DSCADDRU_REG (DR_REG_SDMMC_BASE + 0x9c)
|
||||
#define SDMMC_BUFADDRL_REG (DR_REG_SDMMC_BASE + 0xa0)
|
||||
#define SDMMC_BUFADDRU_REG (DR_REG_SDMMC_BASE + 0xa4)
|
||||
#define SDMMC_CARDTHRCTL_REG (DR_REG_SDMMC_BASE + 0x100)
|
||||
#define SDMMC_BACK_END_POWER_REG (DR_REG_SDMMC_BASE + 0x104)
|
||||
#define SDMMC_UHS_REG_EXT_REG (DR_REG_SDMMC_BASE + 0x108)
|
||||
#define SDMMC_EMMC_DDR_REG_REG (DR_REG_SDMMC_BASE + 0x10c)
|
||||
#define SDMMC_ENABLE_SHIFT_REG (DR_REG_SDMMC_BASE + 0x110)
|
||||
|
||||
#define SDMMC_CLOCK_REG (DR_REG_SDMMC_BASE + 0x800)
|
||||
|
||||
#define SDMMC_INTMASK_IO_SLOT1 BIT(17)
|
||||
#define SDMMC_INTMASK_IO_SLOT0 BIT(16)
|
||||
#define SDMMC_INTMASK_EBE BIT(15)
|
||||
#define SDMMC_INTMASK_ACD BIT(14)
|
||||
#define SDMMC_INTMASK_SBE BIT(13)
|
||||
#define SDMMC_INTMASK_HLE BIT(12)
|
||||
#define SDMMC_INTMASK_FRUN BIT(11)
|
||||
#define SDMMC_INTMASK_HTO BIT(10)
|
||||
#define SDMMC_INTMASK_DTO BIT(9)
|
||||
#define SDMMC_INTMASK_RTO BIT(8)
|
||||
#define SDMMC_INTMASK_DCRC BIT(7)
|
||||
#define SDMMC_INTMASK_RCRC BIT(6)
|
||||
#define SDMMC_INTMASK_RXDR BIT(5)
|
||||
#define SDMMC_INTMASK_TXDR BIT(4)
|
||||
#define SDMMC_INTMASK_DATA_OVER BIT(3)
|
||||
#define SDMMC_INTMASK_CMD_DONE BIT(2)
|
||||
#define SDMMC_INTMASK_RESP_ERR BIT(1)
|
||||
#define SDMMC_INTMASK_CD BIT(0)
|
||||
|
||||
#define SDMMC_IDMAC_INTMASK_AI BIT(9)
|
||||
#define SDMMC_IDMAC_INTMASK_NI BIT(8)
|
||||
#define SDMMC_IDMAC_INTMASK_CES BIT(5)
|
||||
#define SDMMC_IDMAC_INTMASK_DU BIT(4)
|
||||
#define SDMMC_IDMAC_INTMASK_FBE BIT(2)
|
||||
#define SDMMC_IDMAC_INTMASK_RI BIT(1)
|
||||
#define SDMMC_IDMAC_INTMASK_TI BIT(0)
|
||||
@@ -1,446 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef struct sdmmc_desc_s {
|
||||
struct {
|
||||
uint32_t reserved1: 1;
|
||||
uint32_t disable_int_on_completion: 1;
|
||||
uint32_t last_descriptor: 1;
|
||||
uint32_t first_descriptor: 1;
|
||||
uint32_t second_address_chained: 1;
|
||||
uint32_t end_of_ring: 1;
|
||||
uint32_t reserved2: 24;
|
||||
uint32_t card_error_summary: 1;
|
||||
uint32_t owned_by_idmac: 1;
|
||||
};
|
||||
struct {
|
||||
uint32_t buffer1_size: 13;
|
||||
uint32_t buffer2_size: 13;
|
||||
uint32_t reserved3: 6;
|
||||
};
|
||||
void* buffer1_ptr;
|
||||
union {
|
||||
void* buffer2_ptr;
|
||||
void* next_desc_ptr;
|
||||
};
|
||||
} sdmmc_desc_t;
|
||||
|
||||
#define SDMMC_DMA_MAX_BUF_LEN 4096
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(sdmmc_desc_t) == 16, "invalid size of sdmmc_desc_t structure");
|
||||
#endif
|
||||
|
||||
|
||||
typedef struct sdmmc_hw_cmd_s {
|
||||
uint32_t cmd_index: 6; ///< Command index
|
||||
uint32_t response_expect: 1; ///< set if response is expected
|
||||
uint32_t response_long: 1; ///< 0: short response expected, 1: long response expected
|
||||
uint32_t check_response_crc: 1; ///< set if controller should check response CRC
|
||||
uint32_t data_expected: 1; ///< 0: no data expected, 1: data expected
|
||||
uint32_t rw: 1; ///< 0: read from card, 1: write to card (don't care if no data expected)
|
||||
uint32_t stream_mode: 1; ///< 0: block transfer, 1: stream transfer (don't care if no data expected)
|
||||
uint32_t send_auto_stop: 1; ///< set to send stop at the end of the transfer
|
||||
uint32_t wait_complete: 1; ///< 0: send command at once, 1: wait for previous command to complete
|
||||
uint32_t stop_abort_cmd: 1; ///< set if this is a stop or abort command intended to stop current transfer
|
||||
uint32_t send_init: 1; ///< set to send init sequence (80 clocks of 1)
|
||||
uint32_t card_num: 5; ///< card number
|
||||
uint32_t update_clk_reg: 1; ///< 0: normal command, 1: don't send command, just update clock registers
|
||||
uint32_t read_ceata: 1; ///< set if performing read from CE-ATA device
|
||||
uint32_t ccs_expected: 1; ///< set if CCS is expected from CE-ATA device
|
||||
uint32_t enable_boot: 1; ///< set for mandatory boot mode
|
||||
uint32_t expect_boot_ack: 1; ///< when set along with enable_boot, controller expects boot ack pattern
|
||||
uint32_t disable_boot: 1; ///< set to terminate boot operation (don't set along with enable_boot)
|
||||
uint32_t boot_mode: 1; ///< 0: mandatory boot operation, 1: alternate boot operation
|
||||
uint32_t volt_switch: 1; ///< set to enable voltage switching (for CMD11 only)
|
||||
uint32_t use_hold_reg: 1; ///< clear to bypass HOLD register
|
||||
uint32_t reserved: 1;
|
||||
uint32_t start_command: 1; ///< Start command; once command is sent to the card, bit is cleared.
|
||||
} sdmmc_hw_cmd_t; ///< command format used in cmd register; this structure is defined to make it easier to build command values
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(sdmmc_hw_cmd_t) == 4, "invalid size of sdmmc_cmd_t structure");
|
||||
#endif
|
||||
|
||||
|
||||
typedef struct sdmmc_dev_t {
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t controller_reset: 1;
|
||||
uint32_t fifo_reset: 1;
|
||||
uint32_t dma_reset: 1;
|
||||
uint32_t reserved1: 1;
|
||||
uint32_t int_enable: 1;
|
||||
uint32_t dma_enable: 1;
|
||||
uint32_t read_wait: 1;
|
||||
uint32_t send_irq_response: 1;
|
||||
uint32_t abort_read_data: 1;
|
||||
uint32_t send_ccsd: 1;
|
||||
uint32_t send_auto_stop_ccsd: 1;
|
||||
uint32_t ceata_device_interrupt_status: 1;
|
||||
uint32_t reserved2: 4;
|
||||
uint32_t card_voltage_a: 4;
|
||||
uint32_t card_voltage_b: 4;
|
||||
uint32_t enable_od_pullup: 1;
|
||||
uint32_t use_internal_dma: 1;
|
||||
uint32_t reserved3: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} ctrl;
|
||||
|
||||
volatile uint32_t pwren; ///< 1: enable power to card, 0: disable power to card
|
||||
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t div0: 8; ///< 0: bypass, 1-255: divide clock by (2*div0).
|
||||
uint32_t div1: 8; ///< 0: bypass, 1-255: divide clock by (2*div0).
|
||||
uint32_t div2: 8; ///< 0: bypass, 1-255: divide clock by (2*div0).
|
||||
uint32_t div3: 8; ///< 0: bypass, 1-255: divide clock by (2*div0).
|
||||
};
|
||||
uint32_t val;
|
||||
} clkdiv;
|
||||
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t card0: 2; ///< 0-3: select clock divider for card 0 among div0-div3
|
||||
uint32_t card1: 2; ///< 0-3: select clock divider for card 1 among div0-div3
|
||||
uint32_t reserved: 28;
|
||||
};
|
||||
uint32_t val;
|
||||
} clksrc;
|
||||
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t cclk_enable: 16; ///< 1: enable clock to card, 0: disable clock
|
||||
uint32_t cclk_low_power: 16; ///< 1: enable clock gating when card is idle, 0: disable clock gating
|
||||
};
|
||||
uint32_t val;
|
||||
} clkena;
|
||||
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t response: 8; ///< response timeout, in card output clock cycles
|
||||
uint32_t data: 24; ///< data read timeout, in card output clock cycles
|
||||
};
|
||||
uint32_t val;
|
||||
} tmout;
|
||||
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t card_width: 16; ///< one bit for each card: 0: 1-bit mode, 1: 4-bit mode
|
||||
uint32_t card_width_8: 16; ///< one bit for each card: 0: not 8-bit mode (corresponding card_width bit is used), 1: 8-bit mode (card_width bit is ignored)
|
||||
};
|
||||
uint32_t val;
|
||||
} ctype;
|
||||
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t block_size: 16; ///< block size, default 0x200
|
||||
uint32_t reserved: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} blksiz;
|
||||
|
||||
volatile uint32_t bytcnt; ///< number of bytes to be transferred
|
||||
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t cd: 1; ///< Card detect interrupt enable
|
||||
uint32_t re: 1; ///< Response error interrupt enable
|
||||
uint32_t cmd_done: 1; ///< Command done interrupt enable
|
||||
uint32_t dto: 1; ///< Data transfer over interrupt enable
|
||||
uint32_t txdr: 1; ///< Transmit FIFO data request interrupt enable
|
||||
uint32_t rxdr: 1; ///< Receive FIFO data request interrupt enable
|
||||
uint32_t rcrc: 1; ///< Response CRC error interrupt enable
|
||||
uint32_t dcrc: 1; ///< Data CRC error interrupt enable
|
||||
uint32_t rto: 1; ///< Response timeout interrupt enable
|
||||
uint32_t drto: 1; ///< Data read timeout interrupt enable
|
||||
uint32_t hto: 1; ///< Data starvation-by-host timeout interrupt enable
|
||||
uint32_t frun: 1; ///< FIFO underrun/overrun error interrupt enable
|
||||
uint32_t hle: 1; ///< Hardware locked write error interrupt enable
|
||||
uint32_t sbi_bci: 1; ///< Start bit error / busy clear interrupt enable
|
||||
uint32_t acd: 1; ///< Auto command done interrupt enable
|
||||
uint32_t ebe: 1; ///< End bit error / write no CRC interrupt enable
|
||||
uint32_t sdio: 16; ///< SDIO interrupt enable
|
||||
};
|
||||
uint32_t val;
|
||||
} intmask;
|
||||
|
||||
volatile uint32_t cmdarg; ///< Command argument to be passed to card
|
||||
|
||||
volatile sdmmc_hw_cmd_t cmd;
|
||||
|
||||
volatile uint32_t resp[4]; ///< Response from card
|
||||
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t cd: 1; ///< Card detect interrupt masked status
|
||||
uint32_t re: 1; ///< Response error interrupt masked status
|
||||
uint32_t cmd_done: 1; ///< Command done interrupt masked status
|
||||
uint32_t dto: 1; ///< Data transfer over interrupt masked status
|
||||
uint32_t txdr: 1; ///< Transmit FIFO data request interrupt masked status
|
||||
uint32_t rxdr: 1; ///< Receive FIFO data request interrupt masked status
|
||||
uint32_t rcrc: 1; ///< Response CRC error interrupt masked status
|
||||
uint32_t dcrc: 1; ///< Data CRC error interrupt masked status
|
||||
uint32_t rto: 1; ///< Response timeout interrupt masked status
|
||||
uint32_t drto: 1; ///< Data read timeout interrupt masked status
|
||||
uint32_t hto: 1; ///< Data starvation-by-host timeout interrupt masked status
|
||||
uint32_t frun: 1; ///< FIFO underrun/overrun error interrupt masked status
|
||||
uint32_t hle: 1; ///< Hardware locked write error interrupt masked status
|
||||
uint32_t sbi_bci: 1; ///< Start bit error / busy clear interrupt masked status
|
||||
uint32_t acd: 1; ///< Auto command done interrupt masked status
|
||||
uint32_t ebe: 1; ///< End bit error / write no CRC interrupt masked status
|
||||
uint32_t sdio: 16; ///< SDIO interrupt masked status
|
||||
};
|
||||
uint32_t val;
|
||||
} mintsts;
|
||||
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t cd: 1; ///< Card detect raw interrupt status
|
||||
uint32_t re: 1; ///< Response error raw interrupt status
|
||||
uint32_t cmd_done: 1; ///< Command done raw interrupt status
|
||||
uint32_t dto: 1; ///< Data transfer over raw interrupt status
|
||||
uint32_t txdr: 1; ///< Transmit FIFO data request raw interrupt status
|
||||
uint32_t rxdr: 1; ///< Receive FIFO data request raw interrupt status
|
||||
uint32_t rcrc: 1; ///< Response CRC error raw interrupt status
|
||||
uint32_t dcrc: 1; ///< Data CRC error raw interrupt status
|
||||
uint32_t rto: 1; ///< Response timeout raw interrupt status
|
||||
uint32_t drto: 1; ///< Data read timeout raw interrupt status
|
||||
uint32_t hto: 1; ///< Data starvation-by-host timeout raw interrupt status
|
||||
uint32_t frun: 1; ///< FIFO underrun/overrun error raw interrupt status
|
||||
uint32_t hle: 1; ///< Hardware locked write error raw interrupt status
|
||||
uint32_t sbi_bci: 1; ///< Start bit error / busy clear raw interrupt status
|
||||
uint32_t acd: 1; ///< Auto command done raw interrupt status
|
||||
uint32_t ebe: 1; ///< End bit error / write no CRC raw interrupt status
|
||||
uint32_t sdio: 16; ///< SDIO raw interrupt status
|
||||
};
|
||||
uint32_t val;
|
||||
} rintsts; ///< interrupts can be cleared by writing this register
|
||||
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t fifo_rx_watermark: 1; ///< FIFO reached receive watermark level
|
||||
uint32_t fifo_tx_watermark: 1; ///< FIFO reached transmit watermark level
|
||||
uint32_t fifo_empty: 1; ///< FIFO is empty
|
||||
uint32_t fifo_full: 1; ///< FIFO is full
|
||||
uint32_t cmd_fsm_state: 4; ///< command FSM state
|
||||
uint32_t data3_status: 1; ///< this bit reads 1 if card is present
|
||||
uint32_t data_busy: 1; ///< this bit reads 1 if card is busy
|
||||
uint32_t data_fsm_busy: 1; ///< this bit reads 1 if transmit/receive FSM is busy
|
||||
uint32_t response_index: 6; ///< index of the previous response
|
||||
uint32_t fifo_count: 13; ///< number of filled locations in the FIFO
|
||||
uint32_t dma_ack: 1; ///< DMA acknowledge signal
|
||||
uint32_t dma_req: 1; ///< DMA request signal
|
||||
};
|
||||
uint32_t val;
|
||||
} status;
|
||||
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t tx_watermark: 12; ///< FIFO TX watermark level
|
||||
uint32_t reserved1: 4;
|
||||
uint32_t rx_watermark: 12; ///< FIFO RX watermark level
|
||||
uint32_t dw_dma_mts: 3;
|
||||
uint32_t reserved2: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} fifoth;
|
||||
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t cards: 2; ///< bit N reads 0 if card N is present
|
||||
uint32_t reserved: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} cdetect;
|
||||
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t cards: 2; ///< bit N reads 1 if card N is write protected
|
||||
uint32_t reserved: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} wrtprt;
|
||||
|
||||
volatile uint32_t gpio; ///< unused
|
||||
volatile uint32_t tcbcnt; ///< transferred (to card) byte count
|
||||
volatile uint32_t tbbcnt; ///< transferred from host to FIFO byte count
|
||||
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t debounce_count: 24; ///< number of host cycles used by debounce filter, typical time should be 5-25ms
|
||||
uint32_t reserved: 8;
|
||||
};
|
||||
} debnce;
|
||||
|
||||
volatile uint32_t usrid; ///< user ID
|
||||
volatile uint32_t verid; ///< IP block version
|
||||
|
||||
volatile union {
|
||||
struct {
|
||||
/** card_type_reg : RO; bitpos: [0]; default: 1;
|
||||
* Hardware support SDIO and MMC.
|
||||
*/
|
||||
uint32_t card_type_reg:1;
|
||||
/** card_num_reg : RO; bitpos: [5:1]; default: 1;
|
||||
* Support card number is 2.
|
||||
*/
|
||||
uint32_t card_num_reg:5;
|
||||
/** bus_type_reg : RO; bitpos: [6]; default: 1;
|
||||
* Register config is APB bus.
|
||||
*/
|
||||
uint32_t bus_type_reg:1;
|
||||
/** data_width_reg : RO; bitpos: [9:7]; default: 1;
|
||||
* Regisger data width is 32.
|
||||
*/
|
||||
uint32_t data_width_reg:3;
|
||||
/** addr_width_reg : RO; bitpos: [15:10]; default: 19;
|
||||
* Register address width is 32.
|
||||
*/
|
||||
uint32_t addr_width_reg:6;
|
||||
uint32_t reserved_16:2;
|
||||
/** dma_width_reg : RO; bitpos: [20:18]; default: 1;
|
||||
* DMA data width is 32.
|
||||
*/
|
||||
uint32_t dma_width_reg:3;
|
||||
/** ram_indise_reg : RO; bitpos: [21]; default: 0;
|
||||
* Inside RAM in SDMMC module.
|
||||
*/
|
||||
uint32_t ram_indise_reg:1;
|
||||
/** hold_reg : RO; bitpos: [22]; default: 1;
|
||||
* Have a hold register in data path .
|
||||
*/
|
||||
uint32_t hold_reg:1;
|
||||
uint32_t reserved_23:1;
|
||||
/** num_clk_div_reg : RO; bitpos: [25:24]; default: 3;
|
||||
* Have 4 clk divider in design .
|
||||
*/
|
||||
uint32_t num_clk_div_reg:2;
|
||||
uint32_t reserved_26:6;
|
||||
};
|
||||
uint32_t val;
|
||||
} hcon;
|
||||
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t voltage: 16; ///< voltage control for slots; no-op on ESP32.
|
||||
uint32_t ddr: 16; ///< bit N enables DDR mode for card N
|
||||
};
|
||||
uint32_t val;
|
||||
} uhs; ///< UHS related settings
|
||||
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t cards: 2; ///< bit N resets card N, active low
|
||||
uint32_t reserved: 30;
|
||||
};
|
||||
} rst_n;
|
||||
|
||||
uint32_t reserved_7c;
|
||||
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t sw_reset: 1; ///< set to reset DMA controller
|
||||
uint32_t fb: 1; ///< set if AHB master performs fixed burst transfers
|
||||
uint32_t dsl: 5; ///< descriptor skip length: number of words to skip between two unchained descriptors
|
||||
uint32_t enable: 1; ///< set to enable IDMAC
|
||||
uint32_t pbl: 3; ///< programmable burst length
|
||||
uint32_t reserved: 21;
|
||||
};
|
||||
uint32_t val;
|
||||
} bmod;
|
||||
|
||||
volatile uint32_t pldmnd; ///< set any bit to resume IDMAC FSM from suspended state
|
||||
volatile sdmmc_desc_t* dbaddr; ///< descriptor list base
|
||||
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t ti: 1; ///< transmit interrupt status
|
||||
uint32_t ri: 1; ///< receive interrupt status
|
||||
uint32_t fbe: 1; ///< fatal bus error
|
||||
uint32_t reserved1: 1;
|
||||
uint32_t du: 1; ///< descriptor unavailable
|
||||
uint32_t ces: 1; ///< card error summary
|
||||
uint32_t reserved2: 2;
|
||||
uint32_t nis: 1; ///< normal interrupt summary
|
||||
uint32_t ais: 1; ///< abnormal interrupt summary
|
||||
uint32_t fbe_code: 3; ///< code of fatal bus error
|
||||
uint32_t fsm: 4; ///< DMAC FSM state
|
||||
uint32_t reserved3: 15;
|
||||
};
|
||||
uint32_t val;
|
||||
} idsts;
|
||||
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t ti: 1; ///< transmit interrupt enable
|
||||
uint32_t ri: 1; ///< receive interrupt enable
|
||||
uint32_t fbe: 1; ///< fatal bus error interrupt enable
|
||||
uint32_t reserved1: 1;
|
||||
uint32_t du: 1; ///< descriptor unavailable interrupt enable
|
||||
uint32_t ces: 1; ///< card error interrupt enable
|
||||
uint32_t reserved2: 2;
|
||||
uint32_t ni: 1; ///< normal interrupt interrupt enable
|
||||
uint32_t ai: 1; ///< abnormal interrupt enable
|
||||
uint32_t reserved3: 22;
|
||||
};
|
||||
uint32_t val;
|
||||
} idinten;
|
||||
|
||||
volatile uint32_t dscaddr; ///< current host descriptor address
|
||||
volatile uint32_t dscaddrl; ///< unused
|
||||
volatile uint32_t dscaddru; ///< unused
|
||||
volatile uint32_t bufaddrl; ///< unused
|
||||
volatile uint32_t bufaddru; ///< unused
|
||||
volatile uint32_t reserved_a8[22];
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t read_thr_en : 1; ///< initiate transfer only if FIFO has more space than the read threshold
|
||||
uint32_t busy_clr_int_en : 1; ///< enable generation of busy clear interrupts
|
||||
uint32_t write_thr_en : 1; ///< equivalent of read_thr_en for writes
|
||||
uint32_t reserved1 : 13;
|
||||
uint32_t card_threshold : 16; ///< threshold value for reads/writes, in bytes
|
||||
};
|
||||
uint32_t val;
|
||||
} cardthrctl;
|
||||
volatile uint32_t back_end_power;
|
||||
volatile uint32_t uhs_reg_ext;
|
||||
volatile uint32_t emmc_ddr_reg;
|
||||
volatile uint32_t enable_shift;
|
||||
uint32_t reserved_114[443];
|
||||
volatile union {
|
||||
struct {
|
||||
uint32_t phase_dout: 3; ///< phase of data output clock (0x0: 0, 0x1: 90, 0x4: 180, 0x6: 270)
|
||||
uint32_t phase_din: 3; ///< phase of data input clock
|
||||
uint32_t phase_core: 3; ///< phase of the clock to SDMMC peripheral
|
||||
uint32_t div_factor_h: 4; ///< controls length of high pulse; it will be (div_factor_h + 1) / 160MHz
|
||||
uint32_t div_factor_l: 4; ///< controls clock period; it will be (div_factor_l + 1) / 160MHz
|
||||
uint32_t div_factor_n: 4; ///< should be equal to div_factor_l
|
||||
uint32_t reserved1 : 2;
|
||||
uint32_t clk_sel : 1; ///< clock source select (0: XTAL, 1: 160 MHz from PLL)
|
||||
uint32_t reserved24: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} clock;
|
||||
} sdmmc_dev_t;
|
||||
extern sdmmc_dev_t SDMMC;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(sdmmc_dev_t) == 0x804, "invalid size of sdmmc_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,530 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _SOC_SENS_STRUCT_H_
|
||||
#define _SOC_SENS_STRUCT_H_
|
||||
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct sens_dev_s {
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar1_clk_div : 8; /*clock divider*/
|
||||
uint32_t reserved8 : 10;
|
||||
uint32_t sar1_clk_gated : 1;
|
||||
uint32_t sar1_sample_num : 8;
|
||||
uint32_t reserved27 : 1;
|
||||
uint32_t sar1_data_inv : 1; /*Invert SAR ADC1 data*/
|
||||
uint32_t sar1_int_en : 1; /*enable saradc1 to send out interrupt*/
|
||||
uint32_t reserved30 : 2;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_reader1_ctrl;
|
||||
uint32_t sar_reader1_status;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 24;
|
||||
uint32_t force_xpd_amp : 2;
|
||||
uint32_t amp_rst_fb_force : 2;
|
||||
uint32_t amp_short_ref_force : 2;
|
||||
uint32_t amp_short_ref_gnd_force : 2;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_meas1_ctrl1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t meas1_data_sar : 16; /*SAR ADC1 data*/
|
||||
uint32_t meas1_done_sar : 1; /*SAR ADC1 conversion done indication*/
|
||||
uint32_t meas1_start_sar : 1; /*SAR ADC1 controller (in RTC) starts conversion*/
|
||||
uint32_t meas1_start_force : 1; /*1: SAR ADC1 controller (in RTC) is started by SW*/
|
||||
uint32_t sar1_en_pad : 12; /*SAR ADC1 pad enable bitmap*/
|
||||
uint32_t sar1_en_pad_force : 1; /*1: SAR ADC1 pad enable bitmap is controlled by SW*/
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_meas1_ctrl2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 31;
|
||||
uint32_t sar1_dig_force : 1; /*1: SAR ADC1 controlled by DIG ADC1 CTRL*/
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_meas1_mux;
|
||||
uint32_t sar_atten1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar_amp_wait1 : 16;
|
||||
uint32_t sar_amp_wait2 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_amp_ctrl1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar1_dac_xpd_fsm_idle : 1;
|
||||
uint32_t xpd_sar_amp_fsm_idle : 1;
|
||||
uint32_t amp_rst_fb_fsm_idle : 1;
|
||||
uint32_t amp_short_ref_fsm_idle : 1;
|
||||
uint32_t amp_short_ref_gnd_fsm_idle : 1;
|
||||
uint32_t xpd_sar_fsm_idle : 1;
|
||||
uint32_t sar_rstb_fsm_idle : 1;
|
||||
uint32_t reserved7 : 9;
|
||||
uint32_t sar_amp_wait3 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_amp_ctrl2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar1_dac_xpd_fsm : 4;
|
||||
uint32_t xpd_sar_amp_fsm : 4;
|
||||
uint32_t amp_rst_fb_fsm : 4;
|
||||
uint32_t amp_short_ref_fsm : 4;
|
||||
uint32_t amp_short_ref_gnd_fsm : 4;
|
||||
uint32_t xpd_sar_fsm : 4;
|
||||
uint32_t sar_rstb_fsm : 4;
|
||||
uint32_t reserved28 : 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_amp_ctrl3;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar2_clk_div : 8; /*clock divider*/
|
||||
uint32_t reserved8 : 8;
|
||||
uint32_t sar2_wait_arb_cycle : 2; /*wait arbit stable after sar_done*/
|
||||
uint32_t sar2_clk_gated : 1;
|
||||
uint32_t sar2_sample_num : 8;
|
||||
uint32_t reserved27 : 2;
|
||||
uint32_t sar2_data_inv : 1; /*Invert SAR ADC2 data*/
|
||||
uint32_t sar2_int_en : 1; /*enable saradc2 to send out interrupt*/
|
||||
uint32_t reserved31 : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_reader2_ctrl;
|
||||
uint32_t sar_reader2_status;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar2_cntl_state : 3; /*saradc2_cntl_fsm*/
|
||||
uint32_t sar2_pwdet_cal_en : 1; /*rtc control pwdet enable*/
|
||||
uint32_t sar2_pkdet_cal_en : 1; /*rtc control pkdet enable*/
|
||||
uint32_t sar2_en_test : 1; /*SAR2_EN_TEST*/
|
||||
uint32_t sar2_rstb_force : 2;
|
||||
uint32_t sar2_standby_wait : 8;
|
||||
uint32_t sar2_rstb_wait : 8;
|
||||
uint32_t sar2_xpd_wait : 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_meas2_ctrl1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t meas2_data_sar : 16; /*SAR ADC2 data*/
|
||||
uint32_t meas2_done_sar : 1; /*SAR ADC2 conversion done indication*/
|
||||
uint32_t meas2_start_sar : 1; /*SAR ADC2 controller (in RTC) starts conversion*/
|
||||
uint32_t meas2_start_force : 1; /*1: SAR ADC2 controller (in RTC) is started by SW*/
|
||||
uint32_t sar2_en_pad : 12; /*SAR ADC2 pad enable bitmap*/
|
||||
uint32_t sar2_en_pad_force : 1; /*1: SAR ADC2 pad enable bitmap is controlled by SW*/
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_meas2_ctrl2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 28;
|
||||
uint32_t sar2_pwdet_cct : 3; /*SAR2_PWDET_CCT*/
|
||||
uint32_t sar2_rtc_force : 1; /*in sleep, force to use rtc to control ADC*/
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_meas2_mux;
|
||||
uint32_t sar_atten2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 29;
|
||||
uint32_t force_xpd_sar : 2;
|
||||
uint32_t sarclk_en : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_power_xpd_sar;
|
||||
union {
|
||||
struct {
|
||||
uint32_t i2c_slave_addr1 : 11;
|
||||
uint32_t i2c_slave_addr0 : 11;
|
||||
uint32_t meas_status : 8;
|
||||
uint32_t reserved30 : 2;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_slave_addr1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t i2c_slave_addr3 : 11;
|
||||
uint32_t i2c_slave_addr2 : 11;
|
||||
uint32_t reserved22 : 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_slave_addr2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t i2c_slave_addr5 : 11;
|
||||
uint32_t i2c_slave_addr4 : 11;
|
||||
uint32_t reserved22 : 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_slave_addr3;
|
||||
union {
|
||||
struct {
|
||||
uint32_t i2c_slave_addr7 : 11;
|
||||
uint32_t i2c_slave_addr6 : 11;
|
||||
uint32_t reserved22 : 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_slave_addr4;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tsens_out : 8; /*temperature sensor data out*/
|
||||
uint32_t tsens_ready : 1; /*indicate temperature sensor out ready*/
|
||||
uint32_t reserved9 : 3;
|
||||
uint32_t tsens_int_en : 1; /*enable temperature sensor to send out interrupt*/
|
||||
uint32_t tsens_in_inv : 1; /*invert temperature sensor data*/
|
||||
uint32_t tsens_clk_div : 8; /*temperature sensor clock divider*/
|
||||
uint32_t tsens_power_up : 1; /*temperature sensor power up*/
|
||||
uint32_t tsens_power_up_force : 1; /*1: dump out & power up controlled by SW*/
|
||||
uint32_t tsens_dump_out : 1; /*temperature sensor dump out*/
|
||||
uint32_t reserved25 : 7;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_tctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tsens_xpd_wait : 12;
|
||||
uint32_t tsens_xpd_force : 2;
|
||||
uint32_t tsens_clk_inv : 1;
|
||||
uint32_t reserved15 : 17;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_tctrl2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar_i2c_ctrl : 28; /*I2C control data*/
|
||||
uint32_t sar_i2c_start : 1; /*start I2C*/
|
||||
uint32_t sar_i2c_start_force : 1; /*1: I2C started by SW*/
|
||||
uint32_t reserved30 : 2;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_i2c_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t touch_outen : 15; /*touch controller output enable*/
|
||||
uint32_t touch_status_clr : 1; /*clear all touch active status*/
|
||||
uint32_t touch_data_sel : 2; /*3: smooth data 2: benchmark 1,0: raw_data*/
|
||||
uint32_t touch_denoise_end : 1; /*touch_denoise_done*/
|
||||
uint32_t touch_unit_end : 1; /*touch_unit_done*/
|
||||
uint32_t touch_approach_pad2 : 4; /*indicate which pad is approach pad2*/
|
||||
uint32_t touch_approach_pad1 : 4; /*indicate which pad is approach pad1*/
|
||||
uint32_t touch_approach_pad0 : 4; /*indicate which pad is approach pad0*/
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_touch_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t touch_denoise_data : 22;
|
||||
uint32_t reserved22 : 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_touch_denoise;
|
||||
union {
|
||||
struct {
|
||||
uint32_t thresh : 22; /*Finger threshold for touch pad 1*/
|
||||
uint32_t reserved22 : 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} touch_thresh[14];
|
||||
union {
|
||||
struct {
|
||||
uint32_t touch_pad_active : 15; /*touch active status*/
|
||||
uint32_t touch_channel_clr : 15; /*Clear touch channel*/
|
||||
uint32_t reserved30 : 1;
|
||||
uint32_t touch_meas_done : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_touch_chn_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t touch_denoise_data : 22; /*the counter for touch pad 0*/
|
||||
uint32_t touch_scan_curr : 4;
|
||||
uint32_t reserved26 : 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_touch_status0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t touch_pad_data : 22;
|
||||
uint32_t reserved22 : 7;
|
||||
uint32_t touch_pad_debounce : 3;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_touch_status[14];
|
||||
union {
|
||||
struct {
|
||||
uint32_t touch_slp_data : 22;
|
||||
uint32_t reserved22 : 7;
|
||||
uint32_t touch_slp_debounce : 3;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_touch_slp_status;
|
||||
union {
|
||||
struct {
|
||||
uint32_t touch_approach_pad2_cnt : 8;
|
||||
uint32_t touch_approach_pad1_cnt : 8;
|
||||
uint32_t touch_approach_pad0_cnt : 8;
|
||||
uint32_t touch_slp_approach_cnt : 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_touch_appr_status;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 25;
|
||||
uint32_t dbg_trigger : 1; /*trigger cocpu debug registers*/
|
||||
uint32_t clk_en_st : 1; /*check cocpu whether clk on*/
|
||||
uint32_t reset_n : 1; /*check cocpu whether in reset state*/
|
||||
uint32_t eoi : 1; /*check cocpu whether in interrupt state*/
|
||||
uint32_t trap : 1; /*check cocpu whether in trap state*/
|
||||
uint32_t ebreak : 1; /*check cocpu whether in ebreak*/
|
||||
uint32_t reserved31 : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_cocpu_state;
|
||||
union {
|
||||
struct {
|
||||
uint32_t touch_done : 1; /*int from touch done*/
|
||||
uint32_t touch_inactive : 1; /*int from touch inactive*/
|
||||
uint32_t touch_active : 1; /*int from touch active*/
|
||||
uint32_t saradc1 : 1; /*int from saradc1*/
|
||||
uint32_t saradc2 : 1; /*int from saradc2*/
|
||||
uint32_t tsens : 1; /*int from tsens*/
|
||||
uint32_t start : 1; /*int from start*/
|
||||
uint32_t sw : 1; /*int from software*/
|
||||
uint32_t swd : 1; /*int from super watch dog*/
|
||||
uint32_t touch_timeout : 1;
|
||||
uint32_t touch_approach_loop_done : 1;
|
||||
uint32_t touch_scan_done : 1;
|
||||
uint32_t reserved12 : 20;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_cocpu_int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t touch_done : 1;
|
||||
uint32_t touch_inactive : 1;
|
||||
uint32_t touch_active : 1;
|
||||
uint32_t saradc1 : 1;
|
||||
uint32_t saradc2 : 1;
|
||||
uint32_t tsens : 1;
|
||||
uint32_t start : 1;
|
||||
uint32_t sw : 1; /*cocpu int enable*/
|
||||
uint32_t swd : 1;
|
||||
uint32_t touch_timeout : 1;
|
||||
uint32_t touch_approach_loop_done : 1;
|
||||
uint32_t touch_scan_done : 1;
|
||||
uint32_t reserved12 : 20;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_cocpu_int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t touch_done : 1;
|
||||
uint32_t touch_inactive : 1;
|
||||
uint32_t touch_active : 1;
|
||||
uint32_t saradc1 : 1;
|
||||
uint32_t saradc2 : 1;
|
||||
uint32_t tsens : 1;
|
||||
uint32_t start : 1;
|
||||
uint32_t sw : 1; /*cocpu int status*/
|
||||
uint32_t swd : 1;
|
||||
uint32_t touch_timeout : 1;
|
||||
uint32_t touch_approach_loop_done : 1;
|
||||
uint32_t touch_scan_done : 1;
|
||||
uint32_t reserved12 : 20;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_cocpu_int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t touch_done : 1;
|
||||
uint32_t touch_inactive : 1;
|
||||
uint32_t touch_active : 1;
|
||||
uint32_t saradc1 : 1;
|
||||
uint32_t saradc2 : 1;
|
||||
uint32_t tsens : 1;
|
||||
uint32_t start : 1;
|
||||
uint32_t sw : 1; /*cocpu int clear*/
|
||||
uint32_t swd : 1;
|
||||
uint32_t touch_timeout : 1;
|
||||
uint32_t touch_approach_loop_done : 1;
|
||||
uint32_t touch_scan_done : 1;
|
||||
uint32_t reserved12 : 20;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_cocpu_int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t pc : 13; /*cocpu Program counter*/
|
||||
uint32_t mem_vld : 1; /*cocpu mem valid output*/
|
||||
uint32_t mem_rdy : 1; /*cocpu mem ready input*/
|
||||
uint32_t mem_wen : 4; /*cocpu mem write enable output*/
|
||||
uint32_t mem_addr : 13; /*cocpu mem address output*/
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_cocpu_debug;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 28;
|
||||
uint32_t xpd_hall : 1; /*Power on hall sensor and connect to VP and VN*/
|
||||
uint32_t xpd_hall_force : 1; /*1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by FSM in ULP-coprocessor*/
|
||||
uint32_t hall_phase : 1; /*Reverse phase of hall sensor*/
|
||||
uint32_t hall_phase_force : 1; /*1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled by FSM in ULP-coprocessor*/
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_hall_ctrl;
|
||||
uint32_t sar_nouse;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 27;
|
||||
uint32_t rtc_i2c_clk_en : 1;
|
||||
uint32_t reserved28 : 1;
|
||||
uint32_t tsens_clk_en : 1;
|
||||
uint32_t saradc_clk_en : 1;
|
||||
uint32_t iomux_clk_en : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_peri_clk_gate_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 25;
|
||||
uint32_t reset : 1;
|
||||
uint32_t reserved26 : 1;
|
||||
uint32_t rtc_i2c_reset : 1;
|
||||
uint32_t reserved28 : 1;
|
||||
uint32_t tsens_reset : 1;
|
||||
uint32_t saradc_reset : 1;
|
||||
uint32_t reserved31 : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_peri_reset_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t touch_done_w1ts : 1;
|
||||
uint32_t touch_inactive_w1ts : 1;
|
||||
uint32_t touch_active_w1ts : 1;
|
||||
uint32_t saradc1_w1ts : 1;
|
||||
uint32_t saradc2_w1ts : 1;
|
||||
uint32_t tsens_w1ts : 1;
|
||||
uint32_t start_w1ts : 1;
|
||||
uint32_t sw_w1ts : 1;
|
||||
uint32_t swd_w1ts : 1;
|
||||
uint32_t touch_timeout_w1ts : 1;
|
||||
uint32_t touch_approach_loop_done_w1ts : 1;
|
||||
uint32_t touch_scan_done_w1ts : 1;
|
||||
uint32_t reserved12 : 20;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_cocpu_int_ena_w1ts;
|
||||
union {
|
||||
struct {
|
||||
uint32_t touch_done_w1tc : 1;
|
||||
uint32_t touch_inactive_w1tc : 1;
|
||||
uint32_t touch_active_w1tc : 1;
|
||||
uint32_t saradc1_w1tc : 1;
|
||||
uint32_t saradc2_w1tc : 1;
|
||||
uint32_t tsens_w1tc : 1;
|
||||
uint32_t start_w1tc : 1;
|
||||
uint32_t sw_w1tc : 1;
|
||||
uint32_t swd_w1tc : 1;
|
||||
uint32_t touch_timeout_w1tc : 1;
|
||||
uint32_t touch_approach_loop_done_w1tc : 1;
|
||||
uint32_t touch_scan_done_w1tc : 1;
|
||||
uint32_t reserved12 : 20;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_cocpu_int_ena_w1tc;
|
||||
union {
|
||||
struct {
|
||||
uint32_t debug_bit_sel : 5;
|
||||
uint32_t reserved5 : 27;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_debug_conf;
|
||||
uint32_t reserved_118;
|
||||
uint32_t reserved_11c;
|
||||
uint32_t reserved_120;
|
||||
uint32_t reserved_124;
|
||||
uint32_t reserved_128;
|
||||
uint32_t reserved_12c;
|
||||
uint32_t reserved_130;
|
||||
uint32_t reserved_134;
|
||||
uint32_t reserved_138;
|
||||
uint32_t reserved_13c;
|
||||
uint32_t reserved_140;
|
||||
uint32_t reserved_144;
|
||||
uint32_t reserved_148;
|
||||
uint32_t reserved_14c;
|
||||
uint32_t reserved_150;
|
||||
uint32_t reserved_154;
|
||||
uint32_t reserved_158;
|
||||
uint32_t reserved_15c;
|
||||
uint32_t reserved_160;
|
||||
uint32_t reserved_164;
|
||||
uint32_t reserved_168;
|
||||
uint32_t reserved_16c;
|
||||
uint32_t reserved_170;
|
||||
uint32_t reserved_174;
|
||||
uint32_t reserved_178;
|
||||
uint32_t reserved_17c;
|
||||
uint32_t reserved_180;
|
||||
uint32_t reserved_184;
|
||||
uint32_t reserved_188;
|
||||
uint32_t reserved_18c;
|
||||
uint32_t reserved_190;
|
||||
uint32_t reserved_194;
|
||||
uint32_t reserved_198;
|
||||
uint32_t reserved_19c;
|
||||
uint32_t reserved_1a0;
|
||||
uint32_t reserved_1a4;
|
||||
uint32_t reserved_1a8;
|
||||
uint32_t reserved_1ac;
|
||||
uint32_t reserved_1b0;
|
||||
uint32_t reserved_1b4;
|
||||
uint32_t reserved_1b8;
|
||||
uint32_t reserved_1bc;
|
||||
uint32_t reserved_1c0;
|
||||
uint32_t reserved_1c4;
|
||||
uint32_t reserved_1c8;
|
||||
uint32_t reserved_1cc;
|
||||
uint32_t reserved_1d0;
|
||||
uint32_t reserved_1d4;
|
||||
uint32_t reserved_1d8;
|
||||
uint32_t reserved_1dc;
|
||||
uint32_t reserved_1e0;
|
||||
uint32_t reserved_1e4;
|
||||
uint32_t reserved_1e8;
|
||||
uint32_t reserved_1ec;
|
||||
uint32_t reserved_1f0;
|
||||
uint32_t reserved_1f4;
|
||||
uint32_t reserved_1f8;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar_date : 28;
|
||||
uint32_t reserved28 : 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} sardate;
|
||||
} sens_dev_t;
|
||||
extern sens_dev_t SENS;
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /*_SOC_SENS_STRUCT_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -12,7 +12,7 @@
|
||||
#endif
|
||||
|
||||
#include "esp_bit_defs.h"
|
||||
#include "reg_base.h"
|
||||
#include "soc/reg_base.h"
|
||||
|
||||
#define PRO_CPU_NUM (0)
|
||||
#define APP_CPU_NUM (1)
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,781 +0,0 @@
|
||||
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_SPI_MEM_STRUCT_H_
|
||||
#define _SOC_SPI_MEM_STRUCT_H_
|
||||
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct spi_mem_dev_s {
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 17; /*reserved*/
|
||||
uint32_t flash_pe : 1; /*In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with SPI_MEM_USR bit. The bit will be cleared once the operation done.1: enable 0: disable. */
|
||||
uint32_t usr : 1; /*User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
|
||||
uint32_t flash_hpm : 1; /*Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable. */
|
||||
uint32_t flash_res : 1; /*This bit combined with SPI_MEM_RESANDRES bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable. */
|
||||
uint32_t flash_dp : 1; /*Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
|
||||
uint32_t flash_ce : 1; /*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
|
||||
uint32_t flash_be : 1; /*Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
|
||||
uint32_t flash_se : 1; /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
|
||||
uint32_t flash_pp : 1; /*Page program enable(1 byte ~64 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable. */
|
||||
uint32_t flash_wrsr : 1; /*Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
|
||||
uint32_t flash_rdsr : 1; /*Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
|
||||
uint32_t flash_rdid : 1; /*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
|
||||
uint32_t flash_wrdi : 1; /*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
|
||||
uint32_t flash_wren : 1; /*Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
|
||||
uint32_t flash_read : 1; /*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable. */
|
||||
};
|
||||
uint32_t val;
|
||||
} cmd;
|
||||
uint32_t addr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 3; /*reserved*/
|
||||
uint32_t fdummy_out : 1; /*In the DUMMY phase the signal level of SPI bus is output by the SPI0 controller.*/
|
||||
uint32_t fdout_oct : 1; /*Set this bit to enable 8-bit-mode(8-bm) in DOUT phase.*/
|
||||
uint32_t fdin_oct : 1; /*Set this bit to enable 8-bit-mode(8-bm) in DIN phase.*/
|
||||
uint32_t faddr_oct : 1; /*Set this bit to enable 8-bit-mode(8-bm) in ADDR phase.*/
|
||||
uint32_t fcmd_dual : 1; /*Set this bit to enable 2-bit-mode(2-bm) in CMD phase.*/
|
||||
uint32_t fcmd_quad : 1; /*Set this bit to enable 4-bit-mode(4-bm) in CMD phase.*/
|
||||
uint32_t fcmd_oct : 1; /*Set this bit to enable 8-bit-mode(8-bm) in CMD phase.*/
|
||||
uint32_t fcs_crc_en : 1; /*For SPI1, initialize crc32 module before writing encrypted data to flash. Active low.*/
|
||||
uint32_t tx_crc_en : 1; /*For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/
|
||||
uint32_t reserved12 : 1; /*reserved*/
|
||||
uint32_t fastrd_mode : 1; /*This bit should be set when SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD or SPI_MEM_FREAD_DUAL is set.*/
|
||||
uint32_t fread_dual : 1; /*In hardware 0x3B read operation, DIN phase apply 2 signals. 1: enable 0: disable. */
|
||||
uint32_t resandres : 1; /*The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable. */
|
||||
uint32_t reserved16 : 2; /*reserved*/
|
||||
uint32_t q_pol : 1; /*The bit is used to set MISO line polarity, 1: high 0, low*/
|
||||
uint32_t d_pol : 1; /*The bit is used to set MOSI line polarity, 1: high 0, low*/
|
||||
uint32_t fread_quad : 1; /*In hardware 0x6B read operation, DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable. */
|
||||
uint32_t wp : 1; /*Write protect signal output when SPI is idle. 1: output high, 0: output low. */
|
||||
uint32_t wrsr_2b : 1; /*Two bytes data will be written to status register when it is set. 1: enable 0: disable. */
|
||||
uint32_t fread_dio : 1; /*In hardware 0xBB read operation, ADDR phase and DIN phase apply 2 signals(2-bit-mode). 1: enable 0: disable. */
|
||||
uint32_t fread_qio : 1; /*In hardware 0xEB read operation, ADDR phase and DIN phase apply 4 signals(4-bit-mode). 1: enable 0: disable. */
|
||||
uint32_t reserved25 : 7; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_mode : 2; /*SPI Bus clock (SPI_CLK) mode bits. 0: SPI Bus clock (SPI_CLK) is off when CS inactive 1: SPI_CLK is delayed one cycle after SPI_CS inactive 2: SPI_CLK is delayed two cycles after SPI_CS inactive 3: SPI_CLK is always on.*/
|
||||
uint32_t cs_hold_dly_res : 10; /*After RES/DP/HPM/PES/PER command is sent, SPI1 may waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or * 256) SPI_CLK cycles.*/
|
||||
uint32_t reserved2 : 18; /*reserved*/
|
||||
uint32_t rxfifo_rst : 1; /*SPI0 RX FIFO reset signal. Set this bit and clear it before SPI0 transfer starts.*/
|
||||
uint32_t reserved31 : 1; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} ctrl1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cs_setup_time : 5; /*(cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits are combined with SPI_MEM_CS_SETUP bit.*/
|
||||
uint32_t cs_hold_time : 5; /*SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_MEM_CS_HOLD bit.*/
|
||||
uint32_t ecc_cs_hold_time : 3; /*SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI_CS hold cycle in ECC mode when accessed flash.*/
|
||||
uint32_t ecc_skip_page_corner : 1; /*1: MSPI skips page corner when accesses flash. 0: Not skip page corner when accesses flash.*/
|
||||
uint32_t ecc_16to18_byte_en : 1; /*Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses flash.*/
|
||||
uint32_t reserved15 : 10; /*reserved*/
|
||||
uint32_t cs_hold_delay : 6; /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/
|
||||
uint32_t sync_reset : 1; /*The FSM will be reset.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} ctrl2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clkcnt_l : 8; /*It must equal to the value of SPI_MEM_CLKCNT_N. */
|
||||
uint32_t clkcnt_h : 8; /*It must be a floor value of ((SPI_MEM_CLKCNT_N+1)/2-1).*/
|
||||
uint32_t clkcnt_n : 8; /*When SPI0 accesses flash, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_CLKCNT_N+1)*/
|
||||
uint32_t reserved24 : 7; /*reserved*/
|
||||
uint32_t clk_equ_sysclk : 1; /*When SPI0 accesses flash, set this bit in 1-division mode, f_SPI_CLK = f_MSPI_CORE_CLK.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} clock;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 6; /*reserved*/
|
||||
uint32_t cs_hold : 1; /*Set this bit to keep SPI_CS low when MSPI is in DONE state.*/
|
||||
uint32_t cs_setup : 1; /*Set this bit to keep SPI_CS low when MSPI is in PREP state.*/
|
||||
uint32_t reserved8 : 1; /*reserved*/
|
||||
uint32_t ck_out_edge : 1; /*This bit, combined with SPI_MEM_CK_IDLE_EDGE bit, is used to change the clock mode 0~3 of SPI_CLK. */
|
||||
uint32_t reserved10 : 2; /*reserved*/
|
||||
uint32_t fwrite_dual : 1; /*Set this bit to enable 2-bm in DOUT phase in SPI1 write operation.*/
|
||||
uint32_t fwrite_quad : 1; /*Set this bit to enable 4-bm in DOUT phase in SPI1 write operation.*/
|
||||
uint32_t fwrite_dio : 1; /*Set this bit to enable 2-bm in ADDR and DOUT phase in SPI1 write operation.*/
|
||||
uint32_t fwrite_qio : 1; /*Set this bit to enable 4-bit-mode(4-bm) in ADDR and DOUT phase in SPI1 write operation.*/
|
||||
uint32_t reserved16 : 8; /*reserved*/
|
||||
uint32_t usr_miso_highpart : 1; /*DIN phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG. 1: enable 0: disable. */
|
||||
uint32_t usr_mosi_highpart : 1; /*DOUT phase only access to high-part of the buffer SPI_MEM_W8_REG~SPI_MEM_W15_REG. 1: enable 0: disable. */
|
||||
uint32_t usr_dummy_idle : 1; /*SPI_CLK is disabled(No clock edges) in DUMMY phase when the bit is enable.*/
|
||||
uint32_t usr_mosi : 1; /*Set this bit to enable the DOUT phase of an write-data operation.*/
|
||||
uint32_t usr_miso : 1; /*Set this bit to enable enable the DIN phase of a read-data operation.*/
|
||||
uint32_t usr_dummy : 1; /*Set this bit to enable enable the DUMMY phase of an operation.*/
|
||||
uint32_t usr_addr : 1; /*Set this bit to enable enable the ADDR phase of an operation.*/
|
||||
uint32_t usr_command : 1; /*Set this bit to enable enable the CMD phase of an operation.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} user;
|
||||
union {
|
||||
struct {
|
||||
uint32_t usr_dummy_cyclelen : 6; /*The SPI_CLK cycle length minus 1 of DUMMY phase.*/
|
||||
uint32_t reserved6 : 20; /*reserved*/
|
||||
uint32_t usr_addr_bitlen : 6; /*The length in bits of ADDR phase. The register value shall be (bit_num-1).*/
|
||||
};
|
||||
uint32_t val;
|
||||
} user1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t usr_command_value : 16; /*The value of user defined(USR) command.*/
|
||||
uint32_t reserved16 : 12; /*reserved*/
|
||||
uint32_t usr_command_bitlen : 4; /*The length in bits of CMD phase. The register value shall be (bit_num-1)*/
|
||||
};
|
||||
uint32_t val;
|
||||
} user2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t usr_mosi_bit_len : 10; /*The length in bits of DOUT phase. The register value shall be (bit_num-1).*/
|
||||
uint32_t reserved10 : 22; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} mosi_dlen;
|
||||
union {
|
||||
struct {
|
||||
uint32_t usr_miso_bit_len : 10; /*The length in bits of DIN phase. The register value shall be (bit_num-1).*/
|
||||
uint32_t reserved10 : 22; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} miso_dlen;
|
||||
union {
|
||||
struct {
|
||||
uint32_t status : 16; /*The value is stored when set SPI_MEM_FLASH_RDSR bit and SPI_MEM_FLASH_RES bit.*/
|
||||
uint32_t wb_mode : 8; /*Mode bits in the flash fast read mode it is combined with SPI_MEM_FASTRD_MODE bit.*/
|
||||
uint32_t reserved24 : 8; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} rd_status;
|
||||
uint32_t ext_addr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cs0_dis : 1; /*Set this bit to raise high SPI_CS pin, which means that the SPI device(flash) connected to SPI_CS is in low level when SPI1 transfer starts.*/
|
||||
uint32_t cs1_dis : 1; /*Set this bit to raise high SPI_CS1 pin, which means that the SPI device(Ext_RAM) connected to SPI_CS1 is in low level when SPI1 transfer starts.*/
|
||||
uint32_t reserved0 : 5; /*reserved*/
|
||||
uint32_t fsub_pin : 1; /*Flash is connected to SPI SUBPIN bus.*/
|
||||
uint32_t ssub_pin : 1; /*Ext_RAM is connected to SPI SUBPIN bus.*/
|
||||
uint32_t ck_idle_edge : 1; /*1: SPI_CLK line is high when idle. 0: SPI_CLK line is low when idle */
|
||||
uint32_t cs_keep_active : 1; /*SPI_CS line keep low when the bit is set.*/
|
||||
uint32_t auto_per : 1; /*Set this bit to enable auto PER function. Hardware will sent out PER command if PES command is sent.*/
|
||||
uint32_t reserved12 : 20; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} misc;
|
||||
uint32_t tx_crc;
|
||||
union {
|
||||
struct {
|
||||
uint32_t req_en : 1; /*Set this bit to enable Cache's access and SPI0's transfer.*/
|
||||
uint32_t usr_cmd_4byte : 1; /*Set this bit to enable SPI0 read flash with 32 bits address. The value of SPI_MEM_USR_ADDR_BITLEN should be 31.*/
|
||||
uint32_t flash_usr_cmd : 1; /*1: The command value of SPI0 reads flash is SPI_MEM_USR_COMMAND_VALUE. 0: Hardware read command value, controlled by SPI_MEM_FREAD_QIO, SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD, SPI_MEM_FREAD_DUAL and SPI_MEM_FASTRD_MODE bits.*/
|
||||
uint32_t fdin_dual : 1; /*When SPI0 accesses to flash, set this bit to enable 2-bm in DIN phase.*/
|
||||
uint32_t fdout_dual : 1; /*When SPI0 accesses to flash, set this bit to enable 2-bm in DOUT phase.*/
|
||||
uint32_t faddr_dual : 1; /*When SPI0 accesses to flash, set this bit to enable 2-bm in ADDR phase.*/
|
||||
uint32_t fdin_quad : 1; /*When SPI0 accesses to flash, set this bit to enable 4-bm in DIN phase.*/
|
||||
uint32_t fdout_quad : 1; /*When SPI0 accesses to flash, set this bit to enable 4-bm in DOUT phase.*/
|
||||
uint32_t faddr_quad : 1; /*When SPI0 accesses to flash, set this bit to enable 4-bm in ADDR phase.*/
|
||||
uint32_t reserved9 : 23; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} cache_fctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t usr_scmd_4byte : 1; /*Set this bit to enable SPI0 read Ext_RAM with 32 bits address. The value of SPI_MEM_SRAM_ADDR_BITLEN should be 31.*/
|
||||
uint32_t usr_sram_dio : 1; /*Set the bit to enable 2-bm in all the phases of SPI0 Ext_RAM transfer.*/
|
||||
uint32_t usr_sram_qio : 1; /*Set the bit to enable QPI mode in all SPI0 Ext_RAM transfer.*/
|
||||
uint32_t usr_wr_sram_dummy : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in write operations.*/
|
||||
uint32_t usr_rd_sram_dummy : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY phase in read operations.*/
|
||||
uint32_t usr_rcmd : 1; /*1: The command value of SPI0 read Ext_RAM is SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE. 0: The value is 0x2.*/
|
||||
uint32_t sram_rdummy_cyclelen : 6; /*When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in read data transfer.*/
|
||||
uint32_t reserved12 : 2; /*reserved*/
|
||||
uint32_t sram_addr_bitlen : 6; /*When SPI0 accesses to Ext_RAM, it is the length in bits of ADDR phase. The register value shall be (bit_num-1).*/
|
||||
uint32_t usr_wcmd : 1; /*1: The command value of SPI0 write Ext_RAM is SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE. 0: The value is 0x3.*/
|
||||
uint32_t sram_oct : 1; /*Set the bit to enable OPI mode in all SPI0 Ext_RAM transfer.*/
|
||||
uint32_t sram_wdummy_cyclelen : 6; /*When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus 1 of DUMMY phase in write data transfer.*/
|
||||
uint32_t reserved28 : 4; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} cache_sctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sclk_mode : 2; /*SPI_CLK mode bits when SPI0 accesses to Ext_RAM. 0: SPI_CLK is off when CS inactive 1: SPI_CLK is delayed one cycle after CS inactive 2: SPI_CLK is delayed two cycles after CS inactive 3: SPI_CLK is always on.*/
|
||||
uint32_t swb_mode : 8; /*Mode bits when SPI0 accesses to Ext_RAM.*/
|
||||
uint32_t sdin_dual : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DIN phase.*/
|
||||
uint32_t sdout_dual : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in DOUT phase.*/
|
||||
uint32_t saddr_dual : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in ADDR phase.*/
|
||||
uint32_t scmd_dual : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in CMD phase.*/
|
||||
uint32_t sdin_quad : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DIN phase.*/
|
||||
uint32_t sdout_quad : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in DOUT phase.*/
|
||||
uint32_t saddr_quad : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in ADDR phase.*/
|
||||
uint32_t scmd_quad : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in CMD phase.*/
|
||||
uint32_t sdin_oct : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DIN phase.*/
|
||||
uint32_t sdout_oct : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in DOUT phase.*/
|
||||
uint32_t saddr_oct : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in ADDR phase.*/
|
||||
uint32_t scmd_oct : 1; /*When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in CMD phase.*/
|
||||
uint32_t sdummy_out : 1; /*When SPI0 accesses to Ext_RAM, in the DUMMY phase the signal level of SPI bus is output by the SPI0 controller.*/
|
||||
uint32_t reserved23 : 9; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} sram_cmd;
|
||||
union {
|
||||
struct {
|
||||
uint32_t usr_rd_cmd_value : 16; /*When SPI0 reads Ext_RAM, it is the command value of CMD phase.*/
|
||||
uint32_t reserved16 : 12; /*reserved*/
|
||||
uint32_t usr_rd_cmd_bitlen : 4; /*When SPI0 reads Ext_RAM, it is the length in bits of CMD phase. The register value shall be (bit_num-1).*/
|
||||
};
|
||||
uint32_t val;
|
||||
} sram_drd_cmd;
|
||||
union {
|
||||
struct {
|
||||
uint32_t usr_wr_cmd_value : 16; /*When SPI0 writes Ext_RAM, it is the command value of CMD phase.*/
|
||||
uint32_t reserved16 : 12; /*reserved*/
|
||||
uint32_t usr_wr_cmd_bitlen : 4; /*When SPI0 writes Ext_RAM, it is the length in bits of CMD phase. The register value shall be (bit_num-1).*/
|
||||
};
|
||||
uint32_t val;
|
||||
} sram_dwr_cmd;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cnt_l : 8; /*It must equal to the value of SPI_MEM_SCLKCNT_N. */
|
||||
uint32_t cnt_h : 8; /*It must be a floor value of ((SPI_MEM_SCLKCNT_N+1)/2-1).*/
|
||||
uint32_t cnt_n : 8; /*When SPI0 accesses to Ext_RAM, f_SPI_CLK = f_MSPI_CORE_CLK/(SPI_MEM_SCLKCNT_N+1)*/
|
||||
uint32_t reserved24 : 7; /*reserved*/
|
||||
uint32_t equ_sysclk : 1; /*When SPI0 accesses to Ext_RAM, set this bit in 1-division mode, f_SPI_CLK = f_MSPI_CORE_CLK.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} sram_clk;
|
||||
union {
|
||||
struct {
|
||||
uint32_t st : 3; /*The status of SPI0 state machine. 0: idle state(IDLE), 1: preparation state(PREP), 2: send command state(CMD), 3: send address state(ADDR), 4: red data state(DIN), 5:write data state(DOUT), 6: wait state(DUMMY), 7: done state(DONE).*/
|
||||
uint32_t reserved3 : 29; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} fsm;
|
||||
uint32_t data_buf[16]; /*data buffer*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t waiti_en : 1; /*Set this bit to enable auto-waiting flash idle operation when PP/SE/BE/CE/WRSR/PES command is sent.*/
|
||||
uint32_t waiti_dummy : 1; /*Set this bit to enable DUMMY phase in auto wait flash idle transfer(RDSR).*/
|
||||
uint32_t waiti_cmd : 8; /*The command value of auto wait flash idle transfer(RDSR).*/
|
||||
uint32_t waiti_dummy_cyclelen : 6; /*The dummy cycle length when wait flash idle(RDSR).*/
|
||||
uint32_t reserved16 : 16; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_waiti_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_per : 1; /*program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
|
||||
uint32_t flash_pes : 1; /*program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. */
|
||||
uint32_t flash_per_wait_en : 1; /*Set this bit to add delay time after program erase resume(PER) is sent.*/
|
||||
uint32_t flash_pes_wait_en : 1; /*Set this bit to add delay time after program erase suspend(PES) command is sent.*/
|
||||
uint32_t pes_per_en : 1; /*Set this bit to enable PES transfer trigger PES transfer option.*/
|
||||
uint32_t pesr_idle_en : 1; /*1: Separate PER flash wait idle and PES flash wait idle. 0: Not separate.*/
|
||||
uint32_t reserved6 : 26; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_sus_cmd;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_pes_en : 1; /*Set this bit to enable auto-suspend function.*/
|
||||
uint32_t flash_per_command : 8; /*Program/Erase resume command value.*/
|
||||
uint32_t flash_pes_command : 8; /*Program/Erase suspend command value.*/
|
||||
uint32_t reserved17 : 15; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_sus_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_sus : 1; /*The status of flash suspend. This bit is set when PES command is sent, and cleared when PER is sent. Only used in SPI1.*/
|
||||
uint32_t reserved1 : 1; /*reserved*/
|
||||
uint32_t flash_hpm_dly_256 : 1; /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.*/
|
||||
uint32_t flash_res_dly_256 : 1; /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.*/
|
||||
uint32_t flash_dp_dly_256 : 1; /*1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.*/
|
||||
uint32_t flash_per_dly_256 : 1; /*Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.*/
|
||||
uint32_t flash_pes_dly_256 : 1; /*Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.*/
|
||||
uint32_t reserved7 : 25; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} sus_status;
|
||||
union {
|
||||
struct {
|
||||
uint32_t timing_clk_ena : 1; /*Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equals to that of PLL. Otherwise, the frequency equals to that of XTAL.*/
|
||||
uint32_t timing_cali : 1; /*Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operations.*/
|
||||
uint32_t extra_dummy_cyclelen : 3; /*Extra SPI_CLK cycles added in DUMMY phase for timing compensation, when SPI0 accesses to flash. Active when SPI_MEM_TIMING_CALI bit is set.*/
|
||||
uint32_t reserved5 : 27; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} timing_cali;
|
||||
union {
|
||||
struct {
|
||||
uint32_t din0_mode : 3; /*SPI_D input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
|
||||
uint32_t din1_mode : 3; /*SPI_Q input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
|
||||
uint32_t din2_mode : 3; /*SPI_WP input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
|
||||
uint32_t din3_mode : 3; /*SPI_HD input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
|
||||
uint32_t din4_mode : 3; /*SPI_IO4 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
|
||||
uint32_t din5_mode : 3; /*SPI_IO5 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
|
||||
uint32_t din6_mode : 3; /*SPI_IO6 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
|
||||
uint32_t din7_mode : 3; /*SPI_IO7 input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
|
||||
uint32_t dins_mode : 3; /*SPI_DQS input delay mode. 0: No delay. 1: Delay for (SPI_MEM_DINS_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
|
||||
uint32_t reserved27 : 5; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} din_mode;
|
||||
union {
|
||||
struct {
|
||||
uint32_t din0_num : 2; /*SPI_D input delay number.*/
|
||||
uint32_t din1_num : 2; /*SPI_Q input delay number.*/
|
||||
uint32_t din2_num : 2; /*SPI_WP input delay number.*/
|
||||
uint32_t din3_num : 2; /*SPI_HD input delay number.*/
|
||||
uint32_t din4_num : 2; /*SPI_IO4 input delay number.*/
|
||||
uint32_t din5_num : 2; /*SPI_IO5 input delay number.*/
|
||||
uint32_t din6_num : 2; /*SPI_IO6 input delay number.*/
|
||||
uint32_t din7_num : 2; /*SPI_IO7 input delay number.*/
|
||||
uint32_t dins_num : 2; /*SPI_DQS input delay number.*/
|
||||
uint32_t reserved18 : 14; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} din_num;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dout0_mode : 1; /*SPI_D output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
|
||||
uint32_t dout1_mode : 1; /*SPI_Q output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
|
||||
uint32_t dout2_mode : 1; /*SPI_WP output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
|
||||
uint32_t dout3_mode : 1; /*SPI_HD output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
|
||||
uint32_t dout4_mode : 1; /*SPI_IO4 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
|
||||
uint32_t dout5_mode : 1; /*SPI_IO5 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
|
||||
uint32_t dout6_mode : 1; /*SPI_IO6 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
|
||||
uint32_t dout7_mode : 1; /*SPI_IO7 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
|
||||
uint32_t douts_mode : 1; /*SPI_DQS output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
|
||||
uint32_t reserved9 : 23; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} dout_mode;
|
||||
uint32_t reserved_b8;
|
||||
union {
|
||||
struct {
|
||||
uint32_t smem_timing_clk_ena : 1; /*Set this bit to power on HCLK. When PLL is powered on, the frequency of HCLK equals to that of PLL. Otherwise, the frequency equals to that of XTAL.*/
|
||||
uint32_t smem_timing_cali : 1; /*Set this bit to add extra SPI_CLK cycles in DUMMY phase for all reading operations.*/
|
||||
uint32_t smem_extra_dummy_cyclelen : 3; /*Extra SPI_CLK cycles added in DUMMY phase for timing compensation, when SPI0 accesses to Ext_RAM. Active when SPI_SMEM_TIMING_CALI bit is set.*/
|
||||
uint32_t reserved5 : 27; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} spi_smem_timing_cali;
|
||||
union {
|
||||
struct {
|
||||
uint32_t smem_din0_mode : 3; /*SPI_D input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
|
||||
uint32_t smem_din1_mode : 3; /*SPI_Q input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
|
||||
uint32_t smem_din2_mode : 3; /*SPI_WP input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
|
||||
uint32_t smem_din3_mode : 3; /*SPI_HD input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
|
||||
uint32_t smem_din4_mode : 3; /*SPI_IO4 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
|
||||
uint32_t smem_din5_mode : 3; /*SPI_IO5 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
|
||||
uint32_t smem_din6_mode : 3; /*SPI_IO6 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
|
||||
uint32_t smem_din7_mode : 3; /*SPI_IO7 input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
|
||||
uint32_t smem_dins_mode : 3; /*SPI_DQS input delay mode. 0: No delay. 1: Delay for (SPI_SMEM_DINS_NUM+1) cycles at MSPI_CORE_CLK negative edge. 2: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. 4: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge.*/
|
||||
uint32_t reserved27 : 5; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} spi_smem_din_mode;
|
||||
union {
|
||||
struct {
|
||||
uint32_t smem_din0_num : 2; /*SPI_D input delay number.*/
|
||||
uint32_t smem_din1_num : 2; /*SPI_Q input delay number.*/
|
||||
uint32_t smem_din2_num : 2; /*SPI_WP input delay number.*/
|
||||
uint32_t smem_din3_num : 2; /*SPI_HD input delay number.*/
|
||||
uint32_t smem_din4_num : 2; /*SPI_IO4 input delay number.*/
|
||||
uint32_t smem_din5_num : 2; /*SPI_IO5 input delay number.*/
|
||||
uint32_t smem_din6_num : 2; /*SPI_IO6 input delay number.*/
|
||||
uint32_t smem_din7_num : 2; /*SPI_IO7 input delay number.*/
|
||||
uint32_t smem_dins_num : 2; /*SPI_DQS input delay number.*/
|
||||
uint32_t reserved18 : 14; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} spi_smem_din_num;
|
||||
union {
|
||||
struct {
|
||||
uint32_t smem_dout0_mode : 1; /*SPI_D output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
|
||||
uint32_t smem_dout1_mode : 1; /*SPI_Q output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
|
||||
uint32_t smem_dout2_mode : 1; /*SPI_WP output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
|
||||
uint32_t smem_dout3_mode : 1; /*SPI_HD output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
|
||||
uint32_t smem_dout4_mode : 1; /*SPI_IO4 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
|
||||
uint32_t smem_dout5_mode : 1; /*SPI_IO5 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
|
||||
uint32_t smem_dout6_mode : 1; /*SPI_IO6 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
|
||||
uint32_t smem_dout7_mode : 1; /*SPI_IO7 output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
|
||||
uint32_t smem_douts_mode : 1; /*SPI_DQS output delay mode. 0: No delay. 1: Delay one cycle at MSPI_CORE_CLK negative edge.*/
|
||||
uint32_t reserved9 : 23; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} spi_smem_dout_mode;
|
||||
union {
|
||||
struct {
|
||||
uint32_t ecc_err_int_num : 8; /*Set the error times of MSPI ECC read to generate MSPI SPI_MEM_ECC_ERR_INT interrupt.*/
|
||||
uint32_t fmem_ecc_err_int_en : 1; /*Set this bit to calculate the error times of MSPI ECC read when accesses to flash.*/
|
||||
uint32_t reserved9 : 23; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} ecc_ctrl;
|
||||
uint32_t ecc_err_addr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 6; /*reserved*/
|
||||
uint32_t ecc_data_err_bit : 7; /*It records the first ECC data error bit number when SPI_FMEM_ECC_ERR_INT_EN/SPI_SMEM_ECC_ERR_INT_EN is set and accessed to flash/Ext_RAM. The value ranges from 0~127, corresponding to the bit number in 16 data bytes. It is cleared by SPI_MEM_ECC_ERR_INT_CLR bit.*/
|
||||
uint32_t ecc_chk_err_bit : 3; /*When SPI_MEM_ECC_BYTE_ERR is set, these bits show the error bit number of ECC byte.*/
|
||||
uint32_t ecc_byte_err : 1; /*It records the first ECC byte error when SPI_FMEM_ECC_ERR_INT_EN/SPI_SMEM_ECC_ERR_INT_EN is set and accessed to flash/Ext_RAM. It is cleared by SPI_MEM_ECC_ERR_INT_CLR bit.*/
|
||||
uint32_t ecc_err_cnt : 8; /*This bits show the error times of MSPI ECC read, including ECC byte error and data byte error. It is cleared by when SPI_MEM_ECC_ERR_INT_CLR bit is set. */
|
||||
uint32_t reserved25 : 7; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} ecc_err_bit;
|
||||
uint32_t reserved_d8;
|
||||
union {
|
||||
struct {
|
||||
uint32_t smem_cs_setup : 1; /*Set this bit to keep SPI_CS low when MSPI is in PREP state.*/
|
||||
uint32_t smem_cs_hold : 1; /*Set this bit to keep SPI_CS low when MSPI is in DONE state.*/
|
||||
uint32_t smem_cs_setup_time : 5; /*(cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS setup time. These bits are combined with SPI_MEM_CS_SETUP bit.*/
|
||||
uint32_t smem_cs_hold_time : 5; /*SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits are combined with SPI_MEM_CS_HOLD bit.*/
|
||||
uint32_t smem_ecc_cs_hold_time : 3; /*SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the MSPI CS hold cycles in ECC mode when accesses to external RAM.*/
|
||||
uint32_t smem_ecc_skip_page_corner : 1; /*1: MSPI skips page corner when accesses to external RAM. 0: Not skip page corner when accesses to external RAM.*/
|
||||
uint32_t smem_ecc_16to18_byte_en : 1; /*Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses to external RAM.*/
|
||||
uint32_t reserved17 : 7; /*reserved*/
|
||||
uint32_t smem_ecc_err_int_en : 1; /*Set this bit to calculate the error times of MSPI ECC read when accesses to external RAM.*/
|
||||
uint32_t smem_cs_hold_delay : 6; /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/
|
||||
uint32_t reserved31 : 1; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} spi_smem_ac;
|
||||
union {
|
||||
struct {
|
||||
uint32_t fmem_ddr_en : 1; /*1: in ddr mode, 0 in sdr mode*/
|
||||
uint32_t fmem_var_dummy : 1; /*Set the bit to enable variable dummy cycle in DDR mode.*/
|
||||
uint32_t fmem_ddr_rdat_swp : 1; /*Set the bit to reorder RX data of the word in DDR mode.*/
|
||||
uint32_t fmem_ddr_wdat_swp : 1; /*Set the bit to swap TX data of a word in DDR mode.*/
|
||||
uint32_t fmem_ddr_cmd_dis : 1; /*the bit is used to disable dual edge in CMD phase when ddr mode.*/
|
||||
uint32_t fmem_outminbytelen : 7; /*It is the minimum output data length in the panda device.*/
|
||||
uint32_t fmem_tx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in MSPI ECC DDR write mode, when accesses to flash.*/
|
||||
uint32_t fmem_rx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when accesses to flash.*/
|
||||
uint32_t fmem_usr_ddr_dqs_thd : 7; /*The delay number of data strobe which from memory based on SPI_CLK.*/
|
||||
uint32_t fmem_ddr_dqs_loop : 1; /*1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module*/
|
||||
uint32_t fmem_ddr_dqs_loop_mode : 1; /*When SPI_FMEM_DDR_DQS_LOOP and SPI_FMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active.*/
|
||||
uint32_t reserved23 : 1; /*reserved*/
|
||||
uint32_t fmem_clk_diff_en : 1; /*Set this bit to enable the differential SPI_CLK#.*/
|
||||
uint32_t fmem_hyperbus_mode : 1; /*Set this bit to enable the SPI HyperBus mode.*/
|
||||
uint32_t fmem_dqs_ca_in : 1; /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/
|
||||
uint32_t fmem_hyperbus_dummy_2x : 1; /*Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses to flash or SPI1 accesses flash or sram.*/
|
||||
uint32_t fmem_clk_diff_inv : 1; /*Set this bit to invert SPI_DIFF when accesses to flash. .*/
|
||||
uint32_t fmem_octa_ram_addr : 1; /*Set this bit to enable octa_ram address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.*/
|
||||
uint32_t fmem_hyperbus_ca : 1; /*Set this bit to enable HyperRAM address out when accesses to flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.*/
|
||||
uint32_t reserved31 : 1; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} ddr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t smem_ddr_en : 1; /*1: in ddr mode, 0 in sdr mode*/
|
||||
uint32_t smem_var_dummy : 1; /*Set the bit to enable variable dummy cycle in spi ddr mode.*/
|
||||
uint32_t smem_ddr_rdat_swp : 1; /*Set the bit to reorder rx data of the word in spi ddr mode.*/
|
||||
uint32_t smem_ddr_wdat_swp : 1; /*Set the bit to reorder tx data of the word in spi ddr mode.*/
|
||||
uint32_t smem_ddr_cmd_dis : 1; /*the bit is used to disable dual edge in CMD phase when ddr mode.*/
|
||||
uint32_t smem_outminbytelen : 7; /*It is the minimum output data length in the ddr psram.*/
|
||||
uint32_t smem_tx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in MSPI ECC DDR write mode, when accesses to external RAM.*/
|
||||
uint32_t smem_rx_ddr_msk_en : 1; /*Set this bit to mask the first or the last byte in MSPI ECC DDR read mode, when accesses to external RAM.*/
|
||||
uint32_t smem_usr_ddr_dqs_thd : 7; /*The delay number of data strobe which from memory based on SPI_CLK.*/
|
||||
uint32_t smem_ddr_dqs_loop : 1; /*1: Use internal signal as data strobe, the strobe can not be delayed by input timing module. 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be delayed by input timing module*/
|
||||
uint32_t smem_ddr_dqs_loop_mode : 1; /*When SPI_SMEM_DDR_DQS_LOOP and SPI_SMEM_DDR_EN are set, 1: Use internal SPI_CLK as data strobe. 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not active.*/
|
||||
uint32_t reserved23 : 1; /*reserved*/
|
||||
uint32_t smem_clk_diff_en : 1; /*Set this bit to enable the differential SPI_CLK#.*/
|
||||
uint32_t smem_hyperbus_mode : 1; /*Set this bit to enable the SPI HyperBus mode.*/
|
||||
uint32_t smem_dqs_ca_in : 1; /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/
|
||||
uint32_t smem_hyperbus_dummy_2x : 1; /*Set this bit to enable the vary dummy function in SPI HyperBus mode, when SPI0 accesses to flash or SPI1 accesses flash or sram.*/
|
||||
uint32_t smem_clk_diff_inv : 1; /*Set this bit to invert SPI_DIFF when accesses to external RAM. .*/
|
||||
uint32_t smem_octa_ram_addr : 1; /*Set this bit to enable octa_ram address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, spi_usr_addr_value[3:1], 1'b0}.*/
|
||||
uint32_t smem_hyperbus_ca : 1; /*Set this bit to enable HyperRAM address out when accesses to external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, spi_usr_addr_value[3:1]}.*/
|
||||
uint32_t reserved31 : 1; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} spi_smem_ddr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_en : 1; /*Register clock gate enable signal. 1: Enable. 0: Disable.*/
|
||||
uint32_t reserved1 : 31; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} clock_gate;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_clk_sel : 2; /*When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of SPI_MEM_CORE_CLK_SEL: 0: SPI0/1 module clock (MSPI_CORE_CLK) is 80MHz. 1: MSPI_CORE_CLK is 120MHz. 2: MSPI_CORE_CLK is 160MHz. 3: MSPI_CORE_CLK is 240MHz. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of SPI_MEM_CORE_CLK_SEL: 0: MSPI_CORE_CLK is 80MHz. 1: MSPI_CORE_CLK is 80MHz. 2: MSPI_CORE_CLK 160MHz. 3: Not used. */
|
||||
uint32_t reserved2 : 30; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} core_clk_sel;
|
||||
union {
|
||||
struct {
|
||||
uint32_t per_end_en : 1; /*The enable bit for SPI_MEM_PER_END_INT interrupt.*/
|
||||
uint32_t pes_end_en : 1; /*The enable bit for SPI_MEM_PES_END_INT interrupt.*/
|
||||
uint32_t total_trans_end_en : 1; /*The enable bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt.*/
|
||||
uint32_t brown_out_en : 1; /*The enable bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
|
||||
uint32_t ecc_err_en : 1; /*The enable bit for SPI_MEM_ECC_ERR_INT interrupt.*/
|
||||
uint32_t reserved5 : 27; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t per_end_int_clr : 1; /*The clear bit for SPI_MEM_PER_END_INT interrupt.*/
|
||||
uint32_t pes_end_int_clr : 1; /*The clear bit for SPI_MEM_PES_END_INT interrupt.*/
|
||||
uint32_t total_trans_end_int_clr : 1; /*The clear bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt.*/
|
||||
uint32_t brown_out_int_clr : 1; /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
|
||||
uint32_t ecc_err_int_clr : 1; /*The clear bit for SPI_MEM_ECC_ERR_INT interrupt. SPI_MEM_ECC_ERR_ADDR and SPI_MEM_ECC_ERR_CNT will be cleared by the pulse of this bit.*/
|
||||
uint32_t reserved5 : 27; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t per_end_int_raw : 1; /*The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed successfully. 0: Others.*/
|
||||
uint32_t pes_end_int_raw : 1; /*The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended successfully. 0: Others.*/
|
||||
uint32_t total_trans_end_int_raw : 1; /*The raw bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. 1: Triggered when SPI1 transfer is done and flash is already idle. When WRSR/PP/SE/BE/CE is sent and PES/PER command is sent, this bit is set when WRSR/PP/SE/BE/CE is success. 0: Others.*/
|
||||
uint32_t brown_out_int_raw : 1; /*The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.*/
|
||||
uint32_t ecc_err_int_raw : 1; /*The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When APB_CTRL_FECC_ERR_INT_EN is set and APB_CTRL_SECC_ERR_INT_EN is cleared, this bit is triggered when the error times of SPI0/1 ECC read flash are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN is cleared and APB_CTRL_SECC_ERR_INT_EN is set, this bit is triggered when the error times of SPI0/1 ECC read external RAM are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and APB_CTRL_SECC_ERR_INT_EN are set, this bit is triggered when the total error times of SPI0/1 ECC read external RAM and flash are equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and APB_CTRL_SECC_ERR_INT_EN are cleared, this bit will not be triggered.*/
|
||||
uint32_t reserved5 : 27; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t per_end_int_st : 1; /*The status bit for SPI_MEM_PER_END_INT interrupt.*/
|
||||
uint32_t pes_end_int_st : 1; /*The status bit for SPI_MEM_PES_END_INT interrupt.*/
|
||||
uint32_t total_trans_end_int_st : 1; /*The status bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt.*/
|
||||
uint32_t brown_out_int_st : 1; /*The status bit for SPI_MEM_BROWN_OUT_INT interrupt.*/
|
||||
uint32_t ecc_err_int_st : 1; /*The status bit for SPI_MEM_ECC_ERR_INT interrupt.*/
|
||||
uint32_t reserved5 : 27; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_st;
|
||||
uint32_t reserved_100;
|
||||
uint32_t reserved_104;
|
||||
uint32_t reserved_108;
|
||||
uint32_t reserved_10c;
|
||||
uint32_t reserved_110;
|
||||
uint32_t reserved_114;
|
||||
uint32_t reserved_118;
|
||||
uint32_t reserved_11c;
|
||||
uint32_t reserved_120;
|
||||
uint32_t reserved_124;
|
||||
uint32_t reserved_128;
|
||||
uint32_t reserved_12c;
|
||||
uint32_t reserved_130;
|
||||
uint32_t reserved_134;
|
||||
uint32_t reserved_138;
|
||||
uint32_t reserved_13c;
|
||||
uint32_t reserved_140;
|
||||
uint32_t reserved_144;
|
||||
uint32_t reserved_148;
|
||||
uint32_t reserved_14c;
|
||||
uint32_t reserved_150;
|
||||
uint32_t reserved_154;
|
||||
uint32_t reserved_158;
|
||||
uint32_t reserved_15c;
|
||||
uint32_t reserved_160;
|
||||
uint32_t reserved_164;
|
||||
uint32_t reserved_168;
|
||||
uint32_t reserved_16c;
|
||||
uint32_t reserved_170;
|
||||
uint32_t reserved_174;
|
||||
uint32_t reserved_178;
|
||||
uint32_t reserved_17c;
|
||||
uint32_t reserved_180;
|
||||
uint32_t reserved_184;
|
||||
uint32_t reserved_188;
|
||||
uint32_t reserved_18c;
|
||||
uint32_t reserved_190;
|
||||
uint32_t reserved_194;
|
||||
uint32_t reserved_198;
|
||||
uint32_t reserved_19c;
|
||||
uint32_t reserved_1a0;
|
||||
uint32_t reserved_1a4;
|
||||
uint32_t reserved_1a8;
|
||||
uint32_t reserved_1ac;
|
||||
uint32_t reserved_1b0;
|
||||
uint32_t reserved_1b4;
|
||||
uint32_t reserved_1b8;
|
||||
uint32_t reserved_1bc;
|
||||
uint32_t reserved_1c0;
|
||||
uint32_t reserved_1c4;
|
||||
uint32_t reserved_1c8;
|
||||
uint32_t reserved_1cc;
|
||||
uint32_t reserved_1d0;
|
||||
uint32_t reserved_1d4;
|
||||
uint32_t reserved_1d8;
|
||||
uint32_t reserved_1dc;
|
||||
uint32_t reserved_1e0;
|
||||
uint32_t reserved_1e4;
|
||||
uint32_t reserved_1e8;
|
||||
uint32_t reserved_1ec;
|
||||
uint32_t reserved_1f0;
|
||||
uint32_t reserved_1f4;
|
||||
uint32_t reserved_1f8;
|
||||
uint32_t reserved_1fc;
|
||||
uint32_t reserved_200;
|
||||
uint32_t reserved_204;
|
||||
uint32_t reserved_208;
|
||||
uint32_t reserved_20c;
|
||||
uint32_t reserved_210;
|
||||
uint32_t reserved_214;
|
||||
uint32_t reserved_218;
|
||||
uint32_t reserved_21c;
|
||||
uint32_t reserved_220;
|
||||
uint32_t reserved_224;
|
||||
uint32_t reserved_228;
|
||||
uint32_t reserved_22c;
|
||||
uint32_t reserved_230;
|
||||
uint32_t reserved_234;
|
||||
uint32_t reserved_238;
|
||||
uint32_t reserved_23c;
|
||||
uint32_t reserved_240;
|
||||
uint32_t reserved_244;
|
||||
uint32_t reserved_248;
|
||||
uint32_t reserved_24c;
|
||||
uint32_t reserved_250;
|
||||
uint32_t reserved_254;
|
||||
uint32_t reserved_258;
|
||||
uint32_t reserved_25c;
|
||||
uint32_t reserved_260;
|
||||
uint32_t reserved_264;
|
||||
uint32_t reserved_268;
|
||||
uint32_t reserved_26c;
|
||||
uint32_t reserved_270;
|
||||
uint32_t reserved_274;
|
||||
uint32_t reserved_278;
|
||||
uint32_t reserved_27c;
|
||||
uint32_t reserved_280;
|
||||
uint32_t reserved_284;
|
||||
uint32_t reserved_288;
|
||||
uint32_t reserved_28c;
|
||||
uint32_t reserved_290;
|
||||
uint32_t reserved_294;
|
||||
uint32_t reserved_298;
|
||||
uint32_t reserved_29c;
|
||||
uint32_t reserved_2a0;
|
||||
uint32_t reserved_2a4;
|
||||
uint32_t reserved_2a8;
|
||||
uint32_t reserved_2ac;
|
||||
uint32_t reserved_2b0;
|
||||
uint32_t reserved_2b4;
|
||||
uint32_t reserved_2b8;
|
||||
uint32_t reserved_2bc;
|
||||
uint32_t reserved_2c0;
|
||||
uint32_t reserved_2c4;
|
||||
uint32_t reserved_2c8;
|
||||
uint32_t reserved_2cc;
|
||||
uint32_t reserved_2d0;
|
||||
uint32_t reserved_2d4;
|
||||
uint32_t reserved_2d8;
|
||||
uint32_t reserved_2dc;
|
||||
uint32_t reserved_2e0;
|
||||
uint32_t reserved_2e4;
|
||||
uint32_t reserved_2e8;
|
||||
uint32_t reserved_2ec;
|
||||
uint32_t reserved_2f0;
|
||||
uint32_t reserved_2f4;
|
||||
uint32_t reserved_2f8;
|
||||
uint32_t reserved_2fc;
|
||||
uint32_t reserved_300;
|
||||
uint32_t reserved_304;
|
||||
uint32_t reserved_308;
|
||||
uint32_t reserved_30c;
|
||||
uint32_t reserved_310;
|
||||
uint32_t reserved_314;
|
||||
uint32_t reserved_318;
|
||||
uint32_t reserved_31c;
|
||||
uint32_t reserved_320;
|
||||
uint32_t reserved_324;
|
||||
uint32_t reserved_328;
|
||||
uint32_t reserved_32c;
|
||||
uint32_t reserved_330;
|
||||
uint32_t reserved_334;
|
||||
uint32_t reserved_338;
|
||||
uint32_t reserved_33c;
|
||||
uint32_t reserved_340;
|
||||
uint32_t reserved_344;
|
||||
uint32_t reserved_348;
|
||||
uint32_t reserved_34c;
|
||||
uint32_t reserved_350;
|
||||
uint32_t reserved_354;
|
||||
uint32_t reserved_358;
|
||||
uint32_t reserved_35c;
|
||||
uint32_t reserved_360;
|
||||
uint32_t reserved_364;
|
||||
uint32_t reserved_368;
|
||||
uint32_t reserved_36c;
|
||||
uint32_t reserved_370;
|
||||
uint32_t reserved_374;
|
||||
uint32_t reserved_378;
|
||||
uint32_t reserved_37c;
|
||||
uint32_t reserved_380;
|
||||
uint32_t reserved_384;
|
||||
uint32_t reserved_388;
|
||||
uint32_t reserved_38c;
|
||||
uint32_t reserved_390;
|
||||
uint32_t reserved_394;
|
||||
uint32_t reserved_398;
|
||||
uint32_t reserved_39c;
|
||||
uint32_t reserved_3a0;
|
||||
uint32_t reserved_3a4;
|
||||
uint32_t reserved_3a8;
|
||||
uint32_t reserved_3ac;
|
||||
uint32_t reserved_3b0;
|
||||
uint32_t reserved_3b4;
|
||||
uint32_t reserved_3b8;
|
||||
uint32_t reserved_3bc;
|
||||
uint32_t reserved_3c0;
|
||||
uint32_t reserved_3c4;
|
||||
uint32_t reserved_3c8;
|
||||
uint32_t reserved_3cc;
|
||||
uint32_t reserved_3d0;
|
||||
uint32_t reserved_3d4;
|
||||
uint32_t reserved_3d8;
|
||||
uint32_t reserved_3dc;
|
||||
uint32_t reserved_3e0;
|
||||
uint32_t reserved_3e4;
|
||||
uint32_t reserved_3e8;
|
||||
uint32_t reserved_3ec;
|
||||
uint32_t reserved_3f0;
|
||||
uint32_t reserved_3f4;
|
||||
uint32_t reserved_3f8;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reg_smem_spiclk_fun_drv : 2; /*The driver of SPI_CLK PAD is controlled by the bits SPI_SMEM_SPICLK_FUN_DRV[1:0] when the bit SPI_SPICLK_PAD_DRV_CTL_EN is set and MSPI accesses to external RAM.*/
|
||||
uint32_t fmem_spiclk_fun_drv : 2; /*The driver of SPI_CLK PAD is controlled by the bits SPI_FMEM_SPICLK_FUN_DRV[1:0] when the bit SPI_SPICLK_PAD_DRV_CTL_EN is set and MSPI accesses to flash.*/
|
||||
uint32_t reg_spiclk_pad_drv_ctl_en : 1; /*SPI_CLK PAD driver control signal. 1: The driver of SPI_CLK PAD is controlled by the bits SPI_FMEM_SPICLK_FUN_DRV[1:0] and SPI_SMEM_SPICLK_FUN_DRV[1:0]. 0: The driver of SPI_CLK PAD is controlled by the bits IO_MUX_FUNC_DRV[1:0] of SPICLK PAD.*/
|
||||
uint32_t date : 23; /*SPI register version.*/
|
||||
uint32_t reserved28 : 4; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} date;
|
||||
} spi_mem_dev_t;
|
||||
extern spi_mem_dev_t SPIMEM0;
|
||||
extern spi_mem_dev_t SPIMEM1;
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /*_SOC_SPI_MEM_STRUCT_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,428 +0,0 @@
|
||||
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_SPI_STRUCT_H_
|
||||
#define _SOC_SPI_STRUCT_H_
|
||||
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct spi_dev_s {
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf_bitlen : 18; /*Define the APB cycles of SPI_CONF state. Can be configured in CONF state.*/
|
||||
uint32_t reserved18 : 5; /*reserved*/
|
||||
uint32_t update : 1; /*Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode.*/
|
||||
uint32_t usr : 1; /*User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf.*/
|
||||
uint32_t reserved25 : 7; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} cmd;
|
||||
uint32_t addr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 3; /*reserved*/
|
||||
uint32_t dummy_out : 1; /*0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase, the FSPI bus signals are output. Can be configured in CONF state.*/
|
||||
uint32_t reserved4 : 1; /*reserved*/
|
||||
uint32_t faddr_dual : 1; /*Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/
|
||||
uint32_t faddr_quad : 1; /*Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/
|
||||
uint32_t faddr_oct : 1; /*Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/
|
||||
uint32_t fcmd_dual : 1; /*Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/
|
||||
uint32_t fcmd_quad : 1; /*Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/
|
||||
uint32_t fcmd_oct : 1; /*Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/
|
||||
uint32_t reserved11 : 3; /*reserved*/
|
||||
uint32_t fread_dual : 1; /*In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.*/
|
||||
uint32_t fread_quad : 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state.*/
|
||||
uint32_t fread_oct : 1; /*In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state.*/
|
||||
uint32_t reserved17 : 1; /*reserved*/
|
||||
uint32_t q_pol : 1; /*The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state.*/
|
||||
uint32_t d_pol : 1; /*The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.*/
|
||||
uint32_t hold_pol : 1; /*SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.*/
|
||||
uint32_t wp_pol : 1; /*Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.*/
|
||||
uint32_t reserved22 : 1; /*reserved*/
|
||||
uint32_t rd_bit_order : 2; /*In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.*/
|
||||
uint32_t wr_bit_order : 2; /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.*/
|
||||
uint32_t reserved27 : 5; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clkcnt_l : 6; /*In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state.*/
|
||||
uint32_t clkcnt_h : 6; /*In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state.*/
|
||||
uint32_t clkcnt_n : 6; /*In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.*/
|
||||
uint32_t clkdiv_pre : 4; /*In the master mode it is pre-divider of spi_clk. Can be configured in CONF state.*/
|
||||
uint32_t reserved22 : 9; /*reserved*/
|
||||
uint32_t clk_equ_sysclk : 1; /*In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} clock;
|
||||
union {
|
||||
struct {
|
||||
uint32_t doutdin : 1; /*Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state.*/
|
||||
uint32_t reserved1 : 2; /*reserved*/
|
||||
uint32_t qpi_mode : 1; /*Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.*/
|
||||
uint32_t opi_mode : 1; /*Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state.*/
|
||||
uint32_t tsck_i_edge : 1; /*In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.*/
|
||||
uint32_t cs_hold : 1; /*spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state.*/
|
||||
uint32_t cs_setup : 1; /*spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state.*/
|
||||
uint32_t rsck_i_edge : 1; /*In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.*/
|
||||
uint32_t ck_out_edge : 1; /*the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state.*/
|
||||
uint32_t reserved10 : 2; /*reserved*/
|
||||
uint32_t fwrite_dual : 1; /*In the write operations read-data phase apply 2 signals. Can be configured in CONF state.*/
|
||||
uint32_t fwrite_quad : 1; /*In the write operations read-data phase apply 4 signals. Can be configured in CONF state.*/
|
||||
uint32_t fwrite_oct : 1; /*In the write operations read-data phase apply 8 signals. Can be configured in CONF state.*/
|
||||
uint32_t usr_conf_nxt : 1; /*1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.*/
|
||||
uint32_t reserved16 : 1; /*reserved*/
|
||||
uint32_t sio : 1; /*Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.*/
|
||||
uint32_t reserved18 : 6; /*reserved*/
|
||||
uint32_t usr_miso_highpart : 1; /*read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.*/
|
||||
uint32_t usr_mosi_highpart : 1; /*write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.*/
|
||||
uint32_t usr_dummy_idle : 1; /*spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state.*/
|
||||
uint32_t usr_mosi : 1; /*This bit enable the write-data phase of an operation. Can be configured in CONF state.*/
|
||||
uint32_t usr_miso : 1; /*This bit enable the read-data phase of an operation. Can be configured in CONF state.*/
|
||||
uint32_t usr_dummy : 1; /*This bit enable the dummy phase of an operation. Can be configured in CONF state.*/
|
||||
uint32_t usr_addr : 1; /*This bit enable the address phase of an operation. Can be configured in CONF state.*/
|
||||
uint32_t usr_command : 1; /*This bit enable the command phase of an operation. Can be configured in CONF state.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} user;
|
||||
union {
|
||||
struct {
|
||||
uint32_t usr_dummy_cyclelen : 8; /*The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state.*/
|
||||
uint32_t reserved8 : 8; /*reserved*/
|
||||
uint32_t mst_wfull_err_end_en : 1; /*1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode.*/
|
||||
uint32_t cs_setup_time : 5; /*(cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state.*/
|
||||
uint32_t cs_hold_time : 5; /*delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state.*/
|
||||
uint32_t usr_addr_bitlen : 5; /*The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} user1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t usr_command_value : 16; /*The value of command. Can be configured in CONF state.*/
|
||||
uint32_t reserved16 : 11; /*reserved*/
|
||||
uint32_t mst_rempty_err_end_en : 1; /*1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode.*/
|
||||
uint32_t usr_command_bitlen : 4; /*The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} user2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t ms_data_bitlen : 18; /*The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state.*/
|
||||
uint32_t reserved18 : 14; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} ms_dlen;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cs0_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
|
||||
uint32_t cs1_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
|
||||
uint32_t cs2_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
|
||||
uint32_t cs3_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
|
||||
uint32_t cs4_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
|
||||
uint32_t cs5_dis : 1; /*SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/
|
||||
uint32_t ck_dis : 1; /*1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state.*/
|
||||
uint32_t master_cs_pol : 6; /*In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.*/
|
||||
uint32_t reserved13 : 3; /*reserved*/
|
||||
uint32_t clk_data_dtr_en : 1; /*1: SPI master DTR mode is applied to SPI clk, data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19. */
|
||||
uint32_t data_dtr_en : 1; /*1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state.*/
|
||||
uint32_t addr_dtr_en : 1; /*1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state.*/
|
||||
uint32_t cmd_dtr_en : 1; /*1: SPI clk and data of SPI_SEND_CMD state are in DTR mode, including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state.*/
|
||||
uint32_t reserved20 : 3; /*reserved*/
|
||||
uint32_t slave_cs_pol : 1; /*spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state.*/
|
||||
uint32_t dqs_idle_edge : 1; /*The default value of spi_dqs. Can be configured in CONF state.*/
|
||||
uint32_t reserved25 : 4; /*reserved*/
|
||||
uint32_t ck_idle_edge : 1; /*1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state.*/
|
||||
uint32_t cs_keep_active : 1; /*spi cs line keep low when the bit is set. Can be configured in CONF state.*/
|
||||
uint32_t quad_din_pin_swap : 1; /*1: SPI quad input swap enable, swap FSPID with FSPIQ, swap FSPIWP with FSPIHD. 0: spi quad input swap disable. Can be configured in CONF state.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} misc;
|
||||
union {
|
||||
struct {
|
||||
uint32_t din0_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
|
||||
uint32_t din1_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
|
||||
uint32_t din2_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
|
||||
uint32_t din3_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
|
||||
uint32_t din4_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
|
||||
uint32_t din5_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
|
||||
uint32_t din6_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
|
||||
uint32_t din7_mode : 2; /*the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.*/
|
||||
uint32_t timing_hclk_active : 1; /*1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state.*/
|
||||
uint32_t reserved17 : 15; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} din_mode;
|
||||
union {
|
||||
struct {
|
||||
uint32_t din0_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/
|
||||
uint32_t din1_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/
|
||||
uint32_t din2_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/
|
||||
uint32_t din3_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/
|
||||
uint32_t din4_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/
|
||||
uint32_t din5_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/
|
||||
uint32_t din6_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/
|
||||
uint32_t din7_num : 2; /*the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.*/
|
||||
uint32_t reserved16 : 16; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} din_num;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dout0_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
|
||||
uint32_t dout1_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
|
||||
uint32_t dout2_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
|
||||
uint32_t dout3_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
|
||||
uint32_t dout4_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
|
||||
uint32_t dout5_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
|
||||
uint32_t dout6_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
|
||||
uint32_t dout7_mode : 1; /*The output signal $n is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
|
||||
uint32_t d_dqs_mode : 1; /*The output signal SPI_DQS is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/
|
||||
uint32_t reserved9 : 23; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} dout_mode;
|
||||
union {
|
||||
struct {
|
||||
uint32_t outfifo_empty : 1; /*Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data.*/
|
||||
uint32_t infifo_full : 1; /*Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data.*/
|
||||
uint32_t reserved2 : 16; /*reserved*/
|
||||
uint32_t dma_seg_trans_en : 1; /*Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.*/
|
||||
uint32_t rx_seg_trans_clr_en : 1; /*1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.*/
|
||||
uint32_t tx_seg_trans_clr_en : 1; /*1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.*/
|
||||
uint32_t rx_eof_en : 1; /*1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.*/
|
||||
uint32_t reserved22 : 5; /*reserved*/
|
||||
uint32_t dma_rx_ena : 1; /*Set this bit to enable SPI DMA controlled receive data mode.*/
|
||||
uint32_t dma_tx_ena : 1; /*Set this bit to enable SPI DMA controlled send data mode.*/
|
||||
uint32_t rx_afifo_rst : 1; /*Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer.*/
|
||||
uint32_t buf_afifo_rst : 1; /*Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer.*/
|
||||
uint32_t dma_afifo_rst : 1; /*Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} dma_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t infifo_full_err : 1; /*The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/
|
||||
uint32_t outfifo_empty_err : 1; /*The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/
|
||||
uint32_t ex_qpi : 1; /*The enable bit for SPI slave Ex_QPI interrupt.*/
|
||||
uint32_t en_qpi : 1; /*The enable bit for SPI slave En_QPI interrupt.*/
|
||||
uint32_t cmd7 : 1; /*The enable bit for SPI slave CMD7 interrupt.*/
|
||||
uint32_t cmd8 : 1; /*The enable bit for SPI slave CMD8 interrupt.*/
|
||||
uint32_t cmd9 : 1; /*The enable bit for SPI slave CMD9 interrupt.*/
|
||||
uint32_t cmda : 1; /*The enable bit for SPI slave CMDA interrupt.*/
|
||||
uint32_t rd_dma_done : 1; /*The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/
|
||||
uint32_t wr_dma_done : 1; /*The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/
|
||||
uint32_t rd_buf_done : 1; /*The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/
|
||||
uint32_t wr_buf_done : 1; /*The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
|
||||
uint32_t trans_done : 1; /*The enable bit for SPI_TRANS_DONE_INT interrupt.*/
|
||||
uint32_t dma_seg_trans_done : 1; /*The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/
|
||||
uint32_t seg_magic_err : 1; /*The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
|
||||
uint32_t buf_addr_err : 1; /*The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
|
||||
uint32_t cmd_err : 1; /*The enable bit for SPI_SLV_CMD_ERR_INT interrupt.*/
|
||||
uint32_t mst_rx_afifo_wfull_err : 1; /*The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
|
||||
uint32_t mst_tx_afifo_rempty_err : 1; /*The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
|
||||
uint32_t app2 : 1; /*The enable bit for SPI_APP2_INT interrupt.*/
|
||||
uint32_t app1 : 1; /*The enable bit for SPI_APP1_INT interrupt.*/
|
||||
uint32_t reserved21 : 11; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} dma_int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t infifo_full_err : 1; /*The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/
|
||||
uint32_t outfifo_empty_err : 1; /*The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/
|
||||
uint32_t ex_qpi : 1; /*The clear bit for SPI slave Ex_QPI interrupt.*/
|
||||
uint32_t en_qpi : 1; /*The clear bit for SPI slave En_QPI interrupt.*/
|
||||
uint32_t cmd7 : 1; /*The clear bit for SPI slave CMD7 interrupt.*/
|
||||
uint32_t cmd8 : 1; /*The clear bit for SPI slave CMD8 interrupt.*/
|
||||
uint32_t cmd9 : 1; /*The clear bit for SPI slave CMD9 interrupt.*/
|
||||
uint32_t cmda : 1; /*The clear bit for SPI slave CMDA interrupt.*/
|
||||
uint32_t rd_dma_done : 1; /*The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/
|
||||
uint32_t wr_dma_done : 1; /*The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/
|
||||
uint32_t rd_buf_done : 1; /*The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/
|
||||
uint32_t wr_buf_done : 1; /*The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
|
||||
uint32_t trans_done : 1; /*The clear bit for SPI_TRANS_DONE_INT interrupt.*/
|
||||
uint32_t dma_seg_trans_done : 1; /*The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/
|
||||
uint32_t seg_magic_err : 1; /*The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
|
||||
uint32_t buf_addr_err : 1; /*The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
|
||||
uint32_t cmd_err : 1; /*The clear bit for SPI_SLV_CMD_ERR_INT interrupt.*/
|
||||
uint32_t mst_rx_afifo_wfull_err : 1; /*The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
|
||||
uint32_t mst_tx_afifo_rempty_err : 1; /*The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
|
||||
uint32_t app2 : 1; /*The clear bit for SPI_APP2_INT interrupt.*/
|
||||
uint32_t app1 : 1; /*The clear bit for SPI_APP1_INT interrupt.*/
|
||||
uint32_t reserved21 : 11; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} dma_int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t infifo_full_err : 1; /*1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others. */
|
||||
uint32_t outfifo_empty_err : 1; /*1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others. */
|
||||
uint32_t ex_qpi : 1; /*The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others.*/
|
||||
uint32_t en_qpi : 1; /*The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others.*/
|
||||
uint32_t cmd7 : 1; /*The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others.*/
|
||||
uint32_t cmd8 : 1; /*The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others.*/
|
||||
uint32_t cmd9 : 1; /*The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others.*/
|
||||
uint32_t cmda : 1; /*The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others.*/
|
||||
uint32_t rd_dma_done : 1; /*The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others.*/
|
||||
uint32_t wr_dma_done : 1; /*The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others.*/
|
||||
uint32_t rd_buf_done : 1; /*The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others.*/
|
||||
uint32_t wr_buf_done : 1; /*The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others.*/
|
||||
uint32_t trans_done : 1; /*The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others.*/
|
||||
uint32_t dma_seg_trans_done : 1; /*The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred. */
|
||||
uint32_t seg_magic_err : 1; /*The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others.*/
|
||||
uint32_t buf_addr_err : 1; /*The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others.*/
|
||||
uint32_t cmd_err : 1; /*The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others.*/
|
||||
uint32_t mst_rx_afifo_wfull_err : 1; /*The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others.*/
|
||||
uint32_t mst_tx_afifo_rempty_err : 1; /*The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others.*/
|
||||
uint32_t app2 : 1; /*The raw bit for SPI_APP2_INT interrupt. The value is only controlled by software.*/
|
||||
uint32_t app1 : 1; /*The raw bit for SPI_APP1_INT interrupt. The value is only controlled by software.*/
|
||||
uint32_t reserved21 : 11; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} dma_int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t infifo_full_err : 1; /*The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/
|
||||
uint32_t outfifo_empty_err : 1; /*The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/
|
||||
uint32_t ex_qpi : 1; /*The status bit for SPI slave Ex_QPI interrupt.*/
|
||||
uint32_t en_qpi : 1; /*The status bit for SPI slave En_QPI interrupt.*/
|
||||
uint32_t cmd7 : 1; /*The status bit for SPI slave CMD7 interrupt.*/
|
||||
uint32_t cmd8 : 1; /*The status bit for SPI slave CMD8 interrupt.*/
|
||||
uint32_t cmd9 : 1; /*The status bit for SPI slave CMD9 interrupt.*/
|
||||
uint32_t cmda : 1; /*The status bit for SPI slave CMDA interrupt.*/
|
||||
uint32_t rd_dma_done : 1; /*The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/
|
||||
uint32_t wr_dma_done : 1; /*The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/
|
||||
uint32_t rd_buf_done : 1; /*The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/
|
||||
uint32_t wr_buf_done : 1; /*The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
|
||||
uint32_t trans_done : 1; /*The status bit for SPI_TRANS_DONE_INT interrupt.*/
|
||||
uint32_t dma_seg_trans_done : 1; /*The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/
|
||||
uint32_t seg_magic_err : 1; /*The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
|
||||
uint32_t buf_addr_err : 1; /*The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
|
||||
uint32_t cmd_err : 1; /*The status bit for SPI_SLV_CMD_ERR_INT interrupt.*/
|
||||
uint32_t mst_rx_afifo_wfull_err : 1; /*The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
|
||||
uint32_t mst_tx_afifo_rempty_err : 1; /*The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
|
||||
uint32_t app2 : 1; /*The status bit for SPI_APP2_INT interrupt.*/
|
||||
uint32_t app1 : 1; /*The status bit for SPI_APP1_INT interrupt.*/
|
||||
uint32_t reserved21 : 11; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} dma_int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t infifo_full_err_int_set : 1; /*The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/
|
||||
uint32_t outfifo_empty_err_int_set : 1; /*The software set bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/
|
||||
uint32_t ex_qpi_int_set : 1; /*The software set bit for SPI slave Ex_QPI interrupt.*/
|
||||
uint32_t en_qpi_int_set : 1; /*The software set bit for SPI slave En_QPI interrupt.*/
|
||||
uint32_t cmd7_int_set : 1; /*The software set bit for SPI slave CMD7 interrupt.*/
|
||||
uint32_t cmd8_int_set : 1; /*The software set bit for SPI slave CMD8 interrupt.*/
|
||||
uint32_t cmd9_int_set : 1; /*The software set bit for SPI slave CMD9 interrupt.*/
|
||||
uint32_t cmda_int_set : 1; /*The software set bit for SPI slave CMDA interrupt.*/
|
||||
uint32_t rd_dma_done_int_set : 1; /*The software set bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/
|
||||
uint32_t wr_dma_done_int_set : 1; /*The software set bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/
|
||||
uint32_t rd_buf_done_int_set : 1; /*The software set bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/
|
||||
uint32_t wr_buf_done_int_set : 1; /*The software set bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/
|
||||
uint32_t trans_done_int_set : 1; /*The software set bit for SPI_TRANS_DONE_INT interrupt.*/
|
||||
uint32_t dma_seg_trans_done_int_set : 1; /*The software set bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/
|
||||
uint32_t seg_magic_err_int_set : 1; /*The software set bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/
|
||||
uint32_t buf_addr_err_int_set : 1; /*The software set bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/
|
||||
uint32_t cmd_err_int_set : 1; /*The software set bit for SPI_SLV_CMD_ERR_INT interrupt.*/
|
||||
uint32_t mst_rx_afifo_wfull_err_int_set: 1; /*The software set bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.*/
|
||||
uint32_t mst_tx_afifo_rempty_err_int_set: 1; /*The software set bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.*/
|
||||
uint32_t app2_int_set : 1; /*The software set bit for SPI_APP2_INT interrupt.*/
|
||||
uint32_t app1_int_set : 1; /*The software set bit for SPI_APP1_INT interrupt.*/
|
||||
uint32_t reserved21 : 11; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} dma_int_set;
|
||||
uint32_t reserved_48;
|
||||
uint32_t reserved_4c;
|
||||
uint32_t reserved_50;
|
||||
uint32_t reserved_54;
|
||||
uint32_t reserved_58;
|
||||
uint32_t reserved_5c;
|
||||
uint32_t reserved_60;
|
||||
uint32_t reserved_64;
|
||||
uint32_t reserved_68;
|
||||
uint32_t reserved_6c;
|
||||
uint32_t reserved_70;
|
||||
uint32_t reserved_74;
|
||||
uint32_t reserved_78;
|
||||
uint32_t reserved_7c;
|
||||
uint32_t reserved_80;
|
||||
uint32_t reserved_84;
|
||||
uint32_t reserved_88;
|
||||
uint32_t reserved_8c;
|
||||
uint32_t reserved_90;
|
||||
uint32_t reserved_94;
|
||||
uint32_t data_buf[16]; /*SPI CPU-controlled buffer0*/
|
||||
uint32_t reserved_d8;
|
||||
uint32_t reserved_dc;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.*/
|
||||
uint32_t clk_mode_13 : 1; /*{CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].*/
|
||||
uint32_t rsck_data_out : 1; /*It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge */
|
||||
uint32_t reserved4 : 4; /*reserved*/
|
||||
uint32_t rddma_bitlen_en : 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others*/
|
||||
uint32_t wrdma_bitlen_en : 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others*/
|
||||
uint32_t rdbuf_bitlen_en : 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others*/
|
||||
uint32_t wrbuf_bitlen_en : 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others*/
|
||||
uint32_t reserved12 : 10; /*reserved*/
|
||||
uint32_t dma_seg_magic_value : 4; /*The magic value of BM table in master DMA seg-trans.*/
|
||||
uint32_t slave_mode : 1; /*Set SPI work mode. 1: slave mode 0: master mode.*/
|
||||
uint32_t soft_reset : 1; /*Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state.*/
|
||||
uint32_t usr_conf : 1; /*1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode.*/
|
||||
uint32_t reserved29 : 3; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} slave;
|
||||
union {
|
||||
struct {
|
||||
uint32_t data_bitlen : 18; /*The transferred data bit length in SPI slave FD and HD mode. */
|
||||
uint32_t last_command : 8; /*In the slave mode it is the value of command.*/
|
||||
uint32_t last_addr : 6; /*In the slave mode it is the value of address.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} slave1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_en : 1; /*Set this bit to enable clk gate*/
|
||||
uint32_t mst_clk_active : 1; /*Set this bit to power on the SPI module clock.*/
|
||||
uint32_t mst_clk_sel : 1; /*This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK.*/
|
||||
uint32_t reserved3 : 29; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} clk_gate;
|
||||
uint32_t reserved_ec;
|
||||
union {
|
||||
struct {
|
||||
uint32_t date : 28; /*SPI register version.*/
|
||||
uint32_t reserved28 : 4; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} date;
|
||||
} spi_dev_t;
|
||||
extern spi_dev_t GPSPI2;
|
||||
extern spi_dev_t GPSPI3;
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /*_SOC_SPI_STRUCT_H_ */
|
||||
@@ -1,720 +0,0 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#ifndef _SOC_SYSCON_REG_H_
|
||||
#define _SOC_SYSCON_REG_H_
|
||||
|
||||
|
||||
#include "soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define SYSCON_SYSCLK_CONF_REG (DR_REG_SYSCON_BASE + 0x0)
|
||||
/* SYSCON_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_RST_TICK_CNT (BIT(12))
|
||||
#define SYSCON_RST_TICK_CNT_M (BIT(12))
|
||||
#define SYSCON_RST_TICK_CNT_V 0x1
|
||||
#define SYSCON_RST_TICK_CNT_S 12
|
||||
/* SYSCON_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_CLK_EN (BIT(11))
|
||||
#define SYSCON_CLK_EN_M (BIT(11))
|
||||
#define SYSCON_CLK_EN_V 0x1
|
||||
#define SYSCON_CLK_EN_S 11
|
||||
/* SYSCON_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_CLK_320M_EN (BIT(10))
|
||||
#define SYSCON_CLK_320M_EN_M (BIT(10))
|
||||
#define SYSCON_CLK_320M_EN_V 0x1
|
||||
#define SYSCON_CLK_320M_EN_S 10
|
||||
/* SYSCON_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_PRE_DIV_CNT 0x000003FF
|
||||
#define SYSCON_PRE_DIV_CNT_M ((SYSCON_PRE_DIV_CNT_V)<<(SYSCON_PRE_DIV_CNT_S))
|
||||
#define SYSCON_PRE_DIV_CNT_V 0x3FF
|
||||
#define SYSCON_PRE_DIV_CNT_S 0
|
||||
|
||||
#define SYSCON_TICK_CONF_REG (DR_REG_SYSCON_BASE + 0x4)
|
||||
/* SYSCON_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_TICK_ENABLE (BIT(16))
|
||||
#define SYSCON_TICK_ENABLE_M (BIT(16))
|
||||
#define SYSCON_TICK_ENABLE_V 0x1
|
||||
#define SYSCON_TICK_ENABLE_S 16
|
||||
/* SYSCON_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_CK8M_TICK_NUM 0x000000FF
|
||||
#define SYSCON_CK8M_TICK_NUM_M ((SYSCON_CK8M_TICK_NUM_V)<<(SYSCON_CK8M_TICK_NUM_S))
|
||||
#define SYSCON_CK8M_TICK_NUM_V 0xFF
|
||||
#define SYSCON_CK8M_TICK_NUM_S 8
|
||||
/* SYSCON_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_XTAL_TICK_NUM 0x000000FF
|
||||
#define SYSCON_XTAL_TICK_NUM_M ((SYSCON_XTAL_TICK_NUM_V)<<(SYSCON_XTAL_TICK_NUM_S))
|
||||
#define SYSCON_XTAL_TICK_NUM_V 0xFF
|
||||
#define SYSCON_XTAL_TICK_NUM_S 0
|
||||
|
||||
#define SYSCON_CLK_OUT_EN_REG (DR_REG_SYSCON_BASE + 0x8)
|
||||
/* SYSCON_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_CLK_XTAL_OEN (BIT(10))
|
||||
#define SYSCON_CLK_XTAL_OEN_M (BIT(10))
|
||||
#define SYSCON_CLK_XTAL_OEN_V 0x1
|
||||
#define SYSCON_CLK_XTAL_OEN_S 10
|
||||
/* SYSCON_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_CLK40X_BB_OEN (BIT(9))
|
||||
#define SYSCON_CLK40X_BB_OEN_M (BIT(9))
|
||||
#define SYSCON_CLK40X_BB_OEN_V 0x1
|
||||
#define SYSCON_CLK40X_BB_OEN_S 9
|
||||
/* SYSCON_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_CLK_DAC_CPU_OEN (BIT(8))
|
||||
#define SYSCON_CLK_DAC_CPU_OEN_M (BIT(8))
|
||||
#define SYSCON_CLK_DAC_CPU_OEN_V 0x1
|
||||
#define SYSCON_CLK_DAC_CPU_OEN_S 8
|
||||
/* SYSCON_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_CLK_ADC_INF_OEN (BIT(7))
|
||||
#define SYSCON_CLK_ADC_INF_OEN_M (BIT(7))
|
||||
#define SYSCON_CLK_ADC_INF_OEN_V 0x1
|
||||
#define SYSCON_CLK_ADC_INF_OEN_S 7
|
||||
/* SYSCON_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_CLK_320M_OEN (BIT(6))
|
||||
#define SYSCON_CLK_320M_OEN_M (BIT(6))
|
||||
#define SYSCON_CLK_320M_OEN_V 0x1
|
||||
#define SYSCON_CLK_320M_OEN_S 6
|
||||
/* SYSCON_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_CLK160_OEN (BIT(5))
|
||||
#define SYSCON_CLK160_OEN_M (BIT(5))
|
||||
#define SYSCON_CLK160_OEN_V 0x1
|
||||
#define SYSCON_CLK160_OEN_S 5
|
||||
/* SYSCON_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_CLK80_OEN (BIT(4))
|
||||
#define SYSCON_CLK80_OEN_M (BIT(4))
|
||||
#define SYSCON_CLK80_OEN_V 0x1
|
||||
#define SYSCON_CLK80_OEN_S 4
|
||||
/* SYSCON_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_CLK_BB_OEN (BIT(3))
|
||||
#define SYSCON_CLK_BB_OEN_M (BIT(3))
|
||||
#define SYSCON_CLK_BB_OEN_V 0x1
|
||||
#define SYSCON_CLK_BB_OEN_S 3
|
||||
/* SYSCON_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_CLK44_OEN (BIT(2))
|
||||
#define SYSCON_CLK44_OEN_M (BIT(2))
|
||||
#define SYSCON_CLK44_OEN_V 0x1
|
||||
#define SYSCON_CLK44_OEN_S 2
|
||||
/* SYSCON_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_CLK22_OEN (BIT(1))
|
||||
#define SYSCON_CLK22_OEN_M (BIT(1))
|
||||
#define SYSCON_CLK22_OEN_V 0x1
|
||||
#define SYSCON_CLK22_OEN_S 1
|
||||
/* SYSCON_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_CLK20_OEN (BIT(0))
|
||||
#define SYSCON_CLK20_OEN_M (BIT(0))
|
||||
#define SYSCON_CLK20_OEN_V 0x1
|
||||
#define SYSCON_CLK20_OEN_S 0
|
||||
|
||||
#define SYSCON_WIFI_BB_CFG_REG (DR_REG_SYSCON_BASE + 0xC)
|
||||
/* SYSCON_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_WIFI_BB_CFG 0xFFFFFFFF
|
||||
#define SYSCON_WIFI_BB_CFG_M ((SYSCON_WIFI_BB_CFG_V)<<(SYSCON_WIFI_BB_CFG_S))
|
||||
#define SYSCON_WIFI_BB_CFG_V 0xFFFFFFFF
|
||||
#define SYSCON_WIFI_BB_CFG_S 0
|
||||
|
||||
#define SYSCON_WIFI_BB_CFG_2_REG (DR_REG_SYSCON_BASE + 0x10)
|
||||
/* SYSCON_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_WIFI_BB_CFG_2 0xFFFFFFFF
|
||||
#define SYSCON_WIFI_BB_CFG_2_M ((SYSCON_WIFI_BB_CFG_2_V)<<(SYSCON_WIFI_BB_CFG_2_S))
|
||||
#define SYSCON_WIFI_BB_CFG_2_V 0xFFFFFFFF
|
||||
#define SYSCON_WIFI_BB_CFG_2_S 0
|
||||
|
||||
#define SYSCON_WIFI_CLK_EN_REG (DR_REG_SYSCON_BASE + 0x14)
|
||||
/* SYSCON_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_WIFI_CLK_EN 0xFFFFFFFF
|
||||
#define SYSCON_WIFI_CLK_EN_M ((SYSCON_WIFI_CLK_EN_V)<<(SYSCON_WIFI_CLK_EN_S))
|
||||
#define SYSCON_WIFI_CLK_EN_V 0xFFFFFFFF
|
||||
#define SYSCON_WIFI_CLK_EN_S 0
|
||||
|
||||
#define SYSCON_WIFI_RST_EN_REG (DR_REG_SYSCON_BASE + 0x18)
|
||||
/* SYSCON_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_WIFI_RST 0xFFFFFFFF
|
||||
#define SYSCON_WIFI_RST_M ((SYSCON_WIFI_RST_V)<<(SYSCON_WIFI_RST_S))
|
||||
#define SYSCON_WIFI_RST_V 0xFFFFFFFF
|
||||
#define SYSCON_WIFI_RST_S 0
|
||||
|
||||
#define SYSTEM_WIFI_CLK_EN_REG SYSCON_WIFI_CLK_EN_REG
|
||||
/* SYSTEM_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
|
||||
/*description: */
|
||||
#define SYSTEM_WIFI_CLK_EN 0x00FB9FCF
|
||||
#define SYSTEM_WIFI_CLK_EN_M ((SYSTEM_WIFI_CLK_EN_V) << (SYSTEM_WIFI_CLK_EN_S))
|
||||
#define SYSTEM_WIFI_CLK_EN_V 0x00FB9FCF
|
||||
#define SYSTEM_WIFI_CLK_EN_S 0
|
||||
|
||||
/* Mask for all Wifi clock bits, 6 */
|
||||
#define SYSTEM_WIFI_CLK_WIFI_EN 0x0
|
||||
#define SYSTEM_WIFI_CLK_WIFI_EN_M ((SYSTEM_WIFI_CLK_WIFI_EN_V)<<(SYSTEM_WIFI_CLK_WIFI_EN_S))
|
||||
#define SYSTEM_WIFI_CLK_WIFI_EN_V 0x0
|
||||
#define SYSTEM_WIFI_CLK_WIFI_EN_S 0
|
||||
/* Mask for all Bluetooth clock bits, 11, 16, 17 */
|
||||
#define SYSTEM_WIFI_CLK_BT_EN 0x0
|
||||
#define SYSTEM_WIFI_CLK_BT_EN_M ((SYSTEM_WIFI_CLK_BT_EN_V)<<(SYSTEM_WIFI_CLK_BT_EN_S))
|
||||
#define SYSTEM_WIFI_CLK_BT_EN_V 0x0
|
||||
#define SYSTEM_WIFI_CLK_BT_EN_S 0
|
||||
/* Mask for clock bits used by both WIFI and Bluetooth, 0, 1, 2, 3, 7, 8, 9, 10, 19, 20, 21, 22, 23 */
|
||||
#define SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M 0x78078F
|
||||
|
||||
//bluetooth baseband bit11
|
||||
#define SYSTEM_BT_BASEBAND_EN BIT(11)
|
||||
//bluetooth LC bit16 and bit17
|
||||
#define SYSTEM_BT_LC_EN (BIT(16) | BIT(17))
|
||||
|
||||
/* Remaining single bit clock masks */
|
||||
#define SYSTEM_WIFI_CLK_I2C_CLK_EN BIT(5)
|
||||
#define SYSTEM_WIFI_CLK_UNUSED_BIT12 BIT(12)
|
||||
#define SYSTEM_WIFI_CLK_SDIO_HOST_EN BIT(13)
|
||||
#define SYSTEM_WIFI_CLK_EMAC_EN BIT(14)
|
||||
#define SYSTEM_WIFI_CLK_RNG_EN BIT(15)
|
||||
|
||||
#define SYSTEM_CORE_RST_EN_REG SYSTEM_WIFI_RST_EN_REG
|
||||
#define SYSTEM_WIFI_RST_EN_REG SYSCON_WIFI_RST_EN_REG
|
||||
/* SYSTEM_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: */
|
||||
#define SYSTEM_WIFI_RST 0xFFFFFFFF
|
||||
#define SYSTEM_WIFI_RST_M ((SYSTEM_WIFI_RST_V) << (SYSTEM_WIFI_RST_S))
|
||||
#define SYSTEM_WIFI_RST_V 0xFFFFFFFF
|
||||
#define SYSTEM_WIFI_RST_S 0
|
||||
|
||||
#define SYSTEM_WIFIBB_RST BIT(0)
|
||||
#define SYSTEM_FE_RST BIT(1)
|
||||
#define SYSTEM_WIFIMAC_RST BIT(2)
|
||||
#define SYSTEM_BTBB_RST BIT(3) /* Bluetooth Baseband */
|
||||
#define SYSTEM_BTMAC_RST BIT(4) /* deprecated */
|
||||
#define SYSTEM_SDIO_RST BIT(5)
|
||||
#define SYSTEM_EMAC_RST BIT(7)
|
||||
#define SYSTEM_MACPWR_RST BIT(8)
|
||||
#define SYSTEM_RW_BTMAC_RST BIT(9) /* Bluetooth MAC */
|
||||
#define SYSTEM_RW_BTLP_RST BIT(10) /* Bluetooth Low Power Module */
|
||||
#define SYSTEM_RW_BTMAC_REG_RST BIT(11) /* Bluetooth MAC Regsiters */
|
||||
#define SYSTEM_RW_BTLP_REG_RST BIT(12) /* Bluetooth Low Power Registers */
|
||||
#define SYSTEM_BTBB_REG_RST BIT(13) /* Bluetooth Baseband Registers */
|
||||
|
||||
#define MODEM_RESET_FIELD_WHEN_PU (SYSTEM_WIFIBB_RST | \
|
||||
SYSTEM_FE_RST | \
|
||||
SYSTEM_WIFIMAC_RST | \
|
||||
SYSTEM_BTBB_RST | \
|
||||
SYSTEM_BTMAC_RST | \
|
||||
SYSTEM_RW_BTMAC_RST | \
|
||||
SYSTEM_RW_BTMAC_REG_RST | \
|
||||
SYSTEM_BTBB_REG_RST)
|
||||
|
||||
#define SYSCON_HOST_INF_SEL_REG (DR_REG_SYSCON_BASE + 0x1C)
|
||||
/* SYSCON_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_PERI_IO_SWAP 0x000000FF
|
||||
#define SYSCON_PERI_IO_SWAP_M ((SYSCON_PERI_IO_SWAP_V)<<(SYSCON_PERI_IO_SWAP_S))
|
||||
#define SYSCON_PERI_IO_SWAP_V 0xFF
|
||||
#define SYSCON_PERI_IO_SWAP_S 0
|
||||
|
||||
#define SYSCON_EXT_MEM_PMS_LOCK_REG (DR_REG_SYSCON_BASE + 0x20)
|
||||
/* SYSCON_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_EXT_MEM_PMS_LOCK (BIT(0))
|
||||
#define SYSCON_EXT_MEM_PMS_LOCK_M (BIT(0))
|
||||
#define SYSCON_EXT_MEM_PMS_LOCK_V 0x1
|
||||
#define SYSCON_EXT_MEM_PMS_LOCK_S 0
|
||||
|
||||
#define SYSCON_EXT_MEM_WRITEBACK_BYPASS_REG (DR_REG_SYSCON_BASE + 0x24)
|
||||
/* SYSCON_WRITEBACK_BYPASS : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: Set 1 to bypass cache writeback request to external memory so that spi will not
|
||||
check its attribute..*/
|
||||
#define SYSCON_WRITEBACK_BYPASS (BIT(0))
|
||||
#define SYSCON_WRITEBACK_BYPASS_M (BIT(0))
|
||||
#define SYSCON_WRITEBACK_BYPASS_V 0x1
|
||||
#define SYSCON_WRITEBACK_BYPASS_S 0
|
||||
|
||||
#define SYSCON_FLASH_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x28)
|
||||
/* SYSCON_FLASH_ACE0_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_FLASH_ACE0_ATTR 0x000001FF
|
||||
#define SYSCON_FLASH_ACE0_ATTR_M ((SYSCON_FLASH_ACE0_ATTR_V)<<(SYSCON_FLASH_ACE0_ATTR_S))
|
||||
#define SYSCON_FLASH_ACE0_ATTR_V 0x1FF
|
||||
#define SYSCON_FLASH_ACE0_ATTR_S 0
|
||||
|
||||
#define SYSCON_FLASH_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x2C)
|
||||
/* SYSCON_FLASH_ACE1_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_FLASH_ACE1_ATTR 0x000001FF
|
||||
#define SYSCON_FLASH_ACE1_ATTR_M ((SYSCON_FLASH_ACE1_ATTR_V)<<(SYSCON_FLASH_ACE1_ATTR_S))
|
||||
#define SYSCON_FLASH_ACE1_ATTR_V 0x1FF
|
||||
#define SYSCON_FLASH_ACE1_ATTR_S 0
|
||||
|
||||
#define SYSCON_FLASH_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x30)
|
||||
/* SYSCON_FLASH_ACE2_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_FLASH_ACE2_ATTR 0x000001FF
|
||||
#define SYSCON_FLASH_ACE2_ATTR_M ((SYSCON_FLASH_ACE2_ATTR_V)<<(SYSCON_FLASH_ACE2_ATTR_S))
|
||||
#define SYSCON_FLASH_ACE2_ATTR_V 0x1FF
|
||||
#define SYSCON_FLASH_ACE2_ATTR_S 0
|
||||
|
||||
#define SYSCON_FLASH_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x34)
|
||||
/* SYSCON_FLASH_ACE3_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_FLASH_ACE3_ATTR 0x000001FF
|
||||
#define SYSCON_FLASH_ACE3_ATTR_M ((SYSCON_FLASH_ACE3_ATTR_V)<<(SYSCON_FLASH_ACE3_ATTR_S))
|
||||
#define SYSCON_FLASH_ACE3_ATTR_V 0x1FF
|
||||
#define SYSCON_FLASH_ACE3_ATTR_S 0
|
||||
|
||||
#define SYSCON_FLASH_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x38)
|
||||
/* SYSCON_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_FLASH_ACE0_ADDR_S 0xFFFFFFFF
|
||||
#define SYSCON_FLASH_ACE0_ADDR_S_M ((SYSCON_FLASH_ACE0_ADDR_S_V)<<(SYSCON_FLASH_ACE0_ADDR_S_S))
|
||||
#define SYSCON_FLASH_ACE0_ADDR_S_V 0xFFFFFFFF
|
||||
#define SYSCON_FLASH_ACE0_ADDR_S_S 0
|
||||
|
||||
#define SYSCON_FLASH_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x3C)
|
||||
/* SYSCON_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_FLASH_ACE1_ADDR_S 0xFFFFFFFF
|
||||
#define SYSCON_FLASH_ACE1_ADDR_S_M ((SYSCON_FLASH_ACE1_ADDR_S_V)<<(SYSCON_FLASH_ACE1_ADDR_S_S))
|
||||
#define SYSCON_FLASH_ACE1_ADDR_S_V 0xFFFFFFFF
|
||||
#define SYSCON_FLASH_ACE1_ADDR_S_S 0
|
||||
|
||||
#define SYSCON_FLASH_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x40)
|
||||
/* SYSCON_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_FLASH_ACE2_ADDR_S 0xFFFFFFFF
|
||||
#define SYSCON_FLASH_ACE2_ADDR_S_M ((SYSCON_FLASH_ACE2_ADDR_S_V)<<(SYSCON_FLASH_ACE2_ADDR_S_S))
|
||||
#define SYSCON_FLASH_ACE2_ADDR_S_V 0xFFFFFFFF
|
||||
#define SYSCON_FLASH_ACE2_ADDR_S_S 0
|
||||
|
||||
#define SYSCON_FLASH_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x44)
|
||||
/* SYSCON_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_FLASH_ACE3_ADDR_S 0xFFFFFFFF
|
||||
#define SYSCON_FLASH_ACE3_ADDR_S_M ((SYSCON_FLASH_ACE3_ADDR_S_V)<<(SYSCON_FLASH_ACE3_ADDR_S_S))
|
||||
#define SYSCON_FLASH_ACE3_ADDR_S_V 0xFFFFFFFF
|
||||
#define SYSCON_FLASH_ACE3_ADDR_S_S 0
|
||||
|
||||
#define SYSCON_FLASH_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x48)
|
||||
/* SYSCON_FLASH_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_FLASH_ACE0_SIZE 0x0000FFFF
|
||||
#define SYSCON_FLASH_ACE0_SIZE_M ((SYSCON_FLASH_ACE0_SIZE_V)<<(SYSCON_FLASH_ACE0_SIZE_S))
|
||||
#define SYSCON_FLASH_ACE0_SIZE_V 0xFFFF
|
||||
#define SYSCON_FLASH_ACE0_SIZE_S 0
|
||||
|
||||
#define SYSCON_FLASH_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x4C)
|
||||
/* SYSCON_FLASH_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_FLASH_ACE1_SIZE 0x0000FFFF
|
||||
#define SYSCON_FLASH_ACE1_SIZE_M ((SYSCON_FLASH_ACE1_SIZE_V)<<(SYSCON_FLASH_ACE1_SIZE_S))
|
||||
#define SYSCON_FLASH_ACE1_SIZE_V 0xFFFF
|
||||
#define SYSCON_FLASH_ACE1_SIZE_S 0
|
||||
|
||||
#define SYSCON_FLASH_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x50)
|
||||
/* SYSCON_FLASH_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_FLASH_ACE2_SIZE 0x0000FFFF
|
||||
#define SYSCON_FLASH_ACE2_SIZE_M ((SYSCON_FLASH_ACE2_SIZE_V)<<(SYSCON_FLASH_ACE2_SIZE_S))
|
||||
#define SYSCON_FLASH_ACE2_SIZE_V 0xFFFF
|
||||
#define SYSCON_FLASH_ACE2_SIZE_S 0
|
||||
|
||||
#define SYSCON_FLASH_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x54)
|
||||
/* SYSCON_FLASH_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_FLASH_ACE3_SIZE 0x0000FFFF
|
||||
#define SYSCON_FLASH_ACE3_SIZE_M ((SYSCON_FLASH_ACE3_SIZE_V)<<(SYSCON_FLASH_ACE3_SIZE_S))
|
||||
#define SYSCON_FLASH_ACE3_SIZE_V 0xFFFF
|
||||
#define SYSCON_FLASH_ACE3_SIZE_S 0
|
||||
|
||||
#define SYSCON_SRAM_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x58)
|
||||
/* SYSCON_SRAM_ACE0_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_SRAM_ACE0_ATTR 0x000001FF
|
||||
#define SYSCON_SRAM_ACE0_ATTR_M ((SYSCON_SRAM_ACE0_ATTR_V)<<(SYSCON_SRAM_ACE0_ATTR_S))
|
||||
#define SYSCON_SRAM_ACE0_ATTR_V 0x1FF
|
||||
#define SYSCON_SRAM_ACE0_ATTR_S 0
|
||||
|
||||
#define SYSCON_SRAM_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x5C)
|
||||
/* SYSCON_SRAM_ACE1_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_SRAM_ACE1_ATTR 0x000001FF
|
||||
#define SYSCON_SRAM_ACE1_ATTR_M ((SYSCON_SRAM_ACE1_ATTR_V)<<(SYSCON_SRAM_ACE1_ATTR_S))
|
||||
#define SYSCON_SRAM_ACE1_ATTR_V 0x1FF
|
||||
#define SYSCON_SRAM_ACE1_ATTR_S 0
|
||||
|
||||
#define SYSCON_SRAM_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x60)
|
||||
/* SYSCON_SRAM_ACE2_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_SRAM_ACE2_ATTR 0x000001FF
|
||||
#define SYSCON_SRAM_ACE2_ATTR_M ((SYSCON_SRAM_ACE2_ATTR_V)<<(SYSCON_SRAM_ACE2_ATTR_S))
|
||||
#define SYSCON_SRAM_ACE2_ATTR_V 0x1FF
|
||||
#define SYSCON_SRAM_ACE2_ATTR_S 0
|
||||
|
||||
#define SYSCON_SRAM_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x64)
|
||||
/* SYSCON_SRAM_ACE3_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_SRAM_ACE3_ATTR 0x000001FF
|
||||
#define SYSCON_SRAM_ACE3_ATTR_M ((SYSCON_SRAM_ACE3_ATTR_V)<<(SYSCON_SRAM_ACE3_ATTR_S))
|
||||
#define SYSCON_SRAM_ACE3_ATTR_V 0x1FF
|
||||
#define SYSCON_SRAM_ACE3_ATTR_S 0
|
||||
|
||||
#define SYSCON_SRAM_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x68)
|
||||
/* SYSCON_SRAM_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_SRAM_ACE0_ADDR_S 0xFFFFFFFF
|
||||
#define SYSCON_SRAM_ACE0_ADDR_S_M ((SYSCON_SRAM_ACE0_ADDR_S_V)<<(SYSCON_SRAM_ACE0_ADDR_S_S))
|
||||
#define SYSCON_SRAM_ACE0_ADDR_S_V 0xFFFFFFFF
|
||||
#define SYSCON_SRAM_ACE0_ADDR_S_S 0
|
||||
|
||||
#define SYSCON_SRAM_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x6C)
|
||||
/* SYSCON_SRAM_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_SRAM_ACE1_ADDR_S 0xFFFFFFFF
|
||||
#define SYSCON_SRAM_ACE1_ADDR_S_M ((SYSCON_SRAM_ACE1_ADDR_S_V)<<(SYSCON_SRAM_ACE1_ADDR_S_S))
|
||||
#define SYSCON_SRAM_ACE1_ADDR_S_V 0xFFFFFFFF
|
||||
#define SYSCON_SRAM_ACE1_ADDR_S_S 0
|
||||
|
||||
#define SYSCON_SRAM_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x70)
|
||||
/* SYSCON_SRAM_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_SRAM_ACE2_ADDR_S 0xFFFFFFFF
|
||||
#define SYSCON_SRAM_ACE2_ADDR_S_M ((SYSCON_SRAM_ACE2_ADDR_S_V)<<(SYSCON_SRAM_ACE2_ADDR_S_S))
|
||||
#define SYSCON_SRAM_ACE2_ADDR_S_V 0xFFFFFFFF
|
||||
#define SYSCON_SRAM_ACE2_ADDR_S_S 0
|
||||
|
||||
#define SYSCON_SRAM_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x74)
|
||||
/* SYSCON_SRAM_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_SRAM_ACE3_ADDR_S 0xFFFFFFFF
|
||||
#define SYSCON_SRAM_ACE3_ADDR_S_M ((SYSCON_SRAM_ACE3_ADDR_S_V)<<(SYSCON_SRAM_ACE3_ADDR_S_S))
|
||||
#define SYSCON_SRAM_ACE3_ADDR_S_V 0xFFFFFFFF
|
||||
#define SYSCON_SRAM_ACE3_ADDR_S_S 0
|
||||
|
||||
#define SYSCON_SRAM_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x78)
|
||||
/* SYSCON_SRAM_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_SRAM_ACE0_SIZE 0x0000FFFF
|
||||
#define SYSCON_SRAM_ACE0_SIZE_M ((SYSCON_SRAM_ACE0_SIZE_V)<<(SYSCON_SRAM_ACE0_SIZE_S))
|
||||
#define SYSCON_SRAM_ACE0_SIZE_V 0xFFFF
|
||||
#define SYSCON_SRAM_ACE0_SIZE_S 0
|
||||
|
||||
#define SYSCON_SRAM_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x7C)
|
||||
/* SYSCON_SRAM_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_SRAM_ACE1_SIZE 0x0000FFFF
|
||||
#define SYSCON_SRAM_ACE1_SIZE_M ((SYSCON_SRAM_ACE1_SIZE_V)<<(SYSCON_SRAM_ACE1_SIZE_S))
|
||||
#define SYSCON_SRAM_ACE1_SIZE_V 0xFFFF
|
||||
#define SYSCON_SRAM_ACE1_SIZE_S 0
|
||||
|
||||
#define SYSCON_SRAM_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x80)
|
||||
/* SYSCON_SRAM_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_SRAM_ACE2_SIZE 0x0000FFFF
|
||||
#define SYSCON_SRAM_ACE2_SIZE_M ((SYSCON_SRAM_ACE2_SIZE_V)<<(SYSCON_SRAM_ACE2_SIZE_S))
|
||||
#define SYSCON_SRAM_ACE2_SIZE_V 0xFFFF
|
||||
#define SYSCON_SRAM_ACE2_SIZE_S 0
|
||||
|
||||
#define SYSCON_SRAM_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x84)
|
||||
/* SYSCON_SRAM_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_SRAM_ACE3_SIZE 0x0000FFFF
|
||||
#define SYSCON_SRAM_ACE3_SIZE_M ((SYSCON_SRAM_ACE3_SIZE_V)<<(SYSCON_SRAM_ACE3_SIZE_S))
|
||||
#define SYSCON_SRAM_ACE3_SIZE_V 0xFFFF
|
||||
#define SYSCON_SRAM_ACE3_SIZE_S 0
|
||||
|
||||
#define SYSCON_SPI_MEM_PMS_CTRL_REG (DR_REG_SYSCON_BASE + 0x88)
|
||||
/* SYSCON_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_SPI_MEM_REJECT_CDE 0x0000001F
|
||||
#define SYSCON_SPI_MEM_REJECT_CDE_M ((SYSCON_SPI_MEM_REJECT_CDE_V)<<(SYSCON_SPI_MEM_REJECT_CDE_S))
|
||||
#define SYSCON_SPI_MEM_REJECT_CDE_V 0x1F
|
||||
#define SYSCON_SPI_MEM_REJECT_CDE_S 2
|
||||
/* SYSCON_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_SPI_MEM_REJECT_CLR (BIT(1))
|
||||
#define SYSCON_SPI_MEM_REJECT_CLR_M (BIT(1))
|
||||
#define SYSCON_SPI_MEM_REJECT_CLR_V 0x1
|
||||
#define SYSCON_SPI_MEM_REJECT_CLR_S 1
|
||||
/* SYSCON_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_SPI_MEM_REJECT_INT (BIT(0))
|
||||
#define SYSCON_SPI_MEM_REJECT_INT_M (BIT(0))
|
||||
#define SYSCON_SPI_MEM_REJECT_INT_V 0x1
|
||||
#define SYSCON_SPI_MEM_REJECT_INT_S 0
|
||||
|
||||
#define SYSCON_SPI_MEM_REJECT_ADDR_REG (DR_REG_SYSCON_BASE + 0x8C)
|
||||
/* SYSCON_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_SPI_MEM_REJECT_ADDR 0xFFFFFFFF
|
||||
#define SYSCON_SPI_MEM_REJECT_ADDR_M ((SYSCON_SPI_MEM_REJECT_ADDR_V)<<(SYSCON_SPI_MEM_REJECT_ADDR_S))
|
||||
#define SYSCON_SPI_MEM_REJECT_ADDR_V 0xFFFFFFFF
|
||||
#define SYSCON_SPI_MEM_REJECT_ADDR_S 0
|
||||
|
||||
#define SYSCON_SDIO_CTRL_REG (DR_REG_SYSCON_BASE + 0x90)
|
||||
/* SYSCON_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_SDIO_WIN_ACCESS_EN (BIT(0))
|
||||
#define SYSCON_SDIO_WIN_ACCESS_EN_M (BIT(0))
|
||||
#define SYSCON_SDIO_WIN_ACCESS_EN_V 0x1
|
||||
#define SYSCON_SDIO_WIN_ACCESS_EN_S 0
|
||||
|
||||
#define SYSCON_REDCY_SIG0_REG (DR_REG_SYSCON_BASE + 0x94)
|
||||
/* SYSCON_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_REDCY_ANDOR (BIT(31))
|
||||
#define SYSCON_REDCY_ANDOR_M (BIT(31))
|
||||
#define SYSCON_REDCY_ANDOR_V 0x1
|
||||
#define SYSCON_REDCY_ANDOR_S 31
|
||||
/* SYSCON_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_REDCY_SIG0 0x7FFFFFFF
|
||||
#define SYSCON_REDCY_SIG0_M ((SYSCON_REDCY_SIG0_V)<<(SYSCON_REDCY_SIG0_S))
|
||||
#define SYSCON_REDCY_SIG0_V 0x7FFFFFFF
|
||||
#define SYSCON_REDCY_SIG0_S 0
|
||||
|
||||
#define SYSCON_REDCY_SIG1_REG (DR_REG_SYSCON_BASE + 0x98)
|
||||
/* SYSCON_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_REDCY_NANDOR (BIT(31))
|
||||
#define SYSCON_REDCY_NANDOR_M (BIT(31))
|
||||
#define SYSCON_REDCY_NANDOR_V 0x1
|
||||
#define SYSCON_REDCY_NANDOR_S 31
|
||||
/* SYSCON_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_REDCY_SIG1 0x7FFFFFFF
|
||||
#define SYSCON_REDCY_SIG1_M ((SYSCON_REDCY_SIG1_V)<<(SYSCON_REDCY_SIG1_S))
|
||||
#define SYSCON_REDCY_SIG1_V 0x7FFFFFFF
|
||||
#define SYSCON_REDCY_SIG1_S 0
|
||||
|
||||
#define SYSCON_FRONT_END_MEM_PD_REG (DR_REG_SYSCON_BASE + 0x9C)
|
||||
/* SYSCON_FREQ_MEM_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_FREQ_MEM_FORCE_PD (BIT(7))
|
||||
#define SYSCON_FREQ_MEM_FORCE_PD_M (BIT(7))
|
||||
#define SYSCON_FREQ_MEM_FORCE_PD_V 0x1
|
||||
#define SYSCON_FREQ_MEM_FORCE_PD_S 7
|
||||
/* SYSCON_FREQ_MEM_FORCE_PU : R/W ;bitpos:[6] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_FREQ_MEM_FORCE_PU (BIT(6))
|
||||
#define SYSCON_FREQ_MEM_FORCE_PU_M (BIT(6))
|
||||
#define SYSCON_FREQ_MEM_FORCE_PU_V 0x1
|
||||
#define SYSCON_FREQ_MEM_FORCE_PU_S 6
|
||||
/* SYSCON_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_DC_MEM_FORCE_PD (BIT(5))
|
||||
#define SYSCON_DC_MEM_FORCE_PD_M (BIT(5))
|
||||
#define SYSCON_DC_MEM_FORCE_PD_V 0x1
|
||||
#define SYSCON_DC_MEM_FORCE_PD_S 5
|
||||
/* SYSCON_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_DC_MEM_FORCE_PU (BIT(4))
|
||||
#define SYSCON_DC_MEM_FORCE_PU_M (BIT(4))
|
||||
#define SYSCON_DC_MEM_FORCE_PU_V 0x1
|
||||
#define SYSCON_DC_MEM_FORCE_PU_S 4
|
||||
/* SYSCON_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_PBUS_MEM_FORCE_PD (BIT(3))
|
||||
#define SYSCON_PBUS_MEM_FORCE_PD_M (BIT(3))
|
||||
#define SYSCON_PBUS_MEM_FORCE_PD_V 0x1
|
||||
#define SYSCON_PBUS_MEM_FORCE_PD_S 3
|
||||
/* SYSCON_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_PBUS_MEM_FORCE_PU (BIT(2))
|
||||
#define SYSCON_PBUS_MEM_FORCE_PU_M (BIT(2))
|
||||
#define SYSCON_PBUS_MEM_FORCE_PU_V 0x1
|
||||
#define SYSCON_PBUS_MEM_FORCE_PU_S 2
|
||||
/* SYSCON_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_AGC_MEM_FORCE_PD (BIT(1))
|
||||
#define SYSCON_AGC_MEM_FORCE_PD_M (BIT(1))
|
||||
#define SYSCON_AGC_MEM_FORCE_PD_V 0x1
|
||||
#define SYSCON_AGC_MEM_FORCE_PD_S 1
|
||||
/* SYSCON_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_AGC_MEM_FORCE_PU (BIT(0))
|
||||
#define SYSCON_AGC_MEM_FORCE_PU_M (BIT(0))
|
||||
#define SYSCON_AGC_MEM_FORCE_PU_V 0x1
|
||||
#define SYSCON_AGC_MEM_FORCE_PU_S 0
|
||||
|
||||
#define SYSCON_SPI_MEM_ECC_CTRL_REG (DR_REG_SYSCON_BASE + 0xA0)
|
||||
/* SYSCON_SRAM_PAGE_SIZE : R/W ;bitpos:[21:20] ;default: 2'd2 ; */
|
||||
/*description: Set the page size of the used MSPI external RAM. 0: 256 bytes. 1: 512 bytes. 2:
|
||||
1024 bytes. 3: 2048 bytes..*/
|
||||
#define SYSCON_SRAM_PAGE_SIZE 0x00000003
|
||||
#define SYSCON_SRAM_PAGE_SIZE_M ((SYSCON_SRAM_PAGE_SIZE_V)<<(SYSCON_SRAM_PAGE_SIZE_S))
|
||||
#define SYSCON_SRAM_PAGE_SIZE_V 0x3
|
||||
#define SYSCON_SRAM_PAGE_SIZE_S 20
|
||||
/* SYSCON_FLASH_PAGE_SIZE : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
|
||||
/*description: Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512 bytes. 2: 1024 by
|
||||
tes. 3: 2048 bytes..*/
|
||||
#define SYSCON_FLASH_PAGE_SIZE 0x00000003
|
||||
#define SYSCON_FLASH_PAGE_SIZE_M ((SYSCON_FLASH_PAGE_SIZE_V)<<(SYSCON_FLASH_PAGE_SIZE_S))
|
||||
#define SYSCON_FLASH_PAGE_SIZE_V 0x3
|
||||
#define SYSCON_FLASH_PAGE_SIZE_S 18
|
||||
|
||||
#define SYSCON_CLKGATE_FORCE_ON_REG (DR_REG_SYSCON_BASE + 0xA8)
|
||||
/* SYSCON_SRAM_CLKGATE_FORCE_ON : R/W ;bitpos:[13:3] ;default: ~11'b0 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_SRAM_CLKGATE_FORCE_ON 0x000007FF
|
||||
#define SYSCON_SRAM_CLKGATE_FORCE_ON_M ((SYSCON_SRAM_CLKGATE_FORCE_ON_V)<<(SYSCON_SRAM_CLKGATE_FORCE_ON_S))
|
||||
#define SYSCON_SRAM_CLKGATE_FORCE_ON_V 0x7FF
|
||||
#define SYSCON_SRAM_CLKGATE_FORCE_ON_S 3
|
||||
/* SYSCON_ROM_CLKGATE_FORCE_ON : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_ROM_CLKGATE_FORCE_ON 0x00000007
|
||||
#define SYSCON_ROM_CLKGATE_FORCE_ON_M ((SYSCON_ROM_CLKGATE_FORCE_ON_V)<<(SYSCON_ROM_CLKGATE_FORCE_ON_S))
|
||||
#define SYSCON_ROM_CLKGATE_FORCE_ON_V 0x7
|
||||
#define SYSCON_ROM_CLKGATE_FORCE_ON_S 0
|
||||
|
||||
#define SYSCON_MEM_POWER_DOWN_REG (DR_REG_SYSCON_BASE + 0xAC)
|
||||
/* SYSCON_SRAM_POWER_DOWN : R/W ;bitpos:[13:3] ;default: 11'b0 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_SRAM_POWER_DOWN 0x000007FF
|
||||
#define SYSCON_SRAM_POWER_DOWN_M ((SYSCON_SRAM_POWER_DOWN_V)<<(SYSCON_SRAM_POWER_DOWN_S))
|
||||
#define SYSCON_SRAM_POWER_DOWN_V 0x7FF
|
||||
#define SYSCON_SRAM_POWER_DOWN_S 3
|
||||
/* SYSCON_ROM_POWER_DOWN : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_ROM_POWER_DOWN 0x00000007
|
||||
#define SYSCON_ROM_POWER_DOWN_M ((SYSCON_ROM_POWER_DOWN_V)<<(SYSCON_ROM_POWER_DOWN_S))
|
||||
#define SYSCON_ROM_POWER_DOWN_V 0x7
|
||||
#define SYSCON_ROM_POWER_DOWN_S 0
|
||||
|
||||
#define SYSCON_MEM_POWER_UP_REG (DR_REG_SYSCON_BASE + 0xB0)
|
||||
/* SYSCON_SRAM_POWER_UP : R/W ;bitpos:[13:3] ;default: ~11'b0 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_SRAM_POWER_UP 0x000007FF
|
||||
#define SYSCON_SRAM_POWER_UP_M ((SYSCON_SRAM_POWER_UP_V)<<(SYSCON_SRAM_POWER_UP_S))
|
||||
#define SYSCON_SRAM_POWER_UP_V 0x7FF
|
||||
#define SYSCON_SRAM_POWER_UP_S 3
|
||||
/* SYSCON_ROM_POWER_UP : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_ROM_POWER_UP 0x00000007
|
||||
#define SYSCON_ROM_POWER_UP_M ((SYSCON_ROM_POWER_UP_V)<<(SYSCON_ROM_POWER_UP_S))
|
||||
#define SYSCON_ROM_POWER_UP_V 0x7
|
||||
#define SYSCON_ROM_POWER_UP_S 0
|
||||
|
||||
#define SYSCON_RETENTION_CTRL_REG (DR_REG_SYSCON_BASE + 0xB4)
|
||||
/* SYSCON_NOBYPASS_CPU_ISO_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_NOBYPASS_CPU_ISO_RST (BIT(27))
|
||||
#define SYSCON_NOBYPASS_CPU_ISO_RST_M (BIT(27))
|
||||
#define SYSCON_NOBYPASS_CPU_ISO_RST_V 0x1
|
||||
#define SYSCON_NOBYPASS_CPU_ISO_RST_S 27
|
||||
/* SYSCON_RETENTION_CPU_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_RETENTION_CPU_LINK_ADDR 0x07FFFFFF
|
||||
#define SYSCON_RETENTION_CPU_LINK_ADDR_M ((SYSCON_RETENTION_CPU_LINK_ADDR_V)<<(SYSCON_RETENTION_CPU_LINK_ADDR_S))
|
||||
#define SYSCON_RETENTION_CPU_LINK_ADDR_V 0x7FFFFFF
|
||||
#define SYSCON_RETENTION_CPU_LINK_ADDR_S 0
|
||||
|
||||
#define SYSCON_RETENTION_CTRL1_REG (DR_REG_SYSCON_BASE + 0xB8)
|
||||
/* SYSCON_RETENTION_TAG_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_RETENTION_TAG_LINK_ADDR 0x07FFFFFF
|
||||
#define SYSCON_RETENTION_TAG_LINK_ADDR_M ((SYSCON_RETENTION_TAG_LINK_ADDR_V)<<(SYSCON_RETENTION_TAG_LINK_ADDR_S))
|
||||
#define SYSCON_RETENTION_TAG_LINK_ADDR_V 0x7FFFFFF
|
||||
#define SYSCON_RETENTION_TAG_LINK_ADDR_S 0
|
||||
|
||||
#define SYSCON_RETENTION_CTRL2_REG (DR_REG_SYSCON_BASE + 0xBC)
|
||||
/* SYSCON_RET_ICACHE_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_RET_ICACHE_ENABLE (BIT(31))
|
||||
#define SYSCON_RET_ICACHE_ENABLE_M (BIT(31))
|
||||
#define SYSCON_RET_ICACHE_ENABLE_V 0x1
|
||||
#define SYSCON_RET_ICACHE_ENABLE_S 31
|
||||
/* SYSCON_RET_ICACHE_START_POINT : R/W ;bitpos:[29:22] ;default: 8'd0 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_RET_ICACHE_START_POINT 0x000000FF
|
||||
#define SYSCON_RET_ICACHE_START_POINT_M ((SYSCON_RET_ICACHE_START_POINT_V)<<(SYSCON_RET_ICACHE_START_POINT_S))
|
||||
#define SYSCON_RET_ICACHE_START_POINT_V 0xFF
|
||||
#define SYSCON_RET_ICACHE_START_POINT_S 22
|
||||
/* SYSCON_RET_ICACHE_VLD_SIZE : R/W ;bitpos:[20:13] ;default: 8'hff ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_RET_ICACHE_VLD_SIZE 0x000000FF
|
||||
#define SYSCON_RET_ICACHE_VLD_SIZE_M ((SYSCON_RET_ICACHE_VLD_SIZE_V)<<(SYSCON_RET_ICACHE_VLD_SIZE_S))
|
||||
#define SYSCON_RET_ICACHE_VLD_SIZE_V 0xFF
|
||||
#define SYSCON_RET_ICACHE_VLD_SIZE_S 13
|
||||
/* SYSCON_RET_ICACHE_SIZE : R/W ;bitpos:[11:4] ;default: 8'hff ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_RET_ICACHE_SIZE 0x000000FF
|
||||
#define SYSCON_RET_ICACHE_SIZE_M ((SYSCON_RET_ICACHE_SIZE_V)<<(SYSCON_RET_ICACHE_SIZE_S))
|
||||
#define SYSCON_RET_ICACHE_SIZE_V 0xFF
|
||||
#define SYSCON_RET_ICACHE_SIZE_S 4
|
||||
|
||||
#define SYSCON_RETENTION_CTRL3_REG (DR_REG_SYSCON_BASE + 0xC0)
|
||||
/* SYSCON_RET_DCACHE_ENABLE : R/W ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_RET_DCACHE_ENABLE (BIT(31))
|
||||
#define SYSCON_RET_DCACHE_ENABLE_M (BIT(31))
|
||||
#define SYSCON_RET_DCACHE_ENABLE_V 0x1
|
||||
#define SYSCON_RET_DCACHE_ENABLE_S 31
|
||||
/* SYSCON_RET_DCACHE_START_POINT : R/W ;bitpos:[30:22] ;default: 9'd0 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_RET_DCACHE_START_POINT 0x000001FF
|
||||
#define SYSCON_RET_DCACHE_START_POINT_M ((SYSCON_RET_DCACHE_START_POINT_V)<<(SYSCON_RET_DCACHE_START_POINT_S))
|
||||
#define SYSCON_RET_DCACHE_START_POINT_V 0x1FF
|
||||
#define SYSCON_RET_DCACHE_START_POINT_S 22
|
||||
/* SYSCON_RET_DCACHE_VLD_SIZE : R/W ;bitpos:[21:13] ;default: 9'h1ff ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_RET_DCACHE_VLD_SIZE 0x000001FF
|
||||
#define SYSCON_RET_DCACHE_VLD_SIZE_M ((SYSCON_RET_DCACHE_VLD_SIZE_V)<<(SYSCON_RET_DCACHE_VLD_SIZE_S))
|
||||
#define SYSCON_RET_DCACHE_VLD_SIZE_V 0x1FF
|
||||
#define SYSCON_RET_DCACHE_VLD_SIZE_S 13
|
||||
/* SYSCON_RET_DCACHE_SIZE : R/W ;bitpos:[12:4] ;default: 9'h1ff ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_RET_DCACHE_SIZE 0x000001FF
|
||||
#define SYSCON_RET_DCACHE_SIZE_M ((SYSCON_RET_DCACHE_SIZE_V)<<(SYSCON_RET_DCACHE_SIZE_S))
|
||||
#define SYSCON_RET_DCACHE_SIZE_V 0x1FF
|
||||
#define SYSCON_RET_DCACHE_SIZE_S 4
|
||||
|
||||
#define SYSCON_RETENTION_CTRL4_REG (DR_REG_SYSCON_BASE + 0xC4)
|
||||
/* SYSCON_RETENTION_INV_CFG : R/W ;bitpos:[31:0] ;default: ~32'h0 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_RETENTION_INV_CFG 0xFFFFFFFF
|
||||
#define SYSCON_RETENTION_INV_CFG_M ((SYSCON_RETENTION_INV_CFG_V)<<(SYSCON_RETENTION_INV_CFG_S))
|
||||
#define SYSCON_RETENTION_INV_CFG_V 0xFFFFFFFF
|
||||
#define SYSCON_RETENTION_INV_CFG_S 0
|
||||
|
||||
#define SYSCON_RETENTION_CTRL5_REG (DR_REG_SYSCON_BASE + 0xC8)
|
||||
/* SYSCON_RETENTION_DISABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define SYSCON_RETENTION_DISABLE (BIT(0))
|
||||
#define SYSCON_RETENTION_DISABLE_M (BIT(0))
|
||||
#define SYSCON_RETENTION_DISABLE_V 0x1
|
||||
#define SYSCON_RETENTION_DISABLE_S 0
|
||||
|
||||
#define SYSCON_DATE_REG (DR_REG_SYSCON_BASE + 0x3FC)
|
||||
/* SYSCON_DATE : R/W ;bitpos:[31:0] ;default: 32'h2101150 ; */
|
||||
/*description: Version control.*/
|
||||
#define SYSCON_DATE 0xFFFFFFFF
|
||||
#define SYSCON_DATE_M ((SYSCON_DATE_V)<<(SYSCON_DATE_S))
|
||||
#define SYSCON_DATE_V 0xFFFFFFFF
|
||||
#define SYSCON_DATE_S 0
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /*_SOC_SYSCON_REG_H_ */
|
||||
@@ -1,543 +0,0 @@
|
||||
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_SYSCON_STRUCT_H_
|
||||
#define _SOC_SYSCON_STRUCT_H_
|
||||
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct syscon_dev_s {
|
||||
union {
|
||||
struct {
|
||||
uint32_t pre_div : 10;
|
||||
uint32_t clk_320m_en : 1;
|
||||
uint32_t clk_en : 1;
|
||||
uint32_t rst_tick : 1;
|
||||
uint32_t reserved13 : 19;
|
||||
};
|
||||
uint32_t val;
|
||||
} clk_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t xtal_tick : 8;
|
||||
uint32_t ck8m_tick : 8;
|
||||
uint32_t tick_enable : 1;
|
||||
uint32_t reserved17 : 15;
|
||||
};
|
||||
uint32_t val;
|
||||
} tick_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk20_oen : 1;
|
||||
uint32_t clk22_oen : 1;
|
||||
uint32_t clk44_oen : 1;
|
||||
uint32_t clk_bb_oen : 1;
|
||||
uint32_t clk80_oen : 1;
|
||||
uint32_t clk160_oen : 1;
|
||||
uint32_t clk_320m_oen : 1;
|
||||
uint32_t clk_adc_inf_oen : 1;
|
||||
uint32_t clk_dac_cpu_oen : 1;
|
||||
uint32_t clk40x_bb_oen : 1;
|
||||
uint32_t clk_xtal_oen : 1;
|
||||
uint32_t reserved11 : 21;
|
||||
};
|
||||
uint32_t val;
|
||||
} clk_out_en;
|
||||
uint32_t wifi_bb_cfg;
|
||||
uint32_t wifi_bb_cfg_2;
|
||||
uint32_t wifi_clk_en;
|
||||
uint32_t wifi_rst_en;
|
||||
union {
|
||||
struct {
|
||||
uint32_t peri_io_swap : 8;
|
||||
uint32_t reserved8 : 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} host_inf_sel;
|
||||
union {
|
||||
struct {
|
||||
uint32_t ext_mem_pms_lock : 1;
|
||||
uint32_t reserved1 : 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} ext_mem_pms_lock;
|
||||
union {
|
||||
struct {
|
||||
uint32_t writeback_bypass : 1; /*Set 1 to bypass cache writeback request to external memory so that spi will not check its attribute.*/
|
||||
uint32_t reserved1 : 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} ext_mem_writeback_bypass;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace0_attr : 9;
|
||||
uint32_t reserved9 : 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace0_attr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace1_attr : 9;
|
||||
uint32_t reserved9 : 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace1_attr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace2_attr : 9;
|
||||
uint32_t reserved9 : 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace2_attr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace3_attr : 9;
|
||||
uint32_t reserved9 : 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace3_attr;
|
||||
uint32_t flash_ace0_addr;
|
||||
uint32_t flash_ace1_addr;
|
||||
uint32_t flash_ace2_addr;
|
||||
uint32_t flash_ace3_addr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace0_size : 16;
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace0_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace1_size : 16;
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace1_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace2_size : 16;
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace2_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace3_size : 16;
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace3_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sram_ace0_attr : 9;
|
||||
uint32_t reserved9 : 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} sram_ace0_attr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sram_ace1_attr : 9;
|
||||
uint32_t reserved9 : 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} sram_ace1_attr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sram_ace2_attr : 9;
|
||||
uint32_t reserved9 : 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} sram_ace2_attr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sram_ace3_attr : 9;
|
||||
uint32_t reserved9 : 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} sram_ace3_attr;
|
||||
uint32_t sram_ace0_addr;
|
||||
uint32_t sram_ace1_addr;
|
||||
uint32_t sram_ace2_addr;
|
||||
uint32_t sram_ace3_addr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sram_ace0_size : 16;
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} sram_ace0_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sram_ace1_size : 16;
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} sram_ace1_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sram_ace2_size : 16;
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} sram_ace2_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sram_ace3_size : 16;
|
||||
uint32_t reserved16 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} sram_ace3_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t spi_mem_reject_int : 1;
|
||||
uint32_t spi_mem_reject_clr : 1;
|
||||
uint32_t spi_mem_reject_cde : 5;
|
||||
uint32_t reserved7 : 25;
|
||||
};
|
||||
uint32_t val;
|
||||
} spi_mem_pms_ctrl;
|
||||
uint32_t spi_mem_reject_addr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sdio_win_access_en : 1;
|
||||
uint32_t reserved1 : 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} sdio_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t redcy_sig0 : 31;
|
||||
uint32_t redcy_andor : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} redcy_sig0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t redcy_sig1 : 31;
|
||||
uint32_t redcy_nandor : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} redcy_sig1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t agc_mem_force_pu : 1;
|
||||
uint32_t agc_mem_force_pd : 1;
|
||||
uint32_t pbus_mem_force_pu : 1;
|
||||
uint32_t pbus_mem_force_pd : 1;
|
||||
uint32_t dc_mem_force_pu : 1;
|
||||
uint32_t dc_mem_force_pd : 1;
|
||||
uint32_t freq_mem_force_pu : 1;
|
||||
uint32_t freq_mem_force_pd : 1;
|
||||
uint32_t reserved8 : 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} front_end_mem_pd;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 18; /*reserved*/
|
||||
uint32_t flash_page_size : 2; /*Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
|
||||
uint32_t sram_page_size : 2; /*Set the page size of the used MSPI external RAM. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
|
||||
uint32_t reserved22 : 10; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} spi_mem_ecc_ctrl;
|
||||
uint32_t reserved_a4;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rom_clkgate_force_on : 3;
|
||||
uint32_t sram_clkgate_force_on : 11;
|
||||
uint32_t reserved14 : 18;
|
||||
};
|
||||
uint32_t val;
|
||||
} clkgate_force_on;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rom_power_down : 3;
|
||||
uint32_t sram_power_down : 11;
|
||||
uint32_t reserved14 : 18;
|
||||
};
|
||||
uint32_t val;
|
||||
} mem_power_down;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rom_power_up : 3;
|
||||
uint32_t sram_power_up : 11;
|
||||
uint32_t reserved14 : 18;
|
||||
};
|
||||
uint32_t val;
|
||||
} mem_power_up;
|
||||
union {
|
||||
struct {
|
||||
uint32_t retention_cpu_link_addr : 27;
|
||||
uint32_t nobypass_cpu_iso_rst : 1;
|
||||
uint32_t reserved28 : 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} retention_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t retention_tag_link_addr : 27;
|
||||
uint32_t reserved27 : 5;
|
||||
};
|
||||
uint32_t val;
|
||||
} retention_ctrl1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 4;
|
||||
uint32_t ret_icache_size : 8;
|
||||
uint32_t reserved12 : 1;
|
||||
uint32_t ret_icache_vld_size : 8;
|
||||
uint32_t reserved21 : 1;
|
||||
uint32_t ret_icache_start_point : 8;
|
||||
uint32_t reserved30 : 1;
|
||||
uint32_t ret_icache_enable : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} retention_ctrl2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0 : 4;
|
||||
uint32_t ret_dcache_size : 9;
|
||||
uint32_t ret_dcache_vld_size : 9;
|
||||
uint32_t ret_dcache_start_point : 9;
|
||||
uint32_t ret_dcache_enable : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} retention_ctrl3;
|
||||
uint32_t retention_ctrl4;
|
||||
union {
|
||||
struct {
|
||||
uint32_t retention_disable : 1;
|
||||
uint32_t reserved1 : 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} retention_ctrl5;
|
||||
uint32_t reserved_cc;
|
||||
uint32_t reserved_d0;
|
||||
uint32_t reserved_d4;
|
||||
uint32_t reserved_d8;
|
||||
uint32_t reserved_dc;
|
||||
uint32_t reserved_e0;
|
||||
uint32_t reserved_e4;
|
||||
uint32_t reserved_e8;
|
||||
uint32_t reserved_ec;
|
||||
uint32_t reserved_f0;
|
||||
uint32_t reserved_f4;
|
||||
uint32_t reserved_f8;
|
||||
uint32_t reserved_fc;
|
||||
uint32_t reserved_100;
|
||||
uint32_t reserved_104;
|
||||
uint32_t reserved_108;
|
||||
uint32_t reserved_10c;
|
||||
uint32_t reserved_110;
|
||||
uint32_t reserved_114;
|
||||
uint32_t reserved_118;
|
||||
uint32_t reserved_11c;
|
||||
uint32_t reserved_120;
|
||||
uint32_t reserved_124;
|
||||
uint32_t reserved_128;
|
||||
uint32_t reserved_12c;
|
||||
uint32_t reserved_130;
|
||||
uint32_t reserved_134;
|
||||
uint32_t reserved_138;
|
||||
uint32_t reserved_13c;
|
||||
uint32_t reserved_140;
|
||||
uint32_t reserved_144;
|
||||
uint32_t reserved_148;
|
||||
uint32_t reserved_14c;
|
||||
uint32_t reserved_150;
|
||||
uint32_t reserved_154;
|
||||
uint32_t reserved_158;
|
||||
uint32_t reserved_15c;
|
||||
uint32_t reserved_160;
|
||||
uint32_t reserved_164;
|
||||
uint32_t reserved_168;
|
||||
uint32_t reserved_16c;
|
||||
uint32_t reserved_170;
|
||||
uint32_t reserved_174;
|
||||
uint32_t reserved_178;
|
||||
uint32_t reserved_17c;
|
||||
uint32_t reserved_180;
|
||||
uint32_t reserved_184;
|
||||
uint32_t reserved_188;
|
||||
uint32_t reserved_18c;
|
||||
uint32_t reserved_190;
|
||||
uint32_t reserved_194;
|
||||
uint32_t reserved_198;
|
||||
uint32_t reserved_19c;
|
||||
uint32_t reserved_1a0;
|
||||
uint32_t reserved_1a4;
|
||||
uint32_t reserved_1a8;
|
||||
uint32_t reserved_1ac;
|
||||
uint32_t reserved_1b0;
|
||||
uint32_t reserved_1b4;
|
||||
uint32_t reserved_1b8;
|
||||
uint32_t reserved_1bc;
|
||||
uint32_t reserved_1c0;
|
||||
uint32_t reserved_1c4;
|
||||
uint32_t reserved_1c8;
|
||||
uint32_t reserved_1cc;
|
||||
uint32_t reserved_1d0;
|
||||
uint32_t reserved_1d4;
|
||||
uint32_t reserved_1d8;
|
||||
uint32_t reserved_1dc;
|
||||
uint32_t reserved_1e0;
|
||||
uint32_t reserved_1e4;
|
||||
uint32_t reserved_1e8;
|
||||
uint32_t reserved_1ec;
|
||||
uint32_t reserved_1f0;
|
||||
uint32_t reserved_1f4;
|
||||
uint32_t reserved_1f8;
|
||||
uint32_t reserved_1fc;
|
||||
uint32_t reserved_200;
|
||||
uint32_t reserved_204;
|
||||
uint32_t reserved_208;
|
||||
uint32_t reserved_20c;
|
||||
uint32_t reserved_210;
|
||||
uint32_t reserved_214;
|
||||
uint32_t reserved_218;
|
||||
uint32_t reserved_21c;
|
||||
uint32_t reserved_220;
|
||||
uint32_t reserved_224;
|
||||
uint32_t reserved_228;
|
||||
uint32_t reserved_22c;
|
||||
uint32_t reserved_230;
|
||||
uint32_t reserved_234;
|
||||
uint32_t reserved_238;
|
||||
uint32_t reserved_23c;
|
||||
uint32_t reserved_240;
|
||||
uint32_t reserved_244;
|
||||
uint32_t reserved_248;
|
||||
uint32_t reserved_24c;
|
||||
uint32_t reserved_250;
|
||||
uint32_t reserved_254;
|
||||
uint32_t reserved_258;
|
||||
uint32_t reserved_25c;
|
||||
uint32_t reserved_260;
|
||||
uint32_t reserved_264;
|
||||
uint32_t reserved_268;
|
||||
uint32_t reserved_26c;
|
||||
uint32_t reserved_270;
|
||||
uint32_t reserved_274;
|
||||
uint32_t reserved_278;
|
||||
uint32_t reserved_27c;
|
||||
uint32_t reserved_280;
|
||||
uint32_t reserved_284;
|
||||
uint32_t reserved_288;
|
||||
uint32_t reserved_28c;
|
||||
uint32_t reserved_290;
|
||||
uint32_t reserved_294;
|
||||
uint32_t reserved_298;
|
||||
uint32_t reserved_29c;
|
||||
uint32_t reserved_2a0;
|
||||
uint32_t reserved_2a4;
|
||||
uint32_t reserved_2a8;
|
||||
uint32_t reserved_2ac;
|
||||
uint32_t reserved_2b0;
|
||||
uint32_t reserved_2b4;
|
||||
uint32_t reserved_2b8;
|
||||
uint32_t reserved_2bc;
|
||||
uint32_t reserved_2c0;
|
||||
uint32_t reserved_2c4;
|
||||
uint32_t reserved_2c8;
|
||||
uint32_t reserved_2cc;
|
||||
uint32_t reserved_2d0;
|
||||
uint32_t reserved_2d4;
|
||||
uint32_t reserved_2d8;
|
||||
uint32_t reserved_2dc;
|
||||
uint32_t reserved_2e0;
|
||||
uint32_t reserved_2e4;
|
||||
uint32_t reserved_2e8;
|
||||
uint32_t reserved_2ec;
|
||||
uint32_t reserved_2f0;
|
||||
uint32_t reserved_2f4;
|
||||
uint32_t reserved_2f8;
|
||||
uint32_t reserved_2fc;
|
||||
uint32_t reserved_300;
|
||||
uint32_t reserved_304;
|
||||
uint32_t reserved_308;
|
||||
uint32_t reserved_30c;
|
||||
uint32_t reserved_310;
|
||||
uint32_t reserved_314;
|
||||
uint32_t reserved_318;
|
||||
uint32_t reserved_31c;
|
||||
uint32_t reserved_320;
|
||||
uint32_t reserved_324;
|
||||
uint32_t reserved_328;
|
||||
uint32_t reserved_32c;
|
||||
uint32_t reserved_330;
|
||||
uint32_t reserved_334;
|
||||
uint32_t reserved_338;
|
||||
uint32_t reserved_33c;
|
||||
uint32_t reserved_340;
|
||||
uint32_t reserved_344;
|
||||
uint32_t reserved_348;
|
||||
uint32_t reserved_34c;
|
||||
uint32_t reserved_350;
|
||||
uint32_t reserved_354;
|
||||
uint32_t reserved_358;
|
||||
uint32_t reserved_35c;
|
||||
uint32_t reserved_360;
|
||||
uint32_t reserved_364;
|
||||
uint32_t reserved_368;
|
||||
uint32_t reserved_36c;
|
||||
uint32_t reserved_370;
|
||||
uint32_t reserved_374;
|
||||
uint32_t reserved_378;
|
||||
uint32_t reserved_37c;
|
||||
uint32_t reserved_380;
|
||||
uint32_t reserved_384;
|
||||
uint32_t reserved_388;
|
||||
uint32_t reserved_38c;
|
||||
uint32_t reserved_390;
|
||||
uint32_t reserved_394;
|
||||
uint32_t reserved_398;
|
||||
uint32_t reserved_39c;
|
||||
uint32_t reserved_3a0;
|
||||
uint32_t reserved_3a4;
|
||||
uint32_t reserved_3a8;
|
||||
uint32_t reserved_3ac;
|
||||
uint32_t reserved_3b0;
|
||||
uint32_t reserved_3b4;
|
||||
uint32_t reserved_3b8;
|
||||
uint32_t reserved_3bc;
|
||||
uint32_t reserved_3c0;
|
||||
uint32_t reserved_3c4;
|
||||
uint32_t reserved_3c8;
|
||||
uint32_t reserved_3cc;
|
||||
uint32_t reserved_3d0;
|
||||
uint32_t reserved_3d4;
|
||||
uint32_t reserved_3d8;
|
||||
uint32_t reserved_3dc;
|
||||
uint32_t reserved_3e0;
|
||||
uint32_t reserved_3e4;
|
||||
uint32_t reserved_3e8;
|
||||
uint32_t reserved_3ec;
|
||||
uint32_t reserved_3f0;
|
||||
uint32_t reserved_3f4;
|
||||
uint32_t reserved_3f8;
|
||||
uint32_t date;
|
||||
} syscon_dev_t;
|
||||
extern syscon_dev_t SYSCON;
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /*_SOC_SYSCON_STRUCT_H_ */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,639 +0,0 @@
|
||||
/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** SYSTIMER_CONF_REG register
|
||||
* Configure system timer clock
|
||||
*/
|
||||
#define SYSTIMER_CONF_REG (DR_REG_SYSTIMER_BASE + 0x0)
|
||||
/** SYSTIMER_SYSTIMER_CLK_FO : R/W; bitpos: [0]; default: 0;
|
||||
* systimer clock force on
|
||||
*/
|
||||
#define SYSTIMER_SYSTIMER_CLK_FO (BIT(0))
|
||||
#define SYSTIMER_SYSTIMER_CLK_FO_M (SYSTIMER_SYSTIMER_CLK_FO_V << SYSTIMER_SYSTIMER_CLK_FO_S)
|
||||
#define SYSTIMER_SYSTIMER_CLK_FO_V 0x00000001
|
||||
#define SYSTIMER_SYSTIMER_CLK_FO_S 0
|
||||
/** SYSTIMER_TARGET2_WORK_EN : R/W; bitpos: [22]; default: 0;
|
||||
* target2 work enable
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_WORK_EN (BIT(22))
|
||||
#define SYSTIMER_TARGET2_WORK_EN_M (SYSTIMER_TARGET2_WORK_EN_V << SYSTIMER_TARGET2_WORK_EN_S)
|
||||
#define SYSTIMER_TARGET2_WORK_EN_V 0x00000001
|
||||
#define SYSTIMER_TARGET2_WORK_EN_S 22
|
||||
/** SYSTIMER_TARGET1_WORK_EN : R/W; bitpos: [23]; default: 0;
|
||||
* target1 work enable
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_WORK_EN (BIT(23))
|
||||
#define SYSTIMER_TARGET1_WORK_EN_M (SYSTIMER_TARGET1_WORK_EN_V << SYSTIMER_TARGET1_WORK_EN_S)
|
||||
#define SYSTIMER_TARGET1_WORK_EN_V 0x00000001
|
||||
#define SYSTIMER_TARGET1_WORK_EN_S 23
|
||||
/** SYSTIMER_TARGET0_WORK_EN : R/W; bitpos: [24]; default: 0;
|
||||
* target0 work enable
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_WORK_EN (BIT(24))
|
||||
#define SYSTIMER_TARGET0_WORK_EN_M (SYSTIMER_TARGET0_WORK_EN_V << SYSTIMER_TARGET0_WORK_EN_S)
|
||||
#define SYSTIMER_TARGET0_WORK_EN_V 0x00000001
|
||||
#define SYSTIMER_TARGET0_WORK_EN_S 24
|
||||
/** SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W; bitpos: [25]; default: 1;
|
||||
* If timer unit1 is stalled when core1 stalled
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN (BIT(25))
|
||||
#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V 0x00000001
|
||||
#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S 25
|
||||
/** SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W; bitpos: [26]; default: 1;
|
||||
* If timer unit1 is stalled when core0 stalled
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN (BIT(26))
|
||||
#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V 0x00000001
|
||||
#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S 26
|
||||
/** SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W; bitpos: [27]; default: 0;
|
||||
* If timer unit0 is stalled when core1 stalled
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN (BIT(27))
|
||||
#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V 0x00000001
|
||||
#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S 27
|
||||
/** SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W; bitpos: [28]; default: 0;
|
||||
* If timer unit0 is stalled when core0 stalled
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN (BIT(28))
|
||||
#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V 0x00000001
|
||||
#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S 28
|
||||
/** SYSTIMER_TIMER_UNIT1_WORK_EN : R/W; bitpos: [29]; default: 0;
|
||||
* timer unit1 work enable
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_WORK_EN (BIT(29))
|
||||
#define SYSTIMER_TIMER_UNIT1_WORK_EN_M (SYSTIMER_TIMER_UNIT1_WORK_EN_V << SYSTIMER_TIMER_UNIT1_WORK_EN_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_WORK_EN_V 0x00000001
|
||||
#define SYSTIMER_TIMER_UNIT1_WORK_EN_S 29
|
||||
/** SYSTIMER_TIMER_UNIT0_WORK_EN : R/W; bitpos: [30]; default: 1;
|
||||
* timer unit0 work enable
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_WORK_EN (BIT(30))
|
||||
#define SYSTIMER_TIMER_UNIT0_WORK_EN_M (SYSTIMER_TIMER_UNIT0_WORK_EN_V << SYSTIMER_TIMER_UNIT0_WORK_EN_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_WORK_EN_V 0x00000001
|
||||
#define SYSTIMER_TIMER_UNIT0_WORK_EN_S 30
|
||||
/** SYSTIMER_CLK_EN : R/W; bitpos: [31]; default: 0;
|
||||
* register file clk gating
|
||||
*/
|
||||
#define SYSTIMER_CLK_EN (BIT(31))
|
||||
#define SYSTIMER_CLK_EN_M (SYSTIMER_CLK_EN_V << SYSTIMER_CLK_EN_S)
|
||||
#define SYSTIMER_CLK_EN_V 0x00000001
|
||||
#define SYSTIMER_CLK_EN_S 31
|
||||
|
||||
/** SYSTIMER_UNIT0_OP_REG register
|
||||
* system timer unit0 value update register
|
||||
*/
|
||||
#define SYSTIMER_UNIT0_OP_REG (DR_REG_SYSTIMER_BASE + 0x4)
|
||||
/** SYSTIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0;
|
||||
* timer value is sync and valid
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_VALID (BIT(29))
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_M (SYSTIMER_TIMER_UNIT0_VALUE_VALID_V << SYSTIMER_TIMER_UNIT0_VALUE_VALID_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_V 0x00000001
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_S 29
|
||||
/** SYSTIMER_TIMER_UNIT0_UPDATE : WT; bitpos: [30]; default: 0;
|
||||
* update timer_unit0
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_UPDATE (BIT(30))
|
||||
#define SYSTIMER_TIMER_UNIT0_UPDATE_M (SYSTIMER_TIMER_UNIT0_UPDATE_V << SYSTIMER_TIMER_UNIT0_UPDATE_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_UPDATE_V 0x00000001
|
||||
#define SYSTIMER_TIMER_UNIT0_UPDATE_S 30
|
||||
|
||||
/** SYSTIMER_UNIT1_OP_REG register
|
||||
* system timer unit1 value update register
|
||||
*/
|
||||
#define SYSTIMER_UNIT1_OP_REG (DR_REG_SYSTIMER_BASE + 0x8)
|
||||
/** SYSTIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0;
|
||||
* timer value is sync and valid
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_VALID (BIT(29))
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_M (SYSTIMER_TIMER_UNIT1_VALUE_VALID_V << SYSTIMER_TIMER_UNIT1_VALUE_VALID_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_V 0x00000001
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_S 29
|
||||
/** SYSTIMER_TIMER_UNIT1_UPDATE : WT; bitpos: [30]; default: 0;
|
||||
* update timer unit1
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_UPDATE (BIT(30))
|
||||
#define SYSTIMER_TIMER_UNIT1_UPDATE_M (SYSTIMER_TIMER_UNIT1_UPDATE_V << SYSTIMER_TIMER_UNIT1_UPDATE_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_UPDATE_V 0x00000001
|
||||
#define SYSTIMER_TIMER_UNIT1_UPDATE_S 30
|
||||
|
||||
/** SYSTIMER_UNIT0_LOAD_HI_REG register
|
||||
* system timer unit0 value high load register
|
||||
*/
|
||||
#define SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0xc)
|
||||
/** SYSTIMER_TIMER_UNIT0_LOAD_HI : R/W; bitpos: [19:0]; default: 0;
|
||||
* timer unit0 load high 20 bits
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_HI 0x000FFFFF
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_HI_M (SYSTIMER_TIMER_UNIT0_LOAD_HI_V << SYSTIMER_TIMER_UNIT0_LOAD_HI_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_HI_V 0x000FFFFF
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_HI_S 0
|
||||
|
||||
/** SYSTIMER_UNIT0_LOAD_LO_REG register
|
||||
* system timer unit0 value low load register
|
||||
*/
|
||||
#define SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x10)
|
||||
/** SYSTIMER_TIMER_UNIT0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
|
||||
* timer unit0 load low 32 bits
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_LO 0xFFFFFFFF
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_LO_M (SYSTIMER_TIMER_UNIT0_LOAD_LO_V << SYSTIMER_TIMER_UNIT0_LOAD_LO_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_LO_V 0xFFFFFFFF
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_LO_S 0
|
||||
|
||||
/** SYSTIMER_UNIT1_LOAD_HI_REG register
|
||||
* system timer unit1 value high load register
|
||||
*/
|
||||
#define SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0x14)
|
||||
/** SYSTIMER_TIMER_UNIT1_LOAD_HI : R/W; bitpos: [19:0]; default: 0;
|
||||
* timer unit1 load high 20 bits
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_HI 0x000FFFFF
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_HI_M (SYSTIMER_TIMER_UNIT1_LOAD_HI_V << SYSTIMER_TIMER_UNIT1_LOAD_HI_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_HI_V 0x000FFFFF
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_HI_S 0
|
||||
|
||||
/** SYSTIMER_UNIT1_LOAD_LO_REG register
|
||||
* system timer unit1 value low load register
|
||||
*/
|
||||
#define SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x18)
|
||||
/** SYSTIMER_TIMER_UNIT1_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
|
||||
* timer unit1 load low 32 bits
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_LO 0xFFFFFFFF
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_LO_M (SYSTIMER_TIMER_UNIT1_LOAD_LO_V << SYSTIMER_TIMER_UNIT1_LOAD_LO_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_LO_V 0xFFFFFFFF
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_LO_S 0
|
||||
|
||||
/** SYSTIMER_TARGET0_HI_REG register
|
||||
* system timer comp0 value high register
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x1c)
|
||||
/** SYSTIMER_TIMER_TARGET0_HI : R/W; bitpos: [19:0]; default: 0;
|
||||
* timer taget0 high 20 bits
|
||||
*/
|
||||
#define SYSTIMER_TIMER_TARGET0_HI 0x000FFFFF
|
||||
#define SYSTIMER_TIMER_TARGET0_HI_M (SYSTIMER_TIMER_TARGET0_HI_V << SYSTIMER_TIMER_TARGET0_HI_S)
|
||||
#define SYSTIMER_TIMER_TARGET0_HI_V 0x000FFFFF
|
||||
#define SYSTIMER_TIMER_TARGET0_HI_S 0
|
||||
|
||||
/** SYSTIMER_TARGET0_LO_REG register
|
||||
* system timer comp0 value low register
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x20)
|
||||
/** SYSTIMER_TIMER_TARGET0_LO : R/W; bitpos: [31:0]; default: 0;
|
||||
* timer taget0 low 32 bits
|
||||
*/
|
||||
#define SYSTIMER_TIMER_TARGET0_LO 0xFFFFFFFF
|
||||
#define SYSTIMER_TIMER_TARGET0_LO_M (SYSTIMER_TIMER_TARGET0_LO_V << SYSTIMER_TIMER_TARGET0_LO_S)
|
||||
#define SYSTIMER_TIMER_TARGET0_LO_V 0xFFFFFFFF
|
||||
#define SYSTIMER_TIMER_TARGET0_LO_S 0
|
||||
|
||||
/** SYSTIMER_TARGET1_HI_REG register
|
||||
* system timer comp1 value high register
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x24)
|
||||
/** SYSTIMER_TIMER_TARGET1_HI : R/W; bitpos: [19:0]; default: 0;
|
||||
* timer taget1 high 20 bits
|
||||
*/
|
||||
#define SYSTIMER_TIMER_TARGET1_HI 0x000FFFFF
|
||||
#define SYSTIMER_TIMER_TARGET1_HI_M (SYSTIMER_TIMER_TARGET1_HI_V << SYSTIMER_TIMER_TARGET1_HI_S)
|
||||
#define SYSTIMER_TIMER_TARGET1_HI_V 0x000FFFFF
|
||||
#define SYSTIMER_TIMER_TARGET1_HI_S 0
|
||||
|
||||
/** SYSTIMER_TARGET1_LO_REG register
|
||||
* system timer comp1 value low register
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x28)
|
||||
/** SYSTIMER_TIMER_TARGET1_LO : R/W; bitpos: [31:0]; default: 0;
|
||||
* timer taget1 low 32 bits
|
||||
*/
|
||||
#define SYSTIMER_TIMER_TARGET1_LO 0xFFFFFFFF
|
||||
#define SYSTIMER_TIMER_TARGET1_LO_M (SYSTIMER_TIMER_TARGET1_LO_V << SYSTIMER_TIMER_TARGET1_LO_S)
|
||||
#define SYSTIMER_TIMER_TARGET1_LO_V 0xFFFFFFFF
|
||||
#define SYSTIMER_TIMER_TARGET1_LO_S 0
|
||||
|
||||
/** SYSTIMER_TARGET2_HI_REG register
|
||||
* system timer comp2 value high register
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x2c)
|
||||
/** SYSTIMER_TIMER_TARGET2_HI : R/W; bitpos: [19:0]; default: 0;
|
||||
* timer taget2 high 20 bits
|
||||
*/
|
||||
#define SYSTIMER_TIMER_TARGET2_HI 0x000FFFFF
|
||||
#define SYSTIMER_TIMER_TARGET2_HI_M (SYSTIMER_TIMER_TARGET2_HI_V << SYSTIMER_TIMER_TARGET2_HI_S)
|
||||
#define SYSTIMER_TIMER_TARGET2_HI_V 0x000FFFFF
|
||||
#define SYSTIMER_TIMER_TARGET2_HI_S 0
|
||||
|
||||
/** SYSTIMER_TARGET2_LO_REG register
|
||||
* system timer comp2 value low register
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x30)
|
||||
/** SYSTIMER_TIMER_TARGET2_LO : R/W; bitpos: [31:0]; default: 0;
|
||||
* timer taget2 low 32 bits
|
||||
*/
|
||||
#define SYSTIMER_TIMER_TARGET2_LO 0xFFFFFFFF
|
||||
#define SYSTIMER_TIMER_TARGET2_LO_M (SYSTIMER_TIMER_TARGET2_LO_V << SYSTIMER_TIMER_TARGET2_LO_S)
|
||||
#define SYSTIMER_TIMER_TARGET2_LO_V 0xFFFFFFFF
|
||||
#define SYSTIMER_TIMER_TARGET2_LO_S 0
|
||||
|
||||
/** SYSTIMER_TARGET0_CONF_REG register
|
||||
* system timer comp0 target mode register
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_CONF_REG (DR_REG_SYSTIMER_BASE + 0x34)
|
||||
/** SYSTIMER_TARGET0_PERIOD : R/W; bitpos: [25:0]; default: 0;
|
||||
* target0 period
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_PERIOD 0x03FFFFFF
|
||||
#define SYSTIMER_TARGET0_PERIOD_M (SYSTIMER_TARGET0_PERIOD_V << SYSTIMER_TARGET0_PERIOD_S)
|
||||
#define SYSTIMER_TARGET0_PERIOD_V 0x03FFFFFF
|
||||
#define SYSTIMER_TARGET0_PERIOD_S 0
|
||||
/** SYSTIMER_TARGET0_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
|
||||
* Set target0 to period mode
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_PERIOD_MODE (BIT(30))
|
||||
#define SYSTIMER_TARGET0_PERIOD_MODE_M (SYSTIMER_TARGET0_PERIOD_MODE_V << SYSTIMER_TARGET0_PERIOD_MODE_S)
|
||||
#define SYSTIMER_TARGET0_PERIOD_MODE_V 0x00000001
|
||||
#define SYSTIMER_TARGET0_PERIOD_MODE_S 30
|
||||
/** SYSTIMER_TARGET0_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
|
||||
* select which unit to compare
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL (BIT(31))
|
||||
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_M (SYSTIMER_TARGET0_TIMER_UNIT_SEL_V << SYSTIMER_TARGET0_TIMER_UNIT_SEL_S)
|
||||
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_V 0x00000001
|
||||
#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_S 31
|
||||
|
||||
/** SYSTIMER_TARGET1_CONF_REG register
|
||||
* system timer comp1 target mode register
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_CONF_REG (DR_REG_SYSTIMER_BASE + 0x38)
|
||||
/** SYSTIMER_TARGET1_PERIOD : R/W; bitpos: [25:0]; default: 0;
|
||||
* target1 period
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_PERIOD 0x03FFFFFF
|
||||
#define SYSTIMER_TARGET1_PERIOD_M (SYSTIMER_TARGET1_PERIOD_V << SYSTIMER_TARGET1_PERIOD_S)
|
||||
#define SYSTIMER_TARGET1_PERIOD_V 0x03FFFFFF
|
||||
#define SYSTIMER_TARGET1_PERIOD_S 0
|
||||
/** SYSTIMER_TARGET1_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
|
||||
* Set target1 to period mode
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_PERIOD_MODE (BIT(30))
|
||||
#define SYSTIMER_TARGET1_PERIOD_MODE_M (SYSTIMER_TARGET1_PERIOD_MODE_V << SYSTIMER_TARGET1_PERIOD_MODE_S)
|
||||
#define SYSTIMER_TARGET1_PERIOD_MODE_V 0x00000001
|
||||
#define SYSTIMER_TARGET1_PERIOD_MODE_S 30
|
||||
/** SYSTIMER_TARGET1_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
|
||||
* select which unit to compare
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL (BIT(31))
|
||||
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_M (SYSTIMER_TARGET1_TIMER_UNIT_SEL_V << SYSTIMER_TARGET1_TIMER_UNIT_SEL_S)
|
||||
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_V 0x00000001
|
||||
#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_S 31
|
||||
|
||||
/** SYSTIMER_TARGET2_CONF_REG register
|
||||
* system timer comp2 target mode register
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_CONF_REG (DR_REG_SYSTIMER_BASE + 0x3c)
|
||||
/** SYSTIMER_TARGET2_PERIOD : R/W; bitpos: [25:0]; default: 0;
|
||||
* target2 period
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_PERIOD 0x03FFFFFF
|
||||
#define SYSTIMER_TARGET2_PERIOD_M (SYSTIMER_TARGET2_PERIOD_V << SYSTIMER_TARGET2_PERIOD_S)
|
||||
#define SYSTIMER_TARGET2_PERIOD_V 0x03FFFFFF
|
||||
#define SYSTIMER_TARGET2_PERIOD_S 0
|
||||
/** SYSTIMER_TARGET2_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
|
||||
* Set target2 to period mode
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_PERIOD_MODE (BIT(30))
|
||||
#define SYSTIMER_TARGET2_PERIOD_MODE_M (SYSTIMER_TARGET2_PERIOD_MODE_V << SYSTIMER_TARGET2_PERIOD_MODE_S)
|
||||
#define SYSTIMER_TARGET2_PERIOD_MODE_V 0x00000001
|
||||
#define SYSTIMER_TARGET2_PERIOD_MODE_S 30
|
||||
/** SYSTIMER_TARGET2_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
|
||||
* select which unit to compare
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL (BIT(31))
|
||||
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_M (SYSTIMER_TARGET2_TIMER_UNIT_SEL_V << SYSTIMER_TARGET2_TIMER_UNIT_SEL_S)
|
||||
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_V 0x00000001
|
||||
#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_S 31
|
||||
|
||||
/** SYSTIMER_UNIT0_VALUE_HI_REG register
|
||||
* system timer unit0 value high register
|
||||
*/
|
||||
#define SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x40)
|
||||
/** SYSTIMER_TIMER_UNIT0_VALUE_HI : RO; bitpos: [19:0]; default: 0;
|
||||
* timer read value high 20bits
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_HI 0x000FFFFF
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_HI_M (SYSTIMER_TIMER_UNIT0_VALUE_HI_V << SYSTIMER_TIMER_UNIT0_VALUE_HI_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_HI_V 0x000FFFFF
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_HI_S 0
|
||||
|
||||
/** SYSTIMER_UNIT0_VALUE_LO_REG register
|
||||
* system timer unit0 value low register
|
||||
*/
|
||||
#define SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x44)
|
||||
/** SYSTIMER_TIMER_UNIT0_VALUE_LO : RO; bitpos: [31:0]; default: 0;
|
||||
* timer read value low 32bits
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_LO 0xFFFFFFFF
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_LO_M (SYSTIMER_TIMER_UNIT0_VALUE_LO_V << SYSTIMER_TIMER_UNIT0_VALUE_LO_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_LO_V 0xFFFFFFFF
|
||||
#define SYSTIMER_TIMER_UNIT0_VALUE_LO_S 0
|
||||
|
||||
/** SYSTIMER_UNIT1_VALUE_HI_REG register
|
||||
* system timer unit1 value high register
|
||||
*/
|
||||
#define SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x48)
|
||||
/** SYSTIMER_TIMER_UNIT1_VALUE_HI : RO; bitpos: [19:0]; default: 0;
|
||||
* timer read value high 20bits
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_HI 0x000FFFFF
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_HI_M (SYSTIMER_TIMER_UNIT1_VALUE_HI_V << SYSTIMER_TIMER_UNIT1_VALUE_HI_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_HI_V 0x000FFFFF
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_HI_S 0
|
||||
|
||||
/** SYSTIMER_UNIT1_VALUE_LO_REG register
|
||||
* system timer unit1 value low register
|
||||
*/
|
||||
#define SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x4c)
|
||||
/** SYSTIMER_TIMER_UNIT1_VALUE_LO : RO; bitpos: [31:0]; default: 0;
|
||||
* timer read value low 32bits
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_LO 0xFFFFFFFF
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_LO_M (SYSTIMER_TIMER_UNIT1_VALUE_LO_V << SYSTIMER_TIMER_UNIT1_VALUE_LO_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_LO_V 0xFFFFFFFF
|
||||
#define SYSTIMER_TIMER_UNIT1_VALUE_LO_S 0
|
||||
|
||||
/** SYSTIMER_COMP0_LOAD_REG register
|
||||
* system timer comp0 conf sync register
|
||||
*/
|
||||
#define SYSTIMER_COMP0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x50)
|
||||
/** SYSTIMER_TIMER_COMP0_LOAD : WT; bitpos: [0]; default: 0;
|
||||
* timer comp0 sync enable signal
|
||||
*/
|
||||
#define SYSTIMER_TIMER_COMP0_LOAD (BIT(0))
|
||||
#define SYSTIMER_TIMER_COMP0_LOAD_M (SYSTIMER_TIMER_COMP0_LOAD_V << SYSTIMER_TIMER_COMP0_LOAD_S)
|
||||
#define SYSTIMER_TIMER_COMP0_LOAD_V 0x00000001
|
||||
#define SYSTIMER_TIMER_COMP0_LOAD_S 0
|
||||
|
||||
/** SYSTIMER_COMP1_LOAD_REG register
|
||||
* system timer comp1 conf sync register
|
||||
*/
|
||||
#define SYSTIMER_COMP1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x54)
|
||||
/** SYSTIMER_TIMER_COMP1_LOAD : WT; bitpos: [0]; default: 0;
|
||||
* timer comp1 sync enable signal
|
||||
*/
|
||||
#define SYSTIMER_TIMER_COMP1_LOAD (BIT(0))
|
||||
#define SYSTIMER_TIMER_COMP1_LOAD_M (SYSTIMER_TIMER_COMP1_LOAD_V << SYSTIMER_TIMER_COMP1_LOAD_S)
|
||||
#define SYSTIMER_TIMER_COMP1_LOAD_V 0x00000001
|
||||
#define SYSTIMER_TIMER_COMP1_LOAD_S 0
|
||||
|
||||
/** SYSTIMER_COMP2_LOAD_REG register
|
||||
* system timer comp2 conf sync register
|
||||
*/
|
||||
#define SYSTIMER_COMP2_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x58)
|
||||
/** SYSTIMER_TIMER_COMP2_LOAD : WT; bitpos: [0]; default: 0;
|
||||
* timer comp2 sync enable signal
|
||||
*/
|
||||
#define SYSTIMER_TIMER_COMP2_LOAD (BIT(0))
|
||||
#define SYSTIMER_TIMER_COMP2_LOAD_M (SYSTIMER_TIMER_COMP2_LOAD_V << SYSTIMER_TIMER_COMP2_LOAD_S)
|
||||
#define SYSTIMER_TIMER_COMP2_LOAD_V 0x00000001
|
||||
#define SYSTIMER_TIMER_COMP2_LOAD_S 0
|
||||
|
||||
/** SYSTIMER_UNIT0_LOAD_REG register
|
||||
* system timer unit0 conf sync register
|
||||
*/
|
||||
#define SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x5c)
|
||||
/** SYSTIMER_TIMER_UNIT0_LOAD : WT; bitpos: [0]; default: 0;
|
||||
* timer unit0 sync enable signal
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD (BIT(0))
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_M (SYSTIMER_TIMER_UNIT0_LOAD_V << SYSTIMER_TIMER_UNIT0_LOAD_S)
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_V 0x00000001
|
||||
#define SYSTIMER_TIMER_UNIT0_LOAD_S 0
|
||||
|
||||
/** SYSTIMER_UNIT1_LOAD_REG register
|
||||
* system timer unit1 conf sync register
|
||||
*/
|
||||
#define SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x60)
|
||||
/** SYSTIMER_TIMER_UNIT1_LOAD : WT; bitpos: [0]; default: 0;
|
||||
* timer unit1 sync enable signal
|
||||
*/
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD (BIT(0))
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_M (SYSTIMER_TIMER_UNIT1_LOAD_V << SYSTIMER_TIMER_UNIT1_LOAD_S)
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_V 0x00000001
|
||||
#define SYSTIMER_TIMER_UNIT1_LOAD_S 0
|
||||
|
||||
/** SYSTIMER_INT_ENA_REG register
|
||||
* systimer interrupt enable register
|
||||
*/
|
||||
#define SYSTIMER_INT_ENA_REG (DR_REG_SYSTIMER_BASE + 0x64)
|
||||
/** SYSTIMER_TARGET0_INT_ENA : R/W; bitpos: [0]; default: 0;
|
||||
* interupt0 enable
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_INT_ENA (BIT(0))
|
||||
#define SYSTIMER_TARGET0_INT_ENA_M (SYSTIMER_TARGET0_INT_ENA_V << SYSTIMER_TARGET0_INT_ENA_S)
|
||||
#define SYSTIMER_TARGET0_INT_ENA_V 0x00000001
|
||||
#define SYSTIMER_TARGET0_INT_ENA_S 0
|
||||
/** SYSTIMER_TARGET1_INT_ENA : R/W; bitpos: [1]; default: 0;
|
||||
* interupt1 enable
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_INT_ENA (BIT(1))
|
||||
#define SYSTIMER_TARGET1_INT_ENA_M (SYSTIMER_TARGET1_INT_ENA_V << SYSTIMER_TARGET1_INT_ENA_S)
|
||||
#define SYSTIMER_TARGET1_INT_ENA_V 0x00000001
|
||||
#define SYSTIMER_TARGET1_INT_ENA_S 1
|
||||
/** SYSTIMER_TARGET2_INT_ENA : R/W; bitpos: [2]; default: 0;
|
||||
* interupt2 enable
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_INT_ENA (BIT(2))
|
||||
#define SYSTIMER_TARGET2_INT_ENA_M (SYSTIMER_TARGET2_INT_ENA_V << SYSTIMER_TARGET2_INT_ENA_S)
|
||||
#define SYSTIMER_TARGET2_INT_ENA_V 0x00000001
|
||||
#define SYSTIMER_TARGET2_INT_ENA_S 2
|
||||
|
||||
/** SYSTIMER_INT_RAW_REG register
|
||||
* systimer interrupt raw register
|
||||
*/
|
||||
#define SYSTIMER_INT_RAW_REG (DR_REG_SYSTIMER_BASE + 0x68)
|
||||
/** SYSTIMER_TARGET0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
|
||||
* interupt0 raw
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_INT_RAW (BIT(0))
|
||||
#define SYSTIMER_TARGET0_INT_RAW_M (SYSTIMER_TARGET0_INT_RAW_V << SYSTIMER_TARGET0_INT_RAW_S)
|
||||
#define SYSTIMER_TARGET0_INT_RAW_V 0x00000001
|
||||
#define SYSTIMER_TARGET0_INT_RAW_S 0
|
||||
/** SYSTIMER_TARGET1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
|
||||
* interupt1 raw
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_INT_RAW (BIT(1))
|
||||
#define SYSTIMER_TARGET1_INT_RAW_M (SYSTIMER_TARGET1_INT_RAW_V << SYSTIMER_TARGET1_INT_RAW_S)
|
||||
#define SYSTIMER_TARGET1_INT_RAW_V 0x00000001
|
||||
#define SYSTIMER_TARGET1_INT_RAW_S 1
|
||||
/** SYSTIMER_TARGET2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
|
||||
* interupt2 raw
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_INT_RAW (BIT(2))
|
||||
#define SYSTIMER_TARGET2_INT_RAW_M (SYSTIMER_TARGET2_INT_RAW_V << SYSTIMER_TARGET2_INT_RAW_S)
|
||||
#define SYSTIMER_TARGET2_INT_RAW_V 0x00000001
|
||||
#define SYSTIMER_TARGET2_INT_RAW_S 2
|
||||
|
||||
/** SYSTIMER_INT_CLR_REG register
|
||||
* systimer interrupt clear register
|
||||
*/
|
||||
#define SYSTIMER_INT_CLR_REG (DR_REG_SYSTIMER_BASE + 0x6c)
|
||||
/** SYSTIMER_TARGET0_INT_CLR : WT; bitpos: [0]; default: 0;
|
||||
* interupt0 clear
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_INT_CLR (BIT(0))
|
||||
#define SYSTIMER_TARGET0_INT_CLR_M (SYSTIMER_TARGET0_INT_CLR_V << SYSTIMER_TARGET0_INT_CLR_S)
|
||||
#define SYSTIMER_TARGET0_INT_CLR_V 0x00000001
|
||||
#define SYSTIMER_TARGET0_INT_CLR_S 0
|
||||
/** SYSTIMER_TARGET1_INT_CLR : WT; bitpos: [1]; default: 0;
|
||||
* interupt1 clear
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_INT_CLR (BIT(1))
|
||||
#define SYSTIMER_TARGET1_INT_CLR_M (SYSTIMER_TARGET1_INT_CLR_V << SYSTIMER_TARGET1_INT_CLR_S)
|
||||
#define SYSTIMER_TARGET1_INT_CLR_V 0x00000001
|
||||
#define SYSTIMER_TARGET1_INT_CLR_S 1
|
||||
/** SYSTIMER_TARGET2_INT_CLR : WT; bitpos: [2]; default: 0;
|
||||
* interupt2 clear
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_INT_CLR (BIT(2))
|
||||
#define SYSTIMER_TARGET2_INT_CLR_M (SYSTIMER_TARGET2_INT_CLR_V << SYSTIMER_TARGET2_INT_CLR_S)
|
||||
#define SYSTIMER_TARGET2_INT_CLR_V 0x00000001
|
||||
#define SYSTIMER_TARGET2_INT_CLR_S 2
|
||||
|
||||
/** SYSTIMER_INT_ST_REG register
|
||||
* systimer interrupt status register
|
||||
*/
|
||||
#define SYSTIMER_INT_ST_REG (DR_REG_SYSTIMER_BASE + 0x70)
|
||||
/** SYSTIMER_TARGET0_INT_ST : RO; bitpos: [0]; default: 0;
|
||||
* interupt0 status
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_INT_ST (BIT(0))
|
||||
#define SYSTIMER_TARGET0_INT_ST_M (SYSTIMER_TARGET0_INT_ST_V << SYSTIMER_TARGET0_INT_ST_S)
|
||||
#define SYSTIMER_TARGET0_INT_ST_V 0x00000001
|
||||
#define SYSTIMER_TARGET0_INT_ST_S 0
|
||||
/** SYSTIMER_TARGET1_INT_ST : RO; bitpos: [1]; default: 0;
|
||||
* interupt1 status
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_INT_ST (BIT(1))
|
||||
#define SYSTIMER_TARGET1_INT_ST_M (SYSTIMER_TARGET1_INT_ST_V << SYSTIMER_TARGET1_INT_ST_S)
|
||||
#define SYSTIMER_TARGET1_INT_ST_V 0x00000001
|
||||
#define SYSTIMER_TARGET1_INT_ST_S 1
|
||||
/** SYSTIMER_TARGET2_INT_ST : RO; bitpos: [2]; default: 0;
|
||||
* interupt2 status
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_INT_ST (BIT(2))
|
||||
#define SYSTIMER_TARGET2_INT_ST_M (SYSTIMER_TARGET2_INT_ST_V << SYSTIMER_TARGET2_INT_ST_S)
|
||||
#define SYSTIMER_TARGET2_INT_ST_V 0x00000001
|
||||
#define SYSTIMER_TARGET2_INT_ST_S 2
|
||||
|
||||
/** SYSTIMER_REAL_TARGET0_LO_REG register
|
||||
* system timer comp0 actual target value low register
|
||||
*/
|
||||
#define SYSTIMER_REAL_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x74)
|
||||
/** SYSTIMER_TARGET0_LO_RO : RO; bitpos: [31:0]; default: 0;
|
||||
* actual target value value low 32bits
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_LO_RO 0xFFFFFFFF
|
||||
#define SYSTIMER_TARGET0_LO_RO_M (SYSTIMER_TARGET0_LO_RO_V << SYSTIMER_TARGET0_LO_RO_S)
|
||||
#define SYSTIMER_TARGET0_LO_RO_V 0xFFFFFFFF
|
||||
#define SYSTIMER_TARGET0_LO_RO_S 0
|
||||
|
||||
/** SYSTIMER_REAL_TARGET0_HI_REG register
|
||||
* system timer comp0 actual target value high register
|
||||
*/
|
||||
#define SYSTIMER_REAL_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x78)
|
||||
/** SYSTIMER_TARGET0_HI_RO : RO; bitpos: [19:0]; default: 0;
|
||||
* actual target value value high 20bits
|
||||
*/
|
||||
#define SYSTIMER_TARGET0_HI_RO 0x000FFFFF
|
||||
#define SYSTIMER_TARGET0_HI_RO_M (SYSTIMER_TARGET0_HI_RO_V << SYSTIMER_TARGET0_HI_RO_S)
|
||||
#define SYSTIMER_TARGET0_HI_RO_V 0x000FFFFF
|
||||
#define SYSTIMER_TARGET0_HI_RO_S 0
|
||||
|
||||
/** SYSTIMER_REAL_TARGET1_LO_REG register
|
||||
* system timer comp1 actual target value low register
|
||||
*/
|
||||
#define SYSTIMER_REAL_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x7c)
|
||||
/** SYSTIMER_TARGET1_LO_RO : RO; bitpos: [31:0]; default: 0;
|
||||
* actual target value value low 32bits
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_LO_RO 0xFFFFFFFF
|
||||
#define SYSTIMER_TARGET1_LO_RO_M (SYSTIMER_TARGET1_LO_RO_V << SYSTIMER_TARGET1_LO_RO_S)
|
||||
#define SYSTIMER_TARGET1_LO_RO_V 0xFFFFFFFF
|
||||
#define SYSTIMER_TARGET1_LO_RO_S 0
|
||||
|
||||
/** SYSTIMER_REAL_TARGET1_HI_REG register
|
||||
* system timer comp1 actual target value high register
|
||||
*/
|
||||
#define SYSTIMER_REAL_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x80)
|
||||
/** SYSTIMER_TARGET1_HI_RO : RO; bitpos: [19:0]; default: 0;
|
||||
* actual target value value high 20bits
|
||||
*/
|
||||
#define SYSTIMER_TARGET1_HI_RO 0x000FFFFF
|
||||
#define SYSTIMER_TARGET1_HI_RO_M (SYSTIMER_TARGET1_HI_RO_V << SYSTIMER_TARGET1_HI_RO_S)
|
||||
#define SYSTIMER_TARGET1_HI_RO_V 0x000FFFFF
|
||||
#define SYSTIMER_TARGET1_HI_RO_S 0
|
||||
|
||||
/** SYSTIMER_REAL_TARGET2_LO_REG register
|
||||
* system timer comp2 actual target value low register
|
||||
*/
|
||||
#define SYSTIMER_REAL_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x84)
|
||||
/** SYSTIMER_TARGET2_LO_RO : RO; bitpos: [31:0]; default: 0;
|
||||
* actual target value value low 32bits
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_LO_RO 0xFFFFFFFF
|
||||
#define SYSTIMER_TARGET2_LO_RO_M (SYSTIMER_TARGET2_LO_RO_V << SYSTIMER_TARGET2_LO_RO_S)
|
||||
#define SYSTIMER_TARGET2_LO_RO_V 0xFFFFFFFF
|
||||
#define SYSTIMER_TARGET2_LO_RO_S 0
|
||||
|
||||
/** SYSTIMER_REAL_TARGET2_HI_REG register
|
||||
* system timer comp2 actual target value high register
|
||||
*/
|
||||
#define SYSTIMER_REAL_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x88)
|
||||
/** SYSTIMER_TARGET2_HI_RO : RO; bitpos: [19:0]; default: 0;
|
||||
* actual target value value high 20bits
|
||||
*/
|
||||
#define SYSTIMER_TARGET2_HI_RO 0x000FFFFF
|
||||
#define SYSTIMER_TARGET2_HI_RO_M (SYSTIMER_TARGET2_HI_RO_V << SYSTIMER_TARGET2_HI_RO_S)
|
||||
#define SYSTIMER_TARGET2_HI_RO_V 0x000FFFFF
|
||||
#define SYSTIMER_TARGET2_HI_RO_S 0
|
||||
|
||||
/** SYSTIMER_DATE_REG register
|
||||
* system timer version control register
|
||||
*/
|
||||
#define SYSTIMER_DATE_REG (DR_REG_SYSTIMER_BASE + 0xfc)
|
||||
/** SYSTIMER_DATE : R/W; bitpos: [31:0]; default: 33628753;
|
||||
* systimer register version
|
||||
*/
|
||||
#define SYSTIMER_DATE 0xFFFFFFFF
|
||||
#define SYSTIMER_DATE_M (SYSTIMER_DATE_V << SYSTIMER_DATE_S)
|
||||
#define SYSTIMER_DATE_V 0xFFFFFFFF
|
||||
#define SYSTIMER_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,409 +0,0 @@
|
||||
/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** SYSTEM TIMER CLK CONTROL REGISTER */
|
||||
/** Type of conf register
|
||||
* Configure system timer clock
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** systimer_clk_fo : R/W; bitpos: [0]; default: 0;
|
||||
* systimer clock force on
|
||||
*/
|
||||
uint32_t systimer_clk_fo: 1;
|
||||
uint32_t reserved_1: 21;
|
||||
/** target2_work_en : R/W; bitpos: [22]; default: 0;
|
||||
* target2 work enable
|
||||
*/
|
||||
uint32_t target2_work_en: 1;
|
||||
/** target1_work_en : R/W; bitpos: [23]; default: 0;
|
||||
* target1 work enable
|
||||
*/
|
||||
uint32_t target1_work_en: 1;
|
||||
/** target0_work_en : R/W; bitpos: [24]; default: 0;
|
||||
* target0 work enable
|
||||
*/
|
||||
uint32_t target0_work_en: 1;
|
||||
/** timer_unit1_core1_stall_en : R/W; bitpos: [25]; default: 1;
|
||||
* If timer unit1 is stalled when core1 stalled
|
||||
*/
|
||||
uint32_t timer_unit1_core1_stall_en: 1;
|
||||
/** timer_unit1_core0_stall_en : R/W; bitpos: [26]; default: 1;
|
||||
* If timer unit1 is stalled when core0 stalled
|
||||
*/
|
||||
uint32_t timer_unit1_core0_stall_en: 1;
|
||||
/** timer_unit0_core1_stall_en : R/W; bitpos: [27]; default: 0;
|
||||
* If timer unit0 is stalled when core1 stalled
|
||||
*/
|
||||
uint32_t timer_unit0_core1_stall_en: 1;
|
||||
/** timer_unit0_core0_stall_en : R/W; bitpos: [28]; default: 0;
|
||||
* If timer unit0 is stalled when core0 stalled
|
||||
*/
|
||||
uint32_t timer_unit0_core0_stall_en: 1;
|
||||
/** timer_unit1_work_en : R/W; bitpos: [29]; default: 0;
|
||||
* timer unit1 work enable
|
||||
*/
|
||||
uint32_t timer_unit1_work_en: 1;
|
||||
/** timer_unit0_work_en : R/W; bitpos: [30]; default: 1;
|
||||
* timer unit0 work enable
|
||||
*/
|
||||
uint32_t timer_unit0_work_en: 1;
|
||||
/** clk_en : R/W; bitpos: [31]; default: 0;
|
||||
* register file clk gating
|
||||
*/
|
||||
uint32_t clk_en: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_conf_reg_t;
|
||||
|
||||
|
||||
/** Type of unit_op register
|
||||
* SYSTIMER_UNIT_OP.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0: 29;
|
||||
/** timer_unit_value_valid : R/SS/WTC; bitpos: [29]; default: 0;
|
||||
* reg_timer_unit0_value_valid
|
||||
*/
|
||||
uint32_t timer_unit_value_valid: 1;
|
||||
/** timer_unit_update : WT; bitpos: [30]; default: 0;
|
||||
* update timer_unit0
|
||||
*/
|
||||
uint32_t timer_unit_update: 1;
|
||||
uint32_t reserved_32: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_unit_op_reg_t;
|
||||
|
||||
/** Type of unit_load register
|
||||
* SYSTIMER_UNIT_LOAD
|
||||
*/
|
||||
typedef struct {
|
||||
union {
|
||||
struct {
|
||||
/** timer_unit_load_hi : R/W; bitpos: [19:0]; default: 0;
|
||||
* timer unit load high 32 bit
|
||||
*/
|
||||
uint32_t timer_unit_load_hi: 20;
|
||||
uint32_t reserved_20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} hi;
|
||||
union {
|
||||
struct {
|
||||
/** timer_unit_load_lo : R/W; bitpos: [31:0]; default: 0;
|
||||
* timer unit load low 32 bit
|
||||
*/
|
||||
uint32_t timer_unit_load_lo: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} lo;
|
||||
} systimer_unit_load_val_reg_t;
|
||||
|
||||
|
||||
/** Type of target register
|
||||
* SYSTIMER_TARGET.
|
||||
*/
|
||||
typedef struct {
|
||||
union {
|
||||
struct {
|
||||
/** timer_target_hi : R/W; bitpos: [19:0]; default: 0;
|
||||
* timer target high 32 bit
|
||||
*/
|
||||
uint32_t timer_target_hi: 20;
|
||||
uint32_t reserved_20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} hi;
|
||||
union {
|
||||
struct {
|
||||
/** timer_target_lo : R/W; bitpos: [31:0]; default: 0;
|
||||
* timer target low 32 bit
|
||||
*/
|
||||
uint32_t timer_target_lo: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} lo;
|
||||
} systimer_target_val_reg_t;
|
||||
|
||||
|
||||
/** Type of target_conf register
|
||||
* SYSTIMER_TARGET_CONF.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** target_period : R/W; bitpos: [25:0]; default: 0;
|
||||
* target period
|
||||
*/
|
||||
uint32_t target_period: 26;
|
||||
uint32_t reserved_26: 4;
|
||||
/** target_period_mode : R/W; bitpos: [30]; default: 0;
|
||||
* Set target to period mode
|
||||
*/
|
||||
uint32_t target_period_mode: 1;
|
||||
/** target_timer_unit_sel : R/W; bitpos: [31]; default: 0;
|
||||
* select which unit to compare
|
||||
*/
|
||||
uint32_t target_timer_unit_sel: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_target_conf_reg_t;
|
||||
|
||||
|
||||
/** Type of unit_value_hi register
|
||||
* SYSTIMER_UNIT_VALUE_HI.
|
||||
*/
|
||||
typedef struct {
|
||||
union {
|
||||
struct {
|
||||
/** timer_unit_value_hi : RO; bitpos: [19:0]; default: 0;
|
||||
* timer read value high 20bit
|
||||
*/
|
||||
uint32_t timer_unit_value_hi: 20;
|
||||
uint32_t reserved_20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} hi;
|
||||
union {
|
||||
struct {
|
||||
/** timer_unit_value_lo : RO; bitpos: [31:0]; default: 0;
|
||||
* timer read value low 32bit
|
||||
*/
|
||||
uint32_t timer_unit_value_lo: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} lo;
|
||||
} systimer_unit_value_reg_t;
|
||||
|
||||
|
||||
/** Type of comp_load register
|
||||
* SYSTIMER_COMP_LOAD.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_comp_load : WT; bitpos: [0]; default: 0;
|
||||
* timer comp load value
|
||||
*/
|
||||
uint32_t timer_comp_load: 1;
|
||||
uint32_t reserved_1: 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_comp_load_reg_t;
|
||||
|
||||
|
||||
/** Type of unit_load register
|
||||
* SYSTIMER_UNIT_LOAD.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** timer_unit_load : WT; bitpos: [0]; default: 0;
|
||||
* timer unit load value
|
||||
*/
|
||||
uint32_t timer_unit_load: 1;
|
||||
uint32_t reserved_1: 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_unit_load_reg_t;
|
||||
|
||||
|
||||
/** SYSTEM TIMER INTERRUPT REGISTER */
|
||||
/** Type of int_ena register
|
||||
* systimer interrupt enable register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** target0_int_ena : R/W; bitpos: [0]; default: 0;
|
||||
* interupt0 enable
|
||||
*/
|
||||
uint32_t target0_int_ena: 1;
|
||||
/** target1_int_ena : R/W; bitpos: [1]; default: 0;
|
||||
* interupt1 enable
|
||||
*/
|
||||
uint32_t target1_int_ena: 1;
|
||||
/** target2_int_ena : R/W; bitpos: [2]; default: 0;
|
||||
* interupt2 enable
|
||||
*/
|
||||
uint32_t target2_int_ena: 1;
|
||||
uint32_t reserved_3: 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_int_ena_reg_t;
|
||||
|
||||
/** Type of int_raw register
|
||||
* systimer interrupt raw register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** target0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
|
||||
* interupt0 raw
|
||||
*/
|
||||
uint32_t target0_int_raw: 1;
|
||||
/** target1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
|
||||
* interupt1 raw
|
||||
*/
|
||||
uint32_t target1_int_raw: 1;
|
||||
/** target2_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
|
||||
* interupt2 raw
|
||||
*/
|
||||
uint32_t target2_int_raw: 1;
|
||||
uint32_t reserved_3: 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_int_raw_reg_t;
|
||||
|
||||
/** Type of int_clr register
|
||||
* systimer interrupt clear register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** target0_int_clr : WT; bitpos: [0]; default: 0;
|
||||
* interupt0 clear
|
||||
*/
|
||||
uint32_t target0_int_clr: 1;
|
||||
/** target1_int_clr : WT; bitpos: [1]; default: 0;
|
||||
* interupt1 clear
|
||||
*/
|
||||
uint32_t target1_int_clr: 1;
|
||||
/** target2_int_clr : WT; bitpos: [2]; default: 0;
|
||||
* interupt2 clear
|
||||
*/
|
||||
uint32_t target2_int_clr: 1;
|
||||
uint32_t reserved_3: 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_int_clr_reg_t;
|
||||
|
||||
/** Type of int_st register
|
||||
* systimer interrupt status register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** target0_int_st : RO; bitpos: [0]; default: 0;
|
||||
* interupt0 status
|
||||
*/
|
||||
uint32_t target0_int_st: 1;
|
||||
/** target1_int_st : RO; bitpos: [1]; default: 0;
|
||||
* interupt1 status
|
||||
*/
|
||||
uint32_t target1_int_st: 1;
|
||||
/** target2_int_st : RO; bitpos: [2]; default: 0;
|
||||
* interupt2 status
|
||||
*/
|
||||
uint32_t target2_int_st: 1;
|
||||
uint32_t reserved_3: 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_int_st_reg_t;
|
||||
|
||||
|
||||
/** SYSTEM TIMER COMP STATUS REGISTER
|
||||
* systimer comp actual target value low register
|
||||
*/
|
||||
typedef struct {
|
||||
union {
|
||||
struct {
|
||||
/** target_lo_ro : RO; bitpos: [31:0]; default: 0;
|
||||
* actual target value value low 32bits
|
||||
*/
|
||||
uint32_t target_lo_ro: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} lo;
|
||||
union {
|
||||
struct {
|
||||
/** target_hi_ro : RO; bitpos: [19:0]; default: 0;
|
||||
* actual target value value high 20bits
|
||||
*/
|
||||
uint32_t target_hi_ro: 20;
|
||||
uint32_t reserved_20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} hi;
|
||||
} systimer_real_target_val_reg_t;
|
||||
|
||||
|
||||
/** VERSION REGISTER */
|
||||
/** Type of date register
|
||||
* system timer version control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** date : R/W; bitpos: [31:0]; default: 33628753;
|
||||
* systimer register version
|
||||
*/
|
||||
uint32_t date: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} systimer_date_reg_t;
|
||||
|
||||
|
||||
typedef struct systimer_dev_t {
|
||||
volatile systimer_conf_reg_t conf;
|
||||
volatile systimer_unit_op_reg_t unit_op[2];
|
||||
volatile systimer_unit_load_val_reg_t unit_load_val[2];
|
||||
volatile systimer_target_val_reg_t target_val[3];
|
||||
volatile systimer_target_conf_reg_t target_conf[3];
|
||||
volatile systimer_unit_value_reg_t unit_val[2];
|
||||
volatile systimer_comp_load_reg_t comp_load[3];
|
||||
volatile systimer_unit_load_reg_t unit_load[2];
|
||||
volatile systimer_int_ena_reg_t int_ena;
|
||||
volatile systimer_int_raw_reg_t int_raw;
|
||||
volatile systimer_int_clr_reg_t int_clr;
|
||||
volatile systimer_int_st_reg_t int_st;
|
||||
volatile systimer_real_target_val_reg_t real_target_val[3];
|
||||
uint32_t reserved_08c;
|
||||
uint32_t reserved_090;
|
||||
uint32_t reserved_094;
|
||||
uint32_t reserved_098;
|
||||
uint32_t reserved_09c;
|
||||
uint32_t reserved_0a0;
|
||||
uint32_t reserved_0a4;
|
||||
uint32_t reserved_0a8;
|
||||
uint32_t reserved_0ac;
|
||||
uint32_t reserved_0b0;
|
||||
uint32_t reserved_0b4;
|
||||
uint32_t reserved_0b8;
|
||||
uint32_t reserved_0bc;
|
||||
uint32_t reserved_0c0;
|
||||
uint32_t reserved_0c4;
|
||||
uint32_t reserved_0c8;
|
||||
uint32_t reserved_0cc;
|
||||
uint32_t reserved_0d0;
|
||||
uint32_t reserved_0d4;
|
||||
uint32_t reserved_0d8;
|
||||
uint32_t reserved_0dc;
|
||||
uint32_t reserved_0e0;
|
||||
uint32_t reserved_0e4;
|
||||
uint32_t reserved_0e8;
|
||||
uint32_t reserved_0ec;
|
||||
uint32_t reserved_0f0;
|
||||
uint32_t reserved_0f4;
|
||||
uint32_t reserved_0f8;
|
||||
volatile systimer_date_reg_t date;
|
||||
} systimer_dev_t;
|
||||
|
||||
extern systimer_dev_t SYSTIMER;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,706 +0,0 @@
|
||||
/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** TIMG_T0CONFIG_REG register
|
||||
* Timer 0 configuration register
|
||||
*/
|
||||
#define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0)
|
||||
/** TIMG_T0_USE_XTAL : R/W; bitpos: [9]; default: 0;
|
||||
* 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source
|
||||
* clock of timer group.
|
||||
*/
|
||||
#define TIMG_T0_USE_XTAL (BIT(9))
|
||||
#define TIMG_T0_USE_XTAL_M (TIMG_T0_USE_XTAL_V << TIMG_T0_USE_XTAL_S)
|
||||
#define TIMG_T0_USE_XTAL_V 0x00000001U
|
||||
#define TIMG_T0_USE_XTAL_S 9
|
||||
/** TIMG_T0_ALARM_EN : R/W/SC; bitpos: [10]; default: 0;
|
||||
* When set, the alarm is enabled. This bit is automatically cleared once an
|
||||
* alarm occurs.
|
||||
*/
|
||||
#define TIMG_T0_ALARM_EN (BIT(10))
|
||||
#define TIMG_T0_ALARM_EN_M (TIMG_T0_ALARM_EN_V << TIMG_T0_ALARM_EN_S)
|
||||
#define TIMG_T0_ALARM_EN_V 0x00000001U
|
||||
#define TIMG_T0_ALARM_EN_S 10
|
||||
/** TIMG_T0_DIVIDER : R/W; bitpos: [28:13]; default: 1;
|
||||
* Timer 0 clock (T0_clk) prescaler value.
|
||||
*/
|
||||
#define TIMG_T0_DIVIDER 0x0000FFFFU
|
||||
#define TIMG_T0_DIVIDER_M (TIMG_T0_DIVIDER_V << TIMG_T0_DIVIDER_S)
|
||||
#define TIMG_T0_DIVIDER_V 0x0000FFFFU
|
||||
#define TIMG_T0_DIVIDER_S 13
|
||||
/** TIMG_T0_AUTORELOAD : R/W; bitpos: [29]; default: 1;
|
||||
* When set, timer 0 auto-reload at alarm is enabled.
|
||||
*/
|
||||
#define TIMG_T0_AUTORELOAD (BIT(29))
|
||||
#define TIMG_T0_AUTORELOAD_M (TIMG_T0_AUTORELOAD_V << TIMG_T0_AUTORELOAD_S)
|
||||
#define TIMG_T0_AUTORELOAD_V 0x00000001U
|
||||
#define TIMG_T0_AUTORELOAD_S 29
|
||||
/** TIMG_T0_INCREASE : R/W; bitpos: [30]; default: 1;
|
||||
* When set, the timer 0 time-base counter will increment every clock tick. When
|
||||
* cleared, the timer 0 time-base counter will decrement.
|
||||
*/
|
||||
#define TIMG_T0_INCREASE (BIT(30))
|
||||
#define TIMG_T0_INCREASE_M (TIMG_T0_INCREASE_V << TIMG_T0_INCREASE_S)
|
||||
#define TIMG_T0_INCREASE_V 0x00000001U
|
||||
#define TIMG_T0_INCREASE_S 30
|
||||
/** TIMG_T0_EN : R/W; bitpos: [31]; default: 0;
|
||||
* When set, the timer 0 time-base counter is enabled.
|
||||
*/
|
||||
#define TIMG_T0_EN (BIT(31))
|
||||
#define TIMG_T0_EN_M (TIMG_T0_EN_V << TIMG_T0_EN_S)
|
||||
#define TIMG_T0_EN_V 0x00000001U
|
||||
#define TIMG_T0_EN_S 31
|
||||
|
||||
/** TIMG_T0LO_REG register
|
||||
* Timer 0 current value, low 32 bits
|
||||
*/
|
||||
#define TIMG_T0LO_REG(i) (REG_TIMG_BASE(i) + 0x4)
|
||||
/** TIMG_T0_LO : RO; bitpos: [31:0]; default: 0;
|
||||
* After writing to TIMG_T0UPDATE_REG, the low 32 bits of the time-base counter
|
||||
* of timer 0 can be read here.
|
||||
*/
|
||||
#define TIMG_T0_LO 0xFFFFFFFFU
|
||||
#define TIMG_T0_LO_M (TIMG_T0_LO_V << TIMG_T0_LO_S)
|
||||
#define TIMG_T0_LO_V 0xFFFFFFFFU
|
||||
#define TIMG_T0_LO_S 0
|
||||
|
||||
/** TIMG_T0HI_REG register
|
||||
* Timer 0 current value, high 22 bits
|
||||
*/
|
||||
#define TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x8)
|
||||
/** TIMG_T0_HI : RO; bitpos: [21:0]; default: 0;
|
||||
* After writing to TIMG_T0UPDATE_REG, the high 22 bits of the time-base counter
|
||||
* of timer 0 can be read here.
|
||||
*/
|
||||
#define TIMG_T0_HI 0x003FFFFFU
|
||||
#define TIMG_T0_HI_M (TIMG_T0_HI_V << TIMG_T0_HI_S)
|
||||
#define TIMG_T0_HI_V 0x003FFFFFU
|
||||
#define TIMG_T0_HI_S 0
|
||||
|
||||
/** TIMG_T0UPDATE_REG register
|
||||
* Write to copy current timer value to TIMGn_T0_(LO/HI)_REG
|
||||
*/
|
||||
#define TIMG_T0UPDATE_REG(i) (REG_TIMG_BASE(i) + 0xc)
|
||||
/** TIMG_T0_UPDATE : R/W/SC; bitpos: [31]; default: 0;
|
||||
* After writing 0 or 1 to TIMG_T0UPDATE_REG, the counter value is latched.
|
||||
*/
|
||||
#define TIMG_T0_UPDATE (BIT(31))
|
||||
#define TIMG_T0_UPDATE_M (TIMG_T0_UPDATE_V << TIMG_T0_UPDATE_S)
|
||||
#define TIMG_T0_UPDATE_V 0x00000001U
|
||||
#define TIMG_T0_UPDATE_S 31
|
||||
|
||||
/** TIMG_T0ALARMLO_REG register
|
||||
* Timer 0 alarm value, low 32 bits
|
||||
*/
|
||||
#define TIMG_T0ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x10)
|
||||
/** TIMG_T0_ALARM_LO : R/W; bitpos: [31:0]; default: 0;
|
||||
* Timer 0 alarm trigger time-base counter value, low 32 bits.
|
||||
*/
|
||||
#define TIMG_T0_ALARM_LO 0xFFFFFFFFU
|
||||
#define TIMG_T0_ALARM_LO_M (TIMG_T0_ALARM_LO_V << TIMG_T0_ALARM_LO_S)
|
||||
#define TIMG_T0_ALARM_LO_V 0xFFFFFFFFU
|
||||
#define TIMG_T0_ALARM_LO_S 0
|
||||
|
||||
/** TIMG_T0ALARMHI_REG register
|
||||
* Timer 0 alarm value, high bits
|
||||
*/
|
||||
#define TIMG_T0ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x14)
|
||||
/** TIMG_T0_ALARM_HI : R/W; bitpos: [21:0]; default: 0;
|
||||
* Timer 0 alarm trigger time-base counter value, high 22 bits.
|
||||
*/
|
||||
#define TIMG_T0_ALARM_HI 0x003FFFFFU
|
||||
#define TIMG_T0_ALARM_HI_M (TIMG_T0_ALARM_HI_V << TIMG_T0_ALARM_HI_S)
|
||||
#define TIMG_T0_ALARM_HI_V 0x003FFFFFU
|
||||
#define TIMG_T0_ALARM_HI_S 0
|
||||
|
||||
/** TIMG_T0LOADLO_REG register
|
||||
* Timer 0 reload value, low 32 bits
|
||||
*/
|
||||
#define TIMG_T0LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x18)
|
||||
/** TIMG_T0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
|
||||
* Low 32 bits of the value that a reload will load onto timer 0 time-base
|
||||
* Counter.
|
||||
*/
|
||||
#define TIMG_T0_LOAD_LO 0xFFFFFFFFU
|
||||
#define TIMG_T0_LOAD_LO_M (TIMG_T0_LOAD_LO_V << TIMG_T0_LOAD_LO_S)
|
||||
#define TIMG_T0_LOAD_LO_V 0xFFFFFFFFU
|
||||
#define TIMG_T0_LOAD_LO_S 0
|
||||
|
||||
/** TIMG_T0LOADHI_REG register
|
||||
* Timer 0 reload value, high 22 bits
|
||||
*/
|
||||
#define TIMG_T0LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x1c)
|
||||
/** TIMG_T0_LOAD_HI : R/W; bitpos: [21:0]; default: 0;
|
||||
* High 22 bits of the value that a reload will load onto timer 0 time-base
|
||||
* counter.
|
||||
*/
|
||||
#define TIMG_T0_LOAD_HI 0x003FFFFFU
|
||||
#define TIMG_T0_LOAD_HI_M (TIMG_T0_LOAD_HI_V << TIMG_T0_LOAD_HI_S)
|
||||
#define TIMG_T0_LOAD_HI_V 0x003FFFFFU
|
||||
#define TIMG_T0_LOAD_HI_S 0
|
||||
|
||||
/** TIMG_T0LOAD_REG register
|
||||
* Write to reload timer from TIMG_T0_(LOADLOLOADHI)_REG
|
||||
*/
|
||||
#define TIMG_T0LOAD_REG(i) (REG_TIMG_BASE(i) + 0x20)
|
||||
/** TIMG_T0_LOAD : WT; bitpos: [31:0]; default: 0;
|
||||
*
|
||||
* Write any value to trigger a timer 0 time-base counter reload.
|
||||
*/
|
||||
#define TIMG_T0_LOAD 0xFFFFFFFFU
|
||||
#define TIMG_T0_LOAD_M (TIMG_T0_LOAD_V << TIMG_T0_LOAD_S)
|
||||
#define TIMG_T0_LOAD_V 0xFFFFFFFFU
|
||||
#define TIMG_T0_LOAD_S 0
|
||||
|
||||
/** TIMG_T1CONFIG_REG register
|
||||
* Timer 1 configuration register
|
||||
*/
|
||||
#define TIMG_T1CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x24)
|
||||
/** TIMG_T1_USE_XTAL : R/W; bitpos: [9]; default: 0;
|
||||
* 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source
|
||||
* clock of timer group.
|
||||
*/
|
||||
#define TIMG_T1_USE_XTAL (BIT(9))
|
||||
#define TIMG_T1_USE_XTAL_M (TIMG_T1_USE_XTAL_V << TIMG_T1_USE_XTAL_S)
|
||||
#define TIMG_T1_USE_XTAL_V 0x00000001U
|
||||
#define TIMG_T1_USE_XTAL_S 9
|
||||
/** TIMG_T1_ALARM_EN : R/W/SC; bitpos: [10]; default: 0;
|
||||
* When set, the alarm is enabled. This bit is automatically cleared once an
|
||||
* alarm occurs.
|
||||
*/
|
||||
#define TIMG_T1_ALARM_EN (BIT(10))
|
||||
#define TIMG_T1_ALARM_EN_M (TIMG_T1_ALARM_EN_V << TIMG_T1_ALARM_EN_S)
|
||||
#define TIMG_T1_ALARM_EN_V 0x00000001U
|
||||
#define TIMG_T1_ALARM_EN_S 10
|
||||
/** TIMG_T1_DIVIDER : R/W; bitpos: [28:13]; default: 1;
|
||||
* Timer 1 clock (T1_clk) prescaler value.
|
||||
*/
|
||||
#define TIMG_T1_DIVIDER 0x0000FFFFU
|
||||
#define TIMG_T1_DIVIDER_M (TIMG_T1_DIVIDER_V << TIMG_T1_DIVIDER_S)
|
||||
#define TIMG_T1_DIVIDER_V 0x0000FFFFU
|
||||
#define TIMG_T1_DIVIDER_S 13
|
||||
/** TIMG_T1_AUTORELOAD : R/W; bitpos: [29]; default: 1;
|
||||
* When set, timer 1 auto-reload at alarm is enabled.
|
||||
*/
|
||||
#define TIMG_T1_AUTORELOAD (BIT(29))
|
||||
#define TIMG_T1_AUTORELOAD_M (TIMG_T1_AUTORELOAD_V << TIMG_T1_AUTORELOAD_S)
|
||||
#define TIMG_T1_AUTORELOAD_V 0x00000001U
|
||||
#define TIMG_T1_AUTORELOAD_S 29
|
||||
/** TIMG_T1_INCREASE : R/W; bitpos: [30]; default: 1;
|
||||
* When set, the timer 1 time-base counter will increment every clock tick. When
|
||||
* cleared, the timer 1 time-base counter will decrement.
|
||||
*/
|
||||
#define TIMG_T1_INCREASE (BIT(30))
|
||||
#define TIMG_T1_INCREASE_M (TIMG_T1_INCREASE_V << TIMG_T1_INCREASE_S)
|
||||
#define TIMG_T1_INCREASE_V 0x00000001U
|
||||
#define TIMG_T1_INCREASE_S 30
|
||||
/** TIMG_T1_EN : R/W; bitpos: [31]; default: 0;
|
||||
* When set, the timer 1 time-base counter is enabled.
|
||||
*/
|
||||
#define TIMG_T1_EN (BIT(31))
|
||||
#define TIMG_T1_EN_M (TIMG_T1_EN_V << TIMG_T1_EN_S)
|
||||
#define TIMG_T1_EN_V 0x00000001U
|
||||
#define TIMG_T1_EN_S 31
|
||||
|
||||
/** TIMG_T1LO_REG register
|
||||
* Timer 1 current value, low 32 bits
|
||||
*/
|
||||
#define TIMG_T1LO_REG(i) (REG_TIMG_BASE(i) + 0x28)
|
||||
/** TIMG_T1_LO : RO; bitpos: [31:0]; default: 0;
|
||||
* After writing to TIMG_T1UPDATE_REG, the low 32 bits of the time-base counter
|
||||
* of timer 1 can be read here.
|
||||
*/
|
||||
#define TIMG_T1_LO 0xFFFFFFFFU
|
||||
#define TIMG_T1_LO_M (TIMG_T1_LO_V << TIMG_T1_LO_S)
|
||||
#define TIMG_T1_LO_V 0xFFFFFFFFU
|
||||
#define TIMG_T1_LO_S 0
|
||||
|
||||
/** TIMG_T1HI_REG register
|
||||
* Timer 1 current value, high 22 bits
|
||||
*/
|
||||
#define TIMG_T1HI_REG(i) (REG_TIMG_BASE(i) + 0x2c)
|
||||
/** TIMG_T1_HI : RO; bitpos: [21:0]; default: 0;
|
||||
* After writing to TIMG_T1UPDATE_REG, the high 22 bits of the time-base counter
|
||||
* of timer 1 can be read here.
|
||||
*/
|
||||
#define TIMG_T1_HI 0x003FFFFFU
|
||||
#define TIMG_T1_HI_M (TIMG_T1_HI_V << TIMG_T1_HI_S)
|
||||
#define TIMG_T1_HI_V 0x003FFFFFU
|
||||
#define TIMG_T1_HI_S 0
|
||||
|
||||
/** TIMG_T1UPDATE_REG register
|
||||
* Write to copy current timer value to TIMGn_T1_(LO/HI)_REG
|
||||
*/
|
||||
#define TIMG_T1UPDATE_REG(i) (REG_TIMG_BASE(i) + 0x30)
|
||||
/** TIMG_T1_UPDATE : R/W/SC; bitpos: [31]; default: 0;
|
||||
* After writing 0 or 1 to TIMG_T1UPDATE_REG, the counter value is latched.
|
||||
*/
|
||||
#define TIMG_T1_UPDATE (BIT(31))
|
||||
#define TIMG_T1_UPDATE_M (TIMG_T1_UPDATE_V << TIMG_T1_UPDATE_S)
|
||||
#define TIMG_T1_UPDATE_V 0x00000001U
|
||||
#define TIMG_T1_UPDATE_S 31
|
||||
|
||||
/** TIMG_T1ALARMLO_REG register
|
||||
* Timer 1 alarm value, low 32 bits
|
||||
*/
|
||||
#define TIMG_T1ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x34)
|
||||
/** TIMG_T1_ALARM_LO : R/W; bitpos: [31:0]; default: 0;
|
||||
* Timer 1 alarm trigger time-base counter value, low 32 bits.
|
||||
*/
|
||||
#define TIMG_T1_ALARM_LO 0xFFFFFFFFU
|
||||
#define TIMG_T1_ALARM_LO_M (TIMG_T1_ALARM_LO_V << TIMG_T1_ALARM_LO_S)
|
||||
#define TIMG_T1_ALARM_LO_V 0xFFFFFFFFU
|
||||
#define TIMG_T1_ALARM_LO_S 0
|
||||
|
||||
/** TIMG_T1ALARMHI_REG register
|
||||
* Timer 1 alarm value, high bits
|
||||
*/
|
||||
#define TIMG_T1ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x38)
|
||||
/** TIMG_T1_ALARM_HI : R/W; bitpos: [21:0]; default: 0;
|
||||
* Timer 1 alarm trigger time-base counter value, high 22 bits.
|
||||
*/
|
||||
#define TIMG_T1_ALARM_HI 0x003FFFFFU
|
||||
#define TIMG_T1_ALARM_HI_M (TIMG_T1_ALARM_HI_V << TIMG_T1_ALARM_HI_S)
|
||||
#define TIMG_T1_ALARM_HI_V 0x003FFFFFU
|
||||
#define TIMG_T1_ALARM_HI_S 0
|
||||
|
||||
/** TIMG_T1LOADLO_REG register
|
||||
* Timer 1 reload value, low 32 bits
|
||||
*/
|
||||
#define TIMG_T1LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x3c)
|
||||
/** TIMG_T1_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
|
||||
* Low 32 bits of the value that a reload will load onto timer 1 time-base
|
||||
* Counter.
|
||||
*/
|
||||
#define TIMG_T1_LOAD_LO 0xFFFFFFFFU
|
||||
#define TIMG_T1_LOAD_LO_M (TIMG_T1_LOAD_LO_V << TIMG_T1_LOAD_LO_S)
|
||||
#define TIMG_T1_LOAD_LO_V 0xFFFFFFFFU
|
||||
#define TIMG_T1_LOAD_LO_S 0
|
||||
|
||||
/** TIMG_T1LOADHI_REG register
|
||||
* Timer 1 reload value, high 22 bits
|
||||
*/
|
||||
#define TIMG_T1LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x40)
|
||||
/** TIMG_T1_LOAD_HI : R/W; bitpos: [21:0]; default: 0;
|
||||
* High 22 bits of the value that a reload will load onto timer 1 time-base
|
||||
* counter.
|
||||
*/
|
||||
#define TIMG_T1_LOAD_HI 0x003FFFFFU
|
||||
#define TIMG_T1_LOAD_HI_M (TIMG_T1_LOAD_HI_V << TIMG_T1_LOAD_HI_S)
|
||||
#define TIMG_T1_LOAD_HI_V 0x003FFFFFU
|
||||
#define TIMG_T1_LOAD_HI_S 0
|
||||
|
||||
/** TIMG_T1LOAD_REG register
|
||||
* Write to reload timer from TIMG_T1_(LOADLOLOADHI)_REG
|
||||
*/
|
||||
#define TIMG_T1LOAD_REG(i) (REG_TIMG_BASE(i) + 0x44)
|
||||
/** TIMG_T1_LOAD : WT; bitpos: [31:0]; default: 0;
|
||||
*
|
||||
* Write any value to trigger a timer 1 time-base counter reload.
|
||||
*/
|
||||
#define TIMG_T1_LOAD 0xFFFFFFFFU
|
||||
#define TIMG_T1_LOAD_M (TIMG_T1_LOAD_V << TIMG_T1_LOAD_S)
|
||||
#define TIMG_T1_LOAD_V 0xFFFFFFFFU
|
||||
#define TIMG_T1_LOAD_S 0
|
||||
|
||||
/** TIMG_WDTCONFIG0_REG register
|
||||
* Watchdog timer configuration register
|
||||
*/
|
||||
#define TIMG_WDTCONFIG0_REG(i) (REG_TIMG_BASE(i) + 0x48)
|
||||
/** TIMG_WDT_APPCPU_RESET_EN : R/W; bitpos: [12]; default: 0;
|
||||
* Reserved
|
||||
*/
|
||||
#define TIMG_WDT_APPCPU_RESET_EN (BIT(12))
|
||||
#define TIMG_WDT_APPCPU_RESET_EN_M (TIMG_WDT_APPCPU_RESET_EN_V << TIMG_WDT_APPCPU_RESET_EN_S)
|
||||
#define TIMG_WDT_APPCPU_RESET_EN_V 0x00000001U
|
||||
#define TIMG_WDT_APPCPU_RESET_EN_S 12
|
||||
/** TIMG_WDT_PROCPU_RESET_EN : R/W; bitpos: [13]; default: 0;
|
||||
* WDT reset CPU enable.
|
||||
*/
|
||||
#define TIMG_WDT_PROCPU_RESET_EN (BIT(13))
|
||||
#define TIMG_WDT_PROCPU_RESET_EN_M (TIMG_WDT_PROCPU_RESET_EN_V << TIMG_WDT_PROCPU_RESET_EN_S)
|
||||
#define TIMG_WDT_PROCPU_RESET_EN_V 0x00000001U
|
||||
#define TIMG_WDT_PROCPU_RESET_EN_S 13
|
||||
/** TIMG_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [14]; default: 1;
|
||||
* When set, Flash boot protection is enabled.
|
||||
*/
|
||||
#define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14))
|
||||
#define TIMG_WDT_FLASHBOOT_MOD_EN_M (TIMG_WDT_FLASHBOOT_MOD_EN_V << TIMG_WDT_FLASHBOOT_MOD_EN_S)
|
||||
#define TIMG_WDT_FLASHBOOT_MOD_EN_V 0x00000001U
|
||||
#define TIMG_WDT_FLASHBOOT_MOD_EN_S 14
|
||||
/** TIMG_WDT_SYS_RESET_LENGTH : R/W; bitpos: [17:15]; default: 1;
|
||||
* System reset signal length selection. 0: 100 ns, 1: 200 ns,
|
||||
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
|
||||
*/
|
||||
#define TIMG_WDT_SYS_RESET_LENGTH 0x00000007U
|
||||
#define TIMG_WDT_SYS_RESET_LENGTH_M (TIMG_WDT_SYS_RESET_LENGTH_V << TIMG_WDT_SYS_RESET_LENGTH_S)
|
||||
#define TIMG_WDT_SYS_RESET_LENGTH_V 0x00000007U
|
||||
#define TIMG_WDT_SYS_RESET_LENGTH_S 15
|
||||
/** TIMG_WDT_CPU_RESET_LENGTH : R/W; bitpos: [20:18]; default: 1;
|
||||
* CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
|
||||
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
|
||||
*/
|
||||
#define TIMG_WDT_CPU_RESET_LENGTH 0x00000007U
|
||||
#define TIMG_WDT_CPU_RESET_LENGTH_M (TIMG_WDT_CPU_RESET_LENGTH_V << TIMG_WDT_CPU_RESET_LENGTH_S)
|
||||
#define TIMG_WDT_CPU_RESET_LENGTH_V 0x00000007U
|
||||
#define TIMG_WDT_CPU_RESET_LENGTH_S 18
|
||||
/** TIMG_WDT_STG3 : R/W; bitpos: [24:23]; default: 0;
|
||||
* Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
|
||||
*/
|
||||
#define TIMG_WDT_STG3 0x00000003U
|
||||
#define TIMG_WDT_STG3_M (TIMG_WDT_STG3_V << TIMG_WDT_STG3_S)
|
||||
#define TIMG_WDT_STG3_V 0x00000003U
|
||||
#define TIMG_WDT_STG3_S 23
|
||||
/** TIMG_WDT_STG2 : R/W; bitpos: [26:25]; default: 0;
|
||||
* Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
|
||||
*/
|
||||
#define TIMG_WDT_STG2 0x00000003U
|
||||
#define TIMG_WDT_STG2_M (TIMG_WDT_STG2_V << TIMG_WDT_STG2_S)
|
||||
#define TIMG_WDT_STG2_V 0x00000003U
|
||||
#define TIMG_WDT_STG2_S 25
|
||||
/** TIMG_WDT_STG1 : R/W; bitpos: [28:27]; default: 0;
|
||||
* Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
|
||||
*/
|
||||
#define TIMG_WDT_STG1 0x00000003U
|
||||
#define TIMG_WDT_STG1_M (TIMG_WDT_STG1_V << TIMG_WDT_STG1_S)
|
||||
#define TIMG_WDT_STG1_V 0x00000003U
|
||||
#define TIMG_WDT_STG1_S 27
|
||||
/** TIMG_WDT_STG0 : R/W; bitpos: [30:29]; default: 0;
|
||||
* Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
|
||||
*/
|
||||
#define TIMG_WDT_STG0 0x00000003U
|
||||
#define TIMG_WDT_STG0_M (TIMG_WDT_STG0_V << TIMG_WDT_STG0_S)
|
||||
#define TIMG_WDT_STG0_V 0x00000003U
|
||||
#define TIMG_WDT_STG0_S 29
|
||||
/** TIMG_WDT_EN : R/W; bitpos: [31]; default: 0;
|
||||
* When set, MWDT is enabled.
|
||||
*/
|
||||
#define TIMG_WDT_EN (BIT(31))
|
||||
#define TIMG_WDT_EN_M (TIMG_WDT_EN_V << TIMG_WDT_EN_S)
|
||||
#define TIMG_WDT_EN_V 0x00000001U
|
||||
#define TIMG_WDT_EN_S 31
|
||||
|
||||
/** TIMG_WDTCONFIG1_REG register
|
||||
* Watchdog timer prescaler register
|
||||
*/
|
||||
#define TIMG_WDTCONFIG1_REG(i) (REG_TIMG_BASE(i) + 0x4c)
|
||||
/** TIMG_WDT_CLK_PRESCALE : R/W; bitpos: [31:16]; default: 1;
|
||||
* MWDT clock prescaler value. MWDT clock period = 12.5 ns *
|
||||
* TIMG_WDT_CLK_PRESCALE.
|
||||
*/
|
||||
#define TIMG_WDT_CLK_PRESCALE 0x0000FFFFU
|
||||
#define TIMG_WDT_CLK_PRESCALE_M (TIMG_WDT_CLK_PRESCALE_V << TIMG_WDT_CLK_PRESCALE_S)
|
||||
#define TIMG_WDT_CLK_PRESCALE_V 0x0000FFFFU
|
||||
#define TIMG_WDT_CLK_PRESCALE_S 16
|
||||
|
||||
/** TIMG_WDTCONFIG2_REG register
|
||||
* Watchdog timer stage 0 timeout value
|
||||
*/
|
||||
#define TIMG_WDTCONFIG2_REG(i) (REG_TIMG_BASE(i) + 0x50)
|
||||
/** TIMG_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 26000000;
|
||||
* Stage 0 timeout value, in MWDT clock cycles.
|
||||
*/
|
||||
#define TIMG_WDT_STG0_HOLD 0xFFFFFFFFU
|
||||
#define TIMG_WDT_STG0_HOLD_M (TIMG_WDT_STG0_HOLD_V << TIMG_WDT_STG0_HOLD_S)
|
||||
#define TIMG_WDT_STG0_HOLD_V 0xFFFFFFFFU
|
||||
#define TIMG_WDT_STG0_HOLD_S 0
|
||||
|
||||
/** TIMG_WDTCONFIG3_REG register
|
||||
* Watchdog timer stage 1 timeout value
|
||||
*/
|
||||
#define TIMG_WDTCONFIG3_REG(i) (REG_TIMG_BASE(i) + 0x54)
|
||||
/** TIMG_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 134217727;
|
||||
* Stage 1 timeout value, in MWDT clock cycles.
|
||||
*/
|
||||
#define TIMG_WDT_STG1_HOLD 0xFFFFFFFFU
|
||||
#define TIMG_WDT_STG1_HOLD_M (TIMG_WDT_STG1_HOLD_V << TIMG_WDT_STG1_HOLD_S)
|
||||
#define TIMG_WDT_STG1_HOLD_V 0xFFFFFFFFU
|
||||
#define TIMG_WDT_STG1_HOLD_S 0
|
||||
|
||||
/** TIMG_WDTCONFIG4_REG register
|
||||
* Watchdog timer stage 2 timeout value
|
||||
*/
|
||||
#define TIMG_WDTCONFIG4_REG(i) (REG_TIMG_BASE(i) + 0x58)
|
||||
/** TIMG_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 1048575;
|
||||
* Stage 2 timeout value, in MWDT clock cycles.
|
||||
*/
|
||||
#define TIMG_WDT_STG2_HOLD 0xFFFFFFFFU
|
||||
#define TIMG_WDT_STG2_HOLD_M (TIMG_WDT_STG2_HOLD_V << TIMG_WDT_STG2_HOLD_S)
|
||||
#define TIMG_WDT_STG2_HOLD_V 0xFFFFFFFFU
|
||||
#define TIMG_WDT_STG2_HOLD_S 0
|
||||
|
||||
/** TIMG_WDTCONFIG5_REG register
|
||||
* Watchdog timer stage 3 timeout value
|
||||
*/
|
||||
#define TIMG_WDTCONFIG5_REG(i) (REG_TIMG_BASE(i) + 0x5c)
|
||||
/** TIMG_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 1048575;
|
||||
* Stage 3 timeout value, in MWDT clock cycles.
|
||||
*/
|
||||
#define TIMG_WDT_STG3_HOLD 0xFFFFFFFFU
|
||||
#define TIMG_WDT_STG3_HOLD_M (TIMG_WDT_STG3_HOLD_V << TIMG_WDT_STG3_HOLD_S)
|
||||
#define TIMG_WDT_STG3_HOLD_V 0xFFFFFFFFU
|
||||
#define TIMG_WDT_STG3_HOLD_S 0
|
||||
|
||||
/** TIMG_WDTFEED_REG register
|
||||
* Write to feed the watchdog timer
|
||||
*/
|
||||
#define TIMG_WDTFEED_REG(i) (REG_TIMG_BASE(i) + 0x60)
|
||||
/** TIMG_WDT_FEED : WT; bitpos: [31:0]; default: 0;
|
||||
* Write any value to feed the MWDT. (WO)
|
||||
*/
|
||||
#define TIMG_WDT_FEED 0xFFFFFFFFU
|
||||
#define TIMG_WDT_FEED_M (TIMG_WDT_FEED_V << TIMG_WDT_FEED_S)
|
||||
#define TIMG_WDT_FEED_V 0xFFFFFFFFU
|
||||
#define TIMG_WDT_FEED_S 0
|
||||
|
||||
/** TIMG_WDTWPROTECT_REG register
|
||||
* Watchdog write protect register
|
||||
*/
|
||||
#define TIMG_WDTWPROTECT_REG(i) (REG_TIMG_BASE(i) + 0x64)
|
||||
/** TIMG_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065;
|
||||
* If the register contains a different value than its reset value, write
|
||||
* protection is enabled.
|
||||
*/
|
||||
#define TIMG_WDT_WKEY 0xFFFFFFFFU
|
||||
#define TIMG_WDT_WKEY_M (TIMG_WDT_WKEY_V << TIMG_WDT_WKEY_S)
|
||||
#define TIMG_WDT_WKEY_V 0xFFFFFFFFU
|
||||
#define TIMG_WDT_WKEY_S 0
|
||||
|
||||
/** TIMG_RTCCALICFG_REG register
|
||||
* RTC calibration configure register
|
||||
*/
|
||||
#define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x68)
|
||||
/** TIMG_RTC_CALI_START_CYCLING : R/W; bitpos: [12]; default: 1;
|
||||
* Reserved
|
||||
*/
|
||||
#define TIMG_RTC_CALI_START_CYCLING (BIT(12))
|
||||
#define TIMG_RTC_CALI_START_CYCLING_M (TIMG_RTC_CALI_START_CYCLING_V << TIMG_RTC_CALI_START_CYCLING_S)
|
||||
#define TIMG_RTC_CALI_START_CYCLING_V 0x00000001U
|
||||
#define TIMG_RTC_CALI_START_CYCLING_S 12
|
||||
/** TIMG_RTC_CALI_CLK_SEL : R/W; bitpos: [14:13]; default: 1;
|
||||
* 0:rtc slow clock. 1:clk_80m. 2:xtal_32k.
|
||||
*/
|
||||
#define TIMG_RTC_CALI_CLK_SEL 0x00000003U
|
||||
#define TIMG_RTC_CALI_CLK_SEL_M (TIMG_RTC_CALI_CLK_SEL_V << TIMG_RTC_CALI_CLK_SEL_S)
|
||||
#define TIMG_RTC_CALI_CLK_SEL_V 0x00000003U
|
||||
#define TIMG_RTC_CALI_CLK_SEL_S 13
|
||||
/** TIMG_RTC_CALI_RDY : RO; bitpos: [15]; default: 0;
|
||||
* Reserved
|
||||
*/
|
||||
#define TIMG_RTC_CALI_RDY (BIT(15))
|
||||
#define TIMG_RTC_CALI_RDY_M (TIMG_RTC_CALI_RDY_V << TIMG_RTC_CALI_RDY_S)
|
||||
#define TIMG_RTC_CALI_RDY_V 0x00000001U
|
||||
#define TIMG_RTC_CALI_RDY_S 15
|
||||
/** TIMG_RTC_CALI_MAX : R/W; bitpos: [30:16]; default: 1;
|
||||
* Reserved
|
||||
*/
|
||||
#define TIMG_RTC_CALI_MAX 0x00007FFFU
|
||||
#define TIMG_RTC_CALI_MAX_M (TIMG_RTC_CALI_MAX_V << TIMG_RTC_CALI_MAX_S)
|
||||
#define TIMG_RTC_CALI_MAX_V 0x00007FFFU
|
||||
#define TIMG_RTC_CALI_MAX_S 16
|
||||
/** TIMG_RTC_CALI_START : R/W; bitpos: [31]; default: 0;
|
||||
* Reserved
|
||||
*/
|
||||
#define TIMG_RTC_CALI_START (BIT(31))
|
||||
#define TIMG_RTC_CALI_START_M (TIMG_RTC_CALI_START_V << TIMG_RTC_CALI_START_S)
|
||||
#define TIMG_RTC_CALI_START_V 0x00000001U
|
||||
#define TIMG_RTC_CALI_START_S 31
|
||||
|
||||
/** TIMG_RTCCALICFG1_REG register
|
||||
* RTC calibration configure1 register
|
||||
*/
|
||||
#define TIMG_RTCCALICFG1_REG(i) (REG_TIMG_BASE(i) + 0x6c)
|
||||
/** TIMG_RTC_CALI_CYCLING_DATA_VLD : RO; bitpos: [0]; default: 0;
|
||||
* Reserved
|
||||
*/
|
||||
#define TIMG_RTC_CALI_CYCLING_DATA_VLD (BIT(0))
|
||||
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M (TIMG_RTC_CALI_CYCLING_DATA_VLD_V << TIMG_RTC_CALI_CYCLING_DATA_VLD_S)
|
||||
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_V 0x00000001U
|
||||
#define TIMG_RTC_CALI_CYCLING_DATA_VLD_S 0
|
||||
/** TIMG_RTC_CALI_VALUE : RO; bitpos: [31:7]; default: 0;
|
||||
* Reserved
|
||||
*/
|
||||
#define TIMG_RTC_CALI_VALUE 0x01FFFFFFU
|
||||
#define TIMG_RTC_CALI_VALUE_M (TIMG_RTC_CALI_VALUE_V << TIMG_RTC_CALI_VALUE_S)
|
||||
#define TIMG_RTC_CALI_VALUE_V 0x01FFFFFFU
|
||||
#define TIMG_RTC_CALI_VALUE_S 7
|
||||
|
||||
/** TIMG_INT_ENA_TIMERS_REG register
|
||||
* Interrupt enable bits
|
||||
*/
|
||||
#define TIMG_INT_ENA_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x70)
|
||||
/** TIMG_T0_INT_ENA : R/W; bitpos: [0]; default: 0;
|
||||
* The interrupt enable bit for the TIMG_T0_INT interrupt.
|
||||
*/
|
||||
#define TIMG_T0_INT_ENA (BIT(0))
|
||||
#define TIMG_T0_INT_ENA_M (TIMG_T0_INT_ENA_V << TIMG_T0_INT_ENA_S)
|
||||
#define TIMG_T0_INT_ENA_V 0x00000001U
|
||||
#define TIMG_T0_INT_ENA_S 0
|
||||
/** TIMG_T1_INT_ENA : R/W; bitpos: [1]; default: 0;
|
||||
* The interrupt enable bit for the TIMG_T1_INT interrupt.
|
||||
*/
|
||||
#define TIMG_T1_INT_ENA (BIT(1))
|
||||
#define TIMG_T1_INT_ENA_M (TIMG_T1_INT_ENA_V << TIMG_T1_INT_ENA_S)
|
||||
#define TIMG_T1_INT_ENA_V 0x00000001U
|
||||
#define TIMG_T1_INT_ENA_S 1
|
||||
/** TIMG_WDT_INT_ENA : R/W; bitpos: [2]; default: 0;
|
||||
* The interrupt enable bit for the TIMG_WDT_INT interrupt.
|
||||
*/
|
||||
#define TIMG_WDT_INT_ENA (BIT(2))
|
||||
#define TIMG_WDT_INT_ENA_M (TIMG_WDT_INT_ENA_V << TIMG_WDT_INT_ENA_S)
|
||||
#define TIMG_WDT_INT_ENA_V 0x00000001U
|
||||
#define TIMG_WDT_INT_ENA_S 2
|
||||
|
||||
/** TIMG_INT_RAW_TIMERS_REG register
|
||||
* Raw interrupt status
|
||||
*/
|
||||
#define TIMG_INT_RAW_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x74)
|
||||
/** TIMG_T0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
|
||||
* The raw interrupt status bit for the TIMG_T0_INT interrupt.
|
||||
*/
|
||||
#define TIMG_T0_INT_RAW (BIT(0))
|
||||
#define TIMG_T0_INT_RAW_M (TIMG_T0_INT_RAW_V << TIMG_T0_INT_RAW_S)
|
||||
#define TIMG_T0_INT_RAW_V 0x00000001U
|
||||
#define TIMG_T0_INT_RAW_S 0
|
||||
/** TIMG_T1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
|
||||
* The raw interrupt status bit for the TIMG_T1_INT interrupt.
|
||||
*/
|
||||
#define TIMG_T1_INT_RAW (BIT(1))
|
||||
#define TIMG_T1_INT_RAW_M (TIMG_T1_INT_RAW_V << TIMG_T1_INT_RAW_S)
|
||||
#define TIMG_T1_INT_RAW_V 0x00000001U
|
||||
#define TIMG_T1_INT_RAW_S 1
|
||||
/** TIMG_WDT_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
|
||||
* The raw interrupt status bit for the TIMG_WDT_INT interrupt.
|
||||
*/
|
||||
#define TIMG_WDT_INT_RAW (BIT(2))
|
||||
#define TIMG_WDT_INT_RAW_M (TIMG_WDT_INT_RAW_V << TIMG_WDT_INT_RAW_S)
|
||||
#define TIMG_WDT_INT_RAW_V 0x00000001U
|
||||
#define TIMG_WDT_INT_RAW_S 2
|
||||
|
||||
/** TIMG_INT_ST_TIMERS_REG register
|
||||
* Masked interrupt status
|
||||
*/
|
||||
#define TIMG_INT_ST_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x78)
|
||||
/** TIMG_T0_INT_ST : RO; bitpos: [0]; default: 0;
|
||||
* The masked interrupt status bit for the TIMG_T0_INT interrupt.
|
||||
*/
|
||||
#define TIMG_T0_INT_ST (BIT(0))
|
||||
#define TIMG_T0_INT_ST_M (TIMG_T0_INT_ST_V << TIMG_T0_INT_ST_S)
|
||||
#define TIMG_T0_INT_ST_V 0x00000001U
|
||||
#define TIMG_T0_INT_ST_S 0
|
||||
/** TIMG_T1_INT_ST : RO; bitpos: [1]; default: 0;
|
||||
* The masked interrupt status bit for the TIMG_T1_INT interrupt.
|
||||
*/
|
||||
#define TIMG_T1_INT_ST (BIT(1))
|
||||
#define TIMG_T1_INT_ST_M (TIMG_T1_INT_ST_V << TIMG_T1_INT_ST_S)
|
||||
#define TIMG_T1_INT_ST_V 0x00000001U
|
||||
#define TIMG_T1_INT_ST_S 1
|
||||
/** TIMG_WDT_INT_ST : RO; bitpos: [2]; default: 0;
|
||||
* The masked interrupt status bit for the TIMG_WDT_INT interrupt.
|
||||
*/
|
||||
#define TIMG_WDT_INT_ST (BIT(2))
|
||||
#define TIMG_WDT_INT_ST_M (TIMG_WDT_INT_ST_V << TIMG_WDT_INT_ST_S)
|
||||
#define TIMG_WDT_INT_ST_V 0x00000001U
|
||||
#define TIMG_WDT_INT_ST_S 2
|
||||
|
||||
/** TIMG_INT_CLR_TIMERS_REG register
|
||||
* Interrupt clear bits
|
||||
*/
|
||||
#define TIMG_INT_CLR_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x7c)
|
||||
/** TIMG_T0_INT_CLR : WT; bitpos: [0]; default: 0;
|
||||
* Set this bit to clear the TIMG_T0_INT interrupt.
|
||||
*/
|
||||
#define TIMG_T0_INT_CLR (BIT(0))
|
||||
#define TIMG_T0_INT_CLR_M (TIMG_T0_INT_CLR_V << TIMG_T0_INT_CLR_S)
|
||||
#define TIMG_T0_INT_CLR_V 0x00000001U
|
||||
#define TIMG_T0_INT_CLR_S 0
|
||||
/** TIMG_T1_INT_CLR : WT; bitpos: [1]; default: 0;
|
||||
* Set this bit to clear the TIMG_T1_INT interrupt.
|
||||
*/
|
||||
#define TIMG_T1_INT_CLR (BIT(1))
|
||||
#define TIMG_T1_INT_CLR_M (TIMG_T1_INT_CLR_V << TIMG_T1_INT_CLR_S)
|
||||
#define TIMG_T1_INT_CLR_V 0x00000001U
|
||||
#define TIMG_T1_INT_CLR_S 1
|
||||
/** TIMG_WDT_INT_CLR : WT; bitpos: [2]; default: 0;
|
||||
* Set this bit to clear the TIMG_WDT_INT interrupt.
|
||||
*/
|
||||
#define TIMG_WDT_INT_CLR (BIT(2))
|
||||
#define TIMG_WDT_INT_CLR_M (TIMG_WDT_INT_CLR_V << TIMG_WDT_INT_CLR_S)
|
||||
#define TIMG_WDT_INT_CLR_V 0x00000001U
|
||||
#define TIMG_WDT_INT_CLR_S 2
|
||||
|
||||
/** TIMG_RTCCALICFG2_REG register
|
||||
* Timer group calibration register
|
||||
*/
|
||||
#define TIMG_RTCCALICFG2_REG(i) (REG_TIMG_BASE(i) + 0x80)
|
||||
/** TIMG_RTC_CALI_TIMEOUT : RO; bitpos: [0]; default: 0;
|
||||
* RTC calibration timeout indicator
|
||||
*/
|
||||
#define TIMG_RTC_CALI_TIMEOUT (BIT(0))
|
||||
#define TIMG_RTC_CALI_TIMEOUT_M (TIMG_RTC_CALI_TIMEOUT_V << TIMG_RTC_CALI_TIMEOUT_S)
|
||||
#define TIMG_RTC_CALI_TIMEOUT_V 0x00000001U
|
||||
#define TIMG_RTC_CALI_TIMEOUT_S 0
|
||||
/** TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W; bitpos: [6:3]; default: 3;
|
||||
* Cycles that release calibration timeout reset
|
||||
*/
|
||||
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT 0x0000000FU
|
||||
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M (TIMG_RTC_CALI_TIMEOUT_RST_CNT_V << TIMG_RTC_CALI_TIMEOUT_RST_CNT_S)
|
||||
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V 0x0000000FU
|
||||
#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S 3
|
||||
/** TIMG_RTC_CALI_TIMEOUT_THRES : R/W; bitpos: [31:7]; default: 33554431;
|
||||
* Threshold value for the RTC calibration timer. If the calibration timer's value
|
||||
* exceeds this threshold, a timeout is triggered.
|
||||
*/
|
||||
#define TIMG_RTC_CALI_TIMEOUT_THRES 0x01FFFFFFU
|
||||
#define TIMG_RTC_CALI_TIMEOUT_THRES_M (TIMG_RTC_CALI_TIMEOUT_THRES_V << TIMG_RTC_CALI_TIMEOUT_THRES_S)
|
||||
#define TIMG_RTC_CALI_TIMEOUT_THRES_V 0x01FFFFFFU
|
||||
#define TIMG_RTC_CALI_TIMEOUT_THRES_S 7
|
||||
|
||||
/** TIMG_NTIMERS_DATE_REG register
|
||||
* Timer version control register
|
||||
*/
|
||||
#define TIMG_NTIMERS_DATE_REG(i) (REG_TIMG_BASE(i) + 0xf8)
|
||||
/** TIMG_NTIMERS_DATE : R/W; bitpos: [27:0]; default: 33566833;
|
||||
* Timer version control register
|
||||
*/
|
||||
#define TIMG_NTIMERS_DATE 0x0FFFFFFFU
|
||||
#define TIMG_NTIMERS_DATE_M (TIMG_NTIMERS_DATE_V << TIMG_NTIMERS_DATE_S)
|
||||
#define TIMG_NTIMERS_DATE_V 0x0FFFFFFFU
|
||||
#define TIMG_NTIMERS_DATE_S 0
|
||||
|
||||
/** TIMG_REGCLK_REG register
|
||||
* Timer group clock gate register
|
||||
*/
|
||||
#define TIMG_REGCLK_REG(i) (REG_TIMG_BASE(i) + 0xfc)
|
||||
/** TIMG_CLK_EN : R/W; bitpos: [31]; default: 0;
|
||||
* Register clock gate signal. 1: The clock for software to read and write registers
|
||||
* is always on. 0: The clock for software to read and write registers only exits when
|
||||
* the operation happens.
|
||||
*/
|
||||
#define TIMG_CLK_EN (BIT(31))
|
||||
#define TIMG_CLK_EN_M (TIMG_CLK_EN_V << TIMG_CLK_EN_S)
|
||||
#define TIMG_CLK_EN_V 0x00000001U
|
||||
#define TIMG_CLK_EN_S 31
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,556 +0,0 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Group: Configuration and control registers */
|
||||
/** Type of tnconfig register
|
||||
* Timer n configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0: 9;
|
||||
/** tn_use_xtal : R/W; bitpos: [9]; default: 0;
|
||||
* 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source
|
||||
* clock of timer group.
|
||||
*/
|
||||
uint32_t tn_use_xtal: 1;
|
||||
/** tn_alarm_en : R/W/SC; bitpos: [10]; default: 0;
|
||||
* When set, the alarm is enabled. This bit is automatically cleared once an
|
||||
* alarm occurs.
|
||||
*/
|
||||
uint32_t tn_alarm_en: 1;
|
||||
uint32_t reserved_11: 1;
|
||||
/** tn_divcnt_rst : WT; bitpos: [12]; default: 0;
|
||||
* When set, Timer n 's clock divider counter will be reset.
|
||||
*/
|
||||
uint32_t tn_divcnt_rst: 1;
|
||||
/** tn_divider : R/W; bitpos: [28:13]; default: 1;
|
||||
* Timer n clock (Tn_clk) prescaler value.
|
||||
*/
|
||||
uint32_t tn_divider: 16;
|
||||
/** tn_autoreload : R/W; bitpos: [29]; default: 1;
|
||||
* When set, timer n auto-reload at alarm is enabled.
|
||||
*/
|
||||
uint32_t tn_autoreload: 1;
|
||||
/** tn_increase : R/W; bitpos: [30]; default: 1;
|
||||
* When set, the timer n time-base counter will increment every clock tick. When
|
||||
* cleared, the timer n time-base counter will decrement.
|
||||
*/
|
||||
uint32_t tn_increase: 1;
|
||||
/** tn_en : R/W; bitpos: [31]; default: 0;
|
||||
* When set, the timer n time-base counter is enabled.
|
||||
*/
|
||||
uint32_t tn_en: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_tnconfig_reg_t;
|
||||
|
||||
/** Type of tnlo register
|
||||
* Timer n current value, low 32 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tn_lo : RO; bitpos: [31:0]; default: 0;
|
||||
* After writing to TIMG_TnUPDATE_REG, the low 32 bits of the time-base counter
|
||||
* of timer n can be read here.
|
||||
*/
|
||||
uint32_t tn_lo: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_tnlo_reg_t;
|
||||
|
||||
/** Type of tnhi register
|
||||
* Timer n current value, high 22 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tn_hi : RO; bitpos: [21:0]; default: 0;
|
||||
* After writing to TIMG_TnUPDATE_REG, the high 22 bits of the time-base counter
|
||||
* of timer n can be read here.
|
||||
*/
|
||||
uint32_t tn_hi: 22;
|
||||
uint32_t reserved_22: 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_tnhi_reg_t;
|
||||
|
||||
/** Type of tnupdate register
|
||||
* Write to copy current timer value to TIMGn_Tn_(LO/HI)_REG
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0: 31;
|
||||
/** tn_update : R/W/SC; bitpos: [31]; default: 0;
|
||||
* After writing 0 or 1 to TIMG_TnUPDATE_REG, the counter value is latched.
|
||||
*/
|
||||
uint32_t tn_update: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_tnupdate_reg_t;
|
||||
|
||||
/** Type of tnalarmlo register
|
||||
* Timer n alarm value, low 32 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tn_alarm_lo : R/W; bitpos: [31:0]; default: 0;
|
||||
* Timer n alarm trigger time-base counter value, low 32 bits.
|
||||
*/
|
||||
uint32_t tn_alarm_lo: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_tnalarmlo_reg_t;
|
||||
|
||||
/** Type of tnalarmhi register
|
||||
* Timer n alarm value, high bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tn_alarm_hi : R/W; bitpos: [21:0]; default: 0;
|
||||
* Timer n alarm trigger time-base counter value, high 22 bits.
|
||||
*/
|
||||
uint32_t tn_alarm_hi: 22;
|
||||
uint32_t reserved_22: 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_tnalarmhi_reg_t;
|
||||
|
||||
/** Type of tnloadlo register
|
||||
* Timer n reload value, low 32 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tn_load_lo : R/W; bitpos: [31:0]; default: 0;
|
||||
* Low 32 bits of the value that a reload will load onto timer n time-base
|
||||
* Counter.
|
||||
*/
|
||||
uint32_t tn_load_lo: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_tnloadlo_reg_t;
|
||||
|
||||
/** Type of tnloadhi register
|
||||
* Timer n reload value, high 22 bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tn_load_hi : R/W; bitpos: [21:0]; default: 0;
|
||||
* High 22 bits of the value that a reload will load onto timer n time-base
|
||||
* counter.
|
||||
*/
|
||||
uint32_t tn_load_hi: 22;
|
||||
uint32_t reserved_22: 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_tnloadhi_reg_t;
|
||||
|
||||
/** Type of tnload register
|
||||
* Write to reload timer from TIMG_Tn_(LOADLOLOADHI)_REG
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** tn_load : WT; bitpos: [31:0]; default: 0;
|
||||
*
|
||||
* Write any value to trigger a timer n time-base counter reload.
|
||||
*/
|
||||
uint32_t tn_load: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_tnload_reg_t;
|
||||
|
||||
|
||||
/** Group: Configuration and control registers for WDT */
|
||||
/** Type of wdtconfig0 register
|
||||
* Watchdog timer configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0: 12;
|
||||
/** wdt_appcpu_reset_en : R/W; bitpos: [12]; default: 0;
|
||||
* Reserved
|
||||
*/
|
||||
uint32_t wdt_appcpu_reset_en: 1;
|
||||
/** wdt_procpu_reset_en : R/W; bitpos: [13]; default: 0;
|
||||
* WDT reset CPU enable.
|
||||
*/
|
||||
uint32_t wdt_procpu_reset_en: 1;
|
||||
/** wdt_flashboot_mod_en : R/W; bitpos: [14]; default: 1;
|
||||
* When set, Flash boot protection is enabled.
|
||||
*/
|
||||
uint32_t wdt_flashboot_mod_en: 1;
|
||||
/** wdt_sys_reset_length : R/W; bitpos: [17:15]; default: 1;
|
||||
* System reset signal length selection. 0: 100 ns, 1: 200 ns,
|
||||
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
|
||||
*/
|
||||
uint32_t wdt_sys_reset_length: 3;
|
||||
/** wdt_cpu_reset_length : R/W; bitpos: [20:18]; default: 1;
|
||||
* CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
|
||||
* 2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 us, 7: 3.2 us.
|
||||
*/
|
||||
uint32_t wdt_cpu_reset_length: 3;
|
||||
uint32_t reserved_21: 2;
|
||||
/** wdt_stg3 : R/W; bitpos: [24:23]; default: 0;
|
||||
* Stage 3 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
|
||||
*/
|
||||
uint32_t wdt_stg3: 2;
|
||||
/** wdt_stg2 : R/W; bitpos: [26:25]; default: 0;
|
||||
* Stage 2 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
|
||||
*/
|
||||
uint32_t wdt_stg2: 2;
|
||||
/** wdt_stg1 : R/W; bitpos: [28:27]; default: 0;
|
||||
* Stage 1 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
|
||||
*/
|
||||
uint32_t wdt_stg1: 2;
|
||||
/** wdt_stg0 : R/W; bitpos: [30:29]; default: 0;
|
||||
* Stage 0 configuration. 0: off, 1: interrupt, 2: reset CPU, 3: reset system.
|
||||
*/
|
||||
uint32_t wdt_stg0: 2;
|
||||
/** wdt_en : R/W; bitpos: [31]; default: 0;
|
||||
* When set, MWDT is enabled.
|
||||
*/
|
||||
uint32_t wdt_en: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_wdtconfig0_reg_t;
|
||||
|
||||
/** Type of wdtconfig1 register
|
||||
* Watchdog timer prescaler register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0: 16;
|
||||
/** wdt_clk_prescale : R/W; bitpos: [31:16]; default: 1;
|
||||
* MWDT clock prescaler value. MWDT clock period = 12.5 ns *
|
||||
* TIMG_WDT_CLK_PRESCALE.
|
||||
*/
|
||||
uint32_t wdt_clk_prescale: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_wdtconfig1_reg_t;
|
||||
|
||||
/** Type of wdtconfig2 register
|
||||
* Watchdog timer stage 0 timeout value
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_stg0_hold : R/W; bitpos: [31:0]; default: 26000000;
|
||||
* Stage 0 timeout value, in MWDT clock cycles.
|
||||
*/
|
||||
uint32_t wdt_stg0_hold: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_wdtconfig2_reg_t;
|
||||
|
||||
/** Type of wdtconfig3 register
|
||||
* Watchdog timer stage 1 timeout value
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_stg1_hold : R/W; bitpos: [31:0]; default: 134217727;
|
||||
* Stage 1 timeout value, in MWDT clock cycles.
|
||||
*/
|
||||
uint32_t wdt_stg1_hold: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_wdtconfig3_reg_t;
|
||||
|
||||
/** Type of wdtconfig4 register
|
||||
* Watchdog timer stage 2 timeout value
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_stg2_hold : R/W; bitpos: [31:0]; default: 1048575;
|
||||
* Stage 2 timeout value, in MWDT clock cycles.
|
||||
*/
|
||||
uint32_t wdt_stg2_hold: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_wdtconfig4_reg_t;
|
||||
|
||||
/** Type of wdtconfig5 register
|
||||
* Watchdog timer stage 3 timeout value
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_stg3_hold : R/W; bitpos: [31:0]; default: 1048575;
|
||||
* Stage 3 timeout value, in MWDT clock cycles.
|
||||
*/
|
||||
uint32_t wdt_stg3_hold: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_wdtconfig5_reg_t;
|
||||
|
||||
/** Type of wdtfeed register
|
||||
* Write to feed the watchdog timer
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_feed : WT; bitpos: [31:0]; default: 0;
|
||||
* Write any value to feed the MWDT. (WO)
|
||||
*/
|
||||
uint32_t wdt_feed: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_wdtfeed_reg_t;
|
||||
|
||||
/** Type of wdtwprotect register
|
||||
* Watchdog write protect register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** wdt_wkey : R/W; bitpos: [31:0]; default: 1356348065;
|
||||
* If the register contains a different value than its reset value, write
|
||||
* protection is enabled.
|
||||
*/
|
||||
uint32_t wdt_wkey: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_wdtwprotect_reg_t;
|
||||
|
||||
|
||||
/** Group: Configuration and control registers for RTC CALI */
|
||||
/** Type of rtccalicfg register
|
||||
* RTC calibration configure register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0: 12;
|
||||
/** rtc_cali_start_cycling : R/W; bitpos: [12]; default: 1;
|
||||
* Reserved
|
||||
*/
|
||||
uint32_t rtc_cali_start_cycling: 1;
|
||||
/** rtc_cali_clk_sel : R/W; bitpos: [14:13]; default: 1;
|
||||
* 0:rtc slow clock. 1:clk_80m. 2:xtal_32k.
|
||||
*/
|
||||
uint32_t rtc_cali_clk_sel: 2;
|
||||
/** rtc_cali_rdy : RO; bitpos: [15]; default: 0;
|
||||
* Reserved
|
||||
*/
|
||||
uint32_t rtc_cali_rdy: 1;
|
||||
/** rtc_cali_max : R/W; bitpos: [30:16]; default: 1;
|
||||
* Reserved
|
||||
*/
|
||||
uint32_t rtc_cali_max: 15;
|
||||
/** rtc_cali_start : R/W; bitpos: [31]; default: 0;
|
||||
* Reserved
|
||||
*/
|
||||
uint32_t rtc_cali_start: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_rtccalicfg_reg_t;
|
||||
|
||||
/** Type of rtccalicfg1 register
|
||||
* RTC calibration configure1 register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** rtc_cali_cycling_data_vld : RO; bitpos: [0]; default: 0;
|
||||
* Reserved
|
||||
*/
|
||||
uint32_t rtc_cali_cycling_data_vld: 1;
|
||||
uint32_t reserved_1: 6;
|
||||
/** rtc_cali_value : RO; bitpos: [31:7]; default: 0;
|
||||
* Reserved
|
||||
*/
|
||||
uint32_t rtc_cali_value: 25;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_rtccalicfg1_reg_t;
|
||||
|
||||
/** Type of rtccalicfg2 register
|
||||
* Timer group calibration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** rtc_cali_timeout : RO; bitpos: [0]; default: 0;
|
||||
* RTC calibration timeout indicator
|
||||
*/
|
||||
uint32_t rtc_cali_timeout: 1;
|
||||
uint32_t reserved_1: 2;
|
||||
/** rtc_cali_timeout_rst_cnt : R/W; bitpos: [6:3]; default: 3;
|
||||
* Cycles that release calibration timeout reset
|
||||
*/
|
||||
uint32_t rtc_cali_timeout_rst_cnt: 4;
|
||||
/** rtc_cali_timeout_thres : R/W; bitpos: [31:7]; default: 33554431;
|
||||
* Threshold value for the RTC calibration timer. If the calibration timer's value
|
||||
* exceeds this threshold, a timeout is triggered.
|
||||
*/
|
||||
uint32_t rtc_cali_timeout_thres: 25;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_rtccalicfg2_reg_t;
|
||||
|
||||
|
||||
/** Group: Interrupt registers */
|
||||
/** Type of int_ena_timers register
|
||||
* Interrupt enable bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** t0_int_ena : R/W; bitpos: [0]; default: 0;
|
||||
* The interrupt enable bit for the TIMG_T0_INT interrupt.
|
||||
*/
|
||||
uint32_t t0_int_ena: 1;
|
||||
/** t1_int_ena : R/W; bitpos: [1]; default: 0;
|
||||
* The interrupt enable bit for the TIMG_T1_INT interrupt.
|
||||
*/
|
||||
uint32_t t1_int_ena: 1;
|
||||
/** wdt_int_ena : R/W; bitpos: [2]; default: 0;
|
||||
* The interrupt enable bit for the TIMG_WDT_INT interrupt.
|
||||
*/
|
||||
uint32_t wdt_int_ena: 1;
|
||||
uint32_t reserved_3: 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_int_ena_timers_reg_t;
|
||||
|
||||
/** Type of int_raw_timers register
|
||||
* Raw interrupt status
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** t0_int_raw : R/WTC/SS; bitpos: [0]; default: 0;
|
||||
* The raw interrupt status bit for the TIMG_T0_INT interrupt.
|
||||
*/
|
||||
uint32_t t0_int_raw: 1;
|
||||
/** t1_int_raw : R/WTC/SS; bitpos: [1]; default: 0;
|
||||
* The raw interrupt status bit for the TIMG_T1_INT interrupt.
|
||||
*/
|
||||
uint32_t t1_int_raw: 1;
|
||||
/** wdt_int_raw : R/WTC/SS; bitpos: [2]; default: 0;
|
||||
* The raw interrupt status bit for the TIMG_WDT_INT interrupt.
|
||||
*/
|
||||
uint32_t wdt_int_raw: 1;
|
||||
uint32_t reserved_3: 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_int_raw_timers_reg_t;
|
||||
|
||||
/** Type of int_st_timers register
|
||||
* Masked interrupt status
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** t0_int_st : RO; bitpos: [0]; default: 0;
|
||||
* The masked interrupt status bit for the TIMG_T0_INT interrupt.
|
||||
*/
|
||||
uint32_t t0_int_st: 1;
|
||||
/** t1_int_st : RO; bitpos: [1]; default: 0;
|
||||
* The masked interrupt status bit for the TIMG_T1_INT interrupt.
|
||||
*/
|
||||
uint32_t t1_int_st: 1;
|
||||
/** wdt_int_st : RO; bitpos: [2]; default: 0;
|
||||
* The masked interrupt status bit for the TIMG_WDT_INT interrupt.
|
||||
*/
|
||||
uint32_t wdt_int_st: 1;
|
||||
uint32_t reserved_3: 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_int_st_timers_reg_t;
|
||||
|
||||
/** Type of int_clr_timers register
|
||||
* Interrupt clear bits
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** t0_int_clr : WT; bitpos: [0]; default: 0;
|
||||
* Set this bit to clear the TIMG_T0_INT interrupt.
|
||||
*/
|
||||
uint32_t t0_int_clr: 1;
|
||||
/** t1_int_clr : WT; bitpos: [1]; default: 0;
|
||||
* Set this bit to clear the TIMG_T1_INT interrupt.
|
||||
*/
|
||||
uint32_t t1_int_clr: 1;
|
||||
/** wdt_int_clr : WT; bitpos: [2]; default: 0;
|
||||
* Set this bit to clear the TIMG_WDT_INT interrupt.
|
||||
*/
|
||||
uint32_t wdt_int_clr: 1;
|
||||
uint32_t reserved_3: 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_int_clr_timers_reg_t;
|
||||
|
||||
|
||||
/** Group: Configuration registers */
|
||||
/** Type of ntimers_date register
|
||||
* Timer version control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** ntimers_date : R/W; bitpos: [27:0]; default: 33566833;
|
||||
* Timer version control register
|
||||
*/
|
||||
uint32_t ntimers_date: 28;
|
||||
uint32_t reserved_28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_ntimers_date_reg_t;
|
||||
|
||||
/** Type of regclk register
|
||||
* Timer group clock gate register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0: 31;
|
||||
/** clk_en : R/W; bitpos: [31]; default: 0;
|
||||
* Register clock gate signal. 1: The clock for software to read and write registers
|
||||
* is always on. 0: The clock for software to read and write registers only exits when
|
||||
* the operation happens.
|
||||
*/
|
||||
uint32_t clk_en: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} timg_regclk_reg_t;
|
||||
|
||||
typedef struct {
|
||||
volatile timg_tnconfig_reg_t config;
|
||||
volatile timg_tnlo_reg_t lo;
|
||||
volatile timg_tnhi_reg_t hi;
|
||||
volatile timg_tnupdate_reg_t update;
|
||||
volatile timg_tnalarmlo_reg_t alarmlo;
|
||||
volatile timg_tnalarmhi_reg_t alarmhi;
|
||||
volatile timg_tnloadlo_reg_t loadlo;
|
||||
volatile timg_tnloadhi_reg_t loadhi;
|
||||
volatile timg_tnload_reg_t load;
|
||||
} timg_hwtimer_reg_t;
|
||||
|
||||
typedef struct timg_dev_t {
|
||||
volatile timg_hwtimer_reg_t hw_timer[2];
|
||||
volatile timg_wdtconfig0_reg_t wdtconfig0;
|
||||
volatile timg_wdtconfig1_reg_t wdtconfig1;
|
||||
volatile timg_wdtconfig2_reg_t wdtconfig2;
|
||||
volatile timg_wdtconfig3_reg_t wdtconfig3;
|
||||
volatile timg_wdtconfig4_reg_t wdtconfig4;
|
||||
volatile timg_wdtconfig5_reg_t wdtconfig5;
|
||||
volatile timg_wdtfeed_reg_t wdtfeed;
|
||||
volatile timg_wdtwprotect_reg_t wdtwprotect;
|
||||
volatile timg_rtccalicfg_reg_t rtccalicfg;
|
||||
volatile timg_rtccalicfg1_reg_t rtccalicfg1;
|
||||
volatile timg_int_ena_timers_reg_t int_ena_timers;
|
||||
volatile timg_int_raw_timers_reg_t int_raw_timers;
|
||||
volatile timg_int_st_timers_reg_t int_st_timers;
|
||||
volatile timg_int_clr_timers_reg_t int_clr_timers;
|
||||
volatile timg_rtccalicfg2_reg_t rtccalicfg2;
|
||||
uint32_t reserved_084[29];
|
||||
volatile timg_ntimers_date_reg_t ntimers_date;
|
||||
volatile timg_regclk_reg_t regclk;
|
||||
} timg_dev_t;
|
||||
|
||||
extern timg_dev_t TIMERG0;
|
||||
extern timg_dev_t TIMERG1;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(timg_dev_t) == 0x100, "Invalid size of timg_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,210 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/* ---------------------------- Register Layout ------------------------------ */
|
||||
|
||||
/* The TWAI peripheral's registers are 8bits, however the ESP32-S3 can only access
|
||||
* peripheral registers every 32bits. Therefore each TWAI register is mapped to
|
||||
* the least significant byte of every 32bits.
|
||||
*/
|
||||
|
||||
typedef volatile struct twai_dev_s {
|
||||
//Configuration and Control Registers
|
||||
union {
|
||||
struct {
|
||||
uint32_t rm: 1; /* MOD.0 Reset Mode */
|
||||
uint32_t lom: 1; /* MOD.1 Listen Only Mode */
|
||||
uint32_t stm: 1; /* MOD.2 Self Test Mode */
|
||||
uint32_t afm: 1; /* MOD.3 Acceptance Filter Mode */
|
||||
uint32_t reserved4: 28; /* Internal Reserved. MOD.4 Sleep Mode not supported */
|
||||
};
|
||||
uint32_t val;
|
||||
} mode_reg; /* Address 0x0000 */
|
||||
union {
|
||||
struct {
|
||||
uint32_t tr: 1; /* CMR.0 Transmission Request */
|
||||
uint32_t at: 1; /* CMR.1 Abort Transmission */
|
||||
uint32_t rrb: 1; /* CMR.2 Release Receive Buffer */
|
||||
uint32_t cdo: 1; /* CMR.3 Clear Data Overrun */
|
||||
uint32_t srr: 1; /* CMR.4 Self Reception Request */
|
||||
uint32_t reserved5: 27; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} command_reg; /* Address 0x0004 */
|
||||
union {
|
||||
struct {
|
||||
uint32_t rbs: 1; /* SR.0 Receive Buffer Status */
|
||||
uint32_t dos: 1; /* SR.1 Data Overrun Status */
|
||||
uint32_t tbs: 1; /* SR.2 Transmit Buffer Status */
|
||||
uint32_t tcs: 1; /* SR.3 Transmission Complete Status */
|
||||
uint32_t rs: 1; /* SR.4 Receive Status */
|
||||
uint32_t ts: 1; /* SR.5 Transmit Status */
|
||||
uint32_t es: 1; /* SR.6 Error Status */
|
||||
uint32_t bs: 1; /* SR.7 Bus Status */
|
||||
uint32_t ms: 1; /* SR.8 Miss Status */
|
||||
uint32_t reserved9: 23; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} status_reg; /* Address 0x0008 */
|
||||
union {
|
||||
struct {
|
||||
uint32_t ri: 1; /* IR.0 Receive Interrupt */
|
||||
uint32_t ti: 1; /* IR.1 Transmit Interrupt */
|
||||
uint32_t ei: 1; /* IR.2 Error Interrupt */
|
||||
uint32_t doi: 1; /* IR.3 Data Overrun Interrupt */
|
||||
uint32_t reserved4: 1; /* Internal Reserved (Wake-up not supported) */
|
||||
uint32_t epi: 1; /* IR.5 Error Passive Interrupt */
|
||||
uint32_t ali: 1; /* IR.6 Arbitration Lost Interrupt */
|
||||
uint32_t bei: 1; /* IR.7 Bus Error Interrupt */
|
||||
uint32_t reserved8: 24; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} interrupt_reg; /* Address 0x000C */
|
||||
union {
|
||||
struct {
|
||||
uint32_t rie: 1; /* IER.0 Receive Interrupt Enable */
|
||||
uint32_t tie: 1; /* IER.1 Transmit Interrupt Enable */
|
||||
uint32_t eie: 1; /* IER.2 Error Interrupt Enable */
|
||||
uint32_t doie: 1; /* IER.3 Data Overrun Interrupt Enable */
|
||||
uint32_t reserved4: 1; /* Internal Reserved (Wake-up not supported) */
|
||||
uint32_t epie: 1; /* IER.5 Error Passive Interrupt Enable */
|
||||
uint32_t alie: 1; /* IER.6 Arbitration Lost Interrupt Enable */
|
||||
uint32_t beie: 1; /* IER.7 Bus Error Interrupt Enable */
|
||||
uint32_t reserved8: 24; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} interrupt_enable_reg; /* Address 0x0010 */
|
||||
uint32_t reserved_14;
|
||||
union {
|
||||
struct {
|
||||
uint32_t brp: 13; /* BTR0[12:0] Baud Rate Prescaler */
|
||||
uint32_t reserved13: 1; /* Internal Reserved */
|
||||
uint32_t sjw: 2; /* BTR0[15:14] Synchronization Jump Width*/
|
||||
uint32_t reserved16: 16; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} bus_timing_0_reg; /* Address 0x0018 */
|
||||
union {
|
||||
struct {
|
||||
uint32_t tseg1: 4; /* BTR1[3:0] Timing Segment 1 */
|
||||
uint32_t tseg2: 3; /* BTR1[6:4] Timing Segment 2 */
|
||||
uint32_t sam: 1; /* BTR1.7 Sampling*/
|
||||
uint32_t reserved8: 24; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} bus_timing_1_reg; /* Address 0x001C */
|
||||
uint32_t reserved_20; /* Address 0x0020 (Output control not supported) */
|
||||
uint32_t reserved_24; /* Address 0x0024 (Test Register not supported) */
|
||||
uint32_t reserved_28; /* Address 0x0028 */
|
||||
|
||||
//Capture and Counter Registers
|
||||
union {
|
||||
struct {
|
||||
uint32_t alc: 5; /* ALC[4:0] Arbitration lost capture */
|
||||
uint32_t reserved5: 27; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} arbitration_lost_captue_reg; /* Address 0x002C */
|
||||
union {
|
||||
struct {
|
||||
uint32_t seg: 5; /* ECC[4:0] Error Code Segment 0 to 5 */
|
||||
uint32_t dir: 1; /* ECC.5 Error Direction (TX/RX) */
|
||||
uint32_t errc: 2; /* ECC[7:6] Error Code */
|
||||
uint32_t reserved8: 24; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} error_code_capture_reg; /* Address 0x0030 */
|
||||
union {
|
||||
struct {
|
||||
uint32_t ewl: 8; /* EWL[7:0] Error Warning Limit */
|
||||
uint32_t reserved8: 24; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} error_warning_limit_reg; /* Address 0x0034 */
|
||||
union {
|
||||
struct {
|
||||
uint32_t rxerr: 8; /* RXERR[7:0] Receive Error Counter */
|
||||
uint32_t reserved8: 24; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} rx_error_counter_reg; /* Address 0x0038 */
|
||||
union {
|
||||
struct {
|
||||
uint32_t txerr: 8; /* TXERR[7:0] Receive Error Counter */
|
||||
uint32_t reserved8: 24; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} tx_error_counter_reg; /* Address 0x003C */
|
||||
|
||||
//Shared Registers (TX Buff/RX Buff/Acc Filter)
|
||||
union {
|
||||
struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t byte: 8; /* ACRx[7:0] Acceptance Code */
|
||||
uint32_t reserved8: 24; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} acr[4];
|
||||
union {
|
||||
struct {
|
||||
uint32_t byte: 8; /* AMRx[7:0] Acceptance Mask */
|
||||
uint32_t reserved8: 24; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} amr[4];
|
||||
uint32_t reserved_60;
|
||||
uint32_t reserved_64;
|
||||
uint32_t reserved_68;
|
||||
uint32_t reserved_6c;
|
||||
uint32_t reserved_70;
|
||||
} acceptance_filter;
|
||||
union {
|
||||
struct {
|
||||
uint32_t byte: 8; /* TX/RX Byte X [7:0] */
|
||||
uint32_t reserved24: 24; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} tx_rx_buffer[13];
|
||||
}; /* Address 0x0040 - 0x0070 */
|
||||
|
||||
//Misc Registers
|
||||
union {
|
||||
struct {
|
||||
uint32_t rmc: 7; /* RMC[6:0] RX Message Counter */
|
||||
uint32_t reserved7: 25; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} rx_message_counter_reg; /* Address 0x0074 */
|
||||
uint32_t reserved_78; /* Address 0x0078 (RX Buffer Start Address not supported) */
|
||||
union {
|
||||
struct {
|
||||
uint32_t cd: 8; /* CDR[7:0] CLKOUT frequency selector based of fOSC */
|
||||
uint32_t co: 1; /* CDR.8 CLKOUT enable/disable */
|
||||
uint32_t reserved9: 23; /* Internal Reserved */
|
||||
};
|
||||
uint32_t val;
|
||||
} clock_divider_reg; /* Address 0x007C */
|
||||
} twai_dev_t;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(twai_dev_t) == 128, "TWAI registers should be 32 * 4 bytes");
|
||||
#endif
|
||||
|
||||
extern twai_dev_t TWAI;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,764 +0,0 @@
|
||||
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_UHCI_REG_H_
|
||||
#define _SOC_UHCI_REG_H_
|
||||
|
||||
|
||||
#include "soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define UHCI_CONF0_REG(i) (REG_UHCI_BASE(i) + 0x0)
|
||||
/* UHCI_UART_RX_BRK_EOF_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_UART_RX_BRK_EOF_EN (BIT(12))
|
||||
#define UHCI_UART_RX_BRK_EOF_EN_M (BIT(12))
|
||||
#define UHCI_UART_RX_BRK_EOF_EN_V 0x1
|
||||
#define UHCI_UART_RX_BRK_EOF_EN_S 12
|
||||
/* UHCI_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_CLK_EN (BIT(11))
|
||||
#define UHCI_CLK_EN_M (BIT(11))
|
||||
#define UHCI_CLK_EN_V 0x1
|
||||
#define UHCI_CLK_EN_S 11
|
||||
/* UHCI_ENCODE_CRC_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_ENCODE_CRC_EN (BIT(10))
|
||||
#define UHCI_ENCODE_CRC_EN_M (BIT(10))
|
||||
#define UHCI_ENCODE_CRC_EN_V 0x1
|
||||
#define UHCI_ENCODE_CRC_EN_S 10
|
||||
/* UHCI_LEN_EOF_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_LEN_EOF_EN (BIT(9))
|
||||
#define UHCI_LEN_EOF_EN_M (BIT(9))
|
||||
#define UHCI_LEN_EOF_EN_V 0x1
|
||||
#define UHCI_LEN_EOF_EN_S 9
|
||||
/* UHCI_UART_IDLE_EOF_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_UART_IDLE_EOF_EN (BIT(8))
|
||||
#define UHCI_UART_IDLE_EOF_EN_M (BIT(8))
|
||||
#define UHCI_UART_IDLE_EOF_EN_V 0x1
|
||||
#define UHCI_UART_IDLE_EOF_EN_S 8
|
||||
/* UHCI_CRC_REC_EN : R/W ;bitpos:[7] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_CRC_REC_EN (BIT(7))
|
||||
#define UHCI_CRC_REC_EN_M (BIT(7))
|
||||
#define UHCI_CRC_REC_EN_V 0x1
|
||||
#define UHCI_CRC_REC_EN_S 7
|
||||
/* UHCI_HEAD_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_HEAD_EN (BIT(6))
|
||||
#define UHCI_HEAD_EN_M (BIT(6))
|
||||
#define UHCI_HEAD_EN_V 0x1
|
||||
#define UHCI_HEAD_EN_S 6
|
||||
/* UHCI_SEPER_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_SEPER_EN (BIT(5))
|
||||
#define UHCI_SEPER_EN_M (BIT(5))
|
||||
#define UHCI_SEPER_EN_V 0x1
|
||||
#define UHCI_SEPER_EN_S 5
|
||||
/* UHCI_UART2_CE : R/W ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_UART2_CE (BIT(4))
|
||||
#define UHCI_UART2_CE_M (BIT(4))
|
||||
#define UHCI_UART2_CE_V 0x1
|
||||
#define UHCI_UART2_CE_S 4
|
||||
/* UHCI_UART1_CE : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_UART1_CE (BIT(3))
|
||||
#define UHCI_UART1_CE_M (BIT(3))
|
||||
#define UHCI_UART1_CE_V 0x1
|
||||
#define UHCI_UART1_CE_S 3
|
||||
/* UHCI_UART0_CE : R/W ;bitpos:[2] ;default: 1'h0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_UART0_CE (BIT(2))
|
||||
#define UHCI_UART0_CE_M (BIT(2))
|
||||
#define UHCI_UART0_CE_V 0x1
|
||||
#define UHCI_UART0_CE_S 2
|
||||
/* UHCI_RX_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_RX_RST (BIT(1))
|
||||
#define UHCI_RX_RST_M (BIT(1))
|
||||
#define UHCI_RX_RST_V 0x1
|
||||
#define UHCI_RX_RST_S 1
|
||||
/* UHCI_TX_RST : R/W ;bitpos:[0] ;default: 1'h0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_TX_RST (BIT(0))
|
||||
#define UHCI_TX_RST_M (BIT(0))
|
||||
#define UHCI_TX_RST_V 0x1
|
||||
#define UHCI_TX_RST_S 0
|
||||
|
||||
#define UHCI_INT_RAW_REG(i) (REG_UHCI_BASE(i) + 0x4)
|
||||
/* UHCI_APP_CTRL1_INT_RAW : R/W ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_APP_CTRL1_INT_RAW (BIT(8))
|
||||
#define UHCI_APP_CTRL1_INT_RAW_M (BIT(8))
|
||||
#define UHCI_APP_CTRL1_INT_RAW_V 0x1
|
||||
#define UHCI_APP_CTRL1_INT_RAW_S 8
|
||||
/* UHCI_APP_CTRL0_INT_RAW : R/W ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_APP_CTRL0_INT_RAW (BIT(7))
|
||||
#define UHCI_APP_CTRL0_INT_RAW_M (BIT(7))
|
||||
#define UHCI_APP_CTRL0_INT_RAW_V 0x1
|
||||
#define UHCI_APP_CTRL0_INT_RAW_S 7
|
||||
/* UHCI_OUTLINK_EOF_ERR_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_OUTLINK_EOF_ERR_INT_RAW (BIT(6))
|
||||
#define UHCI_OUTLINK_EOF_ERR_INT_RAW_M (BIT(6))
|
||||
#define UHCI_OUTLINK_EOF_ERR_INT_RAW_V 0x1
|
||||
#define UHCI_OUTLINK_EOF_ERR_INT_RAW_S 6
|
||||
/* UHCI_SEND_A_Q_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_SEND_A_Q_INT_RAW (BIT(5))
|
||||
#define UHCI_SEND_A_Q_INT_RAW_M (BIT(5))
|
||||
#define UHCI_SEND_A_Q_INT_RAW_V 0x1
|
||||
#define UHCI_SEND_A_Q_INT_RAW_S 5
|
||||
/* UHCI_SEND_S_Q_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_SEND_S_Q_INT_RAW (BIT(4))
|
||||
#define UHCI_SEND_S_Q_INT_RAW_M (BIT(4))
|
||||
#define UHCI_SEND_S_Q_INT_RAW_V 0x1
|
||||
#define UHCI_SEND_S_Q_INT_RAW_S 4
|
||||
/* UHCI_TX_HUNG_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_TX_HUNG_INT_RAW (BIT(3))
|
||||
#define UHCI_TX_HUNG_INT_RAW_M (BIT(3))
|
||||
#define UHCI_TX_HUNG_INT_RAW_V 0x1
|
||||
#define UHCI_TX_HUNG_INT_RAW_S 3
|
||||
/* UHCI_RX_HUNG_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_RX_HUNG_INT_RAW (BIT(2))
|
||||
#define UHCI_RX_HUNG_INT_RAW_M (BIT(2))
|
||||
#define UHCI_RX_HUNG_INT_RAW_V 0x1
|
||||
#define UHCI_RX_HUNG_INT_RAW_S 2
|
||||
/* UHCI_TX_START_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_TX_START_INT_RAW (BIT(1))
|
||||
#define UHCI_TX_START_INT_RAW_M (BIT(1))
|
||||
#define UHCI_TX_START_INT_RAW_V 0x1
|
||||
#define UHCI_TX_START_INT_RAW_S 1
|
||||
/* UHCI_RX_START_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_RX_START_INT_RAW (BIT(0))
|
||||
#define UHCI_RX_START_INT_RAW_M (BIT(0))
|
||||
#define UHCI_RX_START_INT_RAW_V 0x1
|
||||
#define UHCI_RX_START_INT_RAW_S 0
|
||||
|
||||
#define UHCI_INT_ST_REG(i) (REG_UHCI_BASE(i) + 0x8)
|
||||
/* UHCI_APP_CTRL1_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_APP_CTRL1_INT_ST (BIT(8))
|
||||
#define UHCI_APP_CTRL1_INT_ST_M (BIT(8))
|
||||
#define UHCI_APP_CTRL1_INT_ST_V 0x1
|
||||
#define UHCI_APP_CTRL1_INT_ST_S 8
|
||||
/* UHCI_APP_CTRL0_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_APP_CTRL0_INT_ST (BIT(7))
|
||||
#define UHCI_APP_CTRL0_INT_ST_M (BIT(7))
|
||||
#define UHCI_APP_CTRL0_INT_ST_V 0x1
|
||||
#define UHCI_APP_CTRL0_INT_ST_S 7
|
||||
/* UHCI_OUTLINK_EOF_ERR_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_OUTLINK_EOF_ERR_INT_ST (BIT(6))
|
||||
#define UHCI_OUTLINK_EOF_ERR_INT_ST_M (BIT(6))
|
||||
#define UHCI_OUTLINK_EOF_ERR_INT_ST_V 0x1
|
||||
#define UHCI_OUTLINK_EOF_ERR_INT_ST_S 6
|
||||
/* UHCI_SEND_A_Q_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_SEND_A_Q_INT_ST (BIT(5))
|
||||
#define UHCI_SEND_A_Q_INT_ST_M (BIT(5))
|
||||
#define UHCI_SEND_A_Q_INT_ST_V 0x1
|
||||
#define UHCI_SEND_A_Q_INT_ST_S 5
|
||||
/* UHCI_SEND_S_Q_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_SEND_S_Q_INT_ST (BIT(4))
|
||||
#define UHCI_SEND_S_Q_INT_ST_M (BIT(4))
|
||||
#define UHCI_SEND_S_Q_INT_ST_V 0x1
|
||||
#define UHCI_SEND_S_Q_INT_ST_S 4
|
||||
/* UHCI_TX_HUNG_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_TX_HUNG_INT_ST (BIT(3))
|
||||
#define UHCI_TX_HUNG_INT_ST_M (BIT(3))
|
||||
#define UHCI_TX_HUNG_INT_ST_V 0x1
|
||||
#define UHCI_TX_HUNG_INT_ST_S 3
|
||||
/* UHCI_RX_HUNG_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_RX_HUNG_INT_ST (BIT(2))
|
||||
#define UHCI_RX_HUNG_INT_ST_M (BIT(2))
|
||||
#define UHCI_RX_HUNG_INT_ST_V 0x1
|
||||
#define UHCI_RX_HUNG_INT_ST_S 2
|
||||
/* UHCI_TX_START_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_TX_START_INT_ST (BIT(1))
|
||||
#define UHCI_TX_START_INT_ST_M (BIT(1))
|
||||
#define UHCI_TX_START_INT_ST_V 0x1
|
||||
#define UHCI_TX_START_INT_ST_S 1
|
||||
/* UHCI_RX_START_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_RX_START_INT_ST (BIT(0))
|
||||
#define UHCI_RX_START_INT_ST_M (BIT(0))
|
||||
#define UHCI_RX_START_INT_ST_V 0x1
|
||||
#define UHCI_RX_START_INT_ST_S 0
|
||||
|
||||
#define UHCI_INT_ENA_REG(i) (REG_UHCI_BASE(i) + 0xC)
|
||||
/* UHCI_APP_CTRL1_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_APP_CTRL1_INT_ENA (BIT(8))
|
||||
#define UHCI_APP_CTRL1_INT_ENA_M (BIT(8))
|
||||
#define UHCI_APP_CTRL1_INT_ENA_V 0x1
|
||||
#define UHCI_APP_CTRL1_INT_ENA_S 8
|
||||
/* UHCI_APP_CTRL0_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_APP_CTRL0_INT_ENA (BIT(7))
|
||||
#define UHCI_APP_CTRL0_INT_ENA_M (BIT(7))
|
||||
#define UHCI_APP_CTRL0_INT_ENA_V 0x1
|
||||
#define UHCI_APP_CTRL0_INT_ENA_S 7
|
||||
/* UHCI_OUTLINK_EOF_ERR_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_OUTLINK_EOF_ERR_INT_ENA (BIT(6))
|
||||
#define UHCI_OUTLINK_EOF_ERR_INT_ENA_M (BIT(6))
|
||||
#define UHCI_OUTLINK_EOF_ERR_INT_ENA_V 0x1
|
||||
#define UHCI_OUTLINK_EOF_ERR_INT_ENA_S 6
|
||||
/* UHCI_SEND_A_Q_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_SEND_A_Q_INT_ENA (BIT(5))
|
||||
#define UHCI_SEND_A_Q_INT_ENA_M (BIT(5))
|
||||
#define UHCI_SEND_A_Q_INT_ENA_V 0x1
|
||||
#define UHCI_SEND_A_Q_INT_ENA_S 5
|
||||
/* UHCI_SEND_S_Q_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_SEND_S_Q_INT_ENA (BIT(4))
|
||||
#define UHCI_SEND_S_Q_INT_ENA_M (BIT(4))
|
||||
#define UHCI_SEND_S_Q_INT_ENA_V 0x1
|
||||
#define UHCI_SEND_S_Q_INT_ENA_S 4
|
||||
/* UHCI_TX_HUNG_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_TX_HUNG_INT_ENA (BIT(3))
|
||||
#define UHCI_TX_HUNG_INT_ENA_M (BIT(3))
|
||||
#define UHCI_TX_HUNG_INT_ENA_V 0x1
|
||||
#define UHCI_TX_HUNG_INT_ENA_S 3
|
||||
/* UHCI_RX_HUNG_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_RX_HUNG_INT_ENA (BIT(2))
|
||||
#define UHCI_RX_HUNG_INT_ENA_M (BIT(2))
|
||||
#define UHCI_RX_HUNG_INT_ENA_V 0x1
|
||||
#define UHCI_RX_HUNG_INT_ENA_S 2
|
||||
/* UHCI_TX_START_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_TX_START_INT_ENA (BIT(1))
|
||||
#define UHCI_TX_START_INT_ENA_M (BIT(1))
|
||||
#define UHCI_TX_START_INT_ENA_V 0x1
|
||||
#define UHCI_TX_START_INT_ENA_S 1
|
||||
/* UHCI_RX_START_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_RX_START_INT_ENA (BIT(0))
|
||||
#define UHCI_RX_START_INT_ENA_M (BIT(0))
|
||||
#define UHCI_RX_START_INT_ENA_V 0x1
|
||||
#define UHCI_RX_START_INT_ENA_S 0
|
||||
|
||||
#define UHCI_INT_CLR_REG(i) (REG_UHCI_BASE(i) + 0x10)
|
||||
/* UHCI_APP_CTRL1_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_APP_CTRL1_INT_CLR (BIT(8))
|
||||
#define UHCI_APP_CTRL1_INT_CLR_M (BIT(8))
|
||||
#define UHCI_APP_CTRL1_INT_CLR_V 0x1
|
||||
#define UHCI_APP_CTRL1_INT_CLR_S 8
|
||||
/* UHCI_APP_CTRL0_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_APP_CTRL0_INT_CLR (BIT(7))
|
||||
#define UHCI_APP_CTRL0_INT_CLR_M (BIT(7))
|
||||
#define UHCI_APP_CTRL0_INT_CLR_V 0x1
|
||||
#define UHCI_APP_CTRL0_INT_CLR_S 7
|
||||
/* UHCI_OUTLINK_EOF_ERR_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_OUTLINK_EOF_ERR_INT_CLR (BIT(6))
|
||||
#define UHCI_OUTLINK_EOF_ERR_INT_CLR_M (BIT(6))
|
||||
#define UHCI_OUTLINK_EOF_ERR_INT_CLR_V 0x1
|
||||
#define UHCI_OUTLINK_EOF_ERR_INT_CLR_S 6
|
||||
/* UHCI_SEND_A_Q_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_SEND_A_Q_INT_CLR (BIT(5))
|
||||
#define UHCI_SEND_A_Q_INT_CLR_M (BIT(5))
|
||||
#define UHCI_SEND_A_Q_INT_CLR_V 0x1
|
||||
#define UHCI_SEND_A_Q_INT_CLR_S 5
|
||||
/* UHCI_SEND_S_Q_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_SEND_S_Q_INT_CLR (BIT(4))
|
||||
#define UHCI_SEND_S_Q_INT_CLR_M (BIT(4))
|
||||
#define UHCI_SEND_S_Q_INT_CLR_V 0x1
|
||||
#define UHCI_SEND_S_Q_INT_CLR_S 4
|
||||
/* UHCI_TX_HUNG_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_TX_HUNG_INT_CLR (BIT(3))
|
||||
#define UHCI_TX_HUNG_INT_CLR_M (BIT(3))
|
||||
#define UHCI_TX_HUNG_INT_CLR_V 0x1
|
||||
#define UHCI_TX_HUNG_INT_CLR_S 3
|
||||
/* UHCI_RX_HUNG_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_RX_HUNG_INT_CLR (BIT(2))
|
||||
#define UHCI_RX_HUNG_INT_CLR_M (BIT(2))
|
||||
#define UHCI_RX_HUNG_INT_CLR_V 0x1
|
||||
#define UHCI_RX_HUNG_INT_CLR_S 2
|
||||
/* UHCI_TX_START_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_TX_START_INT_CLR (BIT(1))
|
||||
#define UHCI_TX_START_INT_CLR_M (BIT(1))
|
||||
#define UHCI_TX_START_INT_CLR_V 0x1
|
||||
#define UHCI_TX_START_INT_CLR_S 1
|
||||
/* UHCI_RX_START_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_RX_START_INT_CLR (BIT(0))
|
||||
#define UHCI_RX_START_INT_CLR_M (BIT(0))
|
||||
#define UHCI_RX_START_INT_CLR_V 0x1
|
||||
#define UHCI_RX_START_INT_CLR_S 0
|
||||
|
||||
#define UHCI_APP_INT_SET_REG(i) (REG_UHCI_BASE(i) + 0x14)
|
||||
/* UHCI_APP_CTRL1_INT_SET : WO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_APP_CTRL1_INT_SET (BIT(1))
|
||||
#define UHCI_APP_CTRL1_INT_SET_M (BIT(1))
|
||||
#define UHCI_APP_CTRL1_INT_SET_V 0x1
|
||||
#define UHCI_APP_CTRL1_INT_SET_S 1
|
||||
/* UHCI_APP_CTRL0_INT_SET : WO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_APP_CTRL0_INT_SET (BIT(0))
|
||||
#define UHCI_APP_CTRL0_INT_SET_M (BIT(0))
|
||||
#define UHCI_APP_CTRL0_INT_SET_V 0x1
|
||||
#define UHCI_APP_CTRL0_INT_SET_S 0
|
||||
|
||||
#define UHCI_CONF1_REG(i) (REG_UHCI_BASE(i) + 0x18)
|
||||
/* UHCI_SW_START : R/W ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_SW_START (BIT(8))
|
||||
#define UHCI_SW_START_M (BIT(8))
|
||||
#define UHCI_SW_START_V 0x1
|
||||
#define UHCI_SW_START_S 8
|
||||
/* UHCI_WAIT_SW_START : R/W ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_WAIT_SW_START (BIT(7))
|
||||
#define UHCI_WAIT_SW_START_M (BIT(7))
|
||||
#define UHCI_WAIT_SW_START_V 0x1
|
||||
#define UHCI_WAIT_SW_START_S 7
|
||||
/* UHCI_TX_ACK_NUM_RE : R/W ;bitpos:[5] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_TX_ACK_NUM_RE (BIT(5))
|
||||
#define UHCI_TX_ACK_NUM_RE_M (BIT(5))
|
||||
#define UHCI_TX_ACK_NUM_RE_V 0x1
|
||||
#define UHCI_TX_ACK_NUM_RE_S 5
|
||||
/* UHCI_TX_CHECK_SUM_RE : R/W ;bitpos:[4] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_TX_CHECK_SUM_RE (BIT(4))
|
||||
#define UHCI_TX_CHECK_SUM_RE_M (BIT(4))
|
||||
#define UHCI_TX_CHECK_SUM_RE_V 0x1
|
||||
#define UHCI_TX_CHECK_SUM_RE_S 4
|
||||
/* UHCI_SAVE_HEAD : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_SAVE_HEAD (BIT(3))
|
||||
#define UHCI_SAVE_HEAD_M (BIT(3))
|
||||
#define UHCI_SAVE_HEAD_V 0x1
|
||||
#define UHCI_SAVE_HEAD_S 3
|
||||
/* UHCI_CRC_DISABLE : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_CRC_DISABLE (BIT(2))
|
||||
#define UHCI_CRC_DISABLE_M (BIT(2))
|
||||
#define UHCI_CRC_DISABLE_V 0x1
|
||||
#define UHCI_CRC_DISABLE_S 2
|
||||
/* UHCI_CHECK_SEQ_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_CHECK_SEQ_EN (BIT(1))
|
||||
#define UHCI_CHECK_SEQ_EN_M (BIT(1))
|
||||
#define UHCI_CHECK_SEQ_EN_V 0x1
|
||||
#define UHCI_CHECK_SEQ_EN_S 1
|
||||
/* UHCI_CHECK_SUM_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_CHECK_SUM_EN (BIT(0))
|
||||
#define UHCI_CHECK_SUM_EN_M (BIT(0))
|
||||
#define UHCI_CHECK_SUM_EN_V 0x1
|
||||
#define UHCI_CHECK_SUM_EN_S 0
|
||||
|
||||
#define UHCI_STATE0_REG(i) (REG_UHCI_BASE(i) + 0x1C)
|
||||
/* UHCI_DECODE_STATE : RO ;bitpos:[5:3] ;default: 3'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_DECODE_STATE 0x00000007
|
||||
#define UHCI_DECODE_STATE_M ((UHCI_DECODE_STATE_V)<<(UHCI_DECODE_STATE_S))
|
||||
#define UHCI_DECODE_STATE_V 0x7
|
||||
#define UHCI_DECODE_STATE_S 3
|
||||
/* UHCI_RX_ERR_CAUSE : RO ;bitpos:[2:0] ;default: 3'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_RX_ERR_CAUSE 0x00000007
|
||||
#define UHCI_RX_ERR_CAUSE_M ((UHCI_RX_ERR_CAUSE_V)<<(UHCI_RX_ERR_CAUSE_S))
|
||||
#define UHCI_RX_ERR_CAUSE_V 0x7
|
||||
#define UHCI_RX_ERR_CAUSE_S 0
|
||||
|
||||
#define UHCI_STATE1_REG(i) (REG_UHCI_BASE(i) + 0x20)
|
||||
/* UHCI_ENCODE_STATE : RO ;bitpos:[2:0] ;default: 3'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_ENCODE_STATE 0x00000007
|
||||
#define UHCI_ENCODE_STATE_M ((UHCI_ENCODE_STATE_V)<<(UHCI_ENCODE_STATE_S))
|
||||
#define UHCI_ENCODE_STATE_V 0x7
|
||||
#define UHCI_ENCODE_STATE_S 0
|
||||
|
||||
#define UHCI_ESCAPE_CONF_REG(i) (REG_UHCI_BASE(i) + 0x24)
|
||||
/* UHCI_RX_13_ESC_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_RX_13_ESC_EN (BIT(7))
|
||||
#define UHCI_RX_13_ESC_EN_M (BIT(7))
|
||||
#define UHCI_RX_13_ESC_EN_V 0x1
|
||||
#define UHCI_RX_13_ESC_EN_S 7
|
||||
/* UHCI_RX_11_ESC_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_RX_11_ESC_EN (BIT(6))
|
||||
#define UHCI_RX_11_ESC_EN_M (BIT(6))
|
||||
#define UHCI_RX_11_ESC_EN_V 0x1
|
||||
#define UHCI_RX_11_ESC_EN_S 6
|
||||
/* UHCI_RX_DB_ESC_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_RX_DB_ESC_EN (BIT(5))
|
||||
#define UHCI_RX_DB_ESC_EN_M (BIT(5))
|
||||
#define UHCI_RX_DB_ESC_EN_V 0x1
|
||||
#define UHCI_RX_DB_ESC_EN_S 5
|
||||
/* UHCI_RX_C0_ESC_EN : R/W ;bitpos:[4] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_RX_C0_ESC_EN (BIT(4))
|
||||
#define UHCI_RX_C0_ESC_EN_M (BIT(4))
|
||||
#define UHCI_RX_C0_ESC_EN_V 0x1
|
||||
#define UHCI_RX_C0_ESC_EN_S 4
|
||||
/* UHCI_TX_13_ESC_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_TX_13_ESC_EN (BIT(3))
|
||||
#define UHCI_TX_13_ESC_EN_M (BIT(3))
|
||||
#define UHCI_TX_13_ESC_EN_V 0x1
|
||||
#define UHCI_TX_13_ESC_EN_S 3
|
||||
/* UHCI_TX_11_ESC_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_TX_11_ESC_EN (BIT(2))
|
||||
#define UHCI_TX_11_ESC_EN_M (BIT(2))
|
||||
#define UHCI_TX_11_ESC_EN_V 0x1
|
||||
#define UHCI_TX_11_ESC_EN_S 2
|
||||
/* UHCI_TX_DB_ESC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_TX_DB_ESC_EN (BIT(1))
|
||||
#define UHCI_TX_DB_ESC_EN_M (BIT(1))
|
||||
#define UHCI_TX_DB_ESC_EN_V 0x1
|
||||
#define UHCI_TX_DB_ESC_EN_S 1
|
||||
/* UHCI_TX_C0_ESC_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_TX_C0_ESC_EN (BIT(0))
|
||||
#define UHCI_TX_C0_ESC_EN_M (BIT(0))
|
||||
#define UHCI_TX_C0_ESC_EN_V 0x1
|
||||
#define UHCI_TX_C0_ESC_EN_S 0
|
||||
|
||||
#define UHCI_HUNG_CONF_REG(i) (REG_UHCI_BASE(i) + 0x28)
|
||||
/* UHCI_RXFIFO_TIMEOUT_ENA : R/W ;bitpos:[23] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_RXFIFO_TIMEOUT_ENA (BIT(23))
|
||||
#define UHCI_RXFIFO_TIMEOUT_ENA_M (BIT(23))
|
||||
#define UHCI_RXFIFO_TIMEOUT_ENA_V 0x1
|
||||
#define UHCI_RXFIFO_TIMEOUT_ENA_S 23
|
||||
/* UHCI_RXFIFO_TIMEOUT_SHIFT : R/W ;bitpos:[22:20] ;default: 3'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_RXFIFO_TIMEOUT_SHIFT 0x00000007
|
||||
#define UHCI_RXFIFO_TIMEOUT_SHIFT_M ((UHCI_RXFIFO_TIMEOUT_SHIFT_V)<<(UHCI_RXFIFO_TIMEOUT_SHIFT_S))
|
||||
#define UHCI_RXFIFO_TIMEOUT_SHIFT_V 0x7
|
||||
#define UHCI_RXFIFO_TIMEOUT_SHIFT_S 20
|
||||
/* UHCI_RXFIFO_TIMEOUT : R/W ;bitpos:[19:12] ;default: 8'h10 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_RXFIFO_TIMEOUT 0x000000FF
|
||||
#define UHCI_RXFIFO_TIMEOUT_M ((UHCI_RXFIFO_TIMEOUT_V)<<(UHCI_RXFIFO_TIMEOUT_S))
|
||||
#define UHCI_RXFIFO_TIMEOUT_V 0xFF
|
||||
#define UHCI_RXFIFO_TIMEOUT_S 12
|
||||
/* UHCI_TXFIFO_TIMEOUT_ENA : R/W ;bitpos:[11] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_TXFIFO_TIMEOUT_ENA (BIT(11))
|
||||
#define UHCI_TXFIFO_TIMEOUT_ENA_M (BIT(11))
|
||||
#define UHCI_TXFIFO_TIMEOUT_ENA_V 0x1
|
||||
#define UHCI_TXFIFO_TIMEOUT_ENA_S 11
|
||||
/* UHCI_TXFIFO_TIMEOUT_SHIFT : R/W ;bitpos:[10:8] ;default: 3'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_TXFIFO_TIMEOUT_SHIFT 0x00000007
|
||||
#define UHCI_TXFIFO_TIMEOUT_SHIFT_M ((UHCI_TXFIFO_TIMEOUT_SHIFT_V)<<(UHCI_TXFIFO_TIMEOUT_SHIFT_S))
|
||||
#define UHCI_TXFIFO_TIMEOUT_SHIFT_V 0x7
|
||||
#define UHCI_TXFIFO_TIMEOUT_SHIFT_S 8
|
||||
/* UHCI_TXFIFO_TIMEOUT : R/W ;bitpos:[7:0] ;default: 8'h10 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_TXFIFO_TIMEOUT 0x000000FF
|
||||
#define UHCI_TXFIFO_TIMEOUT_M ((UHCI_TXFIFO_TIMEOUT_V)<<(UHCI_TXFIFO_TIMEOUT_S))
|
||||
#define UHCI_TXFIFO_TIMEOUT_V 0xFF
|
||||
#define UHCI_TXFIFO_TIMEOUT_S 0
|
||||
|
||||
#define UHCI_ACK_NUM_REG(i) (REG_UHCI_BASE(i) + 0x2C)
|
||||
/* UHCI_ACK_NUM_LOAD : WO ;bitpos:[3] ;default: 1'b1 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_ACK_NUM_LOAD (BIT(3))
|
||||
#define UHCI_ACK_NUM_LOAD_M (BIT(3))
|
||||
#define UHCI_ACK_NUM_LOAD_V 0x1
|
||||
#define UHCI_ACK_NUM_LOAD_S 3
|
||||
/* UHCI_ACK_NUM : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_ACK_NUM 0x00000007
|
||||
#define UHCI_ACK_NUM_M ((UHCI_ACK_NUM_V)<<(UHCI_ACK_NUM_S))
|
||||
#define UHCI_ACK_NUM_V 0x7
|
||||
#define UHCI_ACK_NUM_S 0
|
||||
|
||||
#define UHCI_RX_HEAD_REG(i) (REG_UHCI_BASE(i) + 0x30)
|
||||
/* UHCI_RX_HEAD : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_RX_HEAD 0xFFFFFFFF
|
||||
#define UHCI_RX_HEAD_M ((UHCI_RX_HEAD_V)<<(UHCI_RX_HEAD_S))
|
||||
#define UHCI_RX_HEAD_V 0xFFFFFFFF
|
||||
#define UHCI_RX_HEAD_S 0
|
||||
|
||||
#define UHCI_QUICK_SENT_REG(i) (REG_UHCI_BASE(i) + 0x34)
|
||||
/* UHCI_ALWAYS_SEND_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_ALWAYS_SEND_EN (BIT(7))
|
||||
#define UHCI_ALWAYS_SEND_EN_M (BIT(7))
|
||||
#define UHCI_ALWAYS_SEND_EN_V 0x1
|
||||
#define UHCI_ALWAYS_SEND_EN_S 7
|
||||
/* UHCI_ALWAYS_SEND_NUM : R/W ;bitpos:[6:4] ;default: 3'h0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_ALWAYS_SEND_NUM 0x00000007
|
||||
#define UHCI_ALWAYS_SEND_NUM_M ((UHCI_ALWAYS_SEND_NUM_V)<<(UHCI_ALWAYS_SEND_NUM_S))
|
||||
#define UHCI_ALWAYS_SEND_NUM_V 0x7
|
||||
#define UHCI_ALWAYS_SEND_NUM_S 4
|
||||
/* UHCI_SINGLE_SEND_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_SINGLE_SEND_EN (BIT(3))
|
||||
#define UHCI_SINGLE_SEND_EN_M (BIT(3))
|
||||
#define UHCI_SINGLE_SEND_EN_V 0x1
|
||||
#define UHCI_SINGLE_SEND_EN_S 3
|
||||
/* UHCI_SINGLE_SEND_NUM : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_SINGLE_SEND_NUM 0x00000007
|
||||
#define UHCI_SINGLE_SEND_NUM_M ((UHCI_SINGLE_SEND_NUM_V)<<(UHCI_SINGLE_SEND_NUM_S))
|
||||
#define UHCI_SINGLE_SEND_NUM_V 0x7
|
||||
#define UHCI_SINGLE_SEND_NUM_S 0
|
||||
|
||||
#define UHCI_Q0_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x38)
|
||||
/* UHCI_SEND_Q0_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_SEND_Q0_WORD0 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q0_WORD0_M ((UHCI_SEND_Q0_WORD0_V)<<(UHCI_SEND_Q0_WORD0_S))
|
||||
#define UHCI_SEND_Q0_WORD0_V 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q0_WORD0_S 0
|
||||
|
||||
#define UHCI_Q0_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x3C)
|
||||
/* UHCI_SEND_Q0_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_SEND_Q0_WORD1 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q0_WORD1_M ((UHCI_SEND_Q0_WORD1_V)<<(UHCI_SEND_Q0_WORD1_S))
|
||||
#define UHCI_SEND_Q0_WORD1_V 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q0_WORD1_S 0
|
||||
|
||||
#define UHCI_Q1_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x40)
|
||||
/* UHCI_SEND_Q1_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_SEND_Q1_WORD0 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q1_WORD0_M ((UHCI_SEND_Q1_WORD0_V)<<(UHCI_SEND_Q1_WORD0_S))
|
||||
#define UHCI_SEND_Q1_WORD0_V 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q1_WORD0_S 0
|
||||
|
||||
#define UHCI_Q1_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x44)
|
||||
/* UHCI_SEND_Q1_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_SEND_Q1_WORD1 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q1_WORD1_M ((UHCI_SEND_Q1_WORD1_V)<<(UHCI_SEND_Q1_WORD1_S))
|
||||
#define UHCI_SEND_Q1_WORD1_V 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q1_WORD1_S 0
|
||||
|
||||
#define UHCI_Q2_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x48)
|
||||
/* UHCI_SEND_Q2_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_SEND_Q2_WORD0 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q2_WORD0_M ((UHCI_SEND_Q2_WORD0_V)<<(UHCI_SEND_Q2_WORD0_S))
|
||||
#define UHCI_SEND_Q2_WORD0_V 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q2_WORD0_S 0
|
||||
|
||||
#define UHCI_Q2_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x4C)
|
||||
/* UHCI_SEND_Q2_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_SEND_Q2_WORD1 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q2_WORD1_M ((UHCI_SEND_Q2_WORD1_V)<<(UHCI_SEND_Q2_WORD1_S))
|
||||
#define UHCI_SEND_Q2_WORD1_V 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q2_WORD1_S 0
|
||||
|
||||
#define UHCI_Q3_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x50)
|
||||
/* UHCI_SEND_Q3_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_SEND_Q3_WORD0 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q3_WORD0_M ((UHCI_SEND_Q3_WORD0_V)<<(UHCI_SEND_Q3_WORD0_S))
|
||||
#define UHCI_SEND_Q3_WORD0_V 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q3_WORD0_S 0
|
||||
|
||||
#define UHCI_Q3_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x54)
|
||||
/* UHCI_SEND_Q3_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_SEND_Q3_WORD1 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q3_WORD1_M ((UHCI_SEND_Q3_WORD1_V)<<(UHCI_SEND_Q3_WORD1_S))
|
||||
#define UHCI_SEND_Q3_WORD1_V 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q3_WORD1_S 0
|
||||
|
||||
#define UHCI_Q4_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x58)
|
||||
/* UHCI_SEND_Q4_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_SEND_Q4_WORD0 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q4_WORD0_M ((UHCI_SEND_Q4_WORD0_V)<<(UHCI_SEND_Q4_WORD0_S))
|
||||
#define UHCI_SEND_Q4_WORD0_V 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q4_WORD0_S 0
|
||||
|
||||
#define UHCI_Q4_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x5C)
|
||||
/* UHCI_SEND_Q4_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_SEND_Q4_WORD1 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q4_WORD1_M ((UHCI_SEND_Q4_WORD1_V)<<(UHCI_SEND_Q4_WORD1_S))
|
||||
#define UHCI_SEND_Q4_WORD1_V 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q4_WORD1_S 0
|
||||
|
||||
#define UHCI_Q5_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x60)
|
||||
/* UHCI_SEND_Q5_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_SEND_Q5_WORD0 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q5_WORD0_M ((UHCI_SEND_Q5_WORD0_V)<<(UHCI_SEND_Q5_WORD0_S))
|
||||
#define UHCI_SEND_Q5_WORD0_V 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q5_WORD0_S 0
|
||||
|
||||
#define UHCI_Q5_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x64)
|
||||
/* UHCI_SEND_Q5_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_SEND_Q5_WORD1 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q5_WORD1_M ((UHCI_SEND_Q5_WORD1_V)<<(UHCI_SEND_Q5_WORD1_S))
|
||||
#define UHCI_SEND_Q5_WORD1_V 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q5_WORD1_S 0
|
||||
|
||||
#define UHCI_Q6_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x68)
|
||||
/* UHCI_SEND_Q6_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_SEND_Q6_WORD0 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q6_WORD0_M ((UHCI_SEND_Q6_WORD0_V)<<(UHCI_SEND_Q6_WORD0_S))
|
||||
#define UHCI_SEND_Q6_WORD0_V 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q6_WORD0_S 0
|
||||
|
||||
#define UHCI_Q6_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x6C)
|
||||
/* UHCI_SEND_Q6_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_SEND_Q6_WORD1 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q6_WORD1_M ((UHCI_SEND_Q6_WORD1_V)<<(UHCI_SEND_Q6_WORD1_S))
|
||||
#define UHCI_SEND_Q6_WORD1_V 0xFFFFFFFF
|
||||
#define UHCI_SEND_Q6_WORD1_S 0
|
||||
|
||||
#define UHCI_ESC_CONF0_REG(i) (REG_UHCI_BASE(i) + 0x70)
|
||||
/* UHCI_SEPER_ESC_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdc ; */
|
||||
/*description: .*/
|
||||
#define UHCI_SEPER_ESC_CHAR1 0x000000FF
|
||||
#define UHCI_SEPER_ESC_CHAR1_M ((UHCI_SEPER_ESC_CHAR1_V)<<(UHCI_SEPER_ESC_CHAR1_S))
|
||||
#define UHCI_SEPER_ESC_CHAR1_V 0xFF
|
||||
#define UHCI_SEPER_ESC_CHAR1_S 16
|
||||
/* UHCI_SEPER_ESC_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */
|
||||
/*description: .*/
|
||||
#define UHCI_SEPER_ESC_CHAR0 0x000000FF
|
||||
#define UHCI_SEPER_ESC_CHAR0_M ((UHCI_SEPER_ESC_CHAR0_V)<<(UHCI_SEPER_ESC_CHAR0_S))
|
||||
#define UHCI_SEPER_ESC_CHAR0_V 0xFF
|
||||
#define UHCI_SEPER_ESC_CHAR0_S 8
|
||||
/* UHCI_SEPER_CHAR : R/W ;bitpos:[7:0] ;default: 8'hc0 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_SEPER_CHAR 0x000000FF
|
||||
#define UHCI_SEPER_CHAR_M ((UHCI_SEPER_CHAR_V)<<(UHCI_SEPER_CHAR_S))
|
||||
#define UHCI_SEPER_CHAR_V 0xFF
|
||||
#define UHCI_SEPER_CHAR_S 0
|
||||
|
||||
#define UHCI_ESC_CONF1_REG(i) (REG_UHCI_BASE(i) + 0x74)
|
||||
/* UHCI_ESC_SEQ0_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdd ; */
|
||||
/*description: .*/
|
||||
#define UHCI_ESC_SEQ0_CHAR1 0x000000FF
|
||||
#define UHCI_ESC_SEQ0_CHAR1_M ((UHCI_ESC_SEQ0_CHAR1_V)<<(UHCI_ESC_SEQ0_CHAR1_S))
|
||||
#define UHCI_ESC_SEQ0_CHAR1_V 0xFF
|
||||
#define UHCI_ESC_SEQ0_CHAR1_S 16
|
||||
/* UHCI_ESC_SEQ0_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */
|
||||
/*description: .*/
|
||||
#define UHCI_ESC_SEQ0_CHAR0 0x000000FF
|
||||
#define UHCI_ESC_SEQ0_CHAR0_M ((UHCI_ESC_SEQ0_CHAR0_V)<<(UHCI_ESC_SEQ0_CHAR0_S))
|
||||
#define UHCI_ESC_SEQ0_CHAR0_V 0xFF
|
||||
#define UHCI_ESC_SEQ0_CHAR0_S 8
|
||||
/* UHCI_ESC_SEQ0 : R/W ;bitpos:[7:0] ;default: 8'hdb ; */
|
||||
/*description: .*/
|
||||
#define UHCI_ESC_SEQ0 0x000000FF
|
||||
#define UHCI_ESC_SEQ0_M ((UHCI_ESC_SEQ0_V)<<(UHCI_ESC_SEQ0_S))
|
||||
#define UHCI_ESC_SEQ0_V 0xFF
|
||||
#define UHCI_ESC_SEQ0_S 0
|
||||
|
||||
#define UHCI_ESC_CONF2_REG(i) (REG_UHCI_BASE(i) + 0x78)
|
||||
/* UHCI_ESC_SEQ1_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hde ; */
|
||||
/*description: .*/
|
||||
#define UHCI_ESC_SEQ1_CHAR1 0x000000FF
|
||||
#define UHCI_ESC_SEQ1_CHAR1_M ((UHCI_ESC_SEQ1_CHAR1_V)<<(UHCI_ESC_SEQ1_CHAR1_S))
|
||||
#define UHCI_ESC_SEQ1_CHAR1_V 0xFF
|
||||
#define UHCI_ESC_SEQ1_CHAR1_S 16
|
||||
/* UHCI_ESC_SEQ1_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */
|
||||
/*description: .*/
|
||||
#define UHCI_ESC_SEQ1_CHAR0 0x000000FF
|
||||
#define UHCI_ESC_SEQ1_CHAR0_M ((UHCI_ESC_SEQ1_CHAR0_V)<<(UHCI_ESC_SEQ1_CHAR0_S))
|
||||
#define UHCI_ESC_SEQ1_CHAR0_V 0xFF
|
||||
#define UHCI_ESC_SEQ1_CHAR0_S 8
|
||||
/* UHCI_ESC_SEQ1 : R/W ;bitpos:[7:0] ;default: 8'h11 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_ESC_SEQ1 0x000000FF
|
||||
#define UHCI_ESC_SEQ1_M ((UHCI_ESC_SEQ1_V)<<(UHCI_ESC_SEQ1_S))
|
||||
#define UHCI_ESC_SEQ1_V 0xFF
|
||||
#define UHCI_ESC_SEQ1_S 0
|
||||
|
||||
#define UHCI_ESC_CONF3_REG(i) (REG_UHCI_BASE(i) + 0x7C)
|
||||
/* UHCI_ESC_SEQ2_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdf ; */
|
||||
/*description: .*/
|
||||
#define UHCI_ESC_SEQ2_CHAR1 0x000000FF
|
||||
#define UHCI_ESC_SEQ2_CHAR1_M ((UHCI_ESC_SEQ2_CHAR1_V)<<(UHCI_ESC_SEQ2_CHAR1_S))
|
||||
#define UHCI_ESC_SEQ2_CHAR1_V 0xFF
|
||||
#define UHCI_ESC_SEQ2_CHAR1_S 16
|
||||
/* UHCI_ESC_SEQ2_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */
|
||||
/*description: .*/
|
||||
#define UHCI_ESC_SEQ2_CHAR0 0x000000FF
|
||||
#define UHCI_ESC_SEQ2_CHAR0_M ((UHCI_ESC_SEQ2_CHAR0_V)<<(UHCI_ESC_SEQ2_CHAR0_S))
|
||||
#define UHCI_ESC_SEQ2_CHAR0_V 0xFF
|
||||
#define UHCI_ESC_SEQ2_CHAR0_S 8
|
||||
/* UHCI_ESC_SEQ2 : R/W ;bitpos:[7:0] ;default: 8'h13 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_ESC_SEQ2 0x000000FF
|
||||
#define UHCI_ESC_SEQ2_M ((UHCI_ESC_SEQ2_V)<<(UHCI_ESC_SEQ2_S))
|
||||
#define UHCI_ESC_SEQ2_V 0xFF
|
||||
#define UHCI_ESC_SEQ2_S 0
|
||||
|
||||
#define UHCI_PKT_THRES_REG(i) (REG_UHCI_BASE(i) + 0x80)
|
||||
/* UHCI_PKT_THRS : R/W ;bitpos:[12:0] ;default: 13'h80 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_PKT_THRS 0x00001FFF
|
||||
#define UHCI_PKT_THRS_M ((UHCI_PKT_THRS_V)<<(UHCI_PKT_THRS_S))
|
||||
#define UHCI_PKT_THRS_V 0x1FFF
|
||||
#define UHCI_PKT_THRS_S 0
|
||||
|
||||
#define UHCI_DATE_REG(i) (REG_UHCI_BASE(i) + 0x84)
|
||||
/* UHCI_DATE : R/W ;bitpos:[31:0] ;default: 32'h2010090 ; */
|
||||
/*description: .*/
|
||||
#define UHCI_DATE 0xFFFFFFFF
|
||||
#define UHCI_DATE_M ((UHCI_DATE_V)<<(UHCI_DATE_S))
|
||||
#define UHCI_DATE_V 0xFFFFFFFF
|
||||
#define UHCI_DATE_S 0
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /*_SOC_UHCI_REG_H_ */
|
||||
@@ -1,234 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#ifndef _SOC_UHCI_STRUCT_H_
|
||||
#define _SOC_UHCI_STRUCT_H_
|
||||
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef volatile struct uhci_dev_s {
|
||||
union {
|
||||
struct {
|
||||
uint32_t tx_rst : 1;
|
||||
uint32_t rx_rst : 1;
|
||||
uint32_t uart0_ce : 1;
|
||||
uint32_t uart1_ce : 1;
|
||||
uint32_t uart2_ce : 1;
|
||||
uint32_t seper_en : 1;
|
||||
uint32_t head_en : 1;
|
||||
uint32_t crc_rec_en : 1;
|
||||
uint32_t uart_idle_eof_en : 1;
|
||||
uint32_t len_eof_en : 1;
|
||||
uint32_t encode_crc_en : 1;
|
||||
uint32_t clk_en : 1;
|
||||
uint32_t uart_rx_brk_eof_en : 1;
|
||||
uint32_t reserved13 : 19;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_start : 1;
|
||||
uint32_t tx_start : 1;
|
||||
uint32_t rx_hung : 1;
|
||||
uint32_t tx_hung : 1;
|
||||
uint32_t send_s_q : 1;
|
||||
uint32_t send_a_q : 1;
|
||||
uint32_t outlink_eof_err : 1;
|
||||
uint32_t app_ctrl0 : 1;
|
||||
uint32_t app_ctrl1 : 1;
|
||||
uint32_t reserved9 : 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_start : 1;
|
||||
uint32_t tx_start : 1;
|
||||
uint32_t rx_hung : 1;
|
||||
uint32_t tx_hung : 1;
|
||||
uint32_t send_s_q : 1;
|
||||
uint32_t send_a_q : 1;
|
||||
uint32_t outlink_eof_err : 1;
|
||||
uint32_t app_ctrl0 : 1;
|
||||
uint32_t app_ctrl1 : 1;
|
||||
uint32_t reserved9 : 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_start : 1;
|
||||
uint32_t tx_start : 1;
|
||||
uint32_t rx_hung : 1;
|
||||
uint32_t tx_hung : 1;
|
||||
uint32_t send_s_q : 1;
|
||||
uint32_t send_a_q : 1;
|
||||
uint32_t outlink_eof_err : 1;
|
||||
uint32_t app_ctrl0 : 1;
|
||||
uint32_t app_ctrl1 : 1;
|
||||
uint32_t reserved9 : 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_start : 1;
|
||||
uint32_t tx_start : 1;
|
||||
uint32_t rx_hung : 1;
|
||||
uint32_t tx_hung : 1;
|
||||
uint32_t send_s_q : 1;
|
||||
uint32_t send_a_q : 1;
|
||||
uint32_t outlink_eof_err : 1;
|
||||
uint32_t app_ctrl0 : 1;
|
||||
uint32_t app_ctrl1 : 1;
|
||||
uint32_t reserved9 : 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t app_ctrl0_int_set : 1;
|
||||
uint32_t app_ctrl1_int_set : 1;
|
||||
uint32_t reserved2 : 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} app_int_set;
|
||||
union {
|
||||
struct {
|
||||
uint32_t check_sum_en : 1;
|
||||
uint32_t check_seq_en : 1;
|
||||
uint32_t crc_disable : 1;
|
||||
uint32_t save_head : 1;
|
||||
uint32_t tx_check_sum_re : 1;
|
||||
uint32_t tx_ack_num_re : 1;
|
||||
uint32_t reserved6 : 1;
|
||||
uint32_t wait_sw_start : 1;
|
||||
uint32_t sw_start : 1;
|
||||
uint32_t reserved9 : 12;
|
||||
uint32_t reserved21 : 11;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_err_cause : 3;
|
||||
uint32_t decode_state : 3;
|
||||
uint32_t reserved6 : 26;
|
||||
};
|
||||
uint32_t val;
|
||||
} state0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t encode_state : 3;
|
||||
uint32_t reserved3 : 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} state1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tx_c0_esc_en : 1;
|
||||
uint32_t tx_db_esc_en : 1;
|
||||
uint32_t tx_11_esc_en : 1;
|
||||
uint32_t tx_13_esc_en : 1;
|
||||
uint32_t rx_c0_esc_en : 1;
|
||||
uint32_t rx_db_esc_en : 1;
|
||||
uint32_t rx_11_esc_en : 1;
|
||||
uint32_t rx_13_esc_en : 1;
|
||||
uint32_t reserved8 : 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} escape_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t txfifo_timeout : 8;
|
||||
uint32_t txfifo_timeout_shift : 3;
|
||||
uint32_t txfifo_timeout_ena : 1;
|
||||
uint32_t rxfifo_timeout : 8;
|
||||
uint32_t rxfifo_timeout_shift : 3;
|
||||
uint32_t rxfifo_timeout_ena : 1;
|
||||
uint32_t reserved24 : 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} hung_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t ack_num : 3;
|
||||
uint32_t ack_num_load : 1;
|
||||
uint32_t reserved4 : 28;
|
||||
};
|
||||
uint32_t val;
|
||||
} ack_num;
|
||||
uint32_t rx_head;
|
||||
union {
|
||||
struct {
|
||||
uint32_t single_send_num : 3;
|
||||
uint32_t single_send_en : 1;
|
||||
uint32_t always_send_num : 3;
|
||||
uint32_t always_send_en : 1;
|
||||
uint32_t reserved8 : 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} quick_sent;
|
||||
struct {
|
||||
uint32_t word[2];
|
||||
} q_data[7];
|
||||
union {
|
||||
struct {
|
||||
uint32_t seper_char : 8;
|
||||
uint32_t seper_esc_char0 : 8;
|
||||
uint32_t seper_esc_char1 : 8;
|
||||
uint32_t reserved24 : 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} esc_conf0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t seq0 : 8;
|
||||
uint32_t seq0_char0 : 8;
|
||||
uint32_t seq0_char1 : 8;
|
||||
uint32_t reserved24 : 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} esc_conf1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t seq1 : 8;
|
||||
uint32_t seq1_char0 : 8;
|
||||
uint32_t seq1_char1 : 8;
|
||||
uint32_t reserved24 : 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} esc_conf2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t seq2 : 8;
|
||||
uint32_t seq2_char0 : 8;
|
||||
uint32_t seq2_char1 : 8;
|
||||
uint32_t reserved24 : 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} esc_conf3;
|
||||
union {
|
||||
struct {
|
||||
uint32_t thrs : 13;
|
||||
uint32_t reserved13 : 19;
|
||||
};
|
||||
uint32_t val;
|
||||
} pkt_thres;
|
||||
uint32_t date;
|
||||
} uhci_dev_t;
|
||||
extern uhci_dev_t UHCI0;
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /*_SOC_UHCI_STRUCT_H_ */
|
||||
@@ -33,7 +33,7 @@ typedef union {
|
||||
uint32_t hnpreq: 1;
|
||||
uint32_t hstsethnpen: 1;
|
||||
uint32_t devhnpen: 1;
|
||||
uint32_t ehen: 1;
|
||||
uint32_t ehen: 1; // codespell:ignore ehen
|
||||
uint32_t reserved_13: 2;
|
||||
uint32_t dbncefltrbypass: 1;
|
||||
uint32_t conidsts: 1;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,732 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#include "soc.h"
|
||||
|
||||
#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0)
|
||||
/* USB_SERIAL_JTAG_RDWR_BYTE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
|
||||
/*description: Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DE
|
||||
VICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into
|
||||
UART Tx FIFO. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is set, user can check USB
|
||||
_DEVICE_OUT_EP1_WR_ADDR USB_SERIAL_JTAG_OUT_EP0_RD_ADDR to know how many data is rece
|
||||
ived, then read data from UART Rx FIFO..*/
|
||||
#define USB_SERIAL_JTAG_RDWR_BYTE 0x000000FF
|
||||
#define USB_SERIAL_JTAG_RDWR_BYTE_M ((USB_DEVICE_RDWR_BYTE_V)<<(USB_DEVICE_RDWR_BYTE_S))
|
||||
#define USB_SERIAL_JTAG_RDWR_BYTE_V 0xFF
|
||||
#define USB_SERIAL_JTAG_RDWR_BYTE_S 0
|
||||
|
||||
#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4)
|
||||
/* USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL : RO ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: 1'b1: Indicate there is data in UART Rx FIFO..*/
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL (BIT(2))
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_M (BIT(2))
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_V 0x1
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_EP_DATA_AVAIL_S 2
|
||||
/* USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE : RO ;bitpos:[1] ;default: 1'b1 ; */
|
||||
/*description: 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writin
|
||||
g USB_SERIAL_JTAG_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by
|
||||
USB Host..*/
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE (BIT(1))
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_M (BIT(1))
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_V 0x1
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE_S 1
|
||||
/* USB_SERIAL_JTAG_WR_DONE : WT ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to indicate writing byte data to UART Tx FIFO is done..*/
|
||||
#define USB_SERIAL_JTAG_WR_DONE (BIT(0))
|
||||
#define USB_SERIAL_JTAG_WR_DONE_M (BIT(0))
|
||||
#define USB_SERIAL_JTAG_WR_DONE_V 0x1
|
||||
#define USB_SERIAL_JTAG_WR_DONE_S 0
|
||||
|
||||
#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x8)
|
||||
/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt bit turns to high level when OUT endpoint 2 received packet wi
|
||||
th zero palyload..*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW (BIT(11))
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_M (BIT(11))
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_V 0x1
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_RAW_S 11
|
||||
/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt bit turns to high level when OUT endpoint 1 received packet wi
|
||||
th zero palyload..*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW (BIT(10))
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_M (BIT(10))
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_V 0x1
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_RAW_S 10
|
||||
/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt bit turns to high level when usb bus reset is detected..*/
|
||||
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW (BIT(9))
|
||||
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_M (BIT(9))
|
||||
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_V 0x1
|
||||
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_RAW_S 9
|
||||
/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt bit turns to high level when IN token for IN endpoint 1 is rec
|
||||
eived..*/
|
||||
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW (BIT(8))
|
||||
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_M (BIT(8))
|
||||
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_V 0x1
|
||||
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_RAW_S 8
|
||||
/* USB_SERIAL_JTAG_STUFF_ERR_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt bit turns to high level when stuff error is detected..*/
|
||||
#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW (BIT(7))
|
||||
#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_M (BIT(7))
|
||||
#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_V 0x1
|
||||
#define USB_SERIAL_JTAG_STUFF_ERR_INT_RAW_S 7
|
||||
/* USB_SERIAL_JTAG_CRC16_ERR_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt bit turns to high level when CRC16 error is detected..*/
|
||||
#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW (BIT(6))
|
||||
#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_M (BIT(6))
|
||||
#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_V 0x1
|
||||
#define USB_SERIAL_JTAG_CRC16_ERR_INT_RAW_S 6
|
||||
/* USB_SERIAL_JTAG_CRC5_ERR_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt bit turns to high level when CRC5 error is detected..*/
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW (BIT(5))
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_M (BIT(5))
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_V 0x1
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_RAW_S 5
|
||||
/* USB_SERIAL_JTAG_PID_ERR_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt bit turns to high level when pid error is detected..*/
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_RAW (BIT(4))
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_M (BIT(4))
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_V 0x1
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_RAW_S 4
|
||||
/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b1 ; */
|
||||
/*description: The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty..*/
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW (BIT(3))
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_M (BIT(3))
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_V 0x1
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_RAW_S 3
|
||||
/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt bit turns to high level when Serial Port OUT Endpoint received
|
||||
one packet..*/
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW (BIT(2))
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_M (BIT(2))
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_V 0x1
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_RAW_S 2
|
||||
/* USB_SERIAL_JTAG_SOF_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt bit turns to high level when SOF frame is received..*/
|
||||
#define USB_SERIAL_JTAG_SOF_INT_RAW (BIT(1))
|
||||
#define USB_SERIAL_JTAG_SOF_INT_RAW_M (BIT(1))
|
||||
#define USB_SERIAL_JTAG_SOF_INT_RAW_V 0x1
|
||||
#define USB_SERIAL_JTAG_SOF_INT_RAW_S 1
|
||||
/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt bit turns to high level when flush cmd is received for IN endp
|
||||
oint 2 of JTAG..*/
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW (BIT(0))
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_M (BIT(0))
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_V 0x1
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW_S 0
|
||||
|
||||
#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0xC)
|
||||
/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interru
|
||||
pt..*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST (BIT(11))
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_M (BIT(11))
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_V 0x1
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ST_S 11
|
||||
/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interru
|
||||
pt..*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST (BIT(10))
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_M (BIT(10))
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_V 0x1
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ST_S 10
|
||||
/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST (BIT(9))
|
||||
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_M (BIT(9))
|
||||
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_V 0x1
|
||||
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ST_S 9
|
||||
/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrup
|
||||
t..*/
|
||||
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST (BIT(8))
|
||||
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_M (BIT(8))
|
||||
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_V 0x1
|
||||
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ST_S 8
|
||||
/* USB_SERIAL_JTAG_STUFF_ERR_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST (BIT(7))
|
||||
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_M (BIT(7))
|
||||
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_V 0x1
|
||||
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ST_S 7
|
||||
/* USB_SERIAL_JTAG_CRC16_ERR_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST (BIT(6))
|
||||
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_M (BIT(6))
|
||||
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_V 0x1
|
||||
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ST_S 6
|
||||
/* USB_SERIAL_JTAG_CRC5_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST (BIT(5))
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_M (BIT(5))
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_V 0x1
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ST_S 5
|
||||
/* USB_SERIAL_JTAG_PID_ERR_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_ST (BIT(4))
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_ST_M (BIT(4))
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_ST_V 0x1
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_ST_S 4
|
||||
/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST (BIT(3))
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_M (BIT(3))
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_V 0x1
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST_S 3
|
||||
/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrup
|
||||
t..*/
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST (BIT(2))
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_M (BIT(2))
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_V 0x1
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST_S 2
|
||||
/* USB_SERIAL_JTAG_SOF_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_SOF_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_SOF_INT_ST (BIT(1))
|
||||
#define USB_SERIAL_JTAG_SOF_INT_ST_M (BIT(1))
|
||||
#define USB_SERIAL_JTAG_SOF_INT_ST_V 0x1
|
||||
#define USB_SERIAL_JTAG_SOF_INT_ST_S 1
|
||||
/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST (BIT(0))
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_M (BIT(0))
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_V 0x1
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST_S 0
|
||||
|
||||
#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x10)
|
||||
/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
|
||||
/*description: The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA (BIT(11))
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_M (BIT(11))
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_V 0x1
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_ENA_S 11
|
||||
/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
|
||||
/*description: The interrupt enable bit for the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA (BIT(10))
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_M (BIT(10))
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_V 0x1
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_ENA_S 10
|
||||
/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
|
||||
/*description: The interrupt enable bit for the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA (BIT(9))
|
||||
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_M (BIT(9))
|
||||
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_V 0x1
|
||||
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_ENA_S 9
|
||||
/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: The interrupt enable bit for the USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA (BIT(8))
|
||||
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_M (BIT(8))
|
||||
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_V 0x1
|
||||
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_ENA_S 8
|
||||
/* USB_SERIAL_JTAG_STUFF_ERR_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: The interrupt enable bit for the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA (BIT(7))
|
||||
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_M (BIT(7))
|
||||
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_V 0x1
|
||||
#define USB_SERIAL_JTAG_STUFF_ERR_INT_ENA_S 7
|
||||
/* USB_SERIAL_JTAG_CRC16_ERR_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: The interrupt enable bit for the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA (BIT(6))
|
||||
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_M (BIT(6))
|
||||
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_V 0x1
|
||||
#define USB_SERIAL_JTAG_CRC16_ERR_INT_ENA_S 6
|
||||
/* USB_SERIAL_JTAG_CRC5_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: The interrupt enable bit for the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA (BIT(5))
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_M (BIT(5))
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_V 0x1
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_ENA_S 5
|
||||
/* USB_SERIAL_JTAG_PID_ERR_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: The interrupt enable bit for the USB_SERIAL_JTAG_PID_ERR_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_ENA (BIT(4))
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_M (BIT(4))
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_V 0x1
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_ENA_S 4
|
||||
/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA (BIT(3))
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_M (BIT(3))
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_V 0x1
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA_S 3
|
||||
/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: The interrupt enable bit for the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA (BIT(2))
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_M (BIT(2))
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_V 0x1
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA_S 2
|
||||
/* USB_SERIAL_JTAG_SOF_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: The interrupt enable bit for the USB_SERIAL_JTAG_SOF_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_SOF_INT_ENA (BIT(1))
|
||||
#define USB_SERIAL_JTAG_SOF_INT_ENA_M (BIT(1))
|
||||
#define USB_SERIAL_JTAG_SOF_INT_ENA_V 0x1
|
||||
#define USB_SERIAL_JTAG_SOF_INT_ENA_S 1
|
||||
/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA (BIT(0))
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_M (BIT(0))
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_V 0x1
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA_S 0
|
||||
|
||||
#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x14)
|
||||
/* USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to clear the USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR (BIT(11))
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_M (BIT(11))
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_V 0x1
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ZERO_PAYLOAD_INT_CLR_S 11
|
||||
/* USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to clear the USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR (BIT(10))
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_M (BIT(10))
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_V 0x1
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ZERO_PAYLOAD_INT_CLR_S 10
|
||||
/* USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to clear the USB_SERIAL_JTAG_USB_BUS_RESET_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR (BIT(9))
|
||||
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_M (BIT(9))
|
||||
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_V 0x1
|
||||
#define USB_SERIAL_JTAG_USB_BUS_RESET_INT_CLR_S 9
|
||||
/* USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to clear the USB_SERIAL_JTAG_IN_TOKEN_IN_EP1_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR (BIT(8))
|
||||
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_M (BIT(8))
|
||||
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_V 0x1
|
||||
#define USB_SERIAL_JTAG_IN_TOKEN_REC_IN_EP1_INT_CLR_S 8
|
||||
/* USB_SERIAL_JTAG_STUFF_ERR_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to clear the USB_SERIAL_JTAG_STUFF_ERR_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR (BIT(7))
|
||||
#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_M (BIT(7))
|
||||
#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_V 0x1
|
||||
#define USB_SERIAL_JTAG_STUFF_ERR_INT_CLR_S 7
|
||||
/* USB_SERIAL_JTAG_CRC16_ERR_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to clear the USB_SERIAL_JTAG_CRC16_ERR_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR (BIT(6))
|
||||
#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_M (BIT(6))
|
||||
#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_V 0x1
|
||||
#define USB_SERIAL_JTAG_CRC16_ERR_INT_CLR_S 6
|
||||
/* USB_SERIAL_JTAG_CRC5_ERR_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to clear the USB_SERIAL_JTAG_CRC5_ERR_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR (BIT(5))
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_M (BIT(5))
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_V 0x1
|
||||
#define USB_SERIAL_JTAG_CRC5_ERR_INT_CLR_S 5
|
||||
/* USB_SERIAL_JTAG_PID_ERR_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to clear the USB_SERIAL_JTAG_PID_ERR_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_CLR (BIT(4))
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_M (BIT(4))
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_V 0x1
|
||||
#define USB_SERIAL_JTAG_PID_ERR_INT_CLR_S 4
|
||||
/* USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to clear the USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR (BIT(3))
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_M (BIT(3))
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_V 0x1
|
||||
#define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_CLR_S 3
|
||||
/* USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to clear the USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR (BIT(2))
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_M (BIT(2))
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_V 0x1
|
||||
#define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_CLR_S 2
|
||||
/* USB_SERIAL_JTAG_SOF_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to clear the USB_SERIAL_JTAG_JTAG_SOF_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_SOF_INT_CLR (BIT(1))
|
||||
#define USB_SERIAL_JTAG_SOF_INT_CLR_M (BIT(1))
|
||||
#define USB_SERIAL_JTAG_SOF_INT_CLR_V 0x1
|
||||
#define USB_SERIAL_JTAG_SOF_INT_CLR_S 1
|
||||
/* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT interrupt..*/
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR (BIT(0))
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_M (BIT(0))
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_V 0x1
|
||||
#define USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR_S 0
|
||||
|
||||
#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18)
|
||||
/* USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */
|
||||
/*description: Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is disc
|
||||
onnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input thr
|
||||
ough GPIO Matrix..*/
|
||||
#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN (BIT(16))
|
||||
#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_M (BIT(16))
|
||||
#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_V 0x1
|
||||
#define USB_SERIAL_JTAG_USB_JTAG_BRIDGE_EN_S 16
|
||||
/* USB_SERIAL_JTAG_PHY_TX_EDGE_SEL : R/W ;bitpos:[15] ;default: 1'b0 ; */
|
||||
/*description: 0: TX output at clock negedge. 1: Tx output at clock posedge..*/
|
||||
#define USB_SERIAL_JTAG_PHY_TX_EDGE_SEL (BIT(15))
|
||||
#define USB_SERIAL_JTAG_PHY_TX_EDGE_SEL_M (BIT(15))
|
||||
#define USB_SERIAL_JTAG_PHY_TX_EDGE_SEL_V 0x1
|
||||
#define USB_SERIAL_JTAG_PHY_TX_EDGE_SEL_S 15
|
||||
/* USB_SERIAL_JTAG_USB_PAD_ENABLE : R/W ;bitpos:[14] ;default: 1'b1 ; */
|
||||
/*description: Enable USB pad function..*/
|
||||
#define USB_SERIAL_JTAG_USB_PAD_ENABLE (BIT(14))
|
||||
#define USB_SERIAL_JTAG_USB_PAD_ENABLE_M (BIT(14))
|
||||
#define USB_SERIAL_JTAG_USB_PAD_ENABLE_V 0x1
|
||||
#define USB_SERIAL_JTAG_USB_PAD_ENABLE_S 14
|
||||
/* USB_SERIAL_JTAG_PULLUP_VALUE : R/W ;bitpos:[13] ;default: 1'b0 ; */
|
||||
/*description: Control pull up value..*/
|
||||
#define USB_SERIAL_JTAG_PULLUP_VALUE (BIT(13))
|
||||
#define USB_SERIAL_JTAG_PULLUP_VALUE_M (BIT(13))
|
||||
#define USB_SERIAL_JTAG_PULLUP_VALUE_V 0x1
|
||||
#define USB_SERIAL_JTAG_PULLUP_VALUE_S 13
|
||||
/* USB_SERIAL_JTAG_DM_PULLDOWN : R/W ;bitpos:[12] ;default: 1'b0 ; */
|
||||
/*description: Control USB D- pull down..*/
|
||||
#define USB_SERIAL_JTAG_DM_PULLDOWN (BIT(12))
|
||||
#define USB_SERIAL_JTAG_DM_PULLDOWN_M (BIT(12))
|
||||
#define USB_SERIAL_JTAG_DM_PULLDOWN_V 0x1
|
||||
#define USB_SERIAL_JTAG_DM_PULLDOWN_S 12
|
||||
/* USB_SERIAL_JTAG_DM_PULLUP : R/W ;bitpos:[11] ;default: 1'b0 ; */
|
||||
/*description: Control USB D- pull up..*/
|
||||
#define USB_SERIAL_JTAG_DM_PULLUP (BIT(11))
|
||||
#define USB_SERIAL_JTAG_DM_PULLUP_M (BIT(11))
|
||||
#define USB_SERIAL_JTAG_DM_PULLUP_V 0x1
|
||||
#define USB_SERIAL_JTAG_DM_PULLUP_S 11
|
||||
/* USB_SERIAL_JTAG_DP_PULLDOWN : R/W ;bitpos:[10] ;default: 1'b0 ; */
|
||||
/*description: Control USB D+ pull down..*/
|
||||
#define USB_SERIAL_JTAG_DP_PULLDOWN (BIT(10))
|
||||
#define USB_SERIAL_JTAG_DP_PULLDOWN_M (BIT(10))
|
||||
#define USB_SERIAL_JTAG_DP_PULLDOWN_V 0x1
|
||||
#define USB_SERIAL_JTAG_DP_PULLDOWN_S 10
|
||||
/* USB_SERIAL_JTAG_DP_PULLUP : R/W ;bitpos:[9] ;default: 1'b1 ; */
|
||||
/*description: Control USB D+ pull up..*/
|
||||
#define USB_SERIAL_JTAG_DP_PULLUP (BIT(9))
|
||||
#define USB_SERIAL_JTAG_DP_PULLUP_M (BIT(9))
|
||||
#define USB_SERIAL_JTAG_DP_PULLUP_V 0x1
|
||||
#define USB_SERIAL_JTAG_DP_PULLUP_S 9
|
||||
/* USB_SERIAL_JTAG_PAD_PULL_OVERRIDE : R/W ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: Enable software control USB D+ D- pullup pulldown.*/
|
||||
#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE (BIT(8))
|
||||
#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_M (BIT(8))
|
||||
#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_V 0x1
|
||||
#define USB_SERIAL_JTAG_PAD_PULL_OVERRIDE_S 8
|
||||
/* USB_SERIAL_JTAG_VREF_OVERRIDE : R/W ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: Enable software control input threshold.*/
|
||||
#define USB_SERIAL_JTAG_VREF_OVERRIDE (BIT(7))
|
||||
#define USB_SERIAL_JTAG_VREF_OVERRIDE_M (BIT(7))
|
||||
#define USB_SERIAL_JTAG_VREF_OVERRIDE_V 0x1
|
||||
#define USB_SERIAL_JTAG_VREF_OVERRIDE_S 7
|
||||
/* USB_SERIAL_JTAG_VREFL : R/W ;bitpos:[6:5] ;default: 2'b0 ; */
|
||||
/*description: Control single-end input low threshold,0.8V to 1.04V, step 80mV.*/
|
||||
#define USB_SERIAL_JTAG_VREFL 0x00000003
|
||||
#define USB_SERIAL_JTAG_VREFL_M ((USB_DEVICE_VREFL_V)<<(USB_DEVICE_VREFL_S))
|
||||
#define USB_SERIAL_JTAG_VREFL_V 0x3
|
||||
#define USB_SERIAL_JTAG_VREFL_S 5
|
||||
/* USB_SERIAL_JTAG_VREFH : R/W ;bitpos:[4:3] ;default: 2'b0 ; */
|
||||
/*description: Control single-end input high threshold,1.76V to 2V, step 80mV.*/
|
||||
#define USB_SERIAL_JTAG_VREFH 0x00000003
|
||||
#define USB_SERIAL_JTAG_VREFH_M ((USB_DEVICE_VREFH_V)<<(USB_DEVICE_VREFH_S))
|
||||
#define USB_SERIAL_JTAG_VREFH_V 0x3
|
||||
#define USB_SERIAL_JTAG_VREFH_S 3
|
||||
/* USB_SERIAL_JTAG_EXCHG_PINS : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: USB D+ D- exchange.*/
|
||||
#define USB_SERIAL_JTAG_EXCHG_PINS (BIT(2))
|
||||
#define USB_SERIAL_JTAG_EXCHG_PINS_M (BIT(2))
|
||||
#define USB_SERIAL_JTAG_EXCHG_PINS_V 0x1
|
||||
#define USB_SERIAL_JTAG_EXCHG_PINS_S 2
|
||||
/* USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: Enable software control USB D+ D- exchange.*/
|
||||
#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE (BIT(1))
|
||||
#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_M (BIT(1))
|
||||
#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_V 0x1
|
||||
#define USB_SERIAL_JTAG_EXCHG_PINS_OVERRIDE_S 1
|
||||
/* USB_SERIAL_JTAG_PHY_SEL : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: Select internal/external PHY.*/
|
||||
#define USB_SERIAL_JTAG_PHY_SEL (BIT(0))
|
||||
#define USB_SERIAL_JTAG_PHY_SEL_M (BIT(0))
|
||||
#define USB_SERIAL_JTAG_PHY_SEL_V 0x1
|
||||
#define USB_SERIAL_JTAG_PHY_SEL_S 0
|
||||
|
||||
#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x1C)
|
||||
/* USB_SERIAL_JTAG_TEST_RX_DM : RO ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: USB D- rx value in test.*/
|
||||
#define USB_SERIAL_JTAG_TEST_RX_DM (BIT(6))
|
||||
#define USB_SERIAL_JTAG_TEST_RX_DM_M (BIT(6))
|
||||
#define USB_SERIAL_JTAG_TEST_RX_DM_V 0x1
|
||||
#define USB_SERIAL_JTAG_TEST_RX_DM_S 6
|
||||
/* USB_SERIAL_JTAG_TEST_RX_DP : RO ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: USB D+ rx value in test.*/
|
||||
#define USB_SERIAL_JTAG_TEST_RX_DP (BIT(5))
|
||||
#define USB_SERIAL_JTAG_TEST_RX_DP_M (BIT(5))
|
||||
#define USB_SERIAL_JTAG_TEST_RX_DP_V 0x1
|
||||
#define USB_SERIAL_JTAG_TEST_RX_DP_S 5
|
||||
/* USB_SERIAL_JTAG_TEST_RX_RCV : RO ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: USB differential rx value in test.*/
|
||||
#define USB_SERIAL_JTAG_TEST_RX_RCV (BIT(4))
|
||||
#define USB_SERIAL_JTAG_TEST_RX_RCV_M (BIT(4))
|
||||
#define USB_SERIAL_JTAG_TEST_RX_RCV_V 0x1
|
||||
#define USB_SERIAL_JTAG_TEST_RX_RCV_S 4
|
||||
/* USB_SERIAL_JTAG_TEST_TX_DM : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: USB D- tx value in test.*/
|
||||
#define USB_SERIAL_JTAG_TEST_TX_DM (BIT(3))
|
||||
#define USB_SERIAL_JTAG_TEST_TX_DM_M (BIT(3))
|
||||
#define USB_SERIAL_JTAG_TEST_TX_DM_V 0x1
|
||||
#define USB_SERIAL_JTAG_TEST_TX_DM_S 3
|
||||
/* USB_SERIAL_JTAG_TEST_TX_DP : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: USB D+ tx value in test.*/
|
||||
#define USB_SERIAL_JTAG_TEST_TX_DP (BIT(2))
|
||||
#define USB_SERIAL_JTAG_TEST_TX_DP_M (BIT(2))
|
||||
#define USB_SERIAL_JTAG_TEST_TX_DP_V 0x1
|
||||
#define USB_SERIAL_JTAG_TEST_TX_DP_S 2
|
||||
/* USB_SERIAL_JTAG_TEST_USB_OE : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: USB pad oen in test.*/
|
||||
#define USB_SERIAL_JTAG_TEST_USB_OE (BIT(1))
|
||||
#define USB_SERIAL_JTAG_TEST_USB_OE_M (BIT(1))
|
||||
#define USB_SERIAL_JTAG_TEST_USB_OE_V 0x1
|
||||
#define USB_SERIAL_JTAG_TEST_USB_OE_S 1
|
||||
/* USB_SERIAL_JTAG_TEST_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: Enable test of the USB pad.*/
|
||||
#define USB_SERIAL_JTAG_TEST_ENABLE (BIT(0))
|
||||
#define USB_SERIAL_JTAG_TEST_ENABLE_M (BIT(0))
|
||||
#define USB_SERIAL_JTAG_TEST_ENABLE_V 0x1
|
||||
#define USB_SERIAL_JTAG_TEST_ENABLE_S 0
|
||||
|
||||
#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x20)
|
||||
/* USB_SERIAL_JTAG_OUT_FIFO_RESET : R/W ;bitpos:[9] ;default: 1'b0 ; */
|
||||
/*description: Write 1 to reset JTAG out fifo..*/
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_RESET (BIT(9))
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_RESET_M (BIT(9))
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_RESET_V 0x1
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_RESET_S 9
|
||||
/* USB_SERIAL_JTAG_IN_FIFO_RESET : R/W ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: Write 1 to reset JTAG in fifo..*/
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_RESET (BIT(8))
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_RESET_M (BIT(8))
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_RESET_V 0x1
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_RESET_S 8
|
||||
/* USB_SERIAL_JTAG_OUT_FIFO_FULL : RO ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: 1: JTAG out fifo is full..*/
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_FULL (BIT(7))
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_FULL_M (BIT(7))
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_FULL_V 0x1
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_FULL_S 7
|
||||
/* USB_SERIAL_JTAG_OUT_FIFO_EMPTY : RO ;bitpos:[6] ;default: 1'b1 ; */
|
||||
/*description: 1: JTAG out fifo is empty..*/
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY (BIT(6))
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_M (BIT(6))
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_V 0x1
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_EMPTY_S 6
|
||||
/* USB_SERIAL_JTAG_OUT_FIFO_CNT : RO ;bitpos:[5:4] ;default: 2'd0 ; */
|
||||
/*description: JTAT out fifo counter..*/
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_CNT 0x00000003
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_CNT_M ((USB_DEVICE_OUT_FIFO_CNT_V)<<(USB_DEVICE_OUT_FIFO_CNT_S))
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_CNT_V 0x3
|
||||
#define USB_SERIAL_JTAG_OUT_FIFO_CNT_S 4
|
||||
/* USB_SERIAL_JTAG_IN_FIFO_FULL : RO ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: 1: JTAG in fifo is full..*/
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_FULL (BIT(3))
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_FULL_M (BIT(3))
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_FULL_V 0x1
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_FULL_S 3
|
||||
/* USB_SERIAL_JTAG_IN_FIFO_EMPTY : RO ;bitpos:[2] ;default: 1'b1 ; */
|
||||
/*description: 1: JTAG in fifo is empty..*/
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_EMPTY (BIT(2))
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_M (BIT(2))
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_V 0x1
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_EMPTY_S 2
|
||||
/* USB_SERIAL_JTAG_IN_FIFO_CNT : RO ;bitpos:[1:0] ;default: 2'd0 ; */
|
||||
/*description: JTAT in fifo counter..*/
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_CNT 0x00000003
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_CNT_M ((USB_DEVICE_IN_FIFO_CNT_V)<<(USB_DEVICE_IN_FIFO_CNT_S))
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_CNT_V 0x3
|
||||
#define USB_SERIAL_JTAG_IN_FIFO_CNT_S 0
|
||||
|
||||
#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x24)
|
||||
/* USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO ;bitpos:[10:0] ;default: 11'd0 ; */
|
||||
/*description: Frame index of received SOF frame..*/
|
||||
#define USB_SERIAL_JTAG_SOF_FRAME_INDEX 0x000007FF
|
||||
#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_M ((USB_DEVICE_SOF_FRAME_INDEX_V)<<(USB_DEVICE_SOF_FRAME_INDEX_S))
|
||||
#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_V 0x7FF
|
||||
#define USB_SERIAL_JTAG_SOF_FRAME_INDEX_S 0
|
||||
|
||||
#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x28)
|
||||
/* USB_SERIAL_JTAG_IN_EP0_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
|
||||
/*description: Read data address of IN endpoint 0..*/
|
||||
#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR 0x0000007F
|
||||
#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_M ((USB_DEVICE_IN_EP0_RD_ADDR_V)<<(USB_DEVICE_IN_EP0_RD_ADDR_S))
|
||||
#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_V 0x7F
|
||||
#define USB_SERIAL_JTAG_IN_EP0_RD_ADDR_S 9
|
||||
/* USB_SERIAL_JTAG_IN_EP0_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */
|
||||
/*description: Write data address of IN endpoint 0..*/
|
||||
#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR 0x0000007F
|
||||
#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_M ((USB_DEVICE_IN_EP0_WR_ADDR_V)<<(USB_DEVICE_IN_EP0_WR_ADDR_S))
|
||||
#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_V 0x7F
|
||||
#define USB_SERIAL_JTAG_IN_EP0_WR_ADDR_S 2
|
||||
/* USB_SERIAL_JTAG_IN_EP0_STATE : RO ;bitpos:[1:0] ;default: 2'b1 ; */
|
||||
/*description: State of IN Endpoint 0..*/
|
||||
#define USB_SERIAL_JTAG_IN_EP0_STATE 0x00000003
|
||||
#define USB_SERIAL_JTAG_IN_EP0_STATE_M ((USB_DEVICE_IN_EP0_STATE_V)<<(USB_DEVICE_IN_EP0_STATE_S))
|
||||
#define USB_SERIAL_JTAG_IN_EP0_STATE_V 0x3
|
||||
#define USB_SERIAL_JTAG_IN_EP0_STATE_S 0
|
||||
|
||||
#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x2C)
|
||||
/* USB_SERIAL_JTAG_IN_EP1_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
|
||||
/*description: Read data address of IN endpoint 1..*/
|
||||
#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR 0x0000007F
|
||||
#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_M ((USB_DEVICE_IN_EP1_RD_ADDR_V)<<(USB_DEVICE_IN_EP1_RD_ADDR_S))
|
||||
#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_V 0x7F
|
||||
#define USB_SERIAL_JTAG_IN_EP1_RD_ADDR_S 9
|
||||
/* USB_SERIAL_JTAG_IN_EP1_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */
|
||||
/*description: Write data address of IN endpoint 1..*/
|
||||
#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR 0x0000007F
|
||||
#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_M ((USB_DEVICE_IN_EP1_WR_ADDR_V)<<(USB_DEVICE_IN_EP1_WR_ADDR_S))
|
||||
#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_V 0x7F
|
||||
#define USB_SERIAL_JTAG_IN_EP1_WR_ADDR_S 2
|
||||
/* USB_SERIAL_JTAG_IN_EP1_STATE : RO ;bitpos:[1:0] ;default: 2'b1 ; */
|
||||
/*description: State of IN Endpoint 1..*/
|
||||
#define USB_SERIAL_JTAG_IN_EP1_STATE 0x00000003
|
||||
#define USB_SERIAL_JTAG_IN_EP1_STATE_M ((USB_DEVICE_IN_EP1_STATE_V)<<(USB_DEVICE_IN_EP1_STATE_S))
|
||||
#define USB_SERIAL_JTAG_IN_EP1_STATE_V 0x3
|
||||
#define USB_SERIAL_JTAG_IN_EP1_STATE_S 0
|
||||
|
||||
#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x30)
|
||||
/* USB_SERIAL_JTAG_IN_EP2_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
|
||||
/*description: Read data address of IN endpoint 2..*/
|
||||
#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR 0x0000007F
|
||||
#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_M ((USB_DEVICE_IN_EP2_RD_ADDR_V)<<(USB_DEVICE_IN_EP2_RD_ADDR_S))
|
||||
#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_V 0x7F
|
||||
#define USB_SERIAL_JTAG_IN_EP2_RD_ADDR_S 9
|
||||
/* USB_SERIAL_JTAG_IN_EP2_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */
|
||||
/*description: Write data address of IN endpoint 2..*/
|
||||
#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR 0x0000007F
|
||||
#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_M ((USB_DEVICE_IN_EP2_WR_ADDR_V)<<(USB_DEVICE_IN_EP2_WR_ADDR_S))
|
||||
#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_V 0x7F
|
||||
#define USB_SERIAL_JTAG_IN_EP2_WR_ADDR_S 2
|
||||
/* USB_SERIAL_JTAG_IN_EP2_STATE : RO ;bitpos:[1:0] ;default: 2'b1 ; */
|
||||
/*description: State of IN Endpoint 2..*/
|
||||
#define USB_SERIAL_JTAG_IN_EP2_STATE 0x00000003
|
||||
#define USB_SERIAL_JTAG_IN_EP2_STATE_M ((USB_DEVICE_IN_EP2_STATE_V)<<(USB_DEVICE_IN_EP2_STATE_S))
|
||||
#define USB_SERIAL_JTAG_IN_EP2_STATE_V 0x3
|
||||
#define USB_SERIAL_JTAG_IN_EP2_STATE_S 0
|
||||
|
||||
#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x34)
|
||||
/* USB_SERIAL_JTAG_IN_EP3_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
|
||||
/*description: Read data address of IN endpoint 3..*/
|
||||
#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR 0x0000007F
|
||||
#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_M ((USB_DEVICE_IN_EP3_RD_ADDR_V)<<(USB_DEVICE_IN_EP3_RD_ADDR_S))
|
||||
#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_V 0x7F
|
||||
#define USB_SERIAL_JTAG_IN_EP3_RD_ADDR_S 9
|
||||
/* USB_SERIAL_JTAG_IN_EP3_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */
|
||||
/*description: Write data address of IN endpoint 3..*/
|
||||
#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR 0x0000007F
|
||||
#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_M ((USB_DEVICE_IN_EP3_WR_ADDR_V)<<(USB_DEVICE_IN_EP3_WR_ADDR_S))
|
||||
#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_V 0x7F
|
||||
#define USB_SERIAL_JTAG_IN_EP3_WR_ADDR_S 2
|
||||
/* USB_SERIAL_JTAG_IN_EP3_STATE : RO ;bitpos:[1:0] ;default: 2'b1 ; */
|
||||
/*description: State of IN Endpoint 3..*/
|
||||
#define USB_SERIAL_JTAG_IN_EP3_STATE 0x00000003
|
||||
#define USB_SERIAL_JTAG_IN_EP3_STATE_M ((USB_DEVICE_IN_EP3_STATE_V)<<(USB_DEVICE_IN_EP3_STATE_S))
|
||||
#define USB_SERIAL_JTAG_IN_EP3_STATE_V 0x3
|
||||
#define USB_SERIAL_JTAG_IN_EP3_STATE_S 0
|
||||
|
||||
#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x38)
|
||||
/* USB_SERIAL_JTAG_OUT_EP0_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
|
||||
/*description: Read data address of OUT endpoint 0..*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR 0x0000007F
|
||||
#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_M ((USB_DEVICE_OUT_EP0_RD_ADDR_V)<<(USB_DEVICE_OUT_EP0_RD_ADDR_S))
|
||||
#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_V 0x7F
|
||||
#define USB_SERIAL_JTAG_OUT_EP0_RD_ADDR_S 9
|
||||
/* USB_SERIAL_JTAG_OUT_EP0_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */
|
||||
/*description: Write data address of OUT endpoint 0. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is
|
||||
detected, there are USB_SERIAL_JTAG_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0..*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR 0x0000007F
|
||||
#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_M ((USB_DEVICE_OUT_EP0_WR_ADDR_V)<<(USB_DEVICE_OUT_EP0_WR_ADDR_S))
|
||||
#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_V 0x7F
|
||||
#define USB_SERIAL_JTAG_OUT_EP0_WR_ADDR_S 2
|
||||
/* USB_SERIAL_JTAG_OUT_EP0_STATE : RO ;bitpos:[1:0] ;default: 2'b0 ; */
|
||||
/*description: State of OUT Endpoint 0..*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP0_STATE 0x00000003
|
||||
#define USB_SERIAL_JTAG_OUT_EP0_STATE_M ((USB_DEVICE_OUT_EP0_STATE_V)<<(USB_DEVICE_OUT_EP0_STATE_S))
|
||||
#define USB_SERIAL_JTAG_OUT_EP0_STATE_V 0x3
|
||||
#define USB_SERIAL_JTAG_OUT_EP0_STATE_S 0
|
||||
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x3C)
|
||||
/* USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT : RO ;bitpos:[22:16] ;default: 7'd0 ; */
|
||||
/*description: Data count in OUT endpoint 1 when one packet is received..*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT 0x0000007F
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_M ((USB_DEVICE_OUT_EP1_REC_DATA_CNT_V)<<(USB_DEVICE_OUT_EP1_REC_DATA_CNT_S))
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_V 0x7F
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT_S 16
|
||||
/* USB_SERIAL_JTAG_OUT_EP1_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
|
||||
/*description: Read data address of OUT endpoint 1..*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR 0x0000007F
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_M ((USB_DEVICE_OUT_EP1_RD_ADDR_V)<<(USB_DEVICE_OUT_EP1_RD_ADDR_S))
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_V 0x7F
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_RD_ADDR_S 9
|
||||
/* USB_SERIAL_JTAG_OUT_EP1_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */
|
||||
/*description: Write data address of OUT endpoint 1. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is
|
||||
detected, there are USB_SERIAL_JTAG_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1..*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR 0x0000007F
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_M ((USB_DEVICE_OUT_EP1_WR_ADDR_V)<<(USB_DEVICE_OUT_EP1_WR_ADDR_S))
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_V 0x7F
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_WR_ADDR_S 2
|
||||
/* USB_SERIAL_JTAG_OUT_EP1_STATE : RO ;bitpos:[1:0] ;default: 2'b0 ; */
|
||||
/*description: State of OUT Endpoint 1..*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_STATE 0x00000003
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_STATE_M ((USB_DEVICE_OUT_EP1_STATE_V)<<(USB_DEVICE_OUT_EP1_STATE_S))
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_STATE_V 0x3
|
||||
#define USB_SERIAL_JTAG_OUT_EP1_STATE_S 0
|
||||
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x40)
|
||||
/* USB_SERIAL_JTAG_OUT_EP2_RD_ADDR : RO ;bitpos:[15:9] ;default: 7'd0 ; */
|
||||
/*description: Read data address of OUT endpoint 2..*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR 0x0000007F
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_M ((USB_DEVICE_OUT_EP2_RD_ADDR_V)<<(USB_DEVICE_OUT_EP2_RD_ADDR_S))
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_V 0x7F
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_RD_ADDR_S 9
|
||||
/* USB_SERIAL_JTAG_OUT_EP2_WR_ADDR : RO ;bitpos:[8:2] ;default: 7'd0 ; */
|
||||
/*description: Write data address of OUT endpoint 2. When USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT is
|
||||
detected, there are USB_SERIAL_JTAG_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2..*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR 0x0000007F
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_M ((USB_DEVICE_OUT_EP2_WR_ADDR_V)<<(USB_DEVICE_OUT_EP2_WR_ADDR_S))
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_V 0x7F
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_WR_ADDR_S 2
|
||||
/* USB_SERIAL_JTAG_OUT_EP2_STATE : RO ;bitpos:[1:0] ;default: 2'b0 ; */
|
||||
/*description: State of OUT Endpoint 2..*/
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_STATE 0x00000003
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_STATE_M ((USB_DEVICE_OUT_EP2_STATE_V)<<(USB_DEVICE_OUT_EP2_STATE_S))
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_STATE_V 0x3
|
||||
#define USB_SERIAL_JTAG_OUT_EP2_STATE_S 0
|
||||
|
||||
#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x44)
|
||||
/* USB_SERIAL_JTAG_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: 1'h1: Force clock on for register. 1'h0: Support clock only when application wri
|
||||
tes registers..*/
|
||||
#define USB_SERIAL_JTAG_CLK_EN (BIT(0))
|
||||
#define USB_SERIAL_JTAG_CLK_EN_M (BIT(0))
|
||||
#define USB_SERIAL_JTAG_CLK_EN_V 0x1
|
||||
#define USB_SERIAL_JTAG_CLK_EN_S 0
|
||||
|
||||
#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x48)
|
||||
/* USB_SERIAL_JTAG_USB_MEM_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
|
||||
/*description: 1: Force clock on for usb memory..*/
|
||||
#define USB_SERIAL_JTAG_USB_MEM_CLK_EN (BIT(1))
|
||||
#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_M (BIT(1))
|
||||
#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_V 0x1
|
||||
#define USB_SERIAL_JTAG_USB_MEM_CLK_EN_S 1
|
||||
/* USB_SERIAL_JTAG_USB_MEM_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: 1: power down usb memory..*/
|
||||
#define USB_SERIAL_JTAG_USB_MEM_PD (BIT(0))
|
||||
#define USB_SERIAL_JTAG_USB_MEM_PD_M (BIT(0))
|
||||
#define USB_SERIAL_JTAG_USB_MEM_PD_V 0x1
|
||||
#define USB_SERIAL_JTAG_USB_MEM_PD_S 0
|
||||
|
||||
#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80)
|
||||
/* USB_SERIAL_JTAG_DATE : R/W ;bitpos:[31:0] ;default: 32'h2101200 ; */
|
||||
/*description: register version..*/
|
||||
#define USB_SERIAL_JTAG_DATE 0xFFFFFFFF
|
||||
#define USB_SERIAL_JTAG_DATE_M ((USB_DEVICE_DATE_V)<<(USB_DEVICE_DATE_S))
|
||||
#define USB_SERIAL_JTAG_DATE_V 0xFFFFFFFF
|
||||
#define USB_SERIAL_JTAG_DATE_S 0
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,267 +0,0 @@
|
||||
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_USB_SERIAL_JTAG_STRUCT_H_
|
||||
#define _SOC_USB_SERIAL_JTAG_STRUCT_H_
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#include "soc.h"
|
||||
|
||||
typedef volatile struct usb_serial_jtag_dev_s {
|
||||
union {
|
||||
struct {
|
||||
uint32_t rdwr_byte : 32; /*Although only low 8-bits is valid, but change it to 32bits to avoid there's no read/modify/write behaviour*/ /*Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} ep1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t wr_done : 1; /*Set this bit to indicate writing byte data to UART Tx FIFO is done.*/
|
||||
uint32_t serial_in_ep_data_free : 1; /*1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB Host.*/
|
||||
uint32_t serial_out_ep_data_avail : 1; /*1'b1: Indicate there is data in UART Rx FIFO.*/
|
||||
uint32_t reserved3 : 29; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} ep1_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t jtag_in_flush_int_raw : 1; /*The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG.*/
|
||||
uint32_t sof_int_raw : 1; /*The raw interrupt bit turns to high level when SOF frame is received.*/
|
||||
uint32_t serial_out_recv_pkt_int_raw: 1; /*The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet.*/
|
||||
uint32_t serial_in_empty_int_raw : 1; /*The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.*/
|
||||
uint32_t pid_err_int_raw : 1; /*The raw interrupt bit turns to high level when pid error is detected.*/
|
||||
uint32_t crc5_err_int_raw : 1; /*The raw interrupt bit turns to high level when CRC5 error is detected.*/
|
||||
uint32_t crc16_err_int_raw : 1; /*The raw interrupt bit turns to high level when CRC16 error is detected.*/
|
||||
uint32_t stuff_err_int_raw : 1; /*The raw interrupt bit turns to high level when stuff error is detected.*/
|
||||
uint32_t in_token_rec_in_ep1_int_raw: 1; /*The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received.*/
|
||||
uint32_t usb_bus_reset_int_raw : 1; /*The raw interrupt bit turns to high level when usb bus reset is detected.*/
|
||||
uint32_t out_ep1_zero_payload_int_raw: 1; /*The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload.*/
|
||||
uint32_t out_ep2_zero_payload_int_raw: 1; /*The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload.*/
|
||||
uint32_t reserved12 : 20; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t jtag_in_flush_int_st : 1; /*The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.*/
|
||||
uint32_t sof_int_st : 1; /*The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt.*/
|
||||
uint32_t serial_out_recv_pkt_int_st: 1; /*The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.*/
|
||||
uint32_t serial_in_empty_int_st : 1; /*The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.*/
|
||||
uint32_t pid_err_int_st : 1; /*The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt.*/
|
||||
uint32_t crc5_err_int_st : 1; /*The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt.*/
|
||||
uint32_t crc16_err_int_st : 1; /*The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt.*/
|
||||
uint32_t stuff_err_int_st : 1; /*The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt.*/
|
||||
uint32_t in_token_rec_in_ep1_int_st: 1; /*The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.*/
|
||||
uint32_t usb_bus_reset_int_st : 1; /*The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.*/
|
||||
uint32_t out_ep1_zero_payload_int_st: 1; /*The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.*/
|
||||
uint32_t out_ep2_zero_payload_int_st: 1; /*The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.*/
|
||||
uint32_t reserved12 : 20; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t jtag_in_flush_int_ena : 1; /*The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.*/
|
||||
uint32_t sof_int_ena : 1; /*The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt.*/
|
||||
uint32_t serial_out_recv_pkt_int_ena: 1; /*The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.*/
|
||||
uint32_t serial_in_empty_int_ena : 1; /*The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.*/
|
||||
uint32_t pid_err_int_ena : 1; /*The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt.*/
|
||||
uint32_t crc5_err_int_ena : 1; /*The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt.*/
|
||||
uint32_t crc16_err_int_ena : 1; /*The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt.*/
|
||||
uint32_t stuff_err_int_ena : 1; /*The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt.*/
|
||||
uint32_t in_token_rec_in_ep1_int_ena: 1; /*The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.*/
|
||||
uint32_t usb_bus_reset_int_ena : 1; /*The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.*/
|
||||
uint32_t out_ep1_zero_payload_int_ena: 1; /*The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.*/
|
||||
uint32_t out_ep2_zero_payload_int_ena: 1; /*The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.*/
|
||||
uint32_t reserved12 : 20; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t jtag_in_flush_int_clr : 1; /*Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.*/
|
||||
uint32_t sof_int_clr : 1; /*Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt.*/
|
||||
uint32_t serial_out_recv_pkt_int_clr: 1; /*Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.*/
|
||||
uint32_t serial_in_empty_int_clr : 1; /*Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.*/
|
||||
uint32_t pid_err_int_clr : 1; /*Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt.*/
|
||||
uint32_t crc5_err_int_clr : 1; /*Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt.*/
|
||||
uint32_t crc16_err_int_clr : 1; /*Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt.*/
|
||||
uint32_t stuff_err_int_clr : 1; /*Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt.*/
|
||||
uint32_t in_token_rec_in_ep1_int_clr: 1; /*Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt.*/
|
||||
uint32_t usb_bus_reset_int_clr : 1; /*Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt.*/
|
||||
uint32_t out_ep1_zero_payload_int_clr: 1; /*Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.*/
|
||||
uint32_t out_ep2_zero_payload_int_clr: 1; /*Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.*/
|
||||
uint32_t reserved12 : 20; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t phy_sel : 1; /*Select internal/external PHY*/
|
||||
uint32_t exchg_pins_override : 1; /*Enable software control USB D+ D- exchange*/
|
||||
uint32_t exchg_pins : 1; /*USB D+ D- exchange*/
|
||||
uint32_t vrefh : 2; /*Control single-end input high threshold,1.76V to 2V, step 80mV*/
|
||||
uint32_t vrefl : 2; /*Control single-end input low threshold,0.8V to 1.04V, step 80mV*/
|
||||
uint32_t vref_override : 1; /*Enable software control input threshold*/
|
||||
uint32_t pad_pull_override : 1; /*Enable software control USB D+ D- pullup pulldown*/
|
||||
uint32_t dp_pullup : 1; /*Control USB D+ pull up.*/
|
||||
uint32_t dp_pulldown : 1; /*Control USB D+ pull down.*/
|
||||
uint32_t dm_pullup : 1; /*Control USB D- pull up.*/
|
||||
uint32_t dm_pulldown : 1; /*Control USB D- pull down.*/
|
||||
uint32_t pullup_value : 1; /*Control pull up value.*/
|
||||
uint32_t usb_pad_enable : 1; /*Enable USB pad function.*/
|
||||
uint32_t phy_tx_edge_sel : 1; /*0: TX output at clock negedge. 1: Tx output at clock posedge.*/
|
||||
uint32_t usb_jtag_bridge_en : 1; /*Set this bit usb_jtag, the connection between usb_jtag and internal JTAG is disconnected, and MTMS, MTDI, MTCK are output through GPIO Matrix, MTDO is input through GPIO Matrix.*/
|
||||
uint32_t reserved17 : 15;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t test_enable : 1; /*Enable test of the USB pad*/
|
||||
uint32_t test_usb_oe : 1; /*USB pad oen in test*/
|
||||
uint32_t test_tx_dp : 1; /*USB D+ tx value in test*/
|
||||
uint32_t test_tx_dm : 1; /*USB D- tx value in test*/
|
||||
uint32_t test_rx_rcv : 1; /*USB differential rx value in test*/
|
||||
uint32_t test_rx_dp : 1; /*USB D+ rx value in test*/
|
||||
uint32_t test_rx_dm : 1; /*USB D- rx value in test*/
|
||||
uint32_t reserved7 : 25;
|
||||
};
|
||||
uint32_t val;
|
||||
} test;
|
||||
union {
|
||||
struct {
|
||||
uint32_t in_fifo_cnt : 2; /*JTAT in fifo counter.*/
|
||||
uint32_t in_fifo_empty : 1; /*1: JTAG in fifo is empty.*/
|
||||
uint32_t in_fifo_full : 1; /*1: JTAG in fifo is full.*/
|
||||
uint32_t out_fifo_cnt : 2; /*JTAT out fifo counter.*/
|
||||
uint32_t out_fifo_empty : 1; /*1: JTAG out fifo is empty.*/
|
||||
uint32_t out_fifo_full : 1; /*1: JTAG out fifo is full.*/
|
||||
uint32_t in_fifo_reset : 1; /*Write 1 to reset JTAG in fifo.*/
|
||||
uint32_t out_fifo_reset : 1; /*Write 1 to reset JTAG out fifo.*/
|
||||
uint32_t reserved10 : 22;
|
||||
};
|
||||
uint32_t val;
|
||||
} jfifo_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sof_frame_index : 11; /*Frame index of received SOF frame.*/
|
||||
uint32_t reserved11 : 21;
|
||||
};
|
||||
uint32_t val;
|
||||
} fram_num;
|
||||
union {
|
||||
struct {
|
||||
uint32_t in_ep0_state : 2; /*State of IN Endpoint 0.*/
|
||||
uint32_t in_ep0_wr_addr : 7; /*Write data address of IN endpoint 0.*/
|
||||
uint32_t in_ep0_rd_addr : 7; /*Read data address of IN endpoint 0.*/
|
||||
uint32_t reserved16 : 16; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} in_ep0_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t in_ep1_state : 2; /*State of IN Endpoint 1.*/
|
||||
uint32_t in_ep1_wr_addr : 7; /*Write data address of IN endpoint 1.*/
|
||||
uint32_t in_ep1_rd_addr : 7; /*Read data address of IN endpoint 1.*/
|
||||
uint32_t reserved16 : 16; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} in_ep1_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t in_ep2_state : 2; /*State of IN Endpoint 2.*/
|
||||
uint32_t in_ep2_wr_addr : 7; /*Write data address of IN endpoint 2.*/
|
||||
uint32_t in_ep2_rd_addr : 7; /*Read data address of IN endpoint 2.*/
|
||||
uint32_t reserved16 : 16; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} in_ep2_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t in_ep3_state : 2; /*State of IN Endpoint 3.*/
|
||||
uint32_t in_ep3_wr_addr : 7; /*Write data address of IN endpoint 3.*/
|
||||
uint32_t in_ep3_rd_addr : 7; /*Read data address of IN endpoint 3.*/
|
||||
uint32_t reserved16 : 16; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} in_ep3_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t out_ep0_state : 2; /*State of OUT Endpoint 0.*/
|
||||
uint32_t out_ep0_wr_addr : 7; /*Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.*/
|
||||
uint32_t out_ep0_rd_addr : 7; /*Read data address of OUT endpoint 0.*/
|
||||
uint32_t reserved16 : 16; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} out_ep0_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t out_ep1_state : 2; /*State of OUT Endpoint 1.*/
|
||||
uint32_t out_ep1_wr_addr : 7; /*Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.*/
|
||||
uint32_t out_ep1_rd_addr : 7; /*Read data address of OUT endpoint 1.*/
|
||||
uint32_t out_ep1_rec_data_cnt : 7; /*Data count in OUT endpoint 1 when one packet is received.*/
|
||||
uint32_t reserved23 : 9; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} out_ep1_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t out_ep2_state : 2; /*State of OUT Endpoint 2.*/
|
||||
uint32_t out_ep2_wr_addr : 7; /*Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.*/
|
||||
uint32_t out_ep2_rd_addr : 7; /*Read data address of OUT endpoint 2.*/
|
||||
uint32_t reserved16 : 16; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} out_ep2_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_en : 1; /*1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.*/
|
||||
uint32_t reserved1 : 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} misc_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t usb_mem_pd : 1; /*1: power down usb memory.*/
|
||||
uint32_t usb_mem_clk_en : 1; /*1: Force clock on for usb memory.*/
|
||||
uint32_t reserved2 : 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} mem_conf;
|
||||
uint32_t reserved_4c;
|
||||
uint32_t reserved_50;
|
||||
uint32_t reserved_54;
|
||||
uint32_t reserved_58;
|
||||
uint32_t reserved_5c;
|
||||
uint32_t reserved_60;
|
||||
uint32_t reserved_64;
|
||||
uint32_t reserved_68;
|
||||
uint32_t reserved_6c;
|
||||
uint32_t reserved_70;
|
||||
uint32_t reserved_74;
|
||||
uint32_t reserved_78;
|
||||
uint32_t reserved_7c;
|
||||
uint32_t date;
|
||||
} usb_serial_jtag_dev_t;
|
||||
extern usb_serial_jtag_dev_t USB_SERIAL_JTAG;
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /*_SOC_USB_SERIAL_JTAG_STRUCT_H_ */
|
||||
@@ -1,121 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* USB IN EP Register block type */
|
||||
typedef struct usb_in_ep_reg {
|
||||
volatile uint32_t diepctl;
|
||||
uint32_t reserved;
|
||||
volatile uint32_t diepint;
|
||||
uint32_t reserved1;
|
||||
volatile uint32_t dieptsiz;
|
||||
volatile uint32_t diepdma;
|
||||
volatile uint32_t dtxfsts;
|
||||
uint32_t reserved2;
|
||||
} usb_in_endpoint_t;
|
||||
|
||||
/* USB OUT EP Register block type */
|
||||
typedef struct usb_out_ep_reg {
|
||||
volatile uint32_t doepctl;
|
||||
uint32_t reserved;
|
||||
volatile uint32_t doepint;
|
||||
uint32_t reserved1;
|
||||
volatile uint32_t doeptsiz;
|
||||
volatile uint32_t doepdma;
|
||||
uint32_t reserved2;
|
||||
uint32_t reserved3;
|
||||
} usb_out_endpoint_t;
|
||||
|
||||
typedef struct usb_reg {
|
||||
volatile uint32_t gotgctl; // 0x0000 OTG Control and Status Register
|
||||
volatile uint32_t gotgint; // 0x0004 OTG Interrupt Register
|
||||
volatile uint32_t gahbcfg; // 0x0008 AHB Configuration Register
|
||||
volatile uint32_t gusbcfg; // 0x000c USB Configuration Register
|
||||
volatile uint32_t grstctl; // 0x0010 Reset Register
|
||||
volatile uint32_t gintsts; // 0x0014 Interrupt Register
|
||||
volatile uint32_t gintmsk; // 0x0018 Interrupt Mask Register
|
||||
volatile uint32_t grxstsr; // 0x001c Receive Status Debug Read Register
|
||||
volatile uint32_t grxstsp; // 0x0020 Receive Status Read/Pop Register
|
||||
volatile uint32_t grxfsiz; // 0x0024 Receive FIFO Size Register
|
||||
volatile uint32_t gnptxfsiz; // 0x0028 Non-periodic Transmit FIFO Size Register
|
||||
volatile uint32_t gnptxsts; // 0x002c Non-periodic Transmit FIFO/Queue Status Register
|
||||
uint32_t reserved_0x0030_0x0040[4]; // 0x0030 to 0x0040
|
||||
volatile uint32_t gsnpsid; // 0x0040 Synopsys ID Register
|
||||
volatile uint32_t ghwcfg1; // 0x0044 User Hardware Configuration 1 Register
|
||||
volatile uint32_t ghwcfg2; // 0x0048 User Hardware Configuration 2 Register
|
||||
volatile uint32_t ghwcfg3; // 0x004c User Hardware Configuration 3 Register
|
||||
volatile uint32_t ghwcfg4; // 0x0050 User Hardware Configuration 4 Register
|
||||
uint32_t reserved_0x0054_0x005c[2]; // 0x0054 to 0x005c
|
||||
volatile uint32_t gdfifocfg; // 0x005c Global DFIFO Configuration Register
|
||||
uint32_t reserved_0x0060_0x0100[40]; // 0x0060 to 0x0100
|
||||
volatile uint32_t hptxfsiz; // 0x0100 Host Periodic Transmit FIFO Size Register
|
||||
volatile uint32_t dieptxf[4]; // 0x0104 to 0x0114 Device IN Endpoint Transmit FIFO Size Register i
|
||||
uint32_t reserved_0x0114_0x0140[11]; // 0x0114 to 0x0140
|
||||
uint32_t reserved_0x0140_0x0400[176]; // 0x0140 to 0x0400
|
||||
/**
|
||||
* Host mode registers offsets from 0x0400 to 0x07FF
|
||||
*/
|
||||
volatile uint32_t hcfg; // 0x0400 Host Configuration Register
|
||||
volatile uint32_t hfir; // 0x0404 Host Frame Interval Register
|
||||
volatile uint32_t hfnum; // 0x0408 Host Frame Number/Frame Remaining Register
|
||||
uint32_t reserved0x40C; // 0x040c Reserved
|
||||
volatile uint32_t hptxsts; // 0x0410 Host Periodic Transmit FIFO/ Queue Status Register
|
||||
volatile uint32_t haint; // 0x0414 Host All Channels Interrupt Register
|
||||
volatile uint32_t haintmsk; // 0x0418 Host All Channels Interrupt Mask Register
|
||||
volatile uint32_t hflbaddr; // 0x041c Host Frame List Base Address Register
|
||||
uint32_t reserved0x0420_0x0440[8]; // 0x0420 to 0x0440
|
||||
volatile uint32_t hprt; // 0x0440 Host Port Control and Status Register
|
||||
uint32_t reserved_0x0444_0x0500[47]; // 0x0444 to 0x0500
|
||||
//Skip over the host channel registers
|
||||
volatile uint32_t host_chan_regs[128]; // 0x0500 to 0x0700
|
||||
uint32_t reserved_0x0700_0x0800[64]; // 0x0700 to 0x0800
|
||||
/**
|
||||
* Device mode registers offsets from
|
||||
*/
|
||||
volatile uint32_t dcfg; // 0x0800 Device Configuration Register
|
||||
volatile uint32_t dctl; // 0x0804 Device Control Register
|
||||
volatile uint32_t dsts; // 0x0808 Device Status Register (Read Only)
|
||||
uint32_t reserved0x80c; // 0x080c
|
||||
volatile uint32_t diepmsk; // 0x0810 Device IN Endpoint Common Interrupt Mask Register
|
||||
volatile uint32_t doepmsk; // 0x0814 Device OUT Endpoint Common Interrupt Mask Register
|
||||
volatile uint32_t daint; // 0x0818 Device All Endpoints Interrupt Register
|
||||
volatile uint32_t daintmsk; // 0x081c Device All Endpoints Interrupt Mask Register
|
||||
uint32_t reserved_0x0820_0x0828[2]; // 0x0820 to 0x0828
|
||||
volatile uint32_t dvbusdis; // 0x0828 Device VBUS discharge Register
|
||||
volatile uint32_t dvbuspulse; // 0x082c Device VBUS Pulse Register
|
||||
volatile uint32_t dthrctl; // 0x0830 Device Thresholding control register (Read/Write)
|
||||
volatile uint32_t dtknqr4_fifoemptymsk; // 0x0834 Device IN Endpoint FIFO Empty Interrupt Mask register
|
||||
uint32_t reserved_0x0838_0x0900[50]; // 0x0838 to 0x0900
|
||||
// Input Endpoints
|
||||
usb_in_endpoint_t in_ep_reg[7]; // 0x0900 to 0x09e0 IN EP registers
|
||||
uint32_t reserved_0x09e0_0x0b00[72]; // 0x09e0 to 0x0b00
|
||||
// Output Endpoints
|
||||
usb_out_endpoint_t out_ep_reg[7]; // 0x0b00 to 0x0be0 OUT EP registers
|
||||
uint32_t reserved_0x0be0_0x0d00[72]; // 0x0be0 to 0x0d00
|
||||
uint32_t reserved_0x0d00_0x0e00[64]; // 0x0d00 to 0x0e00
|
||||
/**
|
||||
* Power Control and direct FIFO access
|
||||
*/
|
||||
uint32_t pcgctrl; // 0x0e00 Power and Clock Gating Control Register
|
||||
uint32_t reserved_0x0e04; // 0x0e04
|
||||
uint8_t reserved8[0x1000 - 0xe08]; // 0x0d00 to 0x1000
|
||||
uint32_t fifo[16][0x400]; // 0x1000 to 0x2000 Device EP i/Host Channel i FIFO
|
||||
uint8_t reserved0x11000[0x20000 - 0x11000];
|
||||
uint32_t dbg_fifo[0x20000]; // 0x2000 to 0x22000 Direct Access to Data FIFO RAM for Debugging
|
||||
} usb_dev_t;
|
||||
|
||||
extern usb_dev_t USB0;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,216 +0,0 @@
|
||||
// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#ifndef _SOC_USB_WRAP_REG_H_
|
||||
#define _SOC_USB_WRAP_REG_H_
|
||||
|
||||
|
||||
#include "soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define USB_WRAP_OTG_CONF_REG (DR_REG_USB_WRAP_BASE + 0x0)
|
||||
/* USB_WRAP_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
|
||||
/*description: Disable auto clock gating of CSR registers .*/
|
||||
#define USB_WRAP_CLK_EN (BIT(31))
|
||||
#define USB_WRAP_CLK_EN_M (BIT(31))
|
||||
#define USB_WRAP_CLK_EN_V 0x1
|
||||
#define USB_WRAP_CLK_EN_S 31
|
||||
/* USB_WRAP_DFIFO_FORCE_PU : R/W ;bitpos:[22] ;default: 1'b0 ; */
|
||||
/*description: Disable the dfifo to go into low power mode. The data in dfifo will not lost..*/
|
||||
#define USB_WRAP_DFIFO_FORCE_PU (BIT(22))
|
||||
#define USB_WRAP_DFIFO_FORCE_PU_M (BIT(22))
|
||||
#define USB_WRAP_DFIFO_FORCE_PU_V 0x1
|
||||
#define USB_WRAP_DFIFO_FORCE_PU_S 22
|
||||
/* USB_WRAP_PHY_TX_EDGE_SEL : R/W ;bitpos:[21] ;default: 1'b0 ; */
|
||||
/*description: Select phy tx signal output clock edge.*/
|
||||
#define USB_WRAP_PHY_TX_EDGE_SEL (BIT(21))
|
||||
#define USB_WRAP_PHY_TX_EDGE_SEL_M (BIT(21))
|
||||
#define USB_WRAP_PHY_TX_EDGE_SEL_V 0x1
|
||||
#define USB_WRAP_PHY_TX_EDGE_SEL_S 21
|
||||
/* USB_WRAP_PHY_CLK_FORCE_ON : R/W ;bitpos:[20] ;default: 1'b1 ; */
|
||||
/*description: Force phy clock always on.*/
|
||||
#define USB_WRAP_PHY_CLK_FORCE_ON (BIT(20))
|
||||
#define USB_WRAP_PHY_CLK_FORCE_ON_M (BIT(20))
|
||||
#define USB_WRAP_PHY_CLK_FORCE_ON_V 0x1
|
||||
#define USB_WRAP_PHY_CLK_FORCE_ON_S 20
|
||||
/* USB_WRAP_AHB_CLK_FORCE_ON : R/W ;bitpos:[19] ;default: 1'b1 ; */
|
||||
/*description: Force ahb clock always on.*/
|
||||
#define USB_WRAP_AHB_CLK_FORCE_ON (BIT(19))
|
||||
#define USB_WRAP_AHB_CLK_FORCE_ON_M (BIT(19))
|
||||
#define USB_WRAP_AHB_CLK_FORCE_ON_V 0x1
|
||||
#define USB_WRAP_AHB_CLK_FORCE_ON_S 19
|
||||
/* USB_WRAP_USB_PAD_ENABLE : R/W ;bitpos:[18] ;default: 1'b1 ; */
|
||||
/*description: Enable USB pad function.*/
|
||||
#define USB_WRAP_USB_PAD_ENABLE (BIT(18))
|
||||
#define USB_WRAP_USB_PAD_ENABLE_M (BIT(18))
|
||||
#define USB_WRAP_USB_PAD_ENABLE_V 0x1
|
||||
#define USB_WRAP_USB_PAD_ENABLE_S 18
|
||||
/* USB_WRAP_PULLUP_VALUE : R/W ;bitpos:[17] ;default: 1'b0 ; */
|
||||
/*description: Controlle pullup value.*/
|
||||
#define USB_WRAP_PULLUP_VALUE (BIT(17))
|
||||
#define USB_WRAP_PULLUP_VALUE_M (BIT(17))
|
||||
#define USB_WRAP_PULLUP_VALUE_V 0x1
|
||||
#define USB_WRAP_PULLUP_VALUE_S 17
|
||||
/* USB_WRAP_DM_PULLDOWN : R/W ;bitpos:[16] ;default: 1'b0 ; */
|
||||
/*description: Controlle USB D+ pulldown.*/
|
||||
#define USB_WRAP_DM_PULLDOWN (BIT(16))
|
||||
#define USB_WRAP_DM_PULLDOWN_M (BIT(16))
|
||||
#define USB_WRAP_DM_PULLDOWN_V 0x1
|
||||
#define USB_WRAP_DM_PULLDOWN_S 16
|
||||
/* USB_WRAP_DM_PULLUP : R/W ;bitpos:[15] ;default: 1'b0 ; */
|
||||
/*description: Controlle USB D+ pullup.*/
|
||||
#define USB_WRAP_DM_PULLUP (BIT(15))
|
||||
#define USB_WRAP_DM_PULLUP_M (BIT(15))
|
||||
#define USB_WRAP_DM_PULLUP_V 0x1
|
||||
#define USB_WRAP_DM_PULLUP_S 15
|
||||
/* USB_WRAP_DP_PULLDOWN : R/W ;bitpos:[14] ;default: 1'b0 ; */
|
||||
/*description: Controlle USB D+ pulldown.*/
|
||||
#define USB_WRAP_DP_PULLDOWN (BIT(14))
|
||||
#define USB_WRAP_DP_PULLDOWN_M (BIT(14))
|
||||
#define USB_WRAP_DP_PULLDOWN_V 0x1
|
||||
#define USB_WRAP_DP_PULLDOWN_S 14
|
||||
/* USB_WRAP_DP_PULLUP : R/W ;bitpos:[13] ;default: 1'b0 ; */
|
||||
/*description: Controlle USB D+ pullup.*/
|
||||
#define USB_WRAP_DP_PULLUP (BIT(13))
|
||||
#define USB_WRAP_DP_PULLUP_M (BIT(13))
|
||||
#define USB_WRAP_DP_PULLUP_V 0x1
|
||||
#define USB_WRAP_DP_PULLUP_S 13
|
||||
/* USB_WRAP_PAD_PULL_OVERRIDE : R/W ;bitpos:[12] ;default: 1'b0 ; */
|
||||
/*description: Enable software controlle USB D+ D- pullup pulldown.*/
|
||||
#define USB_WRAP_PAD_PULL_OVERRIDE (BIT(12))
|
||||
#define USB_WRAP_PAD_PULL_OVERRIDE_M (BIT(12))
|
||||
#define USB_WRAP_PAD_PULL_OVERRIDE_V 0x1
|
||||
#define USB_WRAP_PAD_PULL_OVERRIDE_S 12
|
||||
/* USB_WRAP_VREF_OVERRIDE : R/W ;bitpos:[11] ;default: 1'b0 ; */
|
||||
/*description: Enable software controlle input threshold.*/
|
||||
#define USB_WRAP_VREF_OVERRIDE (BIT(11))
|
||||
#define USB_WRAP_VREF_OVERRIDE_M (BIT(11))
|
||||
#define USB_WRAP_VREF_OVERRIDE_V 0x1
|
||||
#define USB_WRAP_VREF_OVERRIDE_S 11
|
||||
/* USB_WRAP_VREFL : R/W ;bitpos:[10:9] ;default: 2'b0 ; */
|
||||
/*description: Control single-end input low threshold,0.8V to 1.04V, step 80mV.*/
|
||||
#define USB_WRAP_VREFL 0x00000003
|
||||
#define USB_WRAP_VREFL_M ((USB_WRAP_VREFL_V)<<(USB_WRAP_VREFL_S))
|
||||
#define USB_WRAP_VREFL_V 0x3
|
||||
#define USB_WRAP_VREFL_S 9
|
||||
/* USB_WRAP_VREFH : R/W ;bitpos:[8:7] ;default: 2'b0 ; */
|
||||
/*description: Control single-end input high threshold,1.76V to 2V, step 80mV.*/
|
||||
#define USB_WRAP_VREFH 0x00000003
|
||||
#define USB_WRAP_VREFH_M ((USB_WRAP_VREFH_V)<<(USB_WRAP_VREFH_S))
|
||||
#define USB_WRAP_VREFH_V 0x3
|
||||
#define USB_WRAP_VREFH_S 7
|
||||
/* USB_WRAP_EXCHG_PINS : R/W ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: USB D+ D- exchange.*/
|
||||
#define USB_WRAP_EXCHG_PINS (BIT(6))
|
||||
#define USB_WRAP_EXCHG_PINS_M (BIT(6))
|
||||
#define USB_WRAP_EXCHG_PINS_V 0x1
|
||||
#define USB_WRAP_EXCHG_PINS_S 6
|
||||
/* USB_WRAP_EXCHG_PINS_OVERRIDE : R/W ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: Enable software controlle USB D+ D- exchange.*/
|
||||
#define USB_WRAP_EXCHG_PINS_OVERRIDE (BIT(5))
|
||||
#define USB_WRAP_EXCHG_PINS_OVERRIDE_M (BIT(5))
|
||||
#define USB_WRAP_EXCHG_PINS_OVERRIDE_V 0x1
|
||||
#define USB_WRAP_EXCHG_PINS_OVERRIDE_S 5
|
||||
/* USB_WRAP_DBNCE_FLTR_BYPASS : R/W ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals.*/
|
||||
#define USB_WRAP_DBNCE_FLTR_BYPASS (BIT(4))
|
||||
#define USB_WRAP_DBNCE_FLTR_BYPASS_M (BIT(4))
|
||||
#define USB_WRAP_DBNCE_FLTR_BYPASS_V 0x1
|
||||
#define USB_WRAP_DBNCE_FLTR_BYPASS_S 4
|
||||
/* USB_WRAP_DFIFO_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: Force the dfifo to go into low power mode. The data in dfifo will not lost..*/
|
||||
#define USB_WRAP_DFIFO_FORCE_PD (BIT(3))
|
||||
#define USB_WRAP_DFIFO_FORCE_PD_M (BIT(3))
|
||||
#define USB_WRAP_DFIFO_FORCE_PD_V 0x1
|
||||
#define USB_WRAP_DFIFO_FORCE_PD_S 3
|
||||
/* USB_WRAP_PHY_SEL : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: Select internal external PHY.*/
|
||||
#define USB_WRAP_PHY_SEL (BIT(2))
|
||||
#define USB_WRAP_PHY_SEL_M (BIT(2))
|
||||
#define USB_WRAP_PHY_SEL_V 0x1
|
||||
#define USB_WRAP_PHY_SEL_S 2
|
||||
/* USB_WRAP_SRP_SESSEND_VALUE : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: Software over-ride value of srp session end signal..*/
|
||||
#define USB_WRAP_SRP_SESSEND_VALUE (BIT(1))
|
||||
#define USB_WRAP_SRP_SESSEND_VALUE_M (BIT(1))
|
||||
#define USB_WRAP_SRP_SESSEND_VALUE_V 0x1
|
||||
#define USB_WRAP_SRP_SESSEND_VALUE_S 1
|
||||
/* USB_WRAP_SRP_SESSEND_OVERRIDE : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: This bit is used to enable the software over-ride of srp session end signal..*/
|
||||
#define USB_WRAP_SRP_SESSEND_OVERRIDE (BIT(0))
|
||||
#define USB_WRAP_SRP_SESSEND_OVERRIDE_M (BIT(0))
|
||||
#define USB_WRAP_SRP_SESSEND_OVERRIDE_V 0x1
|
||||
#define USB_WRAP_SRP_SESSEND_OVERRIDE_S 0
|
||||
|
||||
#define USB_WRAP_TEST_CONF_REG (DR_REG_USB_WRAP_BASE + 0x4)
|
||||
/* USB_WRAP_TEST_RX_DM : RO ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: USB D- rx value in test.*/
|
||||
#define USB_WRAP_TEST_RX_DM (BIT(6))
|
||||
#define USB_WRAP_TEST_RX_DM_M (BIT(6))
|
||||
#define USB_WRAP_TEST_RX_DM_V 0x1
|
||||
#define USB_WRAP_TEST_RX_DM_S 6
|
||||
/* USB_WRAP_TEST_RX_DP : RO ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: USB D+ rx value in test.*/
|
||||
#define USB_WRAP_TEST_RX_DP (BIT(5))
|
||||
#define USB_WRAP_TEST_RX_DP_M (BIT(5))
|
||||
#define USB_WRAP_TEST_RX_DP_V 0x1
|
||||
#define USB_WRAP_TEST_RX_DP_S 5
|
||||
/* USB_WRAP_TEST_RX_RCV : RO ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: USB differential rx value in test.*/
|
||||
#define USB_WRAP_TEST_RX_RCV (BIT(4))
|
||||
#define USB_WRAP_TEST_RX_RCV_M (BIT(4))
|
||||
#define USB_WRAP_TEST_RX_RCV_V 0x1
|
||||
#define USB_WRAP_TEST_RX_RCV_S 4
|
||||
/* USB_WRAP_TEST_TX_DM : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: USB D- tx value in test.*/
|
||||
#define USB_WRAP_TEST_TX_DM (BIT(3))
|
||||
#define USB_WRAP_TEST_TX_DM_M (BIT(3))
|
||||
#define USB_WRAP_TEST_TX_DM_V 0x1
|
||||
#define USB_WRAP_TEST_TX_DM_S 3
|
||||
/* USB_WRAP_TEST_TX_DP : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: USB D+ tx value in test.*/
|
||||
#define USB_WRAP_TEST_TX_DP (BIT(2))
|
||||
#define USB_WRAP_TEST_TX_DP_M (BIT(2))
|
||||
#define USB_WRAP_TEST_TX_DP_V 0x1
|
||||
#define USB_WRAP_TEST_TX_DP_S 2
|
||||
/* USB_WRAP_TEST_USB_OE : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: USB pad oen in test.*/
|
||||
#define USB_WRAP_TEST_USB_OE (BIT(1))
|
||||
#define USB_WRAP_TEST_USB_OE_M (BIT(1))
|
||||
#define USB_WRAP_TEST_USB_OE_V 0x1
|
||||
#define USB_WRAP_TEST_USB_OE_S 1
|
||||
/* USB_WRAP_TEST_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: Enable test of the USB pad.*/
|
||||
#define USB_WRAP_TEST_ENABLE (BIT(0))
|
||||
#define USB_WRAP_TEST_ENABLE_M (BIT(0))
|
||||
#define USB_WRAP_TEST_ENABLE_V 0x1
|
||||
#define USB_WRAP_TEST_ENABLE_S 0
|
||||
|
||||
#define USB_WRAP_DATE_REG (DR_REG_USB_WRAP_BASE + 0x3FC)
|
||||
/* USB_WRAP_DATE : R/W ;bitpos:[31:0] ;default: 32'h2102010 ; */
|
||||
/*description: Date register.*/
|
||||
#define USB_WRAP_DATE 0xFFFFFFFF
|
||||
#define USB_WRAP_DATE_M ((USB_WRAP_DATE_V)<<(USB_WRAP_DATE_S))
|
||||
#define USB_WRAP_DATE_V 0xFFFFFFFF
|
||||
#define USB_WRAP_DATE_S 0
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /*_SOC_USB_WRAP_REG_H_ */
|
||||
@@ -1,445 +0,0 @@
|
||||
/** Copyright 2020 Espressif Systems (Shanghai) PTE LTD
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Control/Status registers */
|
||||
/** Type of otg_conf register
|
||||
* PAD/DFIFO/PHY configuration register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** srp_sessend_override : R/W; bitpos: [0]; default: 0;
|
||||
* This bit is used to enable the software override of srp session end signal.1'b0:
|
||||
* the signal is controlled by the chip input.1'b1: the signal is controlled by the
|
||||
* software.
|
||||
*/
|
||||
uint32_t srp_sessend_override:1;
|
||||
/** srp_sessend_value : R/W; bitpos: [1]; default: 0;
|
||||
* Software override value of srp session end signal.
|
||||
*/
|
||||
uint32_t srp_sessend_value:1;
|
||||
/** phy_sel : R/W; bitpos: [2]; default: 0;
|
||||
* Select internal or external PHY.1'b0: Select internal PHY.1'b1: Select external PHY
|
||||
*/
|
||||
uint32_t phy_sel:1;
|
||||
/** dfifo_force_pd : R/W; bitpos: [3]; default: 0;
|
||||
* Force the dfifo to go into low power mode. The data in dfifo will not lost.
|
||||
*/
|
||||
uint32_t dfifo_force_pd:1;
|
||||
/** dbnce_fltr_bypass : R/W; bitpos: [4]; default: 0;
|
||||
* Bypass Debounce filters for avalid.
|
||||
*/
|
||||
uint32_t dbnce_fltr_bypass:1;
|
||||
/** exchg_pins_override : R/W; bitpos: [5]; default: 0;
|
||||
* Enable software to control USB D+ D- exchange
|
||||
*/
|
||||
uint32_t exchg_pins_override:1;
|
||||
/** exchg_pins : R/W; bitpos: [6]; default: 0;
|
||||
* USB D+/D- exchange.1'b0: don't change.1'b1: exchange D+ D-.
|
||||
*/
|
||||
uint32_t exchg_pins:1;
|
||||
/** vrefh : R/W; bitpos: [8:7]; default: 0;
|
||||
* Control single-end input high threshold.
|
||||
*/
|
||||
uint32_t vrefh:2;
|
||||
/** vrefl : R/W; bitpos: [10:9]; default: 0;
|
||||
* Control single-end input low threshold.
|
||||
*/
|
||||
uint32_t vrefl:2;
|
||||
/** vref_override : R/W; bitpos: [11]; default: 0;
|
||||
* Enable software to control input threshold.
|
||||
*/
|
||||
uint32_t vref_override:1;
|
||||
/** pad_pull_override : R/W; bitpos: [12]; default: 0;
|
||||
* Enable software to control USB pad in pullup or pulldown mode.
|
||||
*/
|
||||
uint32_t pad_pull_override:1;
|
||||
/** dp_pullup : R/W; bitpos: [13]; default: 0;
|
||||
* Control USB D+ pullup.
|
||||
*/
|
||||
uint32_t dp_pullup:1;
|
||||
/** dp_pulldown : R/W; bitpos: [14]; default: 0;
|
||||
* Control USB D+ pulldown.
|
||||
*/
|
||||
uint32_t dp_pulldown:1;
|
||||
/** dm_pullup : R/W; bitpos: [15]; default: 0;
|
||||
* Control USB D+ pullup.
|
||||
*/
|
||||
uint32_t dm_pullup:1;
|
||||
/** dm_pulldown : R/W; bitpos: [16]; default: 0;
|
||||
* Control USB D+ pulldown.
|
||||
*/
|
||||
uint32_t dm_pulldown:1;
|
||||
/** pullup_value : R/W; bitpos: [17]; default: 0;
|
||||
* Control pullup value.1'b0: typical value is 2.4K.1'b1: typical value is 1.2K.
|
||||
*/
|
||||
uint32_t pullup_value:1;
|
||||
/** pad_enable : R/W; bitpos: [18]; default: 0;
|
||||
* Enable USB pad function.
|
||||
*/
|
||||
uint32_t pad_enable:1;
|
||||
/** ahb_clk_force_on : R/W; bitpos: [19]; default: 1;
|
||||
* Force AHB clock always on.
|
||||
*/
|
||||
uint32_t ahb_clk_force_on:1;
|
||||
/** phy_clk_force_on : R/W; bitpos: [20]; default: 1;
|
||||
* Force PHY clock always on.
|
||||
*/
|
||||
uint32_t phy_clk_force_on:1;
|
||||
/** phy_tx_edge_sel : R/W; bitpos: [21]; default: 0;
|
||||
* Select PHY tx signal output clock edge.1'b0: negedge;1'b1: posedge.
|
||||
*/
|
||||
uint32_t phy_tx_edge_sel:1;
|
||||
/** dfifo_force_pu : R/W; bitpos: [22]; default: 0;
|
||||
* Disable the dfifo to go into low power mode. The data in dfifo will not lost.
|
||||
*/
|
||||
uint32_t dfifo_force_pu:1;
|
||||
uint32_t reserved_23:8;
|
||||
/** clk_en : R/W; bitpos: [31]; default: 0;
|
||||
* Disable auto clock gating of CSR registers.
|
||||
*/
|
||||
uint32_t clk_en:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_wrap_otg_conf_reg_t;
|
||||
|
||||
/** Type of test_conf register
|
||||
* TEST relative configuration registers.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** test_enable : R/W; bitpos: [0]; default: 0;
|
||||
* Enable to test the USB pad.
|
||||
*/
|
||||
uint32_t test_enable:1;
|
||||
/** test_usb_wrap_oe : R/W; bitpos: [1]; default: 0;
|
||||
* USB pad oen in test.
|
||||
*/
|
||||
uint32_t test_usb_wrap_oe:1;
|
||||
/** test_tx_dp : R/W; bitpos: [2]; default: 0;
|
||||
* USB D+ tx value in test.
|
||||
*/
|
||||
uint32_t test_tx_dp:1;
|
||||
/** test_tx_dm : R/W; bitpos: [3]; default: 0;
|
||||
* USB D- tx value in test.
|
||||
*/
|
||||
uint32_t test_tx_dm:1;
|
||||
/** test_rx_rcv : RO; bitpos: [4]; default: 0;
|
||||
* USB differential rx value in test.
|
||||
*/
|
||||
uint32_t test_rx_rcv:1;
|
||||
/** test_rx_dp : RO; bitpos: [5]; default: 0;
|
||||
* USB D+ rx value in test.
|
||||
*/
|
||||
uint32_t test_rx_dp:1;
|
||||
/** test_rx_dm : RO; bitpos: [6]; default: 0;
|
||||
* USB D- rx value in test.
|
||||
*/
|
||||
uint32_t test_rx_dm:1;
|
||||
uint32_t reserved_7:25;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_wrap_test_conf_reg_t;
|
||||
|
||||
|
||||
/** Status registers */
|
||||
/** Type of date register
|
||||
* Version register.
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** date : R/W; bitpos: [31:0]; default: 419631616;
|
||||
* data register.
|
||||
*/
|
||||
uint32_t date:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_wrap_date_reg_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
volatile usb_wrap_otg_conf_reg_t otg_conf;
|
||||
volatile usb_wrap_test_conf_reg_t test_conf;
|
||||
uint32_t reserved_008;
|
||||
uint32_t reserved_00c;
|
||||
uint32_t reserved_010;
|
||||
uint32_t reserved_014;
|
||||
uint32_t reserved_018;
|
||||
uint32_t reserved_01c;
|
||||
uint32_t reserved_020;
|
||||
uint32_t reserved_024;
|
||||
uint32_t reserved_028;
|
||||
uint32_t reserved_02c;
|
||||
uint32_t reserved_030;
|
||||
uint32_t reserved_034;
|
||||
uint32_t reserved_038;
|
||||
uint32_t reserved_03c;
|
||||
uint32_t reserved_040;
|
||||
uint32_t reserved_044;
|
||||
uint32_t reserved_048;
|
||||
uint32_t reserved_04c;
|
||||
uint32_t reserved_050;
|
||||
uint32_t reserved_054;
|
||||
uint32_t reserved_058;
|
||||
uint32_t reserved_05c;
|
||||
uint32_t reserved_060;
|
||||
uint32_t reserved_064;
|
||||
uint32_t reserved_068;
|
||||
uint32_t reserved_06c;
|
||||
uint32_t reserved_070;
|
||||
uint32_t reserved_074;
|
||||
uint32_t reserved_078;
|
||||
uint32_t reserved_07c;
|
||||
uint32_t reserved_080;
|
||||
uint32_t reserved_084;
|
||||
uint32_t reserved_088;
|
||||
uint32_t reserved_08c;
|
||||
uint32_t reserved_090;
|
||||
uint32_t reserved_094;
|
||||
uint32_t reserved_098;
|
||||
uint32_t reserved_09c;
|
||||
uint32_t reserved_0a0;
|
||||
uint32_t reserved_0a4;
|
||||
uint32_t reserved_0a8;
|
||||
uint32_t reserved_0ac;
|
||||
uint32_t reserved_0b0;
|
||||
uint32_t reserved_0b4;
|
||||
uint32_t reserved_0b8;
|
||||
uint32_t reserved_0bc;
|
||||
uint32_t reserved_0c0;
|
||||
uint32_t reserved_0c4;
|
||||
uint32_t reserved_0c8;
|
||||
uint32_t reserved_0cc;
|
||||
uint32_t reserved_0d0;
|
||||
uint32_t reserved_0d4;
|
||||
uint32_t reserved_0d8;
|
||||
uint32_t reserved_0dc;
|
||||
uint32_t reserved_0e0;
|
||||
uint32_t reserved_0e4;
|
||||
uint32_t reserved_0e8;
|
||||
uint32_t reserved_0ec;
|
||||
uint32_t reserved_0f0;
|
||||
uint32_t reserved_0f4;
|
||||
uint32_t reserved_0f8;
|
||||
uint32_t reserved_0fc;
|
||||
uint32_t reserved_100;
|
||||
uint32_t reserved_104;
|
||||
uint32_t reserved_108;
|
||||
uint32_t reserved_10c;
|
||||
uint32_t reserved_110;
|
||||
uint32_t reserved_114;
|
||||
uint32_t reserved_118;
|
||||
uint32_t reserved_11c;
|
||||
uint32_t reserved_120;
|
||||
uint32_t reserved_124;
|
||||
uint32_t reserved_128;
|
||||
uint32_t reserved_12c;
|
||||
uint32_t reserved_130;
|
||||
uint32_t reserved_134;
|
||||
uint32_t reserved_138;
|
||||
uint32_t reserved_13c;
|
||||
uint32_t reserved_140;
|
||||
uint32_t reserved_144;
|
||||
uint32_t reserved_148;
|
||||
uint32_t reserved_14c;
|
||||
uint32_t reserved_150;
|
||||
uint32_t reserved_154;
|
||||
uint32_t reserved_158;
|
||||
uint32_t reserved_15c;
|
||||
uint32_t reserved_160;
|
||||
uint32_t reserved_164;
|
||||
uint32_t reserved_168;
|
||||
uint32_t reserved_16c;
|
||||
uint32_t reserved_170;
|
||||
uint32_t reserved_174;
|
||||
uint32_t reserved_178;
|
||||
uint32_t reserved_17c;
|
||||
uint32_t reserved_180;
|
||||
uint32_t reserved_184;
|
||||
uint32_t reserved_188;
|
||||
uint32_t reserved_18c;
|
||||
uint32_t reserved_190;
|
||||
uint32_t reserved_194;
|
||||
uint32_t reserved_198;
|
||||
uint32_t reserved_19c;
|
||||
uint32_t reserved_1a0;
|
||||
uint32_t reserved_1a4;
|
||||
uint32_t reserved_1a8;
|
||||
uint32_t reserved_1ac;
|
||||
uint32_t reserved_1b0;
|
||||
uint32_t reserved_1b4;
|
||||
uint32_t reserved_1b8;
|
||||
uint32_t reserved_1bc;
|
||||
uint32_t reserved_1c0;
|
||||
uint32_t reserved_1c4;
|
||||
uint32_t reserved_1c8;
|
||||
uint32_t reserved_1cc;
|
||||
uint32_t reserved_1d0;
|
||||
uint32_t reserved_1d4;
|
||||
uint32_t reserved_1d8;
|
||||
uint32_t reserved_1dc;
|
||||
uint32_t reserved_1e0;
|
||||
uint32_t reserved_1e4;
|
||||
uint32_t reserved_1e8;
|
||||
uint32_t reserved_1ec;
|
||||
uint32_t reserved_1f0;
|
||||
uint32_t reserved_1f4;
|
||||
uint32_t reserved_1f8;
|
||||
uint32_t reserved_1fc;
|
||||
uint32_t reserved_200;
|
||||
uint32_t reserved_204;
|
||||
uint32_t reserved_208;
|
||||
uint32_t reserved_20c;
|
||||
uint32_t reserved_210;
|
||||
uint32_t reserved_214;
|
||||
uint32_t reserved_218;
|
||||
uint32_t reserved_21c;
|
||||
uint32_t reserved_220;
|
||||
uint32_t reserved_224;
|
||||
uint32_t reserved_228;
|
||||
uint32_t reserved_22c;
|
||||
uint32_t reserved_230;
|
||||
uint32_t reserved_234;
|
||||
uint32_t reserved_238;
|
||||
uint32_t reserved_23c;
|
||||
uint32_t reserved_240;
|
||||
uint32_t reserved_244;
|
||||
uint32_t reserved_248;
|
||||
uint32_t reserved_24c;
|
||||
uint32_t reserved_250;
|
||||
uint32_t reserved_254;
|
||||
uint32_t reserved_258;
|
||||
uint32_t reserved_25c;
|
||||
uint32_t reserved_260;
|
||||
uint32_t reserved_264;
|
||||
uint32_t reserved_268;
|
||||
uint32_t reserved_26c;
|
||||
uint32_t reserved_270;
|
||||
uint32_t reserved_274;
|
||||
uint32_t reserved_278;
|
||||
uint32_t reserved_27c;
|
||||
uint32_t reserved_280;
|
||||
uint32_t reserved_284;
|
||||
uint32_t reserved_288;
|
||||
uint32_t reserved_28c;
|
||||
uint32_t reserved_290;
|
||||
uint32_t reserved_294;
|
||||
uint32_t reserved_298;
|
||||
uint32_t reserved_29c;
|
||||
uint32_t reserved_2a0;
|
||||
uint32_t reserved_2a4;
|
||||
uint32_t reserved_2a8;
|
||||
uint32_t reserved_2ac;
|
||||
uint32_t reserved_2b0;
|
||||
uint32_t reserved_2b4;
|
||||
uint32_t reserved_2b8;
|
||||
uint32_t reserved_2bc;
|
||||
uint32_t reserved_2c0;
|
||||
uint32_t reserved_2c4;
|
||||
uint32_t reserved_2c8;
|
||||
uint32_t reserved_2cc;
|
||||
uint32_t reserved_2d0;
|
||||
uint32_t reserved_2d4;
|
||||
uint32_t reserved_2d8;
|
||||
uint32_t reserved_2dc;
|
||||
uint32_t reserved_2e0;
|
||||
uint32_t reserved_2e4;
|
||||
uint32_t reserved_2e8;
|
||||
uint32_t reserved_2ec;
|
||||
uint32_t reserved_2f0;
|
||||
uint32_t reserved_2f4;
|
||||
uint32_t reserved_2f8;
|
||||
uint32_t reserved_2fc;
|
||||
uint32_t reserved_300;
|
||||
uint32_t reserved_304;
|
||||
uint32_t reserved_308;
|
||||
uint32_t reserved_30c;
|
||||
uint32_t reserved_310;
|
||||
uint32_t reserved_314;
|
||||
uint32_t reserved_318;
|
||||
uint32_t reserved_31c;
|
||||
uint32_t reserved_320;
|
||||
uint32_t reserved_324;
|
||||
uint32_t reserved_328;
|
||||
uint32_t reserved_32c;
|
||||
uint32_t reserved_330;
|
||||
uint32_t reserved_334;
|
||||
uint32_t reserved_338;
|
||||
uint32_t reserved_33c;
|
||||
uint32_t reserved_340;
|
||||
uint32_t reserved_344;
|
||||
uint32_t reserved_348;
|
||||
uint32_t reserved_34c;
|
||||
uint32_t reserved_350;
|
||||
uint32_t reserved_354;
|
||||
uint32_t reserved_358;
|
||||
uint32_t reserved_35c;
|
||||
uint32_t reserved_360;
|
||||
uint32_t reserved_364;
|
||||
uint32_t reserved_368;
|
||||
uint32_t reserved_36c;
|
||||
uint32_t reserved_370;
|
||||
uint32_t reserved_374;
|
||||
uint32_t reserved_378;
|
||||
uint32_t reserved_37c;
|
||||
uint32_t reserved_380;
|
||||
uint32_t reserved_384;
|
||||
uint32_t reserved_388;
|
||||
uint32_t reserved_38c;
|
||||
uint32_t reserved_390;
|
||||
uint32_t reserved_394;
|
||||
uint32_t reserved_398;
|
||||
uint32_t reserved_39c;
|
||||
uint32_t reserved_3a0;
|
||||
uint32_t reserved_3a4;
|
||||
uint32_t reserved_3a8;
|
||||
uint32_t reserved_3ac;
|
||||
uint32_t reserved_3b0;
|
||||
uint32_t reserved_3b4;
|
||||
uint32_t reserved_3b8;
|
||||
uint32_t reserved_3bc;
|
||||
uint32_t reserved_3c0;
|
||||
uint32_t reserved_3c4;
|
||||
uint32_t reserved_3c8;
|
||||
uint32_t reserved_3cc;
|
||||
uint32_t reserved_3d0;
|
||||
uint32_t reserved_3d4;
|
||||
uint32_t reserved_3d8;
|
||||
uint32_t reserved_3dc;
|
||||
uint32_t reserved_3e0;
|
||||
uint32_t reserved_3e4;
|
||||
uint32_t reserved_3e8;
|
||||
uint32_t reserved_3ec;
|
||||
uint32_t reserved_3f0;
|
||||
uint32_t reserved_3f4;
|
||||
uint32_t reserved_3f8;
|
||||
volatile usb_wrap_date_reg_t date;
|
||||
} usb_wrap_dev_t;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(usb_wrap_dev_t)==0x400, "Invalid USB_WRAP size");
|
||||
#endif
|
||||
|
||||
extern usb_wrap_dev_t USB_WRAP;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user