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https://github.com/espressif/esp-idf.git
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feat(spiram): refactor for spiram device driver for s3/c5
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C.S.M
231
components/hal/esp32s3/include/hal/psram_ctrlr_ll.h
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231
components/hal/esp32s3/include/hal/psram_ctrlr_ll.h
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/*
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*******************************************************************************
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* NOTICE
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* The ll is not public api, don't use in application code.
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* See readme.md in hal/include/hal/readme.md
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******************************************************************************/
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#pragma once
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#include <stdint.h>
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#include <stdbool.h>
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#include <sys/param.h>
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#include "hal/assert.h"
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#include "hal/misc.h"
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#include "soc/spi_mem_struct.h"
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#include "soc/spi_mem_reg.h"
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#include "soc/clk_tree_defs.h"
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#include "rom/opi_flash.h"
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#include "hal/psram_types.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define PSRAM_CTRLR_LL_MSPI_ID_0 0
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#define PSRAM_CTRLR_LL_MSPI_ID_1 1
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#define PSRAM_LL_CS_SEL SPI_MEM_CS1_DIS_M
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/**
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* @brief PSRAM enum for cs id.
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*/
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typedef enum {
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PSRAM_LL_CS_ID_0 = 0,
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PSRAM_LL_CS_ID_1 = 1,
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} psram_ll_cs_id_t;
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/**
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* @brief Set PSRAM write cmd
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*
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* @param mspi_id mspi_id
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* @param cmd_bitlen command bitlen
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* @param cmd_val command value
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*/
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__attribute__((always_inline))
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static inline void psram_ctrlr_ll_set_wr_cmd(uint32_t mspi_id, uint32_t cmd_bitlen, uint32_t cmd_val)
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{
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(void)mspi_id;
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HAL_ASSERT(cmd_bitlen > 0);
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SPIMEM0.cache_sctrl.usr_wcmd = 1;
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SPIMEM0.sram_dwr_cmd.usr_wr_cmd_bitlen = cmd_bitlen - 1;
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HAL_FORCE_MODIFY_U32_REG_FIELD(SPIMEM0.sram_dwr_cmd, usr_wr_cmd_value, cmd_val);
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}
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/**
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* @brief Set PSRAM read cmd
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*
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* @param mspi_id mspi_id
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* @param cmd_bitlen command bitlen
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* @param cmd_val command value
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*/
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__attribute__((always_inline))
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static inline void psram_ctrlr_ll_set_rd_cmd(uint32_t mspi_id, uint32_t cmd_bitlen, uint32_t cmd_val)
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{
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(void)mspi_id;
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HAL_ASSERT(cmd_bitlen > 0);
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SPIMEM0.cache_sctrl.usr_rcmd = 1;
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SPIMEM0.sram_drd_cmd.usr_rd_cmd_bitlen = cmd_bitlen - 1;
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HAL_FORCE_MODIFY_U32_REG_FIELD(SPIMEM0.sram_drd_cmd, usr_rd_cmd_value, cmd_val);
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}
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/**
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* @brief Set PSRAM addr bitlen
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*
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* @param mspi_id mspi_id
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* @param addr_bitlen address bitlen
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*/
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__attribute__((always_inline))
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static inline void psram_ctrlr_ll_set_addr_bitlen(uint32_t mspi_id, uint32_t addr_bitlen)
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{
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(void)mspi_id;
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HAL_ASSERT(addr_bitlen > 0);
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SPIMEM0.cache_sctrl.sram_addr_bitlen = addr_bitlen - 1;
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}
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/**
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* @brief Set PSRAM read dummy
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*
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* @param mspi_id mspi_id
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* @param dummy_n dummy number
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*/
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__attribute__((always_inline))
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static inline void psram_ctrlr_ll_set_rd_dummy(uint32_t mspi_id, uint32_t dummy_n)
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{
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(void)mspi_id;
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HAL_ASSERT(dummy_n > 0);
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SPIMEM0.cache_sctrl.usr_rd_sram_dummy = 1;
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SPIMEM0.cache_sctrl.sram_rdummy_cyclelen = dummy_n - 1;
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}
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/**
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* Configure the psram read mode
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*
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* @param mspi_id mspi_id
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* @param read_mode read mode
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*/
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static inline void psram_ctrlr_ll_set_read_mode(uint32_t mspi_id, psram_hal_cmd_mode_t read_mode)
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{
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typeof (SPIMEM0.cache_sctrl) cache_sctrl;
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cache_sctrl.val = SPIMEM0.cache_sctrl.val;
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cache_sctrl.val &= ~(SPI_MEM_USR_SRAM_DIO_M | SPI_MEM_USR_SRAM_QIO_M);
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switch (read_mode) {
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case PSRAM_HAL_CMD_SPI:
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cache_sctrl.usr_sram_dio = 1;
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break;
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case PSRAM_HAL_CMD_QPI:
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cache_sctrl.usr_sram_qio = 1;
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break;
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default:
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abort();
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}
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SPIMEM0.cache_sctrl.val = cache_sctrl.val;
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}
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/**
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* @brief Set CS setup
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*
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* @param mspi_id mspi_id
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* @param setup_n cs setup time
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*/
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__attribute__((always_inline))
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static inline void psram_ctrlr_ll_set_cs_setup(uint32_t mspi_id, uint32_t setup_n)
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{
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(void)mspi_id;
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HAL_ASSERT(setup_n > 0);
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SPIMEM0.spi_smem_ac.smem_cs_setup = 1;
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SPIMEM0.spi_smem_ac.smem_cs_setup_time = setup_n - 1;
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}
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/**
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* @brief Set CS hold
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*
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* @param mspi_id mspi_id
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* @param hold_n cs hold time
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*/
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__attribute__((always_inline))
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static inline void psram_ctrlr_ll_set_cs_hold(uint32_t mspi_id, uint32_t hold_n)
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{
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(void)mspi_id;
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HAL_ASSERT(hold_n > 0);
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SPIMEM0.spi_smem_ac.smem_cs_hold = 1;
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SPIMEM0.spi_smem_ac.smem_cs_hold_time = hold_n - 1;
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}
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/**
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* @brief Set CS hold delay
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*
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* @param mspi_id mspi_id
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* @param hold_delay_n cs hold delay time
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*/
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__attribute__((always_inline))
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static inline void psram_ctrlr_ll_set_cs_hold_delay(uint32_t mspi_id, uint32_t hold_delay_n)
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{
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(void)mspi_id;
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HAL_ASSERT(hold_delay_n > 0);
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SPIMEM0.spi_smem_ac.smem_cs_hold_delay = hold_delay_n - 1;
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}
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/**
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* @brief PSRAM common transaction
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*
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* See `opi_flash.h` for parameters
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*/
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__attribute__((always_inline))
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static inline void psram_ctrlr_ll_common_transaction_base(uint32_t mspi_id, esp_rom_spiflash_read_mode_t mode,
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uint32_t cmd, uint32_t cmd_bitlen,
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uint32_t addr, uint32_t addr_bitlen,
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uint32_t dummy_bits,
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uint8_t* mosi_data, uint32_t mosi_bitlen,
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uint8_t* miso_data, uint32_t miso_bitlen,
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uint32_t cs_mask,
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bool is_write_erase_operation)
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{
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esp_rom_spi_cmd_t conf = {
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.cmd = cmd,
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.cmdBitLen = cmd_bitlen,
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.addr = &addr,
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.addrBitLen = addr_bitlen,
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.txData = (uint32_t *)mosi_data,
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.txDataBitLen = mosi_bitlen,
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.rxData = (uint32_t *)miso_data,
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.rxDataBitLen = miso_bitlen,
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.dummyBitLen = dummy_bits,
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};
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esp_rom_spi_cmd_config(mspi_id, &conf);
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esp_rom_spi_cmd_start(mspi_id, miso_data, miso_bitlen / 8, cs_mask, is_write_erase_operation);
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}
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/**
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* Select which pin to use for the psram
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*
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* @param mspi_id mspi_id
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* @param cs_id cs_id for psram to use.
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*/
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static inline void psram_ctrlr_ll_set_cs_pin(uint32_t mspi_id, psram_ll_cs_id_t cs_id)
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{
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SPIMEM0.misc.cs0_dis = (cs_id == 0) ? 0 : 1;
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SPIMEM0.misc.cs1_dis = (cs_id == 1) ? 0 : 1;
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}
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/**
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* Enable the psram quad command
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*
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* @param mspi_id mspi_id
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* @param ena true if enable, otherwise false
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*/
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__attribute__((always_inline))
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static inline void psram_ctrlr_ll_enable_quad_command(uint32_t mspi_id, bool ena)
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{
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SPIMEM1.ctrl.fcmd_quad = ena;
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}
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#ifdef __cplusplus
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}
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#endif
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